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/hal/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_udp.h

https://gitlab.com/YaoQ/mbed-for-linknode
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Redistribution and use in source and binary forms, with or without
    11. 

  11.  * modification, are permitted provided that the following conditions are met:
    12. 

  12.  *
    13. 

  13.  * 1. Redistributions of source code must retain the above copyright notice,
    14. 

  14.  *    this list of conditions and the following disclaimer.
    15. 

  15.  *
    16. 

  16.  * 2. Redistributions in binary form must reproduce the above copyright notice,
    17. 

  17.  *    this list of conditions and the following disclaimer in the documentation
    18. 

  18.  *    and/or other materials provided with the distribution.
    19. 

  19.  *
    20. 

  20.  * 3. The name of Atmel may not be used to endorse or promote products derived
    21. 

  21.  *    from this software without specific prior written permission.
    22. 

  22.  *
    23. 

  23.  * 4. This software may only be redistributed and used in connection with an
    24. 

  24.  *    Atmel microcontroller product.
    25. 

  25.  *
    26. 

  26.  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    27. 

  27.  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    28. 

  28.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    29. 

  29.  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    30. 

  30.  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
    31. 

  31.  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
    32. 

  32.  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
    33. 

  33.  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
    34. 

  34.  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
    35. 

  35.  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    36. 

  36.  * POSSIBILITY OF SUCH DAMAGE.
    37. 

  37.  *
    38. 

  38.  * \asf_license_stop
    39. 

  39.  *
    40. 

  40.  */
    41. 

  41. /*
    42. 

  42.  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
    43. 

  43.  */
    44. 

  44. 

  45. #ifndef _SAMG55_UDP_COMPONENT_
    46. 

  46. #define _SAMG55_UDP_COMPONENT_
    47. 

  47. 

  48. /* ============================================================================= */
    49. 

  49. /**  SOFTWARE API DEFINITION FOR USB Device Port */
    50. 

  50. /* ============================================================================= */
    51. 

  51. /** \addtogroup SAMG55_UDP USB Device Port */
    52. 

  52. /*@{*/
    53. 

  53. 

  54. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    55. 

  55. /** \brief Udp hardware registers */
    56. 

  56. typedef struct {
    57. 

  57.     __I  uint32_t UDP_FRM_NUM;  /**< \brief (Udp Offset: 0x000) Frame Number Register */
    58. 

  58.     __IO uint32_t UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
    59. 

  59.     __IO uint32_t UDP_FADDR;    /**< \brief (Udp Offset: 0x008) Function Address Register */
    60. 

  60.     __I  uint32_t Reserved1[1];
    61. 

  61.     __O  uint32_t UDP_IER;      /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
    62. 

  62.     __O  uint32_t UDP_IDR;      /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
    63. 

  63.     __I  uint32_t UDP_IMR;      /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
    64. 

  64.     __I  uint32_t UDP_ISR;      /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
    65. 

  65.     __O  uint32_t UDP_ICR;      /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
    66. 

  66.     __I  uint32_t Reserved2[1];
    67. 

  67.     __IO uint32_t UDP_RST_EP;   /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
    68. 

  68.     __I  uint32_t Reserved3[1];
    69. 

  69.     __IO uint32_t UDP_CSR[6];   /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
    70. 

  70.     __I  uint32_t Reserved4[2];
    71. 

  71.     __IO uint32_t UDP_FDR[6];   /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
    72. 

  72.     __I  uint32_t Reserved5[3];
    73. 

  73.     __IO uint32_t UDP_TXVC;     /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
    74. 

  74. } Udp;
    75. 

  75. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    76. 

  76. /* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
    77. 

  77. #define UDP_FRM_NUM_FRM_NUM_Pos 0
    78. 

  78. #define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
    79. 

  79. #define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
    80. 

  80. #define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
    81. 

  81. /* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
    82. 

  82. #define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
    83. 

  83. #define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
    84. 

  84. #define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
    85. 

  85. #define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT)  */
    86. 

  86. #define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
    87. 

  87. /* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
    88. 

  88. #define UDP_FADDR_FADD_Pos 0
    89. 

  89. #define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
    90. 

  90. #define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
    91. 

  91. #define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
    92. 

  92. /* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
    93. 

  93. #define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
    94. 

  94. #define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
    95. 

  95. #define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
    96. 

  96. #define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
    97. 

  97. #define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
    98. 

  98. #define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
    99. 

  99. #define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
    100. 

  100. #define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
    101. 

  101. #define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER)  */
    102. 

  102. #define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
    103. 

  103. #define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
    104. 

  104. /* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
    105. 

  105. #define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
    106. 

  106. #define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
    107. 

  107. #define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
    108. 

  108. #define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
    109. 

  109. #define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
    110. 

  110. #define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
    111. 

  111. #define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
    112. 

  112. #define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
    113. 

  113. #define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR)  */
    114. 

  114. #define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
    115. 

  115. #define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
    116. 

  116. /* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
    117. 

  117. #define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
    118. 

  118. #define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
    119. 

  119. #define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
    120. 

  120. #define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
    121. 

  121. #define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
    122. 

  122. #define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
    123. 

  123. #define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
    124. 

  124. #define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
    125. 

  125. #define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR)  */
    126. 

  126. #define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
    127. 

  127. #define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
    128. 

  128. #define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
    129. 

  129. /* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
    130. 

  130. #define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
    131. 

  131. #define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
    132. 

  132. #define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
    133. 

  133. #define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
    134. 

  134. #define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
    135. 

  135. #define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
    136. 

  136. #define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
    137. 

  137. #define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
    138. 

  138. #define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR)  */
    139. 

  139. #define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
    140. 

  140. #define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
    141. 

  141. #define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
    142. 

  142. /* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
    143. 

  143. #define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
    144. 

  144. #define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
    145. 

  145. #define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR)  */
    146. 

  146. #define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
    147. 

  147. #define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
    148. 

  148. #define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
    149. 

  149. /* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
    150. 

  150. #define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
    151. 

  151. #define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
    152. 

  152. #define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
    153. 

  153. #define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
    154. 

  154. #define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
    155. 

  155. #define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
    156. 

  156. /* -------- UDP_CSR[6] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
    157. 

  157. #define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[6]) Generates an IN Packet with Data Previously Written in the DPR */
    158. 

  158. #define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[6]) Receive Data Bank 0 */
    159. 

  159. #define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[6]) Received Setup */
    160. 

  160. #define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[6]) Stall Sent */
    161. 

  161. #define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[6]) Transmit Packet Ready */
    162. 

  162. #define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[6]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
    163. 

  163. #define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[6]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
    164. 

  164. #define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[6]) Transfer Direction (only available for control endpoints) */
    165. 

  165. #define UDP_CSR_EPTYPE_Pos 8
    166. 

  166. #define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[6]) Endpoint Type */
    167. 

  167. #define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[6]) Control */
    168. 

  168. #define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[6]) Isochronous OUT */
    169. 

  169. #define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[6]) Bulk OUT */
    170. 

  170. #define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[6]) Interrupt OUT */
    171. 

  171. #define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[6]) Isochronous IN */
    172. 

  172. #define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[6]) Bulk IN */
    173. 

  173. #define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[6]) Interrupt IN */
    174. 

  174. #define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[6]) Data Toggle */
    175. 

  175. #define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[6]) Endpoint Enable Disable */
    176. 

  176. #define UDP_CSR_RXBYTECNT_Pos 16
    177. 

  177. #define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[6]) Number of Bytes Available in the FIFO */
    178. 

  178. #define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
    179. 

  179. #define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[6]) A CRC error has been detected in an isochronous transfer */
    180. 

  180. /* -------- UDP_FDR[6] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
    181. 

  181. #define UDP_FDR_FIFO_DATA_Pos 0
    182. 

  182. #define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[6]) FIFO Data Value */
    183. 

  183. #define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
    184. 

  184. /* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
    185. 

  185. #define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
    186. 

  186. #define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */
    187. 

  187. 

  188. /*@}*/
    189. 

  189. 

  190. 

  191. #endif /* _SAMG55_UDP_COMPONENT_ */
    192. 

  192.