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/hal/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_udp.h

https://gitlab.com/YaoQ/mbed-for-linknode
C Header | 191 lines | 123 code | 6 blank | 62 comment | 1 complexity | 520ffcae0a8c172c3454d68b61ef99f9 MD5 | raw file
  1. /**
  2. * \file
  3. *
  4. * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
  5. *
  6. * \asf_license_start
  7. *
  8. * \page License
  9. *
  10. * Redistribution and use in source and binary forms, with or without
  11. * modification, are permitted provided that the following conditions are met:
  12. *
  13. * 1. Redistributions of source code must retain the above copyright notice,
  14. * this list of conditions and the following disclaimer.
  15. *
  16. * 2. Redistributions in binary form must reproduce the above copyright notice,
  17. * this list of conditions and the following disclaimer in the documentation
  18. * and/or other materials provided with the distribution.
  19. *
  20. * 3. The name of Atmel may not be used to endorse or promote products derived
  21. * from this software without specific prior written permission.
  22. *
  23. * 4. This software may only be redistributed and used in connection with an
  24. * Atmel microcontroller product.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
  27. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  29. * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
  30. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  34. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  35. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  36. * POSSIBILITY OF SUCH DAMAGE.
  37. *
  38. * \asf_license_stop
  39. *
  40. */
  41. /*
  42. * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
  43. */
  44. #ifndef _SAMG55_UDP_COMPONENT_
  45. #define _SAMG55_UDP_COMPONENT_
  46. /* ============================================================================= */
  47. /** SOFTWARE API DEFINITION FOR USB Device Port */
  48. /* ============================================================================= */
  49. /** \addtogroup SAMG55_UDP USB Device Port */
  50. /*@{*/
  51. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  52. /** \brief Udp hardware registers */
  53. typedef struct {
  54. __I uint32_t UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */
  55. __IO uint32_t UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
  56. __IO uint32_t UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */
  57. __I uint32_t Reserved1[1];
  58. __O uint32_t UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
  59. __O uint32_t UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
  60. __I uint32_t UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
  61. __I uint32_t UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
  62. __O uint32_t UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
  63. __I uint32_t Reserved2[1];
  64. __IO uint32_t UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
  65. __I uint32_t Reserved3[1];
  66. __IO uint32_t UDP_CSR[6]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
  67. __I uint32_t Reserved4[2];
  68. __IO uint32_t UDP_FDR[6]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
  69. __I uint32_t Reserved5[3];
  70. __IO uint32_t UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
  71. } Udp;
  72. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
  73. /* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
  74. #define UDP_FRM_NUM_FRM_NUM_Pos 0
  75. #define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
  76. #define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
  77. #define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
  78. /* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
  79. #define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
  80. #define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
  81. #define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
  82. #define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */
  83. #define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
  84. /* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
  85. #define UDP_FADDR_FADD_Pos 0
  86. #define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
  87. #define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
  88. #define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
  89. /* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
  90. #define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
  91. #define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
  92. #define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
  93. #define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
  94. #define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
  95. #define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
  96. #define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
  97. #define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
  98. #define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */
  99. #define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
  100. #define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
  101. /* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
  102. #define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
  103. #define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
  104. #define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
  105. #define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
  106. #define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
  107. #define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
  108. #define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
  109. #define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
  110. #define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */
  111. #define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
  112. #define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
  113. /* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
  114. #define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
  115. #define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
  116. #define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
  117. #define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
  118. #define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
  119. #define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
  120. #define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
  121. #define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
  122. #define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */
  123. #define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
  124. #define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
  125. #define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
  126. /* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
  127. #define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
  128. #define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
  129. #define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
  130. #define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
  131. #define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
  132. #define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
  133. #define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
  134. #define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
  135. #define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */
  136. #define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
  137. #define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
  138. #define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
  139. /* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
  140. #define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
  141. #define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
  142. #define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */
  143. #define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
  144. #define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
  145. #define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
  146. /* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
  147. #define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
  148. #define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
  149. #define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
  150. #define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
  151. #define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
  152. #define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
  153. /* -------- UDP_CSR[6] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
  154. #define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[6]) Generates an IN Packet with Data Previously Written in the DPR */
  155. #define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[6]) Receive Data Bank 0 */
  156. #define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[6]) Received Setup */
  157. #define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[6]) Stall Sent */
  158. #define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[6]) Transmit Packet Ready */
  159. #define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[6]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
  160. #define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[6]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
  161. #define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[6]) Transfer Direction (only available for control endpoints) */
  162. #define UDP_CSR_EPTYPE_Pos 8
  163. #define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[6]) Endpoint Type */
  164. #define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[6]) Control */
  165. #define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[6]) Isochronous OUT */
  166. #define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[6]) Bulk OUT */
  167. #define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[6]) Interrupt OUT */
  168. #define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[6]) Isochronous IN */
  169. #define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[6]) Bulk IN */
  170. #define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[6]) Interrupt IN */
  171. #define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[6]) Data Toggle */
  172. #define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[6]) Endpoint Enable Disable */
  173. #define UDP_CSR_RXBYTECNT_Pos 16
  174. #define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[6]) Number of Bytes Available in the FIFO */
  175. #define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
  176. #define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[6]) A CRC error has been detected in an isochronous transfer */
  177. /* -------- UDP_FDR[6] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
  178. #define UDP_FDR_FIFO_DATA_Pos 0
  179. #define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[6]) FIFO Data Value */
  180. #define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
  181. /* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
  182. #define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
  183. #define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */
  184. /*@}*/
  185. #endif /* _SAMG55_UDP_COMPONENT_ */