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/arch/arm/kernel/swp_emulate.c

https://gitlab.com/jhalayashraj/nkernel
C | 342 lines | 214 code | 57 blank | 71 comment | 39 complexity | 6add8be0c88e225f4012789216052b92 MD5 | raw file
  1. /*
  2. * linux/arch/arm/kernel/swp_emulate.c
  3. *
  4. * Copyright (C) 2009 ARM Limited
  5. * __user_* functions adapted from include/asm/uaccess.h
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Implements emulation of the SWP/SWPB instructions using load-exclusive and
  12. * store-exclusive for processors that have them disabled (or future ones that
  13. * might not implement them).
  14. *
  15. * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
  16. * Where: Rt = destination
  17. * Rt2 = source
  18. * Rn = address
  19. */
  20. #include <linux/init.h>
  21. #include <linux/kernel.h>
  22. #include <linux/proc_fs.h>
  23. #include <linux/sched.h>
  24. #include <linux/syscalls.h>
  25. #include <linux/perf_event.h>
  26. #include <asm/opcodes.h>
  27. #include <asm/traps.h>
  28. #include <asm/uaccess.h>
  29. /*
  30. * Error-checking SWP macros implemented using ldrex{b}/strex{b}
  31. */
  32. #define __user_swpX_asm(data, addr, res, temp, B) \
  33. __asm__ __volatile__( \
  34. " mov %2, %1\n" \
  35. "0: ldrex"B" %1, [%3]\n" \
  36. "1: strex"B" %0, %2, [%3]\n" \
  37. " cmp %0, #0\n" \
  38. " movne %0, %4\n" \
  39. "2:\n" \
  40. " .section .fixup,\"ax\"\n" \
  41. " .align 2\n" \
  42. "3: mov %0, %5\n" \
  43. " b 2b\n" \
  44. " .previous\n" \
  45. " .section __ex_table,\"a\"\n" \
  46. " .align 3\n" \
  47. " .long 0b, 3b\n" \
  48. " .long 1b, 3b\n" \
  49. " .previous" \
  50. : "=&r" (res), "+r" (data), "=&r" (temp) \
  51. : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT) \
  52. : "cc", "memory")
  53. #define __user_swp_asm(data, addr, res, temp) \
  54. __user_swpX_asm(data, addr, res, temp, "")
  55. #define __user_swpb_asm(data, addr, res, temp) \
  56. __user_swpX_asm(data, addr, res, temp, "b")
  57. /*
  58. * Macros/defines for extracting register numbers from instruction.
  59. */
  60. #define EXTRACT_REG_NUM(instruction, offset) \
  61. (((instruction) & (0xf << (offset))) >> (offset))
  62. #define RN_OFFSET 16
  63. #define RT_OFFSET 12
  64. #define RT2_OFFSET 0
  65. /*
  66. * Bit 22 of the instruction encoding distinguishes between
  67. * the SWP and SWPB variants (bit set means SWPB).
  68. */
  69. #define TYPE_SWPB (1 << 22)
  70. static unsigned long swpcounter;
  71. static unsigned long swpbcounter;
  72. static unsigned long abtcounter;
  73. static pid_t previous_pid;
  74. #ifdef CONFIG_PROC_FS
  75. static int proc_read_status(char *page, char **start, off_t off, int count,
  76. int *eof, void *data)
  77. {
  78. char *p = page;
  79. int len;
  80. p += sprintf(p, "Emulated SWP:\t\t%lu\n", swpcounter);
  81. p += sprintf(p, "Emulated SWPB:\t\t%lu\n", swpbcounter);
  82. p += sprintf(p, "Aborted SWP{B}:\t\t%lu\n", abtcounter);
  83. if (previous_pid != 0)
  84. p += sprintf(p, "Last process:\t\t%d\n", previous_pid);
  85. len = (p - page) - off;
  86. if (len < 0)
  87. len = 0;
  88. *eof = (len <= count) ? 1 : 0;
  89. *start = page + off;
  90. return len;
  91. }
  92. #endif
  93. /*
  94. * Set up process info to signal segmentation fault - called on access error.
  95. */
  96. static void set_segfault(struct pt_regs *regs, unsigned long addr)
  97. {
  98. siginfo_t info;
  99. down_read(&current->mm->mmap_sem);
  100. if (find_vma(current->mm, addr) == NULL)
  101. info.si_code = SEGV_MAPERR;
  102. else
  103. info.si_code = SEGV_ACCERR;
  104. up_read(&current->mm->mmap_sem);
  105. info.si_signo = SIGSEGV;
  106. info.si_errno = 0;
  107. info.si_addr = (void *) instruction_pointer(regs);
  108. pr_debug("SWP{B} emulation: access caused memory abort!\n");
  109. arm_notify_die("Illegal memory access", regs, &info, 0, 0);
  110. abtcounter++;
  111. }
  112. static int emulate_swpX(unsigned int address, unsigned int *data,
  113. unsigned int type)
  114. {
  115. unsigned int res = 0;
  116. if ((type != TYPE_SWPB) && (address & 0x3)) {
  117. /* SWP to unaligned address not permitted */
  118. pr_debug("SWP instruction on unaligned pointer!\n");
  119. return -EFAULT;
  120. }
  121. while (1) {
  122. unsigned long temp;
  123. /*
  124. * Barrier required between accessing protected resource and
  125. * releasing a lock for it. Legacy code might not have done
  126. * this, and we cannot determine that this is not the case
  127. * being emulated, so insert always.
  128. */
  129. smp_mb();
  130. if (type == TYPE_SWPB)
  131. __user_swpb_asm(*data, address, res, temp);
  132. else
  133. __user_swp_asm(*data, address, res, temp);
  134. if (likely(res != -EAGAIN) || signal_pending(current))
  135. break;
  136. cond_resched();
  137. }
  138. if (res == 0) {
  139. /*
  140. * Barrier also required between acquiring a lock for a
  141. * protected resource and accessing the resource. Inserted for
  142. * same reason as above.
  143. */
  144. smp_mb();
  145. if (type == TYPE_SWPB)
  146. swpbcounter++;
  147. else
  148. swpcounter++;
  149. }
  150. return res;
  151. }
  152. static int check_condition(struct pt_regs *regs, unsigned int insn)
  153. {
  154. unsigned int base_cond, neg, cond = 0;
  155. unsigned int cpsr_z, cpsr_c, cpsr_n, cpsr_v;
  156. cpsr_n = (regs->ARM_cpsr & PSR_N_BIT) ? 1 : 0;
  157. cpsr_z = (regs->ARM_cpsr & PSR_Z_BIT) ? 1 : 0;
  158. cpsr_c = (regs->ARM_cpsr & PSR_C_BIT) ? 1 : 0;
  159. cpsr_v = (regs->ARM_cpsr & PSR_V_BIT) ? 1 : 0;
  160. /* Upper 3 bits indicate condition, lower bit incicates negation */
  161. base_cond = insn >> 29;
  162. neg = insn & BIT(28) ? 1 : 0;
  163. switch (base_cond) {
  164. case 0x0: /* equal */
  165. cond = cpsr_z;
  166. break;
  167. case 0x1: /* carry set */
  168. cond = cpsr_c;
  169. break;
  170. case 0x2: /* minus / negative */
  171. cond = cpsr_n;
  172. break;
  173. case 0x3: /* overflow */
  174. cond = cpsr_v;
  175. break;
  176. case 0x4: /* unsigned higher */
  177. cond = (cpsr_c == 1) && (cpsr_z == 0);
  178. break;
  179. case 0x5: /* signed greater / equal */
  180. cond = (cpsr_n == cpsr_v);
  181. break;
  182. case 0x6: /* signed greater */
  183. cond = (cpsr_z == 0) && (cpsr_n == cpsr_v);
  184. break;
  185. case 0x7: /* always */
  186. cond = 1;
  187. break;
  188. };
  189. return cond && !neg;
  190. }
  191. /*
  192. * swp_handler logs the id of calling process, dissects the instruction, sanity
  193. * checks the memory location, calls emulate_swpX for the actual operation and
  194. * deals with fixup/error handling before returning
  195. */
  196. static int swp_handler(struct pt_regs *regs, unsigned int instr)
  197. {
  198. unsigned int address, destreg, data, type;
  199. unsigned int res = 0;
  200. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->ARM_pc);
  201. res = arm_check_condition(instr, regs->ARM_cpsr);
  202. switch (res) {
  203. case ARM_OPCODE_CONDTEST_PASS:
  204. break;
  205. case ARM_OPCODE_CONDTEST_FAIL:
  206. /* Condition failed - return to next instruction */
  207. regs->ARM_pc += 4;
  208. return 0;
  209. case ARM_OPCODE_CONDTEST_UNCOND:
  210. /* If unconditional encoding - not a SWP, undef */
  211. return -EFAULT;
  212. default:
  213. return -EINVAL;
  214. }
  215. if (current->pid != previous_pid) {
  216. pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n",
  217. current->comm, (unsigned long)current->pid);
  218. previous_pid = current->pid;
  219. }
  220. /* Ignore the instruction if it fails its condition code check */
  221. if (!check_condition(regs, instr)) {
  222. regs->ARM_pc += 4;
  223. return 0;
  224. }
  225. address = regs->uregs[EXTRACT_REG_NUM(instr, RN_OFFSET)];
  226. data = regs->uregs[EXTRACT_REG_NUM(instr, RT2_OFFSET)];
  227. destreg = EXTRACT_REG_NUM(instr, RT_OFFSET);
  228. type = instr & TYPE_SWPB;
  229. pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
  230. EXTRACT_REG_NUM(instr, RN_OFFSET), address,
  231. destreg, EXTRACT_REG_NUM(instr, RT2_OFFSET), data);
  232. /* Check access in reasonable access range for both SWP and SWPB */
  233. if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
  234. pr_debug("SWP{B} emulation: access to %p not allowed!\n",
  235. (void *)address);
  236. res = -EFAULT;
  237. } else {
  238. res = emulate_swpX(address, &data, type);
  239. }
  240. if (res == 0) {
  241. /*
  242. * On successful emulation, revert the adjustment to the PC
  243. * made in kernel/traps.c in order to resume execution at the
  244. * instruction following the SWP{B}.
  245. */
  246. regs->ARM_pc += 4;
  247. regs->uregs[destreg] = data;
  248. } else if (res == -EFAULT) {
  249. /*
  250. * Memory errors do not mean emulation failed.
  251. * Set up signal info to return SEGV, then return OK
  252. */
  253. set_segfault(regs, address);
  254. }
  255. return 0;
  256. }
  257. /*
  258. * Only emulate SWP/SWPB executed in ARM state/User mode.
  259. * The kernel must be SWP free and SWP{B} does not exist in Thumb/ThumbEE.
  260. */
  261. static struct undef_hook swp_hook = {
  262. .instr_mask = 0x0fb00ff0,
  263. .instr_val = 0x01000090,
  264. .cpsr_mask = MODE_MASK | PSR_T_BIT | PSR_J_BIT,
  265. .cpsr_val = USR_MODE,
  266. .fn = swp_handler
  267. };
  268. /*
  269. * Register handler and create status file in /proc/cpu
  270. * Invoked as late_initcall, since not needed before init spawned.
  271. */
  272. static int __init swp_emulation_init(void)
  273. {
  274. #ifdef CONFIG_PROC_FS
  275. struct proc_dir_entry *res;
  276. res = create_proc_entry("cpu/swp_emulation", S_IRUGO, NULL);
  277. if (!res)
  278. return -ENOMEM;
  279. res->read_proc = proc_read_status;
  280. #endif /* CONFIG_PROC_FS */
  281. printk(KERN_NOTICE "Registering SWP/SWPB emulation handler\n");
  282. register_undef_hook(&swp_hook);
  283. return 0;
  284. }
  285. late_initcall(swp_emulation_init);