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/arch/arm/mm/cache-xsc3l2.c

https://gitlab.com/jhalayashraj/nkernel
C | 220 lines | 144 code | 41 blank | 35 comment | 23 complexity | d9bfd21fff0ba79533b062cf208e9e5b MD5 | raw file
  1. /*
  2. * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
  3. *
  4. * Copyright (C) 2007 ARM Limited
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/highmem.h>
  21. #include <asm/cp15.h>
  22. #include <asm/cputype.h>
  23. #include <asm/cacheflush.h>
  24. #define CR_L2 (1 << 26)
  25. #define CACHE_LINE_SIZE 32
  26. #define CACHE_LINE_SHIFT 5
  27. #define CACHE_WAY_PER_SET 8
  28. #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
  29. #define CACHE_SET_SIZE(l2ctype) (CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)
  30. static inline int xsc3_l2_present(void)
  31. {
  32. unsigned long l2ctype;
  33. __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
  34. return !!(l2ctype & 0xf8);
  35. }
  36. static inline void xsc3_l2_clean_mva(unsigned long addr)
  37. {
  38. __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr));
  39. }
  40. static inline void xsc3_l2_inv_mva(unsigned long addr)
  41. {
  42. __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr));
  43. }
  44. static inline void xsc3_l2_inv_all(void)
  45. {
  46. unsigned long l2ctype, set_way;
  47. int set, way;
  48. __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
  49. for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
  50. for (way = 0; way < CACHE_WAY_PER_SET; way++) {
  51. set_way = (way << 29) | (set << 5);
  52. __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way));
  53. }
  54. }
  55. dsb();
  56. }
  57. static inline void l2_unmap_va(unsigned long va)
  58. {
  59. #ifdef CONFIG_HIGHMEM
  60. if (va != -1)
  61. kunmap_atomic((void *)va);
  62. #endif
  63. }
  64. static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va)
  65. {
  66. #ifdef CONFIG_HIGHMEM
  67. unsigned long va = prev_va & PAGE_MASK;
  68. unsigned long pa_offset = pa << (32 - PAGE_SHIFT);
  69. if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) {
  70. /*
  71. * Switching to a new page. Because cache ops are
  72. * using virtual addresses only, we must put a mapping
  73. * in place for it.
  74. */
  75. l2_unmap_va(prev_va);
  76. va = (unsigned long)kmap_atomic_pfn(pa >> PAGE_SHIFT);
  77. }
  78. return va + (pa_offset >> (32 - PAGE_SHIFT));
  79. #else
  80. return __phys_to_virt(pa);
  81. #endif
  82. }
  83. static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
  84. {
  85. unsigned long vaddr;
  86. if (start == 0 && end == -1ul) {
  87. xsc3_l2_inv_all();
  88. return;
  89. }
  90. vaddr = -1; /* to force the first mapping */
  91. /*
  92. * Clean and invalidate partial first cache line.
  93. */
  94. if (start & (CACHE_LINE_SIZE - 1)) {
  95. vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr);
  96. xsc3_l2_clean_mva(vaddr);
  97. xsc3_l2_inv_mva(vaddr);
  98. start = (start | (CACHE_LINE_SIZE - 1)) + 1;
  99. }
  100. /*
  101. * Invalidate all full cache lines between 'start' and 'end'.
  102. */
  103. while (start < (end & ~(CACHE_LINE_SIZE - 1))) {
  104. vaddr = l2_map_va(start, vaddr);
  105. xsc3_l2_inv_mva(vaddr);
  106. start += CACHE_LINE_SIZE;
  107. }
  108. /*
  109. * Clean and invalidate partial last cache line.
  110. */
  111. if (start < end) {
  112. vaddr = l2_map_va(start, vaddr);
  113. xsc3_l2_clean_mva(vaddr);
  114. xsc3_l2_inv_mva(vaddr);
  115. }
  116. l2_unmap_va(vaddr);
  117. dsb();
  118. }
  119. static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
  120. {
  121. unsigned long vaddr;
  122. vaddr = -1; /* to force the first mapping */
  123. start &= ~(CACHE_LINE_SIZE - 1);
  124. while (start < end) {
  125. vaddr = l2_map_va(start, vaddr);
  126. xsc3_l2_clean_mva(vaddr);
  127. start += CACHE_LINE_SIZE;
  128. }
  129. l2_unmap_va(vaddr);
  130. dsb();
  131. }
  132. /*
  133. * optimize L2 flush all operation by set/way format
  134. */
  135. static inline void xsc3_l2_flush_all(void)
  136. {
  137. unsigned long l2ctype, set_way;
  138. int set, way;
  139. __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
  140. for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
  141. for (way = 0; way < CACHE_WAY_PER_SET; way++) {
  142. set_way = (way << 29) | (set << 5);
  143. __asm__("mcr p15, 1, %0, c7, c15, 2" : : "r"(set_way));
  144. }
  145. }
  146. dsb();
  147. }
  148. static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
  149. {
  150. unsigned long vaddr;
  151. if (start == 0 && end == -1ul) {
  152. xsc3_l2_flush_all();
  153. return;
  154. }
  155. vaddr = -1; /* to force the first mapping */
  156. start &= ~(CACHE_LINE_SIZE - 1);
  157. while (start < end) {
  158. vaddr = l2_map_va(start, vaddr);
  159. xsc3_l2_clean_mva(vaddr);
  160. xsc3_l2_inv_mva(vaddr);
  161. start += CACHE_LINE_SIZE;
  162. }
  163. l2_unmap_va(vaddr);
  164. dsb();
  165. }
  166. static int __init xsc3_l2_init(void)
  167. {
  168. if (!cpu_is_xsc3() || !xsc3_l2_present())
  169. return 0;
  170. if (get_cr() & CR_L2) {
  171. pr_info("XScale3 L2 cache enabled.\n");
  172. xsc3_l2_inv_all();
  173. outer_cache.inv_range = xsc3_l2_inv_range;
  174. outer_cache.clean_range = xsc3_l2_clean_range;
  175. outer_cache.flush_range = xsc3_l2_flush_range;
  176. }
  177. return 0;
  178. }
  179. core_initcall(xsc3_l2_init);