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/drivers/rtc/rtc-imxdi.c

https://gitlab.com/jhalayashraj/nkernel
C | 522 lines | 305 code | 97 blank | 120 comment | 42 complexity | be4257118c5e6a67ed7c313bc936abab MD5 | raw file
  1. /*
  2. * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright 2010 Orex Computed Radiography
  4. */
  5. /*
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /* based on rtc-mc13892.c */
  14. /*
  15. * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
  16. * to implement a Linux RTC. Times and alarms are truncated to seconds.
  17. * Since the RTC framework performs API locking via rtc->ops_lock the
  18. * only simultaneous accesses we need to deal with is updating DryIce
  19. * registers while servicing an alarm.
  20. *
  21. * Note that reading the DSR (DryIce Status Register) automatically clears
  22. * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
  23. * LP (Low Power) domain and set the WCF upon completion. Writes to the
  24. * DIER (DryIce Interrupt Enable Register) are the only exception. These
  25. * occur at normal bus speeds and do not set WCF. Periodic interrupts are
  26. * not supported by the hardware.
  27. */
  28. #include <linux/io.h>
  29. #include <linux/clk.h>
  30. #include <linux/delay.h>
  31. #include <linux/module.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/rtc.h>
  34. #include <linux/sched.h>
  35. #include <linux/workqueue.h>
  36. /* DryIce Register Definitions */
  37. #define DTCMR 0x00 /* Time Counter MSB Reg */
  38. #define DTCLR 0x04 /* Time Counter LSB Reg */
  39. #define DCAMR 0x08 /* Clock Alarm MSB Reg */
  40. #define DCALR 0x0c /* Clock Alarm LSB Reg */
  41. #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
  42. #define DCR 0x10 /* Control Reg */
  43. #define DCR_TCE (1 << 3) /* Time Counter Enable */
  44. #define DSR 0x14 /* Status Reg */
  45. #define DSR_WBF (1 << 10) /* Write Busy Flag */
  46. #define DSR_WNF (1 << 9) /* Write Next Flag */
  47. #define DSR_WCF (1 << 8) /* Write Complete Flag */
  48. #define DSR_WEF (1 << 7) /* Write Error Flag */
  49. #define DSR_CAF (1 << 4) /* Clock Alarm Flag */
  50. #define DSR_NVF (1 << 1) /* Non-Valid Flag */
  51. #define DSR_SVF (1 << 0) /* Security Violation Flag */
  52. #define DIER 0x18 /* Interrupt Enable Reg */
  53. #define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
  54. #define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
  55. #define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
  56. #define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
  57. /**
  58. * struct imxdi_dev - private imxdi rtc data
  59. * @pdev: pionter to platform dev
  60. * @rtc: pointer to rtc struct
  61. * @ioaddr: IO registers pointer
  62. * @irq: dryice normal interrupt
  63. * @clk: input reference clock
  64. * @dsr: copy of the DSR register
  65. * @irq_lock: interrupt enable register (DIER) lock
  66. * @write_wait: registers write complete queue
  67. * @write_mutex: serialize registers write
  68. * @work: schedule alarm work
  69. */
  70. struct imxdi_dev {
  71. struct platform_device *pdev;
  72. struct rtc_device *rtc;
  73. void __iomem *ioaddr;
  74. int irq;
  75. struct clk *clk;
  76. u32 dsr;
  77. spinlock_t irq_lock;
  78. wait_queue_head_t write_wait;
  79. struct mutex write_mutex;
  80. struct work_struct work;
  81. };
  82. /*
  83. * enable a dryice interrupt
  84. */
  85. static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
  86. {
  87. unsigned long flags;
  88. spin_lock_irqsave(&imxdi->irq_lock, flags);
  89. __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
  90. imxdi->ioaddr + DIER);
  91. spin_unlock_irqrestore(&imxdi->irq_lock, flags);
  92. }
  93. /*
  94. * disable a dryice interrupt
  95. */
  96. static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
  97. {
  98. unsigned long flags;
  99. spin_lock_irqsave(&imxdi->irq_lock, flags);
  100. __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
  101. imxdi->ioaddr + DIER);
  102. spin_unlock_irqrestore(&imxdi->irq_lock, flags);
  103. }
  104. /*
  105. * This function attempts to clear the dryice write-error flag.
  106. *
  107. * A dryice write error is similar to a bus fault and should not occur in
  108. * normal operation. Clearing the flag requires another write, so the root
  109. * cause of the problem may need to be fixed before the flag can be cleared.
  110. */
  111. static void clear_write_error(struct imxdi_dev *imxdi)
  112. {
  113. int cnt;
  114. dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
  115. /* clear the write error flag */
  116. __raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
  117. /* wait for it to take effect */
  118. for (cnt = 0; cnt < 1000; cnt++) {
  119. if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
  120. return;
  121. udelay(10);
  122. }
  123. dev_err(&imxdi->pdev->dev,
  124. "ERROR: Cannot clear write-error flag!\n");
  125. }
  126. /*
  127. * Write a dryice register and wait until it completes.
  128. *
  129. * This function uses interrupts to determine when the
  130. * write has completed.
  131. */
  132. static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
  133. {
  134. int ret;
  135. int rc = 0;
  136. /* serialize register writes */
  137. mutex_lock(&imxdi->write_mutex);
  138. /* enable the write-complete interrupt */
  139. di_int_enable(imxdi, DIER_WCIE);
  140. imxdi->dsr = 0;
  141. /* do the register write */
  142. __raw_writel(val, imxdi->ioaddr + reg);
  143. /* wait for the write to finish */
  144. ret = wait_event_interruptible_timeout(imxdi->write_wait,
  145. imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
  146. if (ret < 0) {
  147. rc = ret;
  148. goto out;
  149. } else if (ret == 0) {
  150. dev_warn(&imxdi->pdev->dev,
  151. "Write-wait timeout "
  152. "val = 0x%08x reg = 0x%08x\n", val, reg);
  153. }
  154. /* check for write error */
  155. if (imxdi->dsr & DSR_WEF) {
  156. clear_write_error(imxdi);
  157. rc = -EIO;
  158. }
  159. out:
  160. mutex_unlock(&imxdi->write_mutex);
  161. return rc;
  162. }
  163. /*
  164. * read the seconds portion of the current time from the dryice time counter
  165. */
  166. static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
  167. {
  168. struct imxdi_dev *imxdi = dev_get_drvdata(dev);
  169. unsigned long now;
  170. now = __raw_readl(imxdi->ioaddr + DTCMR);
  171. rtc_time_to_tm(now, tm);
  172. return 0;
  173. }
  174. /*
  175. * set the seconds portion of dryice time counter and clear the
  176. * fractional part.
  177. */
  178. static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
  179. {
  180. struct imxdi_dev *imxdi = dev_get_drvdata(dev);
  181. int rc;
  182. /* zero the fractional part first */
  183. rc = di_write_wait(imxdi, 0, DTCLR);
  184. if (rc == 0)
  185. rc = di_write_wait(imxdi, secs, DTCMR);
  186. return rc;
  187. }
  188. static int dryice_rtc_alarm_irq_enable(struct device *dev,
  189. unsigned int enabled)
  190. {
  191. struct imxdi_dev *imxdi = dev_get_drvdata(dev);
  192. if (enabled)
  193. di_int_enable(imxdi, DIER_CAIE);
  194. else
  195. di_int_disable(imxdi, DIER_CAIE);
  196. return 0;
  197. }
  198. /*
  199. * read the seconds portion of the alarm register.
  200. * the fractional part of the alarm register is always zero.
  201. */
  202. static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  203. {
  204. struct imxdi_dev *imxdi = dev_get_drvdata(dev);
  205. u32 dcamr;
  206. dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
  207. rtc_time_to_tm(dcamr, &alarm->time);
  208. /* alarm is enabled if the interrupt is enabled */
  209. alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
  210. /* don't allow the DSR read to mess up DSR_WCF */
  211. mutex_lock(&imxdi->write_mutex);
  212. /* alarm is pending if the alarm flag is set */
  213. alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
  214. mutex_unlock(&imxdi->write_mutex);
  215. return 0;
  216. }
  217. /*
  218. * set the seconds portion of dryice alarm register
  219. */
  220. static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  221. {
  222. struct imxdi_dev *imxdi = dev_get_drvdata(dev);
  223. unsigned long now;
  224. unsigned long alarm_time;
  225. int rc;
  226. rc = rtc_tm_to_time(&alarm->time, &alarm_time);
  227. if (rc)
  228. return rc;
  229. /* don't allow setting alarm in the past */
  230. now = __raw_readl(imxdi->ioaddr + DTCMR);
  231. if (alarm_time < now)
  232. return -EINVAL;
  233. /* write the new alarm time */
  234. rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
  235. if (rc)
  236. return rc;
  237. if (alarm->enabled)
  238. di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
  239. else
  240. di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
  241. return 0;
  242. }
  243. static struct rtc_class_ops dryice_rtc_ops = {
  244. .read_time = dryice_rtc_read_time,
  245. .set_mmss = dryice_rtc_set_mmss,
  246. .alarm_irq_enable = dryice_rtc_alarm_irq_enable,
  247. .read_alarm = dryice_rtc_read_alarm,
  248. .set_alarm = dryice_rtc_set_alarm,
  249. };
  250. /*
  251. * dryice "normal" interrupt handler
  252. */
  253. static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
  254. {
  255. struct imxdi_dev *imxdi = dev_id;
  256. u32 dsr, dier;
  257. irqreturn_t rc = IRQ_NONE;
  258. dier = __raw_readl(imxdi->ioaddr + DIER);
  259. /* handle write complete and write error cases */
  260. if ((dier & DIER_WCIE)) {
  261. /*If the write wait queue is empty then there is no pending
  262. operations. It means the interrupt is for DryIce -Security.
  263. IRQ must be returned as none.*/
  264. if (list_empty_careful(&imxdi->write_wait.task_list))
  265. return rc;
  266. /* DSR_WCF clears itself on DSR read */
  267. dsr = __raw_readl(imxdi->ioaddr + DSR);
  268. if ((dsr & (DSR_WCF | DSR_WEF))) {
  269. /* mask the interrupt */
  270. di_int_disable(imxdi, DIER_WCIE);
  271. /* save the dsr value for the wait queue */
  272. imxdi->dsr |= dsr;
  273. wake_up_interruptible(&imxdi->write_wait);
  274. rc = IRQ_HANDLED;
  275. }
  276. }
  277. /* handle the alarm case */
  278. if ((dier & DIER_CAIE)) {
  279. /* DSR_WCF clears itself on DSR read */
  280. dsr = __raw_readl(imxdi->ioaddr + DSR);
  281. if (dsr & DSR_CAF) {
  282. /* mask the interrupt */
  283. di_int_disable(imxdi, DIER_CAIE);
  284. /* finish alarm in user context */
  285. schedule_work(&imxdi->work);
  286. rc = IRQ_HANDLED;
  287. }
  288. }
  289. return rc;
  290. }
  291. /*
  292. * post the alarm event from user context so it can sleep
  293. * on the write completion.
  294. */
  295. static void dryice_work(struct work_struct *work)
  296. {
  297. struct imxdi_dev *imxdi = container_of(work,
  298. struct imxdi_dev, work);
  299. /* dismiss the interrupt (ignore error) */
  300. di_write_wait(imxdi, DSR_CAF, DSR);
  301. /* pass the alarm event to the rtc framework. */
  302. rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
  303. }
  304. /*
  305. * probe for dryice rtc device
  306. */
  307. static int dryice_rtc_probe(struct platform_device *pdev)
  308. {
  309. struct resource *res;
  310. struct imxdi_dev *imxdi;
  311. int rc;
  312. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  313. if (!res)
  314. return -ENODEV;
  315. imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
  316. if (!imxdi)
  317. return -ENOMEM;
  318. imxdi->pdev = pdev;
  319. if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
  320. pdev->name))
  321. return -EBUSY;
  322. imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start,
  323. resource_size(res));
  324. if (imxdi->ioaddr == NULL)
  325. return -ENOMEM;
  326. spin_lock_init(&imxdi->irq_lock);
  327. imxdi->irq = platform_get_irq(pdev, 0);
  328. if (imxdi->irq < 0)
  329. return imxdi->irq;
  330. init_waitqueue_head(&imxdi->write_wait);
  331. INIT_WORK(&imxdi->work, dryice_work);
  332. mutex_init(&imxdi->write_mutex);
  333. imxdi->clk = clk_get(&pdev->dev, NULL);
  334. if (IS_ERR(imxdi->clk))
  335. return PTR_ERR(imxdi->clk);
  336. clk_enable(imxdi->clk);
  337. /*
  338. * Initialize dryice hardware
  339. */
  340. /* mask all interrupts */
  341. __raw_writel(0, imxdi->ioaddr + DIER);
  342. rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
  343. IRQF_SHARED, pdev->name, imxdi);
  344. if (rc) {
  345. dev_warn(&pdev->dev, "interrupt not available.\n");
  346. goto err;
  347. }
  348. /* put dryice into valid state */
  349. if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
  350. rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
  351. if (rc)
  352. goto err;
  353. }
  354. /* initialize alarm */
  355. rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
  356. if (rc)
  357. goto err;
  358. rc = di_write_wait(imxdi, 0, DCALR);
  359. if (rc)
  360. goto err;
  361. /* clear alarm flag */
  362. if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
  363. rc = di_write_wait(imxdi, DSR_CAF, DSR);
  364. if (rc)
  365. goto err;
  366. }
  367. /* the timer won't count if it has never been written to */
  368. if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
  369. rc = di_write_wait(imxdi, 0, DTCMR);
  370. if (rc)
  371. goto err;
  372. }
  373. /* start keeping time */
  374. if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
  375. rc = di_write_wait(imxdi,
  376. __raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
  377. DCR);
  378. if (rc)
  379. goto err;
  380. }
  381. platform_set_drvdata(pdev, imxdi);
  382. imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev,
  383. &dryice_rtc_ops, THIS_MODULE);
  384. if (IS_ERR(imxdi->rtc)) {
  385. rc = PTR_ERR(imxdi->rtc);
  386. goto err;
  387. }
  388. return 0;
  389. err:
  390. clk_disable(imxdi->clk);
  391. clk_put(imxdi->clk);
  392. return rc;
  393. }
  394. static int __devexit dryice_rtc_remove(struct platform_device *pdev)
  395. {
  396. struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
  397. flush_work(&imxdi->work);
  398. /* mask all interrupts */
  399. __raw_writel(0, imxdi->ioaddr + DIER);
  400. rtc_device_unregister(imxdi->rtc);
  401. clk_disable(imxdi->clk);
  402. clk_put(imxdi->clk);
  403. return 0;
  404. }
  405. static struct platform_driver dryice_rtc_driver = {
  406. .driver = {
  407. .name = "imxdi_rtc",
  408. .owner = THIS_MODULE,
  409. },
  410. .remove = __devexit_p(dryice_rtc_remove),
  411. };
  412. static int __init dryice_rtc_init(void)
  413. {
  414. return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe);
  415. }
  416. static void __exit dryice_rtc_exit(void)
  417. {
  418. platform_driver_unregister(&dryice_rtc_driver);
  419. }
  420. module_init(dryice_rtc_init);
  421. module_exit(dryice_rtc_exit);
  422. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  423. MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
  424. MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
  425. MODULE_LICENSE("GPL");