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/drivers/clocksource/hyperv_timer.c

https://gitlab.com/deepcypher/linux
C | 568 lines | 330 code | 77 blank | 161 comment | 31 complexity | 2ad2ce827882db920d6d993055f4d750 MD5 | raw file
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Clocksource driver for the synthetic counter and timers
  4. * provided by the Hyper-V hypervisor to guest VMs, as described
  5. * in the Hyper-V Top Level Functional Spec (TLFS). This driver
  6. * is instruction set architecture independent.
  7. *
  8. * Copyright (C) 2019, Microsoft, Inc.
  9. *
  10. * Author: Michael Kelley <mikelley@microsoft.com>
  11. */
  12. #include <linux/percpu.h>
  13. #include <linux/cpumask.h>
  14. #include <linux/clockchips.h>
  15. #include <linux/clocksource.h>
  16. #include <linux/sched_clock.h>
  17. #include <linux/mm.h>
  18. #include <linux/cpuhotplug.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/irq.h>
  21. #include <linux/acpi.h>
  22. #include <clocksource/hyperv_timer.h>
  23. #include <asm/hyperv-tlfs.h>
  24. #include <asm/mshyperv.h>
  25. static struct clock_event_device __percpu *hv_clock_event;
  26. static u64 hv_sched_clock_offset __ro_after_init;
  27. /*
  28. * If false, we're using the old mechanism for stimer0 interrupts
  29. * where it sends a VMbus message when it expires. The old
  30. * mechanism is used when running on older versions of Hyper-V
  31. * that don't support Direct Mode. While Hyper-V provides
  32. * four stimer's per CPU, Linux uses only stimer0.
  33. *
  34. * Because Direct Mode does not require processing a VMbus
  35. * message, stimer interrupts can be enabled earlier in the
  36. * process of booting a CPU, and consistent with when timer
  37. * interrupts are enabled for other clocksource drivers.
  38. * However, for legacy versions of Hyper-V when Direct Mode
  39. * is not enabled, setting up stimer interrupts must be
  40. * delayed until VMbus is initialized and can process the
  41. * interrupt message.
  42. */
  43. static bool direct_mode_enabled;
  44. static int stimer0_irq = -1;
  45. static int stimer0_message_sint;
  46. static DEFINE_PER_CPU(long, stimer0_evt);
  47. /*
  48. * Common code for stimer0 interrupts coming via Direct Mode or
  49. * as a VMbus message.
  50. */
  51. void hv_stimer0_isr(void)
  52. {
  53. struct clock_event_device *ce;
  54. ce = this_cpu_ptr(hv_clock_event);
  55. ce->event_handler(ce);
  56. }
  57. EXPORT_SYMBOL_GPL(hv_stimer0_isr);
  58. /*
  59. * stimer0 interrupt handler for architectures that support
  60. * per-cpu interrupts, which also implies Direct Mode.
  61. */
  62. static irqreturn_t hv_stimer0_percpu_isr(int irq, void *dev_id)
  63. {
  64. hv_stimer0_isr();
  65. return IRQ_HANDLED;
  66. }
  67. static int hv_ce_set_next_event(unsigned long delta,
  68. struct clock_event_device *evt)
  69. {
  70. u64 current_tick;
  71. current_tick = hv_read_reference_counter();
  72. current_tick += delta;
  73. hv_set_register(HV_REGISTER_STIMER0_COUNT, current_tick);
  74. return 0;
  75. }
  76. static int hv_ce_shutdown(struct clock_event_device *evt)
  77. {
  78. hv_set_register(HV_REGISTER_STIMER0_COUNT, 0);
  79. hv_set_register(HV_REGISTER_STIMER0_CONFIG, 0);
  80. if (direct_mode_enabled && stimer0_irq >= 0)
  81. disable_percpu_irq(stimer0_irq);
  82. return 0;
  83. }
  84. static int hv_ce_set_oneshot(struct clock_event_device *evt)
  85. {
  86. union hv_stimer_config timer_cfg;
  87. timer_cfg.as_uint64 = 0;
  88. timer_cfg.enable = 1;
  89. timer_cfg.auto_enable = 1;
  90. if (direct_mode_enabled) {
  91. /*
  92. * When it expires, the timer will directly interrupt
  93. * on the specified hardware vector/IRQ.
  94. */
  95. timer_cfg.direct_mode = 1;
  96. timer_cfg.apic_vector = HYPERV_STIMER0_VECTOR;
  97. if (stimer0_irq >= 0)
  98. enable_percpu_irq(stimer0_irq, IRQ_TYPE_NONE);
  99. } else {
  100. /*
  101. * When it expires, the timer will generate a VMbus message,
  102. * to be handled by the normal VMbus interrupt handler.
  103. */
  104. timer_cfg.direct_mode = 0;
  105. timer_cfg.sintx = stimer0_message_sint;
  106. }
  107. hv_set_register(HV_REGISTER_STIMER0_CONFIG, timer_cfg.as_uint64);
  108. return 0;
  109. }
  110. /*
  111. * hv_stimer_init - Per-cpu initialization of the clockevent
  112. */
  113. static int hv_stimer_init(unsigned int cpu)
  114. {
  115. struct clock_event_device *ce;
  116. if (!hv_clock_event)
  117. return 0;
  118. ce = per_cpu_ptr(hv_clock_event, cpu);
  119. ce->name = "Hyper-V clockevent";
  120. ce->features = CLOCK_EVT_FEAT_ONESHOT;
  121. ce->cpumask = cpumask_of(cpu);
  122. ce->rating = 1000;
  123. ce->set_state_shutdown = hv_ce_shutdown;
  124. ce->set_state_oneshot = hv_ce_set_oneshot;
  125. ce->set_next_event = hv_ce_set_next_event;
  126. clockevents_config_and_register(ce,
  127. HV_CLOCK_HZ,
  128. HV_MIN_DELTA_TICKS,
  129. HV_MAX_MAX_DELTA_TICKS);
  130. return 0;
  131. }
  132. /*
  133. * hv_stimer_cleanup - Per-cpu cleanup of the clockevent
  134. */
  135. int hv_stimer_cleanup(unsigned int cpu)
  136. {
  137. struct clock_event_device *ce;
  138. if (!hv_clock_event)
  139. return 0;
  140. /*
  141. * In the legacy case where Direct Mode is not enabled
  142. * (which can only be on x86/64), stimer cleanup happens
  143. * relatively early in the CPU offlining process. We
  144. * must unbind the stimer-based clockevent device so
  145. * that the LAPIC timer can take over until clockevents
  146. * are no longer needed in the offlining process. Note
  147. * that clockevents_unbind_device() eventually calls
  148. * hv_ce_shutdown().
  149. *
  150. * The unbind should not be done when Direct Mode is
  151. * enabled because we may be on an architecture where
  152. * there are no other clockevent devices to fallback to.
  153. */
  154. ce = per_cpu_ptr(hv_clock_event, cpu);
  155. if (direct_mode_enabled)
  156. hv_ce_shutdown(ce);
  157. else
  158. clockevents_unbind_device(ce, cpu);
  159. return 0;
  160. }
  161. EXPORT_SYMBOL_GPL(hv_stimer_cleanup);
  162. /*
  163. * These placeholders are overridden by arch specific code on
  164. * architectures that need special setup of the stimer0 IRQ because
  165. * they don't support per-cpu IRQs (such as x86/x64).
  166. */
  167. void __weak hv_setup_stimer0_handler(void (*handler)(void))
  168. {
  169. };
  170. void __weak hv_remove_stimer0_handler(void)
  171. {
  172. };
  173. /* Called only on architectures with per-cpu IRQs (i.e., not x86/x64) */
  174. static int hv_setup_stimer0_irq(void)
  175. {
  176. int ret;
  177. ret = acpi_register_gsi(NULL, HYPERV_STIMER0_VECTOR,
  178. ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_HIGH);
  179. if (ret < 0) {
  180. pr_err("Can't register Hyper-V stimer0 GSI. Error %d", ret);
  181. return ret;
  182. }
  183. stimer0_irq = ret;
  184. ret = request_percpu_irq(stimer0_irq, hv_stimer0_percpu_isr,
  185. "Hyper-V stimer0", &stimer0_evt);
  186. if (ret) {
  187. pr_err("Can't request Hyper-V stimer0 IRQ %d. Error %d",
  188. stimer0_irq, ret);
  189. acpi_unregister_gsi(stimer0_irq);
  190. stimer0_irq = -1;
  191. }
  192. return ret;
  193. }
  194. static void hv_remove_stimer0_irq(void)
  195. {
  196. if (stimer0_irq == -1) {
  197. hv_remove_stimer0_handler();
  198. } else {
  199. free_percpu_irq(stimer0_irq, &stimer0_evt);
  200. acpi_unregister_gsi(stimer0_irq);
  201. stimer0_irq = -1;
  202. }
  203. }
  204. /* hv_stimer_alloc - Global initialization of the clockevent and stimer0 */
  205. int hv_stimer_alloc(bool have_percpu_irqs)
  206. {
  207. int ret;
  208. /*
  209. * Synthetic timers are always available except on old versions of
  210. * Hyper-V on x86. In that case, return as error as Linux will use a
  211. * clockevent based on emulated LAPIC timer hardware.
  212. */
  213. if (!(ms_hyperv.features & HV_MSR_SYNTIMER_AVAILABLE))
  214. return -EINVAL;
  215. hv_clock_event = alloc_percpu(struct clock_event_device);
  216. if (!hv_clock_event)
  217. return -ENOMEM;
  218. direct_mode_enabled = ms_hyperv.misc_features &
  219. HV_STIMER_DIRECT_MODE_AVAILABLE;
  220. /*
  221. * If Direct Mode isn't enabled, the remainder of the initialization
  222. * is done later by hv_stimer_legacy_init()
  223. */
  224. if (!direct_mode_enabled)
  225. return 0;
  226. if (have_percpu_irqs) {
  227. ret = hv_setup_stimer0_irq();
  228. if (ret)
  229. goto free_clock_event;
  230. } else {
  231. hv_setup_stimer0_handler(hv_stimer0_isr);
  232. }
  233. /*
  234. * Since we are in Direct Mode, stimer initialization
  235. * can be done now with a CPUHP value in the same range
  236. * as other clockevent devices.
  237. */
  238. ret = cpuhp_setup_state(CPUHP_AP_HYPERV_TIMER_STARTING,
  239. "clockevents/hyperv/stimer:starting",
  240. hv_stimer_init, hv_stimer_cleanup);
  241. if (ret < 0) {
  242. hv_remove_stimer0_irq();
  243. goto free_clock_event;
  244. }
  245. return ret;
  246. free_clock_event:
  247. free_percpu(hv_clock_event);
  248. hv_clock_event = NULL;
  249. return ret;
  250. }
  251. EXPORT_SYMBOL_GPL(hv_stimer_alloc);
  252. /*
  253. * hv_stimer_legacy_init -- Called from the VMbus driver to handle
  254. * the case when Direct Mode is not enabled, and the stimer
  255. * must be initialized late in the CPU onlining process.
  256. *
  257. */
  258. void hv_stimer_legacy_init(unsigned int cpu, int sint)
  259. {
  260. if (direct_mode_enabled)
  261. return;
  262. /*
  263. * This function gets called by each vCPU, so setting the
  264. * global stimer_message_sint value each time is conceptually
  265. * not ideal, but the value passed in is always the same and
  266. * it avoids introducing yet another interface into this
  267. * clocksource driver just to set the sint in the legacy case.
  268. */
  269. stimer0_message_sint = sint;
  270. (void)hv_stimer_init(cpu);
  271. }
  272. EXPORT_SYMBOL_GPL(hv_stimer_legacy_init);
  273. /*
  274. * hv_stimer_legacy_cleanup -- Called from the VMbus driver to
  275. * handle the case when Direct Mode is not enabled, and the
  276. * stimer must be cleaned up early in the CPU offlining
  277. * process.
  278. */
  279. void hv_stimer_legacy_cleanup(unsigned int cpu)
  280. {
  281. if (direct_mode_enabled)
  282. return;
  283. (void)hv_stimer_cleanup(cpu);
  284. }
  285. EXPORT_SYMBOL_GPL(hv_stimer_legacy_cleanup);
  286. /*
  287. * Do a global cleanup of clockevents for the cases of kexec and
  288. * vmbus exit
  289. */
  290. void hv_stimer_global_cleanup(void)
  291. {
  292. int cpu;
  293. /*
  294. * hv_stime_legacy_cleanup() will stop the stimer if Direct
  295. * Mode is not enabled, and fallback to the LAPIC timer.
  296. */
  297. for_each_present_cpu(cpu) {
  298. hv_stimer_legacy_cleanup(cpu);
  299. }
  300. if (!hv_clock_event)
  301. return;
  302. if (direct_mode_enabled) {
  303. cpuhp_remove_state(CPUHP_AP_HYPERV_TIMER_STARTING);
  304. hv_remove_stimer0_irq();
  305. stimer0_irq = -1;
  306. }
  307. free_percpu(hv_clock_event);
  308. hv_clock_event = NULL;
  309. }
  310. EXPORT_SYMBOL_GPL(hv_stimer_global_cleanup);
  311. /*
  312. * Code and definitions for the Hyper-V clocksources. Two
  313. * clocksources are defined: one that reads the Hyper-V defined MSR, and
  314. * the other that uses the TSC reference page feature as defined in the
  315. * TLFS. The MSR version is for compatibility with old versions of
  316. * Hyper-V and 32-bit x86. The TSC reference page version is preferred.
  317. */
  318. static union {
  319. struct ms_hyperv_tsc_page page;
  320. u8 reserved[PAGE_SIZE];
  321. } tsc_pg __aligned(PAGE_SIZE);
  322. struct ms_hyperv_tsc_page *hv_get_tsc_page(void)
  323. {
  324. return &tsc_pg.page;
  325. }
  326. EXPORT_SYMBOL_GPL(hv_get_tsc_page);
  327. static u64 notrace read_hv_clock_tsc(void)
  328. {
  329. u64 current_tick = hv_read_tsc_page(hv_get_tsc_page());
  330. if (current_tick == U64_MAX)
  331. current_tick = hv_get_register(HV_REGISTER_TIME_REF_COUNT);
  332. return current_tick;
  333. }
  334. static u64 notrace read_hv_clock_tsc_cs(struct clocksource *arg)
  335. {
  336. return read_hv_clock_tsc();
  337. }
  338. static u64 notrace read_hv_sched_clock_tsc(void)
  339. {
  340. return (read_hv_clock_tsc() - hv_sched_clock_offset) *
  341. (NSEC_PER_SEC / HV_CLOCK_HZ);
  342. }
  343. static void suspend_hv_clock_tsc(struct clocksource *arg)
  344. {
  345. u64 tsc_msr;
  346. /* Disable the TSC page */
  347. tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
  348. tsc_msr &= ~BIT_ULL(0);
  349. hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
  350. }
  351. static void resume_hv_clock_tsc(struct clocksource *arg)
  352. {
  353. phys_addr_t phys_addr = virt_to_phys(&tsc_pg);
  354. u64 tsc_msr;
  355. /* Re-enable the TSC page */
  356. tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
  357. tsc_msr &= GENMASK_ULL(11, 0);
  358. tsc_msr |= BIT_ULL(0) | (u64)phys_addr;
  359. hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
  360. }
  361. #ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK
  362. static int hv_cs_enable(struct clocksource *cs)
  363. {
  364. vclocks_set_used(VDSO_CLOCKMODE_HVCLOCK);
  365. return 0;
  366. }
  367. #endif
  368. static struct clocksource hyperv_cs_tsc = {
  369. .name = "hyperv_clocksource_tsc_page",
  370. .rating = 500,
  371. .read = read_hv_clock_tsc_cs,
  372. .mask = CLOCKSOURCE_MASK(64),
  373. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  374. .suspend= suspend_hv_clock_tsc,
  375. .resume = resume_hv_clock_tsc,
  376. #ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK
  377. .enable = hv_cs_enable,
  378. .vdso_clock_mode = VDSO_CLOCKMODE_HVCLOCK,
  379. #else
  380. .vdso_clock_mode = VDSO_CLOCKMODE_NONE,
  381. #endif
  382. };
  383. static u64 notrace read_hv_clock_msr(void)
  384. {
  385. /*
  386. * Read the partition counter to get the current tick count. This count
  387. * is set to 0 when the partition is created and is incremented in
  388. * 100 nanosecond units.
  389. */
  390. return hv_get_register(HV_REGISTER_TIME_REF_COUNT);
  391. }
  392. static u64 notrace read_hv_clock_msr_cs(struct clocksource *arg)
  393. {
  394. return read_hv_clock_msr();
  395. }
  396. static u64 notrace read_hv_sched_clock_msr(void)
  397. {
  398. return (read_hv_clock_msr() - hv_sched_clock_offset) *
  399. (NSEC_PER_SEC / HV_CLOCK_HZ);
  400. }
  401. static struct clocksource hyperv_cs_msr = {
  402. .name = "hyperv_clocksource_msr",
  403. .rating = 500,
  404. .read = read_hv_clock_msr_cs,
  405. .mask = CLOCKSOURCE_MASK(64),
  406. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  407. };
  408. /*
  409. * Reference to pv_ops must be inline so objtool
  410. * detection of noinstr violations can work correctly.
  411. */
  412. #ifdef CONFIG_GENERIC_SCHED_CLOCK
  413. static __always_inline void hv_setup_sched_clock(void *sched_clock)
  414. {
  415. /*
  416. * We're on an architecture with generic sched clock (not x86/x64).
  417. * The Hyper-V sched clock read function returns nanoseconds, not
  418. * the normal 100ns units of the Hyper-V synthetic clock.
  419. */
  420. sched_clock_register(sched_clock, 64, NSEC_PER_SEC);
  421. }
  422. #elif defined CONFIG_PARAVIRT
  423. static __always_inline void hv_setup_sched_clock(void *sched_clock)
  424. {
  425. /* We're on x86/x64 *and* using PV ops */
  426. paravirt_set_sched_clock(sched_clock);
  427. }
  428. #else /* !CONFIG_GENERIC_SCHED_CLOCK && !CONFIG_PARAVIRT */
  429. static __always_inline void hv_setup_sched_clock(void *sched_clock) {}
  430. #endif /* CONFIG_GENERIC_SCHED_CLOCK */
  431. static bool __init hv_init_tsc_clocksource(void)
  432. {
  433. u64 tsc_msr;
  434. phys_addr_t phys_addr;
  435. if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE))
  436. return false;
  437. if (hv_root_partition)
  438. return false;
  439. /*
  440. * If Hyper-V offers TSC_INVARIANT, then the virtualized TSC correctly
  441. * handles frequency and offset changes due to live migration,
  442. * pause/resume, and other VM management operations. So lower the
  443. * Hyper-V Reference TSC rating, causing the generic TSC to be used.
  444. * TSC_INVARIANT is not offered on ARM64, so the Hyper-V Reference
  445. * TSC will be preferred over the virtualized ARM64 arch counter.
  446. * While the Hyper-V MSR clocksource won't be used since the
  447. * Reference TSC clocksource is present, change its rating as
  448. * well for consistency.
  449. */
  450. if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
  451. hyperv_cs_tsc.rating = 250;
  452. hyperv_cs_msr.rating = 250;
  453. }
  454. hv_read_reference_counter = read_hv_clock_tsc;
  455. phys_addr = virt_to_phys(hv_get_tsc_page());
  456. /*
  457. * The Hyper-V TLFS specifies to preserve the value of reserved
  458. * bits in registers. So read the existing value, preserve the
  459. * low order 12 bits, and add in the guest physical address
  460. * (which already has at least the low 12 bits set to zero since
  461. * it is page aligned). Also set the "enable" bit, which is bit 0.
  462. */
  463. tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
  464. tsc_msr &= GENMASK_ULL(11, 0);
  465. tsc_msr = tsc_msr | 0x1 | (u64)phys_addr;
  466. hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
  467. clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100);
  468. hv_sched_clock_offset = hv_read_reference_counter();
  469. hv_setup_sched_clock(read_hv_sched_clock_tsc);
  470. return true;
  471. }
  472. void __init hv_init_clocksource(void)
  473. {
  474. /*
  475. * Try to set up the TSC page clocksource. If it succeeds, we're
  476. * done. Otherwise, set up the MSR clocksource. At least one of
  477. * these will always be available except on very old versions of
  478. * Hyper-V on x86. In that case we won't have a Hyper-V
  479. * clocksource, but Linux will still run with a clocksource based
  480. * on the emulated PIT or LAPIC timer.
  481. */
  482. if (hv_init_tsc_clocksource())
  483. return;
  484. if (!(ms_hyperv.features & HV_MSR_TIME_REF_COUNT_AVAILABLE))
  485. return;
  486. hv_read_reference_counter = read_hv_clock_msr;
  487. clocksource_register_hz(&hyperv_cs_msr, NSEC_PER_SEC/100);
  488. hv_sched_clock_offset = hv_read_reference_counter();
  489. hv_setup_sched_clock(read_hv_sched_clock_msr);
  490. }
  491. EXPORT_SYMBOL_GPL(hv_init_clocksource);