PageRenderTime 123ms CodeModel.GetById 21ms RepoModel.GetById 2ms app.codeStats 2ms

/drivers/edac/dmc520_edac.c

https://gitlab.com/deepcypher/linux
C | 656 lines | 504 code | 114 blank | 38 comment | 40 complexity | 168b6de0a43f89ba4d5dc7afd8ac9fe4 MD5 | raw file
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * EDAC driver for DMC-520 memory controller.
  4. *
  5. * The driver supports 10 interrupt lines,
  6. * though only dram_ecc_errc and dram_ecc_errd are currently handled.
  7. *
  8. * Authors: Rui Zhao <ruizhao@microsoft.com>
  9. * Lei Wang <lewan@microsoft.com>
  10. * Shiping Ji <shji@microsoft.com>
  11. */
  12. #include <linux/bitfield.h>
  13. #include <linux/edac.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <linux/spinlock.h>
  21. #include "edac_mc.h"
  22. /* DMC-520 registers */
  23. #define REG_OFFSET_FEATURE_CONFIG 0x130
  24. #define REG_OFFSET_ECC_ERRC_COUNT_31_00 0x158
  25. #define REG_OFFSET_ECC_ERRC_COUNT_63_32 0x15C
  26. #define REG_OFFSET_ECC_ERRD_COUNT_31_00 0x160
  27. #define REG_OFFSET_ECC_ERRD_COUNT_63_32 0x164
  28. #define REG_OFFSET_INTERRUPT_CONTROL 0x500
  29. #define REG_OFFSET_INTERRUPT_CLR 0x508
  30. #define REG_OFFSET_INTERRUPT_STATUS 0x510
  31. #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00 0x528
  32. #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32 0x52C
  33. #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00 0x530
  34. #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32 0x534
  35. #define REG_OFFSET_ADDRESS_CONTROL_NOW 0x1010
  36. #define REG_OFFSET_MEMORY_TYPE_NOW 0x1128
  37. #define REG_OFFSET_SCRUB_CONTROL0_NOW 0x1170
  38. #define REG_OFFSET_FORMAT_CONTROL 0x18
  39. /* DMC-520 types, masks and bitfields */
  40. #define RAM_ECC_INT_CE_BIT BIT(0)
  41. #define RAM_ECC_INT_UE_BIT BIT(1)
  42. #define DRAM_ECC_INT_CE_BIT BIT(2)
  43. #define DRAM_ECC_INT_UE_BIT BIT(3)
  44. #define FAILED_ACCESS_INT_BIT BIT(4)
  45. #define FAILED_PROG_INT_BIT BIT(5)
  46. #define LINK_ERR_INT_BIT BIT(6)
  47. #define TEMPERATURE_EVENT_INT_BIT BIT(7)
  48. #define ARCH_FSM_INT_BIT BIT(8)
  49. #define PHY_REQUEST_INT_BIT BIT(9)
  50. #define MEMORY_WIDTH_MASK GENMASK(1, 0)
  51. #define SCRUB_TRIGGER0_NEXT_MASK GENMASK(1, 0)
  52. #define REG_FIELD_DRAM_ECC_ENABLED GENMASK(1, 0)
  53. #define REG_FIELD_MEMORY_TYPE GENMASK(2, 0)
  54. #define REG_FIELD_DEVICE_WIDTH GENMASK(9, 8)
  55. #define REG_FIELD_ADDRESS_CONTROL_COL GENMASK(2, 0)
  56. #define REG_FIELD_ADDRESS_CONTROL_ROW GENMASK(10, 8)
  57. #define REG_FIELD_ADDRESS_CONTROL_BANK GENMASK(18, 16)
  58. #define REG_FIELD_ADDRESS_CONTROL_RANK GENMASK(25, 24)
  59. #define REG_FIELD_ERR_INFO_LOW_VALID BIT(0)
  60. #define REG_FIELD_ERR_INFO_LOW_COL GENMASK(10, 1)
  61. #define REG_FIELD_ERR_INFO_LOW_ROW GENMASK(28, 11)
  62. #define REG_FIELD_ERR_INFO_LOW_RANK GENMASK(31, 29)
  63. #define REG_FIELD_ERR_INFO_HIGH_BANK GENMASK(3, 0)
  64. #define REG_FIELD_ERR_INFO_HIGH_VALID BIT(31)
  65. #define DRAM_ADDRESS_CONTROL_MIN_COL_BITS 8
  66. #define DRAM_ADDRESS_CONTROL_MIN_ROW_BITS 11
  67. #define DMC520_SCRUB_TRIGGER_ERR_DETECT 2
  68. #define DMC520_SCRUB_TRIGGER_IDLE 3
  69. /* Driver settings */
  70. /*
  71. * The max-length message would be: "rank:7 bank:15 row:262143 col:1023".
  72. * Max length is 34. Using a 40-size buffer is enough.
  73. */
  74. #define DMC520_MSG_BUF_SIZE 40
  75. #define EDAC_MOD_NAME "dmc520-edac"
  76. #define EDAC_CTL_NAME "dmc520"
  77. /* the data bus width for the attached memory chips. */
  78. enum dmc520_mem_width {
  79. MEM_WIDTH_X32 = 2,
  80. MEM_WIDTH_X64 = 3
  81. };
  82. /* memory type */
  83. enum dmc520_mem_type {
  84. MEM_TYPE_DDR3 = 1,
  85. MEM_TYPE_DDR4 = 2
  86. };
  87. /* memory device width */
  88. enum dmc520_dev_width {
  89. DEV_WIDTH_X4 = 0,
  90. DEV_WIDTH_X8 = 1,
  91. DEV_WIDTH_X16 = 2
  92. };
  93. struct ecc_error_info {
  94. u32 col;
  95. u32 row;
  96. u32 bank;
  97. u32 rank;
  98. };
  99. /* The interrupt config */
  100. struct dmc520_irq_config {
  101. char *name;
  102. int mask;
  103. };
  104. /* The interrupt mappings */
  105. static struct dmc520_irq_config dmc520_irq_configs[] = {
  106. {
  107. .name = "ram_ecc_errc",
  108. .mask = RAM_ECC_INT_CE_BIT
  109. },
  110. {
  111. .name = "ram_ecc_errd",
  112. .mask = RAM_ECC_INT_UE_BIT
  113. },
  114. {
  115. .name = "dram_ecc_errc",
  116. .mask = DRAM_ECC_INT_CE_BIT
  117. },
  118. {
  119. .name = "dram_ecc_errd",
  120. .mask = DRAM_ECC_INT_UE_BIT
  121. },
  122. {
  123. .name = "failed_access",
  124. .mask = FAILED_ACCESS_INT_BIT
  125. },
  126. {
  127. .name = "failed_prog",
  128. .mask = FAILED_PROG_INT_BIT
  129. },
  130. {
  131. .name = "link_err",
  132. .mask = LINK_ERR_INT_BIT
  133. },
  134. {
  135. .name = "temperature_event",
  136. .mask = TEMPERATURE_EVENT_INT_BIT
  137. },
  138. {
  139. .name = "arch_fsm",
  140. .mask = ARCH_FSM_INT_BIT
  141. },
  142. {
  143. .name = "phy_request",
  144. .mask = PHY_REQUEST_INT_BIT
  145. }
  146. };
  147. #define NUMBER_OF_IRQS ARRAY_SIZE(dmc520_irq_configs)
  148. /*
  149. * The EDAC driver private data.
  150. * error_lock is to protect concurrent writes to the mci->error_desc through
  151. * edac_mc_handle_error().
  152. */
  153. struct dmc520_edac {
  154. void __iomem *reg_base;
  155. spinlock_t error_lock;
  156. u32 mem_width_in_bytes;
  157. int irqs[NUMBER_OF_IRQS];
  158. int masks[NUMBER_OF_IRQS];
  159. };
  160. static int dmc520_mc_idx;
  161. static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset)
  162. {
  163. return readl(pvt->reg_base + offset);
  164. }
  165. static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset)
  166. {
  167. writel(val, pvt->reg_base + offset);
  168. }
  169. static u32 dmc520_calc_dram_ecc_error(u32 value)
  170. {
  171. u32 total = 0;
  172. /* Each rank's error counter takes one byte. */
  173. while (value > 0) {
  174. total += (value & 0xFF);
  175. value >>= 8;
  176. }
  177. return total;
  178. }
  179. static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt,
  180. bool is_ce)
  181. {
  182. u32 reg_offset_low, reg_offset_high;
  183. u32 err_low, err_high;
  184. u32 err_count;
  185. reg_offset_low = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_31_00 :
  186. REG_OFFSET_ECC_ERRD_COUNT_31_00;
  187. reg_offset_high = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_63_32 :
  188. REG_OFFSET_ECC_ERRD_COUNT_63_32;
  189. err_low = dmc520_read_reg(pvt, reg_offset_low);
  190. err_high = dmc520_read_reg(pvt, reg_offset_high);
  191. /* Reset error counters */
  192. dmc520_write_reg(pvt, 0, reg_offset_low);
  193. dmc520_write_reg(pvt, 0, reg_offset_high);
  194. err_count = dmc520_calc_dram_ecc_error(err_low) +
  195. dmc520_calc_dram_ecc_error(err_high);
  196. return err_count;
  197. }
  198. static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt,
  199. bool is_ce,
  200. struct ecc_error_info *info)
  201. {
  202. u32 reg_offset_low, reg_offset_high;
  203. u32 reg_val_low, reg_val_high;
  204. bool valid;
  205. reg_offset_low = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00 :
  206. REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00;
  207. reg_offset_high = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32 :
  208. REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32;
  209. reg_val_low = dmc520_read_reg(pvt, reg_offset_low);
  210. reg_val_high = dmc520_read_reg(pvt, reg_offset_high);
  211. valid = (FIELD_GET(REG_FIELD_ERR_INFO_LOW_VALID, reg_val_low) != 0) &&
  212. (FIELD_GET(REG_FIELD_ERR_INFO_HIGH_VALID, reg_val_high) != 0);
  213. if (valid) {
  214. info->col = FIELD_GET(REG_FIELD_ERR_INFO_LOW_COL, reg_val_low);
  215. info->row = FIELD_GET(REG_FIELD_ERR_INFO_LOW_ROW, reg_val_low);
  216. info->rank = FIELD_GET(REG_FIELD_ERR_INFO_LOW_RANK, reg_val_low);
  217. info->bank = FIELD_GET(REG_FIELD_ERR_INFO_HIGH_BANK, reg_val_high);
  218. } else {
  219. memset(info, 0, sizeof(*info));
  220. }
  221. }
  222. static bool dmc520_is_ecc_enabled(void __iomem *reg_base)
  223. {
  224. u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG);
  225. return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val);
  226. }
  227. static enum scrub_type dmc520_get_scrub_type(struct dmc520_edac *pvt)
  228. {
  229. enum scrub_type type = SCRUB_NONE;
  230. u32 reg_val, scrub_cfg;
  231. reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW);
  232. scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val);
  233. if (scrub_cfg == DMC520_SCRUB_TRIGGER_ERR_DETECT ||
  234. scrub_cfg == DMC520_SCRUB_TRIGGER_IDLE)
  235. type = SCRUB_HW_PROG;
  236. return type;
  237. }
  238. /* Get the memory data bus width, in number of bytes. */
  239. static u32 dmc520_get_memory_width(struct dmc520_edac *pvt)
  240. {
  241. enum dmc520_mem_width mem_width_field;
  242. u32 mem_width_in_bytes = 0;
  243. u32 reg_val;
  244. reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL);
  245. mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val);
  246. if (mem_width_field == MEM_WIDTH_X32)
  247. mem_width_in_bytes = 4;
  248. else if (mem_width_field == MEM_WIDTH_X64)
  249. mem_width_in_bytes = 8;
  250. return mem_width_in_bytes;
  251. }
  252. static enum mem_type dmc520_get_mtype(struct dmc520_edac *pvt)
  253. {
  254. enum mem_type mt = MEM_UNKNOWN;
  255. enum dmc520_mem_type type;
  256. u32 reg_val;
  257. reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
  258. type = FIELD_GET(REG_FIELD_MEMORY_TYPE, reg_val);
  259. switch (type) {
  260. case MEM_TYPE_DDR3:
  261. mt = MEM_DDR3;
  262. break;
  263. case MEM_TYPE_DDR4:
  264. mt = MEM_DDR4;
  265. break;
  266. }
  267. return mt;
  268. }
  269. static enum dev_type dmc520_get_dtype(struct dmc520_edac *pvt)
  270. {
  271. enum dmc520_dev_width device_width;
  272. enum dev_type dt = DEV_UNKNOWN;
  273. u32 reg_val;
  274. reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
  275. device_width = FIELD_GET(REG_FIELD_DEVICE_WIDTH, reg_val);
  276. switch (device_width) {
  277. case DEV_WIDTH_X4:
  278. dt = DEV_X4;
  279. break;
  280. case DEV_WIDTH_X8:
  281. dt = DEV_X8;
  282. break;
  283. case DEV_WIDTH_X16:
  284. dt = DEV_X16;
  285. break;
  286. }
  287. return dt;
  288. }
  289. static u32 dmc520_get_rank_count(void __iomem *reg_base)
  290. {
  291. u32 reg_val, rank_bits;
  292. reg_val = readl(reg_base + REG_OFFSET_ADDRESS_CONTROL_NOW);
  293. rank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_RANK, reg_val);
  294. return BIT(rank_bits);
  295. }
  296. static u64 dmc520_get_rank_size(struct dmc520_edac *pvt)
  297. {
  298. u32 reg_val, col_bits, row_bits, bank_bits;
  299. reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW);
  300. col_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_COL, reg_val) +
  301. DRAM_ADDRESS_CONTROL_MIN_COL_BITS;
  302. row_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_ROW, reg_val) +
  303. DRAM_ADDRESS_CONTROL_MIN_ROW_BITS;
  304. bank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_BANK, reg_val);
  305. return (u64)pvt->mem_width_in_bytes << (col_bits + row_bits + bank_bits);
  306. }
  307. static void dmc520_handle_dram_ecc_errors(struct mem_ctl_info *mci,
  308. bool is_ce)
  309. {
  310. struct dmc520_edac *pvt = mci->pvt_info;
  311. char message[DMC520_MSG_BUF_SIZE];
  312. struct ecc_error_info info;
  313. u32 cnt;
  314. dmc520_get_dram_ecc_error_info(pvt, is_ce, &info);
  315. cnt = dmc520_get_dram_ecc_error_count(pvt, is_ce);
  316. if (!cnt)
  317. return;
  318. snprintf(message, ARRAY_SIZE(message),
  319. "rank:%d bank:%d row:%d col:%d",
  320. info.rank, info.bank,
  321. info.row, info.col);
  322. spin_lock(&pvt->error_lock);
  323. edac_mc_handle_error((is_ce ? HW_EVENT_ERR_CORRECTED :
  324. HW_EVENT_ERR_UNCORRECTED),
  325. mci, cnt, 0, 0, 0, info.rank, -1, -1,
  326. message, "");
  327. spin_unlock(&pvt->error_lock);
  328. }
  329. static irqreturn_t dmc520_edac_dram_ecc_isr(int irq, struct mem_ctl_info *mci,
  330. bool is_ce)
  331. {
  332. struct dmc520_edac *pvt = mci->pvt_info;
  333. u32 i_mask;
  334. i_mask = is_ce ? DRAM_ECC_INT_CE_BIT : DRAM_ECC_INT_UE_BIT;
  335. dmc520_handle_dram_ecc_errors(mci, is_ce);
  336. dmc520_write_reg(pvt, i_mask, REG_OFFSET_INTERRUPT_CLR);
  337. return IRQ_HANDLED;
  338. }
  339. static irqreturn_t dmc520_edac_dram_all_isr(int irq, struct mem_ctl_info *mci,
  340. u32 irq_mask)
  341. {
  342. struct dmc520_edac *pvt = mci->pvt_info;
  343. irqreturn_t irq_ret = IRQ_NONE;
  344. u32 status;
  345. status = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_STATUS);
  346. if ((irq_mask & DRAM_ECC_INT_CE_BIT) &&
  347. (status & DRAM_ECC_INT_CE_BIT))
  348. irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, true);
  349. if ((irq_mask & DRAM_ECC_INT_UE_BIT) &&
  350. (status & DRAM_ECC_INT_UE_BIT))
  351. irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, false);
  352. return irq_ret;
  353. }
  354. static irqreturn_t dmc520_isr(int irq, void *data)
  355. {
  356. struct mem_ctl_info *mci = data;
  357. struct dmc520_edac *pvt = mci->pvt_info;
  358. u32 mask = 0;
  359. int idx;
  360. for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
  361. if (pvt->irqs[idx] == irq) {
  362. mask = pvt->masks[idx];
  363. break;
  364. }
  365. }
  366. return dmc520_edac_dram_all_isr(irq, mci, mask);
  367. }
  368. static void dmc520_init_csrow(struct mem_ctl_info *mci)
  369. {
  370. struct dmc520_edac *pvt = mci->pvt_info;
  371. struct csrow_info *csi;
  372. struct dimm_info *dimm;
  373. u32 pages_per_rank;
  374. enum dev_type dt;
  375. enum mem_type mt;
  376. int row, ch;
  377. u64 rs;
  378. dt = dmc520_get_dtype(pvt);
  379. mt = dmc520_get_mtype(pvt);
  380. rs = dmc520_get_rank_size(pvt);
  381. pages_per_rank = rs >> PAGE_SHIFT;
  382. for (row = 0; row < mci->nr_csrows; row++) {
  383. csi = mci->csrows[row];
  384. for (ch = 0; ch < csi->nr_channels; ch++) {
  385. dimm = csi->channels[ch]->dimm;
  386. dimm->grain = pvt->mem_width_in_bytes;
  387. dimm->dtype = dt;
  388. dimm->mtype = mt;
  389. dimm->edac_mode = EDAC_SECDED;
  390. dimm->nr_pages = pages_per_rank / csi->nr_channels;
  391. }
  392. }
  393. }
  394. static int dmc520_edac_probe(struct platform_device *pdev)
  395. {
  396. bool registered[NUMBER_OF_IRQS] = { false };
  397. int irqs[NUMBER_OF_IRQS] = { -ENXIO };
  398. int masks[NUMBER_OF_IRQS] = { 0 };
  399. struct edac_mc_layer layers[1];
  400. struct dmc520_edac *pvt = NULL;
  401. struct mem_ctl_info *mci;
  402. void __iomem *reg_base;
  403. u32 irq_mask_all = 0;
  404. struct resource *res;
  405. struct device *dev;
  406. int ret, idx, irq;
  407. u32 reg_val;
  408. /* Parse the device node */
  409. dev = &pdev->dev;
  410. for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
  411. irq = platform_get_irq_byname_optional(pdev, dmc520_irq_configs[idx].name);
  412. irqs[idx] = irq;
  413. masks[idx] = dmc520_irq_configs[idx].mask;
  414. if (irq >= 0) {
  415. irq_mask_all |= dmc520_irq_configs[idx].mask;
  416. edac_dbg(0, "Discovered %s, irq: %d.\n", dmc520_irq_configs[idx].name, irq);
  417. }
  418. }
  419. if (!irq_mask_all) {
  420. edac_printk(KERN_ERR, EDAC_MOD_NAME,
  421. "At least one valid interrupt line is expected.\n");
  422. return -EINVAL;
  423. }
  424. /* Initialize dmc520 edac */
  425. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  426. reg_base = devm_ioremap_resource(dev, res);
  427. if (IS_ERR(reg_base))
  428. return PTR_ERR(reg_base);
  429. if (!dmc520_is_ecc_enabled(reg_base))
  430. return -ENXIO;
  431. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  432. layers[0].size = dmc520_get_rank_count(reg_base);
  433. layers[0].is_virt_csrow = true;
  434. mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt));
  435. if (!mci) {
  436. edac_printk(KERN_ERR, EDAC_MOD_NAME,
  437. "Failed to allocate memory for mc instance\n");
  438. ret = -ENOMEM;
  439. goto err;
  440. }
  441. pvt = mci->pvt_info;
  442. pvt->reg_base = reg_base;
  443. spin_lock_init(&pvt->error_lock);
  444. memcpy(pvt->irqs, irqs, sizeof(irqs));
  445. memcpy(pvt->masks, masks, sizeof(masks));
  446. platform_set_drvdata(pdev, mci);
  447. mci->pdev = dev;
  448. mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
  449. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
  450. mci->edac_cap = EDAC_FLAG_SECDED;
  451. mci->scrub_cap = SCRUB_FLAG_HW_SRC;
  452. mci->scrub_mode = dmc520_get_scrub_type(pvt);
  453. mci->ctl_name = EDAC_CTL_NAME;
  454. mci->dev_name = dev_name(mci->pdev);
  455. mci->mod_name = EDAC_MOD_NAME;
  456. edac_op_state = EDAC_OPSTATE_INT;
  457. pvt->mem_width_in_bytes = dmc520_get_memory_width(pvt);
  458. dmc520_init_csrow(mci);
  459. /* Clear interrupts, not affecting other unrelated interrupts */
  460. reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
  461. dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
  462. REG_OFFSET_INTERRUPT_CONTROL);
  463. dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR);
  464. for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
  465. irq = irqs[idx];
  466. if (irq >= 0) {
  467. ret = devm_request_irq(&pdev->dev, irq,
  468. dmc520_isr, IRQF_SHARED,
  469. dev_name(&pdev->dev), mci);
  470. if (ret < 0) {
  471. edac_printk(KERN_ERR, EDAC_MC,
  472. "Failed to request irq %d\n", irq);
  473. goto err;
  474. }
  475. registered[idx] = true;
  476. }
  477. }
  478. /* Reset DRAM CE/UE counters */
  479. if (irq_mask_all & DRAM_ECC_INT_CE_BIT)
  480. dmc520_get_dram_ecc_error_count(pvt, true);
  481. if (irq_mask_all & DRAM_ECC_INT_UE_BIT)
  482. dmc520_get_dram_ecc_error_count(pvt, false);
  483. ret = edac_mc_add_mc(mci);
  484. if (ret) {
  485. edac_printk(KERN_ERR, EDAC_MOD_NAME,
  486. "Failed to register with EDAC core\n");
  487. goto err;
  488. }
  489. /* Enable interrupts, not affecting other unrelated interrupts */
  490. dmc520_write_reg(pvt, reg_val | irq_mask_all,
  491. REG_OFFSET_INTERRUPT_CONTROL);
  492. return 0;
  493. err:
  494. for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
  495. if (registered[idx])
  496. devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);
  497. }
  498. if (mci)
  499. edac_mc_free(mci);
  500. return ret;
  501. }
  502. static int dmc520_edac_remove(struct platform_device *pdev)
  503. {
  504. u32 reg_val, idx, irq_mask_all = 0;
  505. struct mem_ctl_info *mci;
  506. struct dmc520_edac *pvt;
  507. mci = platform_get_drvdata(pdev);
  508. pvt = mci->pvt_info;
  509. /* Disable interrupts */
  510. reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
  511. dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
  512. REG_OFFSET_INTERRUPT_CONTROL);
  513. /* free irq's */
  514. for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
  515. if (pvt->irqs[idx] >= 0) {
  516. irq_mask_all |= pvt->masks[idx];
  517. devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);
  518. }
  519. }
  520. edac_mc_del_mc(&pdev->dev);
  521. edac_mc_free(mci);
  522. return 0;
  523. }
  524. static const struct of_device_id dmc520_edac_driver_id[] = {
  525. { .compatible = "arm,dmc-520", },
  526. { /* end of table */ }
  527. };
  528. MODULE_DEVICE_TABLE(of, dmc520_edac_driver_id);
  529. static struct platform_driver dmc520_edac_driver = {
  530. .driver = {
  531. .name = "dmc520",
  532. .of_match_table = dmc520_edac_driver_id,
  533. },
  534. .probe = dmc520_edac_probe,
  535. .remove = dmc520_edac_remove
  536. };
  537. module_platform_driver(dmc520_edac_driver);
  538. MODULE_AUTHOR("Rui Zhao <ruizhao@microsoft.com>");
  539. MODULE_AUTHOR("Lei Wang <lewan@microsoft.com>");
  540. MODULE_AUTHOR("Shiping Ji <shji@microsoft.com>");
  541. MODULE_DESCRIPTION("DMC-520 ECC driver");
  542. MODULE_LICENSE("GPL v2");