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/drivers/iommu/hyperv-iommu.c

https://gitlab.com/deepcypher/linux
C | 340 lines | 240 code | 69 blank | 31 comment | 41 complexity | 44fee15b06844a9d1070edaa5fbff61e MD5 | raw file
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Hyper-V stub IOMMU driver.
  4. *
  5. * Copyright (C) 2019, Microsoft, Inc.
  6. *
  7. * Author : Lan Tianyu <Tianyu.Lan@microsoft.com>
  8. */
  9. #include <linux/types.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/irq.h>
  12. #include <linux/iommu.h>
  13. #include <linux/module.h>
  14. #include <asm/apic.h>
  15. #include <asm/cpu.h>
  16. #include <asm/hw_irq.h>
  17. #include <asm/io_apic.h>
  18. #include <asm/irq_remapping.h>
  19. #include <asm/hypervisor.h>
  20. #include <asm/mshyperv.h>
  21. #include "irq_remapping.h"
  22. #ifdef CONFIG_IRQ_REMAP
  23. /*
  24. * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
  25. * Redirection Table. Hyper-V exposes one single IO-APIC and so define
  26. * 24 IO APIC remmapping entries.
  27. */
  28. #define IOAPIC_REMAPPING_ENTRY 24
  29. static cpumask_t ioapic_max_cpumask = { CPU_BITS_NONE };
  30. static struct irq_domain *ioapic_ir_domain;
  31. static int hyperv_ir_set_affinity(struct irq_data *data,
  32. const struct cpumask *mask, bool force)
  33. {
  34. struct irq_data *parent = data->parent_data;
  35. struct irq_cfg *cfg = irqd_cfg(data);
  36. int ret;
  37. /* Return error If new irq affinity is out of ioapic_max_cpumask. */
  38. if (!cpumask_subset(mask, &ioapic_max_cpumask))
  39. return -EINVAL;
  40. ret = parent->chip->irq_set_affinity(parent, mask, force);
  41. if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
  42. return ret;
  43. send_cleanup_vector(cfg);
  44. return 0;
  45. }
  46. static struct irq_chip hyperv_ir_chip = {
  47. .name = "HYPERV-IR",
  48. .irq_ack = apic_ack_irq,
  49. .irq_set_affinity = hyperv_ir_set_affinity,
  50. };
  51. static int hyperv_irq_remapping_alloc(struct irq_domain *domain,
  52. unsigned int virq, unsigned int nr_irqs,
  53. void *arg)
  54. {
  55. struct irq_alloc_info *info = arg;
  56. struct irq_data *irq_data;
  57. struct irq_desc *desc;
  58. int ret = 0;
  59. if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1)
  60. return -EINVAL;
  61. ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
  62. if (ret < 0)
  63. return ret;
  64. irq_data = irq_domain_get_irq_data(domain, virq);
  65. if (!irq_data) {
  66. irq_domain_free_irqs_common(domain, virq, nr_irqs);
  67. return -EINVAL;
  68. }
  69. irq_data->chip = &hyperv_ir_chip;
  70. /*
  71. * Hypver-V IO APIC irq affinity should be in the scope of
  72. * ioapic_max_cpumask because no irq remapping support.
  73. */
  74. desc = irq_data_to_desc(irq_data);
  75. cpumask_copy(desc->irq_common_data.affinity, &ioapic_max_cpumask);
  76. return 0;
  77. }
  78. static void hyperv_irq_remapping_free(struct irq_domain *domain,
  79. unsigned int virq, unsigned int nr_irqs)
  80. {
  81. irq_domain_free_irqs_common(domain, virq, nr_irqs);
  82. }
  83. static int hyperv_irq_remapping_select(struct irq_domain *d,
  84. struct irq_fwspec *fwspec,
  85. enum irq_domain_bus_token bus_token)
  86. {
  87. /* Claim the only I/O APIC emulated by Hyper-V */
  88. return x86_fwspec_is_ioapic(fwspec);
  89. }
  90. static const struct irq_domain_ops hyperv_ir_domain_ops = {
  91. .select = hyperv_irq_remapping_select,
  92. .alloc = hyperv_irq_remapping_alloc,
  93. .free = hyperv_irq_remapping_free,
  94. };
  95. static const struct irq_domain_ops hyperv_root_ir_domain_ops;
  96. static int __init hyperv_prepare_irq_remapping(void)
  97. {
  98. struct fwnode_handle *fn;
  99. int i;
  100. const char *name;
  101. const struct irq_domain_ops *ops;
  102. if (!hypervisor_is_type(X86_HYPER_MS_HYPERV) ||
  103. x86_init.hyper.msi_ext_dest_id() ||
  104. !x2apic_supported())
  105. return -ENODEV;
  106. if (hv_root_partition) {
  107. name = "HYPERV-ROOT-IR";
  108. ops = &hyperv_root_ir_domain_ops;
  109. } else {
  110. name = "HYPERV-IR";
  111. ops = &hyperv_ir_domain_ops;
  112. }
  113. fn = irq_domain_alloc_named_id_fwnode(name, 0);
  114. if (!fn)
  115. return -ENOMEM;
  116. ioapic_ir_domain =
  117. irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
  118. 0, IOAPIC_REMAPPING_ENTRY, fn, ops, NULL);
  119. if (!ioapic_ir_domain) {
  120. irq_domain_free_fwnode(fn);
  121. return -ENOMEM;
  122. }
  123. if (hv_root_partition)
  124. return 0; /* The rest is only relevant to guests */
  125. /*
  126. * Hyper-V doesn't provide irq remapping function for
  127. * IO-APIC and so IO-APIC only accepts 8-bit APIC ID.
  128. * Cpu's APIC ID is read from ACPI MADT table and APIC IDs
  129. * in the MADT table on Hyper-v are sorted monotonic increasingly.
  130. * APIC ID reflects cpu topology. There maybe some APIC ID
  131. * gaps when cpu number in a socket is not power of two. Prepare
  132. * max cpu affinity for IOAPIC irqs. Scan cpu 0-255 and set cpu
  133. * into ioapic_max_cpumask if its APIC ID is less than 256.
  134. */
  135. for (i = min_t(unsigned int, num_possible_cpus() - 1, 255); i >= 0; i--)
  136. if (cpu_physical_id(i) < 256)
  137. cpumask_set_cpu(i, &ioapic_max_cpumask);
  138. return 0;
  139. }
  140. static int __init hyperv_enable_irq_remapping(void)
  141. {
  142. return IRQ_REMAP_X2APIC_MODE;
  143. }
  144. struct irq_remap_ops hyperv_irq_remap_ops = {
  145. .prepare = hyperv_prepare_irq_remapping,
  146. .enable = hyperv_enable_irq_remapping,
  147. };
  148. /* IRQ remapping domain when Linux runs as the root partition */
  149. struct hyperv_root_ir_data {
  150. u8 ioapic_id;
  151. bool is_level;
  152. struct hv_interrupt_entry entry;
  153. };
  154. static void
  155. hyperv_root_ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
  156. {
  157. u64 status;
  158. u32 vector;
  159. struct irq_cfg *cfg;
  160. int ioapic_id;
  161. struct cpumask *affinity;
  162. int cpu;
  163. struct hv_interrupt_entry entry;
  164. struct hyperv_root_ir_data *data = irq_data->chip_data;
  165. struct IO_APIC_route_entry e;
  166. cfg = irqd_cfg(irq_data);
  167. affinity = irq_data_get_effective_affinity_mask(irq_data);
  168. cpu = cpumask_first_and(affinity, cpu_online_mask);
  169. vector = cfg->vector;
  170. ioapic_id = data->ioapic_id;
  171. if (data->entry.source == HV_DEVICE_TYPE_IOAPIC
  172. && data->entry.ioapic_rte.as_uint64) {
  173. entry = data->entry;
  174. status = hv_unmap_ioapic_interrupt(ioapic_id, &entry);
  175. if (status != HV_STATUS_SUCCESS)
  176. pr_debug("%s: unexpected unmap status %lld\n", __func__, status);
  177. data->entry.ioapic_rte.as_uint64 = 0;
  178. data->entry.source = 0; /* Invalid source */
  179. }
  180. status = hv_map_ioapic_interrupt(ioapic_id, data->is_level, cpu,
  181. vector, &entry);
  182. if (status != HV_STATUS_SUCCESS) {
  183. pr_err("%s: map hypercall failed, status %lld\n", __func__, status);
  184. return;
  185. }
  186. data->entry = entry;
  187. /* Turn it into an IO_APIC_route_entry, and generate MSI MSG. */
  188. e.w1 = entry.ioapic_rte.low_uint32;
  189. e.w2 = entry.ioapic_rte.high_uint32;
  190. memset(msg, 0, sizeof(*msg));
  191. msg->arch_data.vector = e.vector;
  192. msg->arch_data.delivery_mode = e.delivery_mode;
  193. msg->arch_addr_lo.dest_mode_logical = e.dest_mode_logical;
  194. msg->arch_addr_lo.dmar_format = e.ir_format;
  195. msg->arch_addr_lo.dmar_index_0_14 = e.ir_index_0_14;
  196. }
  197. static int hyperv_root_ir_set_affinity(struct irq_data *data,
  198. const struct cpumask *mask, bool force)
  199. {
  200. struct irq_data *parent = data->parent_data;
  201. struct irq_cfg *cfg = irqd_cfg(data);
  202. int ret;
  203. ret = parent->chip->irq_set_affinity(parent, mask, force);
  204. if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
  205. return ret;
  206. send_cleanup_vector(cfg);
  207. return 0;
  208. }
  209. static struct irq_chip hyperv_root_ir_chip = {
  210. .name = "HYPERV-ROOT-IR",
  211. .irq_ack = apic_ack_irq,
  212. .irq_set_affinity = hyperv_root_ir_set_affinity,
  213. .irq_compose_msi_msg = hyperv_root_ir_compose_msi_msg,
  214. };
  215. static int hyperv_root_irq_remapping_alloc(struct irq_domain *domain,
  216. unsigned int virq, unsigned int nr_irqs,
  217. void *arg)
  218. {
  219. struct irq_alloc_info *info = arg;
  220. struct irq_data *irq_data;
  221. struct hyperv_root_ir_data *data;
  222. int ret = 0;
  223. if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1)
  224. return -EINVAL;
  225. ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
  226. if (ret < 0)
  227. return ret;
  228. data = kzalloc(sizeof(*data), GFP_KERNEL);
  229. if (!data) {
  230. irq_domain_free_irqs_common(domain, virq, nr_irqs);
  231. return -ENOMEM;
  232. }
  233. irq_data = irq_domain_get_irq_data(domain, virq);
  234. if (!irq_data) {
  235. kfree(data);
  236. irq_domain_free_irqs_common(domain, virq, nr_irqs);
  237. return -EINVAL;
  238. }
  239. data->ioapic_id = info->devid;
  240. data->is_level = info->ioapic.is_level;
  241. irq_data->chip = &hyperv_root_ir_chip;
  242. irq_data->chip_data = data;
  243. return 0;
  244. }
  245. static void hyperv_root_irq_remapping_free(struct irq_domain *domain,
  246. unsigned int virq, unsigned int nr_irqs)
  247. {
  248. struct irq_data *irq_data;
  249. struct hyperv_root_ir_data *data;
  250. struct hv_interrupt_entry *e;
  251. int i;
  252. for (i = 0; i < nr_irqs; i++) {
  253. irq_data = irq_domain_get_irq_data(domain, virq + i);
  254. if (irq_data && irq_data->chip_data) {
  255. data = irq_data->chip_data;
  256. e = &data->entry;
  257. if (e->source == HV_DEVICE_TYPE_IOAPIC
  258. && e->ioapic_rte.as_uint64)
  259. hv_unmap_ioapic_interrupt(data->ioapic_id,
  260. &data->entry);
  261. kfree(data);
  262. }
  263. }
  264. irq_domain_free_irqs_common(domain, virq, nr_irqs);
  265. }
  266. static const struct irq_domain_ops hyperv_root_ir_domain_ops = {
  267. .select = hyperv_irq_remapping_select,
  268. .alloc = hyperv_root_irq_remapping_alloc,
  269. .free = hyperv_root_irq_remapping_free,
  270. };
  271. #endif