/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3Save.h

https://bitbucket.org/incubaid/edk2 · C Header · 159 lines · 97 code · 11 blank · 51 comment · 0 complexity · fbc87500589d23115269f8d9f6cea0a2 MD5 · raw file

  1. /** @file
  2. This is an implementation of the ACPI S3 Save protocol. This is defined in
  3. S3 boot path specification 0.9.
  4. Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
  5. This program and the accompanying materials
  6. are licensed and made available under the terms and conditions
  7. of the BSD License which accompanies this distribution. The
  8. full text of the license may be found at
  9. http://opensource.org/licenses/bsd-license.php
  10. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12. **/
  13. #ifndef _ACPI_S3_SAVE_H_
  14. #define _ACPI_S3_SAVE_H_
  15. #pragma pack(1)
  16. typedef union {
  17. struct {
  18. UINT32 LimitLow : 16;
  19. UINT32 BaseLow : 16;
  20. UINT32 BaseMid : 8;
  21. UINT32 Type : 4;
  22. UINT32 System : 1;
  23. UINT32 Dpl : 2;
  24. UINT32 Present : 1;
  25. UINT32 LimitHigh : 4;
  26. UINT32 Software : 1;
  27. UINT32 Reserved : 1;
  28. UINT32 DefaultSize : 1;
  29. UINT32 Granularity : 1;
  30. UINT32 BaseHigh : 8;
  31. } Bits;
  32. UINT64 Uint64;
  33. } IA32_GDT;
  34. typedef struct {
  35. IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;
  36. UINT32 Offset32To63;
  37. UINT32 Reserved;
  38. } X64_IDT_GATE_DESCRIPTOR;
  39. //
  40. // Page-Map Level-4 Offset (PML4) and
  41. // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  42. //
  43. typedef union {
  44. struct {
  45. UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
  46. UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
  47. UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
  48. UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
  49. UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
  50. UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
  51. UINT64 Reserved:1; // Reserved
  52. UINT64 MustBeZero:2; // Must Be Zero
  53. UINT64 Available:3; // Available for use by system software
  54. UINT64 PageTableBaseAddress:40; // Page Table Base Address
  55. UINT64 AvabilableHigh:11; // Available for use by system software
  56. UINT64 Nx:1; // No Execute bit
  57. } Bits;
  58. UINT64 Uint64;
  59. } PAGE_MAP_AND_DIRECTORY_POINTER;
  60. //
  61. // Page Table Entry 2MB
  62. //
  63. typedef union {
  64. struct {
  65. UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
  66. UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
  67. UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
  68. UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
  69. UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
  70. UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
  71. UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
  72. UINT64 MustBe1:1; // Must be 1
  73. UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  74. UINT64 Available:3; // Available for use by system software
  75. UINT64 PAT:1; //
  76. UINT64 MustBeZero:8; // Must be zero;
  77. UINT64 PageTableBaseAddress:31; // Page Table Base Address
  78. UINT64 AvabilableHigh:11; // Available for use by system software
  79. UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
  80. } Bits;
  81. UINT64 Uint64;
  82. } PAGE_TABLE_ENTRY;
  83. //
  84. // Page Table Entry 1GB
  85. //
  86. typedef union {
  87. struct {
  88. UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
  89. UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
  90. UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
  91. UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
  92. UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
  93. UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
  94. UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
  95. UINT64 MustBe1:1; // Must be 1
  96. UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  97. UINT64 Available:3; // Available for use by system software
  98. UINT64 PAT:1; //
  99. UINT64 MustBeZero:17; // Must be zero;
  100. UINT64 PageTableBaseAddress:22; // Page Table Base Address
  101. UINT64 AvabilableHigh:11; // Available for use by system software
  102. UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
  103. } Bits;
  104. UINT64 Uint64;
  105. } PAGE_TABLE_1G_ENTRY;
  106. #pragma pack()
  107. /**
  108. Gets the buffer of legacy memory below 1 MB
  109. This function is to get the buffer in legacy memory below 1MB that is required during S3 resume.
  110. @param This A pointer to the EFI_ACPI_S3_SAVE_PROTOCOL instance.
  111. @param Size The returned size of legacy memory below 1 MB.
  112. @retval EFI_SUCCESS Size is successfully returned.
  113. @retval EFI_INVALID_PARAMETER The pointer Size is NULL.
  114. **/
  115. EFI_STATUS
  116. EFIAPI
  117. LegacyGetS3MemorySize (
  118. IN EFI_ACPI_S3_SAVE_PROTOCOL * This,
  119. OUT UINTN * Size
  120. );
  121. /**
  122. Prepares all information that is needed in the S3 resume boot path.
  123. Allocate the resources or prepare informations and save in ACPI variable set for S3 resume boot path
  124. @param This A pointer to the EFI_ACPI_S3_SAVE_PROTOCOL instance.
  125. @param LegacyMemoryAddress The base address of legacy memory.
  126. @retval EFI_NOT_FOUND Some necessary information cannot be found.
  127. @retval EFI_SUCCESS All information was saved successfully.
  128. @retval EFI_OUT_OF_RESOURCES Resources were insufficient to save all the information.
  129. @retval EFI_INVALID_PARAMETER The memory range is not located below 1 MB.
  130. **/
  131. EFI_STATUS
  132. EFIAPI
  133. S3Ready (
  134. IN EFI_ACPI_S3_SAVE_PROTOCOL *This,
  135. IN VOID *LegacyMemoryAddress
  136. );
  137. #endif