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/arch/arm/include/asm/io.h

https://bitbucket.org/mdamt/linux-blankon
C Header | 345 lines | 171 code | 51 blank | 123 comment | 6 complexity | 47303be1191401ac62f3458a14160da7 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * arch/arm/include/asm/io.h
  3. *
  4. * Copyright (C) 1996-2000 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Modifications:
  11. * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
  12. * constant addresses and variable addresses.
  13. * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
  14. * specific IO header files.
  15. * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
  16. * 04-Apr-1999 PJB Added check_signature.
  17. * 12-Dec-1999 RMK More cleanups
  18. * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
  19. * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
  20. */
  21. #ifndef __ASM_ARM_IO_H
  22. #define __ASM_ARM_IO_H
  23. #ifdef __KERNEL__
  24. #include <linux/types.h>
  25. #include <asm/byteorder.h>
  26. #include <asm/memory.h>
  27. #include <asm/system.h>
  28. /*
  29. * ISA I/O bus memory addresses are 1:1 with the physical address.
  30. */
  31. #define isa_virt_to_bus virt_to_phys
  32. #define isa_page_to_bus page_to_phys
  33. #define isa_bus_to_virt phys_to_virt
  34. /*
  35. * Generic IO read/write. These perform native-endian accesses. Note
  36. * that some architectures will want to re-define __raw_{read,write}w.
  37. */
  38. extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
  39. extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  40. extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
  41. extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
  42. extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  43. extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  44. #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
  45. #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
  46. #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
  47. #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
  48. #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
  49. #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
  50. /*
  51. * Architecture ioremap implementation.
  52. */
  53. #define MT_DEVICE 0
  54. #define MT_DEVICE_NONSHARED 1
  55. #define MT_DEVICE_CACHED 2
  56. #define MT_DEVICE_WC 3
  57. /*
  58. * types 4 onwards can be found in asm/mach/map.h and are undefined
  59. * for ioremap
  60. */
  61. /*
  62. * __arm_ioremap takes CPU physical address.
  63. * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
  64. * The _caller variety takes a __builtin_return_address(0) value for
  65. * /proc/vmalloc to use - and should only be used in non-inline functions.
  66. */
  67. extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
  68. size_t, unsigned int, void *);
  69. extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
  70. void *);
  71. extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
  72. extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
  73. extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
  74. extern void __iounmap(volatile void __iomem *addr);
  75. /*
  76. * Bad read/write accesses...
  77. */
  78. extern void __readwrite_bug(const char *fn);
  79. /*
  80. * A typesafe __io() helper
  81. */
  82. static inline void __iomem *__typesafe_io(unsigned long addr)
  83. {
  84. return (void __iomem *)addr;
  85. }
  86. /* IO barriers */
  87. #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
  88. #define __iormb() rmb()
  89. #define __iowmb() wmb()
  90. #else
  91. #define __iormb() do { } while (0)
  92. #define __iowmb() do { } while (0)
  93. #endif
  94. /*
  95. * Now, pick up the machine-defined IO definitions
  96. */
  97. #include <mach/io.h>
  98. /*
  99. * This is the limit of PC card/PCI/ISA IO space, which is by default
  100. * 64K if we have PC card, PCI or ISA support. Otherwise, default to
  101. * zero to prevent ISA/PCI drivers claiming IO space (and potentially
  102. * oopsing.)
  103. *
  104. * Only set this larger if you really need inb() et.al. to operate over
  105. * a larger address space. Note that SOC_COMMON ioremaps each sockets
  106. * IO space area, and so inb() et.al. must be defined to operate as per
  107. * readb() et.al. on such platforms.
  108. */
  109. #ifndef IO_SPACE_LIMIT
  110. #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
  111. #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
  112. #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
  113. #define IO_SPACE_LIMIT ((resource_size_t)0xffff)
  114. #else
  115. #define IO_SPACE_LIMIT ((resource_size_t)0)
  116. #endif
  117. #endif
  118. /*
  119. * IO port access primitives
  120. * -------------------------
  121. *
  122. * The ARM doesn't have special IO access instructions; all IO is memory
  123. * mapped. Note that these are defined to perform little endian accesses
  124. * only. Their primary purpose is to access PCI and ISA peripherals.
  125. *
  126. * Note that for a big endian machine, this implies that the following
  127. * big endian mode connectivity is in place, as described by numerous
  128. * ARM documents:
  129. *
  130. * PCI: D0-D7 D8-D15 D16-D23 D24-D31
  131. * ARM: D24-D31 D16-D23 D8-D15 D0-D7
  132. *
  133. * The machine specific io.h include defines __io to translate an "IO"
  134. * address to a memory address.
  135. *
  136. * Note that we prevent GCC re-ordering or caching values in expressions
  137. * by introducing sequence points into the in*() definitions. Note that
  138. * __raw_* do not guarantee this behaviour.
  139. *
  140. * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
  141. */
  142. #ifdef __io
  143. #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
  144. #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
  145. cpu_to_le16(v),__io(p)); })
  146. #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
  147. cpu_to_le32(v),__io(p)); })
  148. #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
  149. #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
  150. __raw_readw(__io(p))); __iormb(); __v; })
  151. #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
  152. __raw_readl(__io(p))); __iormb(); __v; })
  153. #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
  154. #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
  155. #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
  156. #define insb(p,d,l) __raw_readsb(__io(p),d,l)
  157. #define insw(p,d,l) __raw_readsw(__io(p),d,l)
  158. #define insl(p,d,l) __raw_readsl(__io(p),d,l)
  159. #endif
  160. #define outb_p(val,port) outb((val),(port))
  161. #define outw_p(val,port) outw((val),(port))
  162. #define outl_p(val,port) outl((val),(port))
  163. #define inb_p(port) inb((port))
  164. #define inw_p(port) inw((port))
  165. #define inl_p(port) inl((port))
  166. #define outsb_p(port,from,len) outsb(port,from,len)
  167. #define outsw_p(port,from,len) outsw(port,from,len)
  168. #define outsl_p(port,from,len) outsl(port,from,len)
  169. #define insb_p(port,to,len) insb(port,to,len)
  170. #define insw_p(port,to,len) insw(port,to,len)
  171. #define insl_p(port,to,len) insl(port,to,len)
  172. /*
  173. * String version of IO memory access ops:
  174. */
  175. extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
  176. extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
  177. extern void _memset_io(volatile void __iomem *, int, size_t);
  178. #define mmiowb()
  179. /*
  180. * Memory access primitives
  181. * ------------------------
  182. *
  183. * These perform PCI memory accesses via an ioremap region. They don't
  184. * take an address as such, but a cookie.
  185. *
  186. * Again, this are defined to perform little endian accesses. See the
  187. * IO port primitives for more information.
  188. */
  189. #ifdef __mem_pci
  190. #define readb_relaxed(c) ({ u8 __r = __raw_readb(__mem_pci(c)); __r; })
  191. #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
  192. __raw_readw(__mem_pci(c))); __r; })
  193. #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
  194. __raw_readl(__mem_pci(c))); __r; })
  195. #define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c)))
  196. #define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
  197. cpu_to_le16(v),__mem_pci(c)))
  198. #define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
  199. cpu_to_le32(v),__mem_pci(c)))
  200. #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
  201. #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
  202. #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
  203. #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
  204. #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
  205. #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
  206. #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
  207. #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
  208. #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
  209. #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
  210. #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
  211. #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
  212. #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
  213. #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
  214. #define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
  215. #elif !defined(readb)
  216. #define readb(c) (__readwrite_bug("readb"),0)
  217. #define readw(c) (__readwrite_bug("readw"),0)
  218. #define readl(c) (__readwrite_bug("readl"),0)
  219. #define writeb(v,c) __readwrite_bug("writeb")
  220. #define writew(v,c) __readwrite_bug("writew")
  221. #define writel(v,c) __readwrite_bug("writel")
  222. #define check_signature(io,sig,len) (0)
  223. #endif /* __mem_pci */
  224. /*
  225. * ioremap and friends.
  226. *
  227. * ioremap takes a PCI memory address, as specified in
  228. * Documentation/io-mapping.txt.
  229. *
  230. */
  231. #ifndef __arch_ioremap
  232. #define __arch_ioremap __arm_ioremap
  233. #define __arch_iounmap __iounmap
  234. #endif
  235. #define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
  236. #define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
  237. #define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
  238. #define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
  239. #define iounmap __arch_iounmap
  240. /*
  241. * io{read,write}{8,16,32} macros
  242. */
  243. #ifndef ioread8
  244. #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
  245. #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
  246. #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
  247. #define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
  248. #define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
  249. #define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); })
  250. #define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
  251. #define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
  252. #define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); })
  253. #define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); })
  254. #define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
  255. #define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
  256. #define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
  257. #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
  258. #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
  259. #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
  260. extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
  261. extern void ioport_unmap(void __iomem *addr);
  262. #endif
  263. struct pci_dev;
  264. extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
  265. extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
  266. /*
  267. * can the hardware map this into one segment or not, given no other
  268. * constraints.
  269. */
  270. #define BIOVEC_MERGEABLE(vec1, vec2) \
  271. ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
  272. #ifdef CONFIG_MMU
  273. #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
  274. extern int valid_phys_addr_range(unsigned long addr, size_t size);
  275. extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
  276. extern int devmem_is_allowed(unsigned long pfn);
  277. #endif
  278. /*
  279. * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  280. * access
  281. */
  282. #define xlate_dev_mem_ptr(p) __va(p)
  283. /*
  284. * Convert a virtual cached pointer to an uncached pointer
  285. */
  286. #define xlate_dev_kmem_ptr(p) p
  287. /*
  288. * Register ISA memory and port locations for glibc iopl/inb/outb
  289. * emulation.
  290. */
  291. extern void register_isa_ports(unsigned int mmio, unsigned int io,
  292. unsigned int io_shift);
  293. #endif /* __KERNEL__ */
  294. #endif /* __ASM_ARM_IO_H */