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/CPUInfo.cpp

https://github.com/chadaustin/CPUInfo
C++ | 1232 lines | 912 code | 202 blank | 118 comment | 189 complexity | e9d9622acb0919f10ba315075f6749ac MD5 | raw file
    

  1. // Copyright (c) 2005 Chad Austin

    2. 

  2. //

    3. 

  3. // Permission is hereby granted, free of charge, to any person

    4. 

  4. // obtaining a copy of this software and associated documentation

    5. 

  5. // files (the "Software"), to deal in the Software without

    6. 

  6. // restriction, including without limitation the rights to use, copy,

    7. 

  7. // modify, merge, publish, distribute, sublicense, and/or sell copies

    8. 

  8. // of the Software, and to permit persons to whom the Software is

    9. 

  9. // furnished to do so, subject to the following conditions:

    10. 

  10. //

    11. 

  11. // The above copyright notice and this permission notice shall be

    12. 

  12. // included in all copies or substantial portions of the Software.

    13. 

  13. //

    14. 

  14. // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

    15. 

  15. // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

    16. 

  16. // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

    17. 

  17. // NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

    18. 

  18. // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

    19. 

  19. // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

    20. 

  20. // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

    21. 

  21. // SOFTWARE.

    22. 

  22. //

    23. 

  23. //

    24. 

  24. // Logic contained in this software gleaned from the following resources:

    25. 

  25. // 

    26. 

  26. // Intel Software Development Manuals

    27. 

  27. //   http://www.intel.com/design/itanium/manuals/245319.pdf

    28. 

  28. //

    29. 

  29. // AMD Processor Detection

    30. 

  30. //   http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf

    31. 

  31. //   http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_24593.pdf

    32. 

  32. //   http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_24594.pdf

    33. 

  33. //

    34. 

  34. // AMD64 Instruction Set Reference

    35. 

  35. //

    36. 

  36. // sandpile.org

    37. 

  37. // http://www.sandpile.org/post/msgs/20003246.htm

    38. 

  38. // http://www.sandpile.org/ia32/cpuid.htm

    39. 

  39. //

    40. 

  40. // Iain Chesworth @ codeproject

    41. 

  41. //   http://www.codetools.com/system/camel.asp

    42. 

  42. //

    43. 

  43. // Rob Wyatt @ gamasutra:

    44. 

  44. //   http://www.gamasutra.com/features/wyatts_world/19990709/processor_detection_01.htm

    45. 

  45. //

    46. 

  46. // http://grafi.ii.pw.edu.pl/gbm/x86/cpuid.html

    47. 

  47. 

    48. 

  48. 

    49. 

  49. #include <assert.h>

    50. 

  50. #include <stdio.h>

    51. 

  51. #include <string.h>

    52. 

  52. #include "CPUInfo.h"

    53. 

  53. 

    54. 

  54. 

    55. 

  55. #if defined(_MSC_VER) || defined(__CYGWIN__)

    56. 

  56. 

    57. 

  57. #include <windows.h>

    58. 

  58. 

    59. 

  59. typedef DWORD     u32;

    60. 

  60. typedef ULONGLONG u64;

    61. 

  61. 

    62. 

  62. #else

    63. 

  63. 

    64. 

  64. typedef unsigned long      u32;

    65. 

  65. typedef unsigned long long u64;

    66. 

  66. 

    67. 

  67. #endif

    68. 

  68. 

    69. 

  69. 

    70. 

  70. const char* CPUInfo::getVendorName() const {

    71. 

  71.     // Return the vendor ID.

    72. 

  72.     switch (identity.manufacturer) {

    73. 

  73.         case Intel:     return "Intel Corporation";

    74. 

  74.         case AMD:       return "Advanced Micro Devices";

    75. 

  75.         case NSC:       return "National Semiconductor";

    76. 

  76.         case Cyrix:     return "Cyrix Corp., VIA Inc.";

    77. 

  77.         case NexGen:    return "NexGen Inc., Advanced Micro Devices";

    78. 

  78.         case IDT:       return "IDT\\Centaur, Via Inc.";

    79. 

  79.         case UMC:       return "United Microelectronics Corp.";

    80. 

  80.         case Rise:      return "Rise";

    81. 

  81.         case Transmeta: return "Transmeta";

    82. 

  82.         default:        return identity.vendor;

    83. 

  83.     }

    84. 

  84. }

    85. 

  85. 

    86. 

  86. 

    87. 

  87. std::string CPUInfo::getProcessorName() const {

    88. 

  88.     if (identity.hasExtendedName) {

    89. 

  89.         return identity.extendedName + identity.firstNonSpace;

    90. 

  90.     } else if (identity.brand != 0) {

    91. 

  91.         return getProcessorBrandName();

    92. 

  92.     } else {

    93. 

  93.         return getClassicalProcessorName();

    94. 

  94.     }

    95. 

  95. }

    96. 

  96. 

    97. 

  97. 

    98. 

  98. const char* CPUInfo::getProcessorTypeName() const {

    99. 

  99.     switch (identity.type) {

    100. 

  100.         case 0:  return "Original OEM Processor";

    101. 

  101.         case 1:  return "Intel OverDrive Processor";

    102. 

  102.         case 2:  return "Dual Processor";

    103. 

  103.         case 3:  return "Reserved";

    104. 

  104.         default: return "Other";

    105. 

  105.     }

    106. 

  106. }

    107. 

  107. 

    108. 

  108. 

    109. 

  109. std::string CPUInfo::getProcessorBrandName() const {

    110. 

  110.     // http://sandpile.org/ia32/cpuid.htm and IA-32 Manual 2A

    111. 

  111.     switch (identity.brand) {

    112. 

  112.         case 0x00: return "Not Supported";

    113. 

  113.         case 0x01: return "0.18 µm Intel Celeron";

    114. 

  114.         case 0x02: return "0.18 µm Intel Pentium III";

    115. 

  115.         case 0x03: return "0.18 µm Intel Pentium III Xeon"

    116. 

  116.                           " -OR- "

    117. 

  117.                           "0.13 µm Intel Celeron";

    118. 

  118.         case 0x04: return "0.13 µm Intel Pentium III";

    119. 

  119.         case 0x06: return "0.13 µm Intel Pentium III mobile";

    120. 

  120.         case 0x07: return "0.13 µm Intel Celeron mobile";

    121. 

  121.         case 0x08: return "0.18 µm Intel Pentium 4"

    122. 

  122.                           " -OR- "

    123. 

  123.                           "0.13 µm Intel Celeron 4 mobile (0F24h)";

    124. 

  124.         case 0x09: return "0.13 µm Intel Pentium 4";

    125. 

  125.         case 0x0A: return "0.18 µm Intel Celeron 4";

    126. 

  126.         case 0x0B: return "0.18 µm Intel Pentium 4 Xeon MP"

    127. 

  127.                           " -OR- "

    128. 

  128.                           "0.13 µm Intel Pentium 4 Xeon";

    129. 

  129.         case 0x0C: return "0.13 µm Intel Pentium 4 Xeon MP";

    130. 

  130.         case 0x0E: return "0.18 µm Intel Pentium 4 Xeon"

    131. 

  131.                           " -OR- "

    132. 

  132.                           "0.13 µm Intel Pentium 4 mobile (production)";

    133. 

  133.         case 0x0F: return "0.13 µm Intel Celeron 4 mobile (0F27h)"

    134. 

  134.                           " -OR- "

    135. 

  135.                           "0.13 µm Intel Pentium 4 mobile (samples)";

    136. 

  136.         case 0x11: return "Mobile Genuine Intel processor";

    137. 

  137.         case 0x12: return "0.13 µm Intel Celeron M"

    138. 

  138.                           " -OR- "

    139. 

  139.                           "0.09 µm Intel Celeron M";

    140. 

  140.         case 0x13: return "Mobile Intel Celeron processor";

    141. 

  141.         case 0x14: return "Intel Celeron processor";

    142. 

  142.         case 0x15: return "Mobile Genuine Intel processor";

    143. 

  143.         case 0x16: return "0.13 µm Intel Pentium M"

    144. 

  144.                           " -OR- "

    145. 

  145.                           "0.09 µm Intel Pentium M";

    146. 

  146.         case 0x17: return "Mobile Intel Celeron processor";

    147. 

  147.     }

    148. 

  148. 

    149. 

  149.     char buffer[100];

    150. 

  150. 

    151. 

  151.     int top3    = (identity.brand >> 5) & 7;

    152. 

  152.     int bottom5 = identity.brand & 31;

    153. 

  153.     switch (top3) {

    154. 

  154.         case 0: sprintf(buffer, "Engineering Sample %d", bottom5);           return buffer;

    155. 

  155.         case 1: sprintf(buffer, "AMD Athlon 64 %d00+", 22 + bottom5);        return buffer;

    156. 

  156.         case 2: sprintf(buffer, "AMD Athlon 64 %d00+ mobile", 22 + bottom5); return buffer;

    157. 

  157.         case 3: sprintf(buffer, "AMD Opteron UP 1%d", 38 + 2 * bottom5);     return buffer;

    158. 

  158.         case 4: sprintf(buffer, "AMD Opteron DP 2%d", 38 + 2 * bottom5);     return buffer;

    159. 

  159.         case 5: sprintf(buffer, "AMD Opteron MP 8%d", 38 + 2 * bottom5);     return buffer;

    160. 

  160.         // n/a #6   AMD Athlon 64 FX-ZZ (ZZ=24+xxxxxb)

    161. 

  161.         // The upper 3 bits aren't sufficient to encode a value of 9=1001b.

    162. 

  162.         // Thus the Athlon 64 FX requires the 12-bit brand ID.

    163. 

  163.     }

    164. 

  164. 

    165. 

  165.     return "Unknown";

    166. 

  166. }

    167. 

  167. 

    168. 

  168. 

    169. 

  169. const char* CPUInfo::getClassicalProcessorName() const {

    170. 

  170.     switch (identity.manufacturer) {

    171. 

  171.         case Intel:

    172. 

  172.             switch (identity.family) {

    173. 

  173.                 case 3: return "Newer i80386 family";

    174. 

  174.                 case 4:

    175. 

  175.                     switch (identity.model) {

    176. 

  176.                         case 0:  return "i80486DX-25/33";

    177. 

  177.                         case 1:  return "i80486DX-50";

    178. 

  178.                         case 2:  return "i80486SX";

    179. 

  179.                         case 3:  return "i80486DX2";

    180. 

  180.                         case 4:  return "i80486SL";

    181. 

  181.                         case 5:  return "i80486SX2";

    182. 

  182.                         case 7:  return "i80486DX2 WriteBack";

    183. 

  183.                         case 8:  return "i80486DX4";

    184. 

  184.                         case 9:  return "i80486DX4 WriteBack";

    185. 

  185.                         default: return "Unknown 80486 family";

    186. 

  186.                     }

    187. 

  187.                 case 5:

    188. 

  188.                     switch (identity.model) {

    189. 

  189.                         case 0:  return "P5 A-Step";

    190. 

  190.                         case 1:  return "P5";

    191. 

  191.                         case 2:  return "P54C";

    192. 

  192.                         case 3:  return "P24T OverDrive";

    193. 

  193.                         case 4:  return "P55C";

    194. 

  194.                         case 7:  return "P54C";

    195. 

  195.                         case 8:  return "P55C (0.25µm)";

    196. 

  196.                         default: return "Unknown Pentium® family";

    197. 

  197.                     }

    198. 

  198.                 case 6:

    199. 

  199.                     switch (identity.model) {

    200. 

  200.                         case 0:   return "P6 A-Step";

    201. 

  201.                         case 1:   return "P6";

    202. 

  202.                         case 3:   return "Pentium® II (0.28 µm)";

    203. 

  203.                         case 5:   return "Pentium® II (0.25 µm)";

    204. 

  204.                         case 6:   return "Pentium® II With On-Die L2 Cache";

    205. 

  205.                         case 7:   return "Pentium® III (0.25 µm)";

    206. 

  206.                         case 8:   return "Pentium® III (0.18 µm) With 256 KB On-Die L2 Cache";

    207. 

  207.                         case 9:   return "Pentium® M or Celeron M";

    208. 

  208.                         case 0xa: return "Pentium® III (0.18 µm) With 1 Or 2 MB On-Die L2 Cache";

    209. 

  209.                         case 0xb: return "Pentium® III (0.13 µm) With 256 Or 512 KB On-Die L2 Cache";

    210. 

  210.                         case 0xd: return "Pentium M (90 nm)";

    211. 

  211.                         case 0xe: return "Core Solo or Duo (65 nm)";

    212. 

  212.                         case 0xf: return "Core 2 Solo or Duo (65 nm)";

    213. 

  213.                         default:  return "Unknown P6 family";

    214. 

  214.                     }

    215. 

  215.                 case 7: return "Intel Merced (IA-64)";

    216. 

  216.                 case 15:

    217. 

  217.                     switch (identity.model) {

    218. 

  218.                         case 0:  return "Pentium® IV (0.18 µm)";

    219. 

  219.                         case 1:  return "Pentium® IV (0.18 µm)";

    220. 

  220.                         case 2:  return "Pentium® IV (0.13 µm)";

    221. 

  221.                         default: return "Unknown Pentium 4 family";

    222. 

  222.                     }

    223. 

  223.                 case 31: return "Intel McKinley (IA-64)";

    224. 

  224.                 default: return "Unknown Intel family";

    225. 

  225.             }

    226. 

  226. 

    227. 

  227.         case AMD:

    228. 

  228.             switch (identity.family) {

    229. 

  229.                 case 4:

    230. 

  230.                     switch (identity.model) {

    231. 

  231.                         case 3:   return "80486DX2";

    232. 

  232.                         case 7:   return "80486DX2 WriteBack";

    233. 

  233.                         case 8:   return "80486DX4";

    234. 

  234.                         case 9:   return "80486DX4 WriteBack";

    235. 

  235.                         case 0xe: return "5x86";

    236. 

  236.                         case 0xf: return "5x86WB";

    237. 

  237.                         default:  return "Unknown 80486 family";

    238. 

  238.                     }

    239. 

  239.                 case 5:

    240. 

  240.                     switch (identity.model) {

    241. 

  241.                         case 0:   return "SSA5 (PR75, PR90, PR100)";

    242. 

  242.                         case 1:   return "5k86 (PR120, PR133)";

    243. 

  243.                         case 2:   return "5k86 (PR166)";

    244. 

  244.                         case 3:   return "5k86 (PR200)";

    245. 

  245.                         case 6:   return "K6 (0.30 µm)";

    246. 

  246.                         case 7:   return "K6 (0.25 µm)";

    247. 

  247.                         case 8:   return "K6-2";

    248. 

  248.                         case 9:   return "K6-III";

    249. 

  249.                         case 0xd: return "K6-2+ or K6-III+ (0.18 µm)";

    250. 

  250.                         default:  return "Unknown 80586 family";

    251. 

  251.                     }

    252. 

  252.                 case 6:

    253. 

  253.                     switch (identity.model) {

    254. 

  254.                         case 1:  return "Athlon™ (0.25 µm)";

    255. 

  255.                         case 2:  return "Athlon™ (0.18 µm)";

    256. 

  256.                         case 3:  return "Duron™ (SF core)";

    257. 

  257.                         case 4:  return "Athlon™ (Thunderbird core)";

    258. 

  258.                         case 6:  return "Athlon™ (Palomino core)";

    259. 

  259.                         case 7:  return "Duron™ (Morgan core)";

    260. 

  260.                         case 8:  return (features.supportsMP ?

    261. 

  261.                                     "Athlon™ MP (Thoroughbred core)" :

    262. 

  262.                                     "Athlon™ XP (Thoroughbred core)");

    263. 

  263.                         default: return "Unknown K7 family";

    264. 

  264.                     }

    265. 

  265.                 default:

    266. 

  266.                     return "Unknown AMD family";

    267. 

  267.             }

    268. 

  268. 

    269. 

  269.         case Transmeta:

    270. 

  270.             switch (identity.family) {    

    271. 

  271.                 case 5:

    272. 

  272.                     switch (identity.model) {

    273. 

  273.                         case 4:  return "Crusoe TM3x00 and TM5x00";

    274. 

  274.                         default: return "Unknown Crusoe family";

    275. 

  275.                     }

    276. 

  276.                 default:

    277. 

  277.                     return "Unknown Transmeta family";

    278. 

  278.             }

    279. 

  279. 

    280. 

  280.         case Rise:

    281. 

  281.             switch (identity.family) {    

    282. 

  282.                 case 5:

    283. 

  283.                     switch (identity.model) {

    284. 

  284.                         case 0:  return "mP6 (0.25 µm)";

    285. 

  285.                         case 2:  return "mP6 (0.18 µm)";

    286. 

  286.                         default: return "Unknown Rise family";

    287. 

  287.                     }

    288. 

  288.                 default:

    289. 

  289.                     return "Unknown Rise family";

    290. 

  290.             }

    291. 

  291. 

    292. 

  292.         case UMC:

    293. 

  293.             switch (identity.family) {    

    294. 

  294.                 case 4:

    295. 

  295.                     switch (identity.model) {

    296. 

  296.                         case 1:  return "U5D";

    297. 

  297.                         case 2:  return "U5S";

    298. 

  298.                         default: return "Unknown UMC family";

    299. 

  299.                     }

    300. 

  300.                 default:

    301. 

  301.                     return "Unknown UMC family";

    302. 

  302.             }

    303. 

  303. 

    304. 

  304.         case IDT:

    305. 

  305.             switch (identity.family) {    

    306. 

  306.                 case 5:

    307. 

  307.                     switch (identity.model) {

    308. 

  308.                         case 4:  return "C6";

    309. 

  309.                         case 8:  return "C2";

    310. 

  310.                         case 9:  return "C3";

    311. 

  311.                         default: return "Unknown IDT\\Centaur family";

    312. 

  312.                     }

    313. 

  313.                     break;

    314. 

  314.                 case 6:

    315. 

  315.                     switch (identity.model) {

    316. 

  316.                         case 6:  return "VIA Cyrix III - Samuel";

    317. 

  317.                         default: return "Unknown IDT\\Centaur family";

    318. 

  318.                     }

    319. 

  319.                 default:

    320. 

  320.                     return "Unknown IDT\\Centaur family";

    321. 

  321.             }

    322. 

  322. 

    323. 

  323.         case Cyrix:

    324. 

  324.             switch (identity.family) {    

    325. 

  325.                 case 4:

    326. 

  326.                     switch (identity.model) {

    327. 

  327.                         case 4:  return "MediaGX GX, GXm";

    328. 

  328.                         case 9:  return "5x86";

    329. 

  329.                         default: return "Unknown Cx5x86 family";

    330. 

  330.                     }

    331. 

  331.                 case 5:

    332. 

  332.                     switch (identity.model) {

    333. 

  333.                         case 2:  return "Cx6x86";

    334. 

  334.                         case 4:  return "MediaGX GXm";

    335. 

  335.                         default: return "Unknown Cx6x86 family";

    336. 

  336.                     }

    337. 

  337.                 case 6:

    338. 

  338.                     switch (identity.model) {

    339. 

  339.                         case 0:  return "6x86MX";

    340. 

  340.                         case 5:  return "Cyrix M2 Core";

    341. 

  341.                         case 6:  return "WinChip C5A Core";

    342. 

  342.                         case 7:  return "WinChip C5B\\C5C Core";

    343. 

  343.                         case 8:  return "WinChip C5C-T Core";

    344. 

  344.                         default: return "Unknown 6x86MX\\Cyrix III family";

    345. 

  345.                     }

    346. 

  346.                 default:

    347. 

  347.                     return "Unknown Cyrix family";

    348. 

  348.             }

    349. 

  349. 

    350. 

  350.         case NexGen:

    351. 

  351.             switch (identity.family) {    

    352. 

  352.                 case 5:

    353. 

  353.                     switch (identity.model) {

    354. 

  354.                         case 0:  return "Nx586 or Nx586FPU";

    355. 

  355.                         default: return "Unknown NexGen family";

    356. 

  356.                     }

    357. 

  357.                 default:

    358. 

  358.                     return "Unknown NexGen family";

    359. 

  359.             }

    360. 

  360. 

    361. 

  361.         case NSC:

    362. 

  362.             return "Cx486SLC \\ DLC \\ Cx486S A-Step";

    363. 

  363. 

    364. 

  364.         default:

    365. 

  365.             return "Unknown manufacturer.";

    366. 

  366.     }

    367. 

  367. }

    368. 

  368. 

    369. 

  369. 

    370. 

  370. #ifdef _MSC_VER  // Use SEH on Win32.

    371. 

  371. 

    372. 

  372. 

    373. 

  373. #if 0

    374. 

  374. 

    375. 

  375. static bool getCPUIDSupport() {

    376. 

  376.     // The "right" way, which doesn't work under certain Windows versions.

    377. 

  377.     // Courtesy of Iain Chesworth.

    378. 

  378. 

    379. 

  379.     int present = 0;

    380. 

  380.     __asm {

    381. 

  381.         pushfd                      ; save EFLAGS to stack.

    382. 

  382.         pop     eax                 ; store EFLAGS in eax.

    383. 

  383.         mov     edx, eax            ; save in edx for testing later.

    384. 

  384.         xor     eax, 0200000h       ; switch bit 21.

    385. 

  385.         push    eax                 ; copy "changed" value to stack.

    386. 

  386.         popfd                       ; save "changed" eax to EFLAGS.

    387. 

  387.         pushfd

    388. 

  388.         pop     eax

    389. 

  389.         xor     eax, edx            ; See if bit changeable.

    390. 

  390.         jz      cpuid_not_present

    391. 

  391.         mov     present, 1          ; CPUID present - enable its usage

    392. 

  392. 

    393. 

  393.     cpuid_not_present:

    394. 

  394.     }

    395. 

  395. 

    396. 

  396.     return present != 0;

    397. 

  397. }

    398. 

  398. 

    399. 

  399. #endif

    400. 

  400. 

    401. 

  401. 

    402. 

  402. static bool getCPUIDSupport() {

    403. 

  403.     __try {

    404. 

  404.         __asm {

    405. 

  405.             mov eax, 0

    406. 

  406.             cpuid

    407. 

  407.         }

    408. 

  408.     }

    409. 

  409.     __except (EXCEPTION_EXECUTE_HANDLER) {

    410. 

  410.         return false;

    411. 

  411.     }

    412. 

  412.     return true;

    413. 

  413. }

    414. 

  414. 

    415. 

  415. 

    416. 

  416. static bool getSSEFPSupport() {

    417. 

  417.     __try {

    418. 

  418.         __asm {

    419. 

  419.             orps xmm0, xmm0

    420. 

  420.         }

    421. 

  421.     }

    422. 

  422.     __except (EXCEPTION_EXECUTE_HANDLER) {

    423. 

  423.         return false;

    424. 

  424.     }

    425. 

  425.     return true;

    426. 

  426. }

    427. 

  427. 

    428. 

  428. 

    429. 

  429. static void classicalTimingLoop(u32 loopLength) {

    430. 

  430.     __asm {

    431. 

  431.         mov eax, 0x80000000

    432. 

  432.         mov ebx, loopLength

    433. 

  433.     timingLoop:

    434. 

  434.         bsf ecx, eax

    435. 

  435.         dec ebx

    436. 

  436.         jnz timingLoop

    437. 

  437.     }

    438. 

  438. }

    439. 

  439. 

    440. 

  440. 

    441. 

  441. #else  // Assume platform that raises signals for invalid instructions.

    442. 

  442. 

    443. 

  443. 

    444. 

  444. #include <setjmp.h>

    445. 

  445. #include <signal.h>

    446. 

  446. 

    447. 

  447. #ifdef __CYGWIN__

    448. 

  448. #define __thread __declspec(thread)

    449. 

  449. #elif defined(__APPLE__)

    450. 

  450. #define __thread

    451. 

  451. #endif

    452. 

  452. 

    453. 

  453. 

    454. 

  454. typedef void (*SignalHandler)(int);

    455. 

  455. 

    456. 

  456. static __thread jmp_buf check_jmpbuf;

    457. 

  457. 

    458. 

  458. static void handleSignal(int) {

    459. 

  459.     longjmp(check_jmpbuf, 1);

    460. 

  460. }

    461. 

  461. 

    462. 

  462. static bool getCPUIDSupport() {

    463. 

  463.     SignalHandler oldSIGILL  = signal(SIGILL,  handleSignal);

    464. 

  464.     SignalHandler oldSIGSEGV = signal(SIGSEGV, handleSignal);

    465. 

  465. 

    466. 

  466.     bool hasCPUID = false;

    467. 

  467.     if (setjmp(check_jmpbuf) == 0) {

    468. 

  468.         asm("movl $0, %eax\n"

    469. 

  469.             "cpuid\n");

    470. 

  470.         hasCPUID = true;

    471. 

  471.     }

    472. 

  472. 

    473. 

  473.     signal(SIGILL,  oldSIGILL);

    474. 

  474.     signal(SIGSEGV, oldSIGSEGV);

    475. 

  475. 

    476. 

  476.     return hasCPUID;

    477. 

  477. }

    478. 

  478. 

    479. 

  479. 

    480. 

  480. static bool getSSEFPSupport() {

    481. 

  481.     SignalHandler oldSIGILL  = signal(SIGILL,  handleSignal);

    482. 

  482.     SignalHandler oldSIGSEGV = signal(SIGSEGV, handleSignal);

    483. 

  483. 

    484. 

  484.     bool hasSSEFP = false;

    485. 

  485.     if (setjmp(check_jmpbuf) == 0) {

    486. 

  486.         asm("orps %xmm0, %xmm0\n");

    487. 

  487.         hasSSEFP = true;

    488. 

  488.     }

    489. 

  489. 

    490. 

  490.     signal(SIGILL,  oldSIGILL);

    491. 

  491.     signal(SIGSEGV, oldSIGSEGV);

    492. 

  492. 

    493. 

  493.     return hasSSEFP;

    494. 

  494. }

    495. 

  495. 

    496. 

  496. 

    497. 

  497. static void classicalTimingLoop(u32 loopLength) {

    498. 

  498.     asm("mov $0x80000000, %%eax\n"

    499. 

  499.         "timingLoop:\n"

    500. 

  500.         "bsf %%eax, %%ecx\n"

    501. 

  501.         "dec %%ebx\n"

    502. 

  502.         "jnz timingLoop\n"

    503. 

  503.         :

    504. 

  504.         : "b" (loopLength)

    505. 

  505.         : "%eax", "%ecx");

    506. 

  506. }

    507. 

  507. 

    508. 

  508. 

    509. 

  509. #endif

    510. 

  510. 

    511. 

  511. 

    512. 

  512. #ifdef _MSC_VER

    513. 

  513. 

    514. 

  514. static void CPUID(u32 level, u32* eax, u32* ebx, u32* ecx, u32* edx) {

    515. 

  515.     assert(getCPUIDSupport());

    516. 

  516. 

    517. 

  517.     u32 _eax, _ebx, _ecx, _edx;

    518. 

  518.     __asm {

    519. 

  519.         mov eax, level

    520. 

  520.         cpuid

    521. 

  521.         mov _eax, eax

    522. 

  522.         mov _ebx, ebx

    523. 

  523.         mov _ecx, ecx

    524. 

  524.         mov _edx, edx

    525. 

  525.     }

    526. 

  526. 

    527. 

  527.     if (eax) *eax = _eax;

    528. 

  528.     if (ebx) *ebx = _ebx;

    529. 

  529.     if (ecx) *ecx = _ecx;

    530. 

  530.     if (edx) *edx = _edx;

    531. 

  531. }

    532. 

  532. 

    533. 

  533. static u64 RDTSC() {

    534. 

  534.     u32 h, l;

    535. 

  535.     __asm {

    536. 

  536.         rdtsc

    537. 

  537.         mov h, edx

    538. 

  538.         mov l, eax

    539. 

  539.     }

    540. 

  540.     return (u64(h) << 32) + l;

    541. 

  541. }

    542. 

  542. 

    543. 

  543. #else

    544. 

  544. 

    545. 

  545. static void CPUID(u32 level, u32* eax, u32* ebx, u32* ecx, u32* edx) {

    546. 

  546.     assert(getCPUIDSupport());

    547. 

  547. 

    548. 

  548.     u32 _eax, _ebx, _ecx, _edx;

    549. 

  549.     asm("cpuid"

    550. 

  550.         : "=a" (_eax), "=b" (_ebx), "=c" (_ecx), "=d" (_edx)

    551. 

  551.         : "a" (level));

    552. 

  552. 

    553. 

  553.     if (eax) *eax = _eax;

    554. 

  554.     if (ebx) *ebx = _ebx;

    555. 

  555.     if (ecx) *ecx = _ecx;

    556. 

  556.     if (edx) *edx = _edx;

    557. 

  557. }

    558. 

  558. 

    559. 

  559. static u64 RDTSC() {

    560. 

  560.     u32 eax, edx;

    561. 

  561.     asm("rdtsc"

    562. 

  562.         : "=a" (eax), "=d" (edx));

    563. 

  563.     return (u64(edx) << 32) + eax;

    564. 

  564. }

    565. 

  565. 

    566. 

  566. #endif

    567. 

  567. 

    568. 

  568. 

    569. 

  569. #if defined(_MSC_VER) || defined(__CYGWIN__)

    570. 

  570. 

    571. 

  571. static u64 getHPFrequency() {

    572. 

  572.     LARGE_INTEGER frequency;

    573. 

  573.     QueryPerformanceFrequency(&frequency);

    574. 

  574.     return frequency.QuadPart;

    575. 

  575. }

    576. 

  576. 

    577. 

  577. static u64 getHPCounter() {

    578. 

  578.     LARGE_INTEGER counter;

    579. 

  579.     QueryPerformanceCounter(&counter);

    580. 

  580.     return counter.QuadPart;

    581. 

  581. }

    582. 

  582. 

    583. 

  583. #else

    584. 

  584. 

    585. 

  585. #include <sys/time.h>

    586. 

  586. 

    587. 

  587. static u64 getHPFrequency() {

    588. 

  588.     return 1000000;

    589. 

  589. }

    590. 

  590. 

    591. 

  591. static u64 getHPCounter() {

    592. 

  592.     timeval tv;

    593. 

  593.     gettimeofday(&tv, 0);

    594. 

  594.     return tv.tv_sec * 1000000 + tv.tv_usec;

    595. 

  595. }

    596. 

  596. 

    597. 

  597. #endif

    598. 

  598. 

    599. 

  599. 

    600. 

  600. static bool checkExtendedLevelSupport(const CPUInfo::Identity& id, u32 levelToCheck) {

    601. 

  601.     // The way everyone else checks is to see if the result of running with

    602. 

  602.     // input 0x80000000 is greater than or equal to 0x80000000.  The Intel

    603. 

  603.     // docs indicate that this may not always be the case.

    604. 

  604. 

    605. 

  605.     // The extended CPUID is supported by various vendors starting with the

    606. 

  606.     // following CPU models:

    607. 

  607.     //

    608. 

  608.     //      Manufacturer & Chip Name        | Family   Model   Revision

    609. 

  609.     //

    610. 

  610.     //      AMD K6, K6-2                    |    5       6         x

    611. 

  611.     //      Cyrix GXm, Cyrix III "Joshua"   |    5       4         x

    612. 

  612.     //      IDT C6-2                        |    5       8         x

    613. 

  613.     //      VIA Cyrix III                   |    6       5         x

    614. 

  614.     //      Transmeta Crusoe                |    5       x         x

    615. 

  615.     //      Intel Pentium 4                 |    f       x         x

    616. 

  616.     //

    617. 

  617. 

    618. 

  618.     // We check to see if a supported processor is present...

    619. 

  619.     if (id.manufacturer == CPUInfo::AMD) {

    620. 

  620.         if (id.family < 5) return false;

    621. 

  621.         if (id.family == 5 && id.model < 6) return false;

    622. 

  622.     } else if (id.manufacturer == CPUInfo::Cyrix) {

    623. 

  623.         if (id.family < 5) return false;

    624. 

  624.         if (id.family == 5 && id.model < 4) return false;

    625. 

  625.         if (id.family == 6 && id.model < 5) return false;

    626. 

  626.     } else if (id.manufacturer == CPUInfo::IDT) {

    627. 

  627.         if (id.family < 5) return false;

    628. 

  628.         if (id.family == 5 && id.model < 8) return false;

    629. 

  629.     } else if (id.manufacturer == CPUInfo::Transmeta) {

    630. 

  630.         if (id.family < 5) return false;

    631. 

  631.     } else if (id.manufacturer == CPUInfo::Intel) {

    632. 

  632.         if (id.family < 0xF) return false;

    633. 

  633.     }

    634. 

  634. 

    635. 

  635.     u32 maxExtendedLevel = 0;

    636. 

  636.     CPUID(0x80000000, &maxExtendedLevel, NULL, NULL, NULL);

    637. 

  637.     return maxExtendedLevel >= levelToCheck;

    638. 

  638. }

    639. 

  639. 

    640. 

  640. 

    641. 

  641. static void getIdentity(CPUInfo::Identity& id) {

    642. 

  642.     CPUID(0, NULL,

    643. 

  643.           (u32*)id.vendor,

    644. 

  644.           (u32*)(id.vendor + 8),

    645. 

  645.           (u32*)(id.vendor + 4));

    646. 

  646.     id.vendor[12] = 0;

    647. 

  647. 

    648. 

  648. 

    649. 

  649.     if      (memcmp(id.vendor, "GenuineIntel", 12) == 0) id.manufacturer = CPUInfo::Intel;     // Intel Corp.

    650. 

  650.     else if (memcmp(id.vendor, "UMC UMC UMC ", 12) == 0) id.manufacturer = CPUInfo::UMC;       // United Microelectronics Corp.

    651. 

  651.     else if (memcmp(id.vendor, "AuthenticAMD", 12) == 0) id.manufacturer = CPUInfo::AMD;       // Advanced Micro Devices

    652. 

  652.     else if (memcmp(id.vendor, "AMD ISBETTER", 12) == 0) id.manufacturer = CPUInfo::AMD;       // Advanced Micro Devices (1994)

    653. 

  653.     else if (memcmp(id.vendor, "CyrixInstead", 12) == 0) id.manufacturer = CPUInfo::Cyrix;     // Cyrix Corp., VIA Inc.

    654. 

  654.     else if (memcmp(id.vendor, "NexGenDriven", 12) == 0) id.manufacturer = CPUInfo::NexGen;    // NexGen Inc. (now AMD)

    655. 

  655.     else if (memcmp(id.vendor, "CentaurHauls", 12) == 0) id.manufacturer = CPUInfo::IDT;       // IDT/Centaur (now VIA)

    656. 

  656.     else if (memcmp(id.vendor, "RiseRiseRise", 12) == 0) id.manufacturer = CPUInfo::Rise;      // Rise

    657. 

  657.     else if (memcmp(id.vendor, "GenuineTMx86", 12) == 0) id.manufacturer = CPUInfo::Transmeta; // Transmeta

    658. 

  658.     else if (memcmp(id.vendor, "TransmetaCPU", 12) == 0) id.manufacturer = CPUInfo::Transmeta; // Transmeta

    659. 

  659.     else if (memcmp(id.vendor, "Geode By NSC", 12) == 0) id.manufacturer = CPUInfo::NSC;       // National Semiconductor

    660. 

  660.     else                                                 id.manufacturer = CPUInfo::UnknownManufacturer;

    661. 

  661. 

    662. 

  662. 

    663. 

  663.     u32 signature_eax, signature_ebx;

    664. 

  664.     CPUID(1, &signature_eax, &signature_ebx, NULL, NULL);

    665. 

  665. 

    666. 

  666.     unsigned family    = (signature_eax >> 8)  & 0xF;

    667. 

  667.     unsigned ex_family = (signature_eax >> 20) & 0xFF;

    668. 

  668. 

    669. 

  669.     unsigned model    = (signature_eax >> 4)  & 0xF;

    670. 

  670.     unsigned ex_model = (signature_eax >> 16) & 0xF;

    671. 

  671. 

    672. 

  672.     id.type     = (signature_eax >> 12) & 0x3;

    673. 

  673.     id.family   = (ex_family << 4) + family;

    674. 

  674.     id.model    = (ex_model << 4) + model;

    675. 

  675.     id.stepping = signature_eax & 0xF;

    676. 

  676. 

    677. 

  677.     id.brand    = signature_ebx & 0xFF;

    678. 

  678. }

    679. 

  679. 

    680. 

  680. 

    681. 

  681. static void getExtendedIdentity(CPUInfo::Identity& id) {

    682. 

  682.     id.hasExtendedName = false;

    683. 

  683. 

    684. 

  684.     // Make sure this check is supported.

    685. 

  685.     if (!checkExtendedLevelSupport(id, 0x80000002)) return;

    686. 

  686.     if (!checkExtendedLevelSupport(id, 0x80000003)) return;

    687. 

  687.     if (!checkExtendedLevelSupport(id, 0x80000004)) return;

    688. 

  688. 

    689. 

  689.     CPUID(0x80000002,

    690. 

  690.           (u32*)id.extendedName,

    691. 

  691.           (u32*)id.extendedName + 1,

    692. 

  692.           (u32*)id.extendedName + 2,

    693. 

  693.           (u32*)id.extendedName + 3);

    694. 

  694.     CPUID(0x80000003,

    695. 

  695.           (u32*)id.extendedName + 4,

    696. 

  696.           (u32*)id.extendedName + 5,

    697. 

  697.           (u32*)id.extendedName + 6,

    698. 

  698.           (u32*)id.extendedName + 7);

    699. 

  699.     CPUID(0x80000004,

    700. 

  700.           (u32*)id.extendedName + 8,

    701. 

  701.           (u32*)id.extendedName + 9,

    702. 

  702.           (u32*)id.extendedName + 10,

    703. 

  703.           (u32*)id.extendedName + 11);

    704. 

  704.     id.extendedName[48] = 0;

    705. 

  705. 

    706. 

  706.     // Trim leading whitespace.

    707. 

  707.     unsigned firstNonSpace = 0;

    708. 

  708.     while (firstNonSpace < 48 && isspace(id.extendedName[firstNonSpace])) {

    709. 

  709.         ++firstNonSpace;

    710. 

  710.     }

    711. 

  711. 

    712. 

  712.     id.hasExtendedName = true;

    713. 

  713.     id.firstNonSpace = firstNonSpace;

    714. 

  714. }

    715. 

  715. 

    716. 

  716. 

    717. 

  717. static bool isBitSet(unsigned word, int bit) {

    718. 

  718.     return (word & (1 << bit)) != 0;

    719. 

  719. }

    720. 

  720. 

    721. 

  721. 

    722. 

  722. static void getFeatures(CPUInfo::Features& features) {

    723. 

  723.     u32 features_ebx;

    724. 

  724.     u32 features_ecx;

    725. 

  725.     u32 features_edx;

    726. 

  726.     CPUID(1, NULL, &features_ebx, &features_ecx, &features_edx);

    727. 

  727. 

    728. 

  728. #define F(name, bit) features.name = isBitSet(features_edx, (bit))

    729. 

  729. 

    730. 

  730.     F(fpu,     0);

    731. 

  731.     F(vme,     1);

    732. 

  732.     F(de,      2);

    733. 

  733.     F(pse,     3);

    734. 

  734.     F(tsc,     4);

    735. 

  735.     F(msr,     5);

    736. 

  736.     F(pae,     6);

    737. 

  737.     F(mce,     7);

    738. 

  738.     F(cx8,     8);

    739. 

  739.     F(apic,    9);

    740. 

  740.     F(sep,     11);

    741. 

  741.     F(mtrr,    12);

    742. 

  742.     F(pge,     13);

    743. 

  743.     F(mca,     14);

    744. 

  744.     F(cmov,    15);

    745. 

  745.     F(pat,     16);

    746. 

  746.     F(pse36,   17);

    747. 

  747.     F(serial,  18);

    748. 

  748.     F(clfsh,   19);

    749. 

  749.     F(ds,      21);

    750. 

  750.     F(acpi,    22);

    751. 

  751.     F(mmx,     23);

    752. 

  752.     F(fxsr,    24);

    753. 

  753.     F(sse,     25);

    754. 

  754.     F(sse2,    26);

    755. 

  755.     F(ss,      27);

    756. 

  756.     F(htt,     28);

    757. 

  757.     F(thermal, 29);

    758. 

  758.     F(ia64,    30);

    759. 

  759.     F(pbe,     31);

    760. 

  760. 

    761. 

  761. #undef F

    762. 

  762. 

    763. 

  763.     // Verify that floating point SSE works.

    764. 

  764.     if (features.sse) {

    765. 

  765.         features.ssefp = getSSEFPSupport();

    766. 

  766.     } else {

    767. 

  767.         features.ssefp = false;

    768. 

  768.     }

    769. 

  769. 

    770. 

  770.     features.CLFLUSHCacheLineSize = (features_ebx >> 8)  & 0xFF;

    771. 

  771.     features.APIC_ID              = (features_ebx >> 24) & 0xFF;

    772. 

  772. 

    773. 

  773.     features.sse3    = isBitSet(features_ecx, 0);

    774. 

  774.     features.monitor = isBitSet(features_ecx, 3);

    775. 

  775.     features.ds_cpl  = isBitSet(features_ecx, 4);

    776. 

  776.     features.est     = isBitSet(features_ecx, 7);

    777. 

  777.     features.tm2     = isBitSet(features_ecx, 8);

    778. 

  778.     features.cnxt_id = isBitSet(features_ecx, 10);

    779. 

  779. 

    780. 

  780.     features.logicalProcessorsPerPhysical = (features.htt

    781. 

  781.         ? (features_ebx >> 16) & 0xFF

    782. 

  782.         : 1);

    783. 

  783. }

    784. 

  784. 

    785. 

  785. 

    786. 

  786. static void getExtendedFeatures(const CPUInfo::Identity& id, CPUInfo::Features& features) {

    787. 

  787.     if (checkExtendedLevelSupport(id, 0x80000001)) {

    788. 

  788.         u32 ex_signature;

    789. 

  789.         u32 ex_features;

    790. 

  790.         CPUID(0x80000001, &ex_signature, NULL, NULL, &ex_features);

    791. 

  791. 

    792. 

  792.         // Retrieve the extended features of CPU present.

    793. 

  793.         features._3dnow     = isBitSet(ex_features, 31);

    794. 

  794.         features._3dnowPlus = isBitSet(ex_features, 30);

    795. 

  795.         features.ssemmx     = isBitSet(ex_features, 22);

    796. 

  796.         features.supportsMP = isBitSet(ex_features, 19);

    797. 

  797. 

    798. 

  798.         // MMX+ is reported differently by manufacturers.

    799. 

  799.         if (id.manufacturer == CPUInfo::AMD) {

    800. 

  800.             features.mmxPlus = isBitSet(ex_features, 22);

    801. 

  801.         } else if (id.manufacturer == CPUInfo::Cyrix) {

    802. 

  802.             features.mmxPlus = isBitSet(ex_features, 24);

    803. 

  803.         } else {

    804. 

  804.             features.mmxPlus = false;

    805. 

  805.         }

    806. 

  806.     } else {

    807. 

  807.         features._3dnow     = false;

    808. 

  808.         features._3dnowPlus = false;

    809. 

  809.         features.ssemmx     = false;

    810. 

  810.         features.mmxPlus    = false;

    811. 

  811.         features.supportsMP = false;

    812. 

  812.     }

    813. 

  813. }

    814. 

  814. 

    815. 

  815. 

    816. 

  816. static void getSerialNumber(CPUInfo& info) {

    817. 

  817.     // Verify that the processor has a serial number.

    818. 

  818.     assert(info.features.serial);

    819. 

  819. 

    820. 

  820.     unsigned char serialNumber[12];

    821. 

  821.     CPUID(3, NULL,

    822. 

  822.           (u32*)serialNumber,

    823. 

  823.           (u32*)serialNumber + 1,

    824. 

  824.           (u32*)serialNumber + 2);

    825. 

  825. 

    826. 

  826.     sprintf(info.features.serialNumber,

    827. 

  827.             "%.2x%.2x-%.2x%.2x-%.2x%.2x-%.2x%.2x-%.2x%.2x-%.2x%.2x",

    828. 

  828.             serialNumber[0],

    829. 

  829.             serialNumber[1],

    830. 

  830.             serialNumber[2],

    831. 

  831.             serialNumber[3],

    832. 

  832.             serialNumber[4],

    833. 

  833.             serialNumber[5],

    834. 

  834.             serialNumber[6],

    835. 

  835.             serialNumber[7],

    836. 

  836.             serialNumber[8],

    837. 

  837.             serialNumber[9],

    838. 

  838.             serialNumber[10],

    839. 

  839.             serialNumber[11]);

    840. 

  840. }

    841. 

  841. 

    842. 

  842. 

    843. 

  843. static bool getCacheDetails(const CPUInfo::Identity& id, CPUInfo::Cache& cache) {

    844. 

  844.     if (checkExtendedLevelSupport(id, 0x80000005)) {

    845. 

  845.         u32 L1[4];

    846. 

  846.         CPUID(0x80000005, &L1[0], &L1[1], &L1[2], &L1[3]);

    847. 

  847.         cache.L1CacheSize  = (L1[2] >> 24) & 0xFF;

    848. 

  848.         cache.L1CacheSize += (L1[3] >> 24) & 0xFF;

    849. 

  849.     } else {

    850. 

  850.         cache.L1CacheSize = -1;

    851. 

  851.     }

    852. 

  852. 

    853. 

  853.     if (checkExtendedLevelSupport(id, 0x80000006)) {

    854. 

  854.         u32 L2[4];

    855. 

  855.         CPUID(0x80000006, &L2[0], &L2[1], &L2[2], &L2[3]);

    856. 

  856.         cache.L2CacheSize = (L2[2] >> 16) & 0xFFFF;

    857. 

  857.     } else {

    858. 

  858.         cache.L2CacheSize = -1;

    859. 

  859.     }

    860. 

  860. 

    861. 

  861.     // No way to query L3.

    862. 

  862.     cache.L3CacheSize = -1;

    863. 

  863. 

    864. 

  864.     // Return failure if we cannot detect either cache with this method.

    865. 

  865.     return cache.L1CacheSize != -1 ||

    866. 

  866.            cache.L2CacheSize != -1;

    867. 

  867. }

    868. 

  868. 

    869. 

  869. 

    870. 

  870. static void getClassicalCacheDetails(CPUInfo::Cache& cache) {

    871. 

  871.     //int TLBCode   = -1;

    872. 

  872.     //int TLBData   = -1;

    873. 

  873.     int L1Code    = -1;

    874. 

  874.     int L1Data    = -1;

    875. 

  875.     int L1Trace   = -1;

    876. 

  876.     int L2Unified = -1;

    877. 

  877.     int L3Unified = -1;

    878. 

  878. 

    879. 

  879.     int passTotal;

    880. 

  880.     int passCounter = 0;

    881. 

  881.     do {

    882. 

  882.         unsigned char cacheData[16];

    883. 

  883.         CPUID(2,

    884. 

  884.               (u32*)cacheData,

    885. 

  885.               (u32*)cacheData + 1,

    886. 

  886.               (u32*)cacheData + 2,

    887. 

  887.               (u32*)cacheData + 3);

    888. 

  888. 

    889. 

  889.         passTotal = cacheData[0];

    890. 

  890.         for (int counter = 1; counter < 16; ++counter) {

    891. 

  891. 

    892. 

  892.             // Process descriptors.

    893. 

  893.             switch (cacheData[counter]) {

    894. 

  894.                 case 0x00: break;

    895. 

  895.                 //case 0x01: TLBCode = 4;         break;

    896. 

  896.                 //case 0x02: TLBCode = 4096;      break;

    897. 

  897.                 //case 0x03: TLBData = 4;         break;

    898. 

  898.                 //case 0x04: TLBData = 4096;      break;

    899. 

  899.                 case 0x06: L1Code = 8;          break;

    900. 

  900.                 case 0x08: L1Code = 16;         break;

    901. 

  901.                 case 0x0a: L1Data = 8;          break;

    902. 

  902.                 case 0x0c: L1Data = 16;         break;

    903. 

  903.                 case 0x10: L1Data = 16;         break;      // <-- FIXME: IA-64 Only

    904. 

  904.                 case 0x15: L1Code = 16;         break;      // <-- FIXME: IA-64 Only

    905. 

  905.                 case 0x1a: L2Unified = 96;      break;      // <-- FIXME: IA-64 Only

    906. 

  906.                 case 0x22: L3Unified = 512;     break;

    907. 

  907.                 case 0x23: L3Unified = 1024;    break;

    908. 

  908.                 case 0x25: L3Unified = 2048;    break;

    909. 

  909.                 case 0x29: L3Unified = 4096;    break;

    910. 

  910.                 case 0x39: L2Unified = 128;     break;

    911. 

  911.                 case 0x3c: L2Unified = 256;     break;

    912. 

  912.                 case 0x40: L2Unified = 0;       break;      // <-- FIXME: No integrated L2 cache (P6 core) or L3 cache (P4 core).

    913. 

  913.                 case 0x41: L2Unified = 128;     break;

    914. 

  914.                 case 0x42: L2Unified = 256;     break;

    915. 

  915.                 case 0x43: L2Unified = 512;     break;

    916. 

  916.                 case 0x44: L2Unified = 1024;    break;

    917. 

  917.                 case 0x45: L2Unified = 2048;    break;

    918. 

  918.                 //case 0x50: TLBCode = 4096;      break;

    919. 

  919.                 //case 0x51: TLBCode = 4096;      break;

    920. 

  920.                 //case 0x52: TLBCode = 4096;      break;

    921. 

  921.                 //case 0x5b: TLBData = 4096;      break;

    922. 

  922.                 //case 0x5c: TLBData = 4096;      break;

    923. 

  923.                 //case 0x5d: TLBData = 4096;      break;

    924. 

  924.                 case 0x66: L1Data = 8;          break;

    925. 

  925.                 case 0x67: L1Data = 16;         break;

    926. 

  926.                 case 0x68: L1Data = 32;         break;

    927. 

  927.                 case 0x70: L1Trace = 12;        break;

    928. 

  928.                 case 0x71: L1Trace = 16;        break;

    929. 

  929.                 case 0x72: L1Trace = 32;        break;

    930. 

  930.                 case 0x77: L1Code = 16;         break;      // <-- FIXME: IA-64 Only

    931. 

  931.                 case 0x79: L2Unified = 128;     break;

    932. 

  932.                 case 0x7a: L2Unified = 256;     break;

    933. 

  933.                 case 0x7b: L2Unified = 512;     break;

    934. 

  934.                 case 0x7c: L2Unified = 1024;    break;

    935. 

  935.                 case 0x7e: L2Unified = 256;     break;

    936. 

  936.                 case 0x81: L2Unified = 128;     break;

    937. 

  937.                 case 0x82: L2Unified = 256;     break;

    938. 

  938.                 case 0x83: L2Unified = 512;     break;

    939. 

  939.                 case 0x84: L2Unified = 1024;    break;

    940. 

  940.                 case 0x85: L2Unified = 2048;    break;

    941. 

  941.                 case 0x88: L3Unified = 2048;    break;      // <-- FIXME: IA-64 Only

    942. 

  942.                 case 0x89: L3Unified = 4096;    break;      // <-- FIXME: IA-64 Only

    943. 

  943.                 case 0x8a: L3Unified = 8192;    break;      // <-- FIXME: IA-64 Only

    944. 

  944.                 case 0x8d: L3Unified = 3096;    break;      // <-- FIXME: IA-64 Only

    945. 

  945.                 //case 0x90: TLBCode, 262144;     break;      // <-- FIXME: IA-64 Only

    946. 

  946.                 //case 0x96: TLBCode, 262144;     break;      // <-- FIXME: IA-64 Only

    947. 

  947.                 //case 0x9b: TLBCode, 262144;     break;      // <-- FIXME: IA-64 Only

    948. 

  948.             }

    949. 

  949.         }

    950. 

  950. 

    951. 

  951.         ++passCounter;

    952. 

  952. 

    953. 

  953.     } while (passCounter < passTotal);

    954. 

  954. 

    955. 

  955.     if (L1Code == -1 && L1Data == -1 && L1Trace == -1) {

    956. 

  956.         cache.L1CacheSize = -1;

    957. 

  957.     } else {

    958. 

  958.         cache.L1CacheSize = 0;

    959. 

  959.         if (L1Code  != -1) cache.L1CacheSize += L1Code;

    960. 

  960.         if (L1Data  != -1) cache.L1CacheSize += L1Data;

    961. 

  961.         if (L1Trace != -1) cache.L1CacheSize += L1Trace;

    962. 

  962.     }

    963. 

  963. 

    964. 

  964.     cache.L2CacheSize = L2Unified;

    965. 

  965.     cache.L3CacheSize = L3Unified;

    966. 

  966. }

    967. 

  967. 

    968. 

  968. 

    969. 

  969. static void getPowerManagement(const CPUInfo::Identity& id, CPUInfo::PowerManagement& pm) {

    970. 

  970.     if (checkExtendedLevelSupport(id, 0x80000007)) {

    971. 

  971.         u32 pmflags = 0;

    972. 

  972.         CPUID(0x80000007, NULL, NULL, NULL, &pmflags);

    973. 

  973. 

    974. 

  974.         pm.ts  = isBitSet(pmflags, 0);

    975. 

  975.         pm.fid = isBitSet(pmflags, 1);

    976. 

  976.         pm.vid = isBitSet(pmflags, 2);

    977. 

  977.         pm.ttp = isBitSet(pmflags, 3);

    978. 

  978.         pm.tm  = isBitSet(pmflags, 4);

    979. 

  979.         pm.stc = isBitSet(pmflags, 5);

    980. 

  980.     } else {

    981. 

  981.         pm.ts  = false;

    982. 

  982.         pm.fid = false;

    983. 

  983.         pm.vid = false;

    984. 

  984.         pm.ttp = false;

    985. 

  985.         pm.tm  = false;

    986. 

  986.         pm.stc = false;

    987. 

  987.     }

    988. 

  988. }

    989. 

  989. 

    990. 

  990. 

    991. 

  991. /// Duration in milliseconds.

    992. 

  992. static int measureFrequency(unsigned duration) {

    993. 

  993.     // Run a high-performance timer with a known frequency against the

    994. 

  994.     // processor clock to calculate the processor's frequency.

    995. 

  995. 

    996. 

  996.     u64 frequencyPC = getHPFrequency();

    997. 

  997.     u64 ticks = duration * frequencyPC / 1000;

    998. 

  998. 

    999. 

  999.     u64 startPC  = getHPCounter();

    1000. 

  1000.     u64 startTSC = RDTSC();

    1001. 

  1001. 

    1002. 

  1002.     u64 endPC;

    1003. 

  1003.     do {

    1004. 

  1004.         endPC = getHPCounter();

    1005. 

  1005.     } while ((endPC - startPC) < ticks);

    1006. 

  1006. 

    1007. 

  1007.     u64 endTSC = RDTSC();

    1008. 

  1008. 

    1009. 

  1009.     u64 elapsedPC  = endPC  - startPC;

    1010. 

  1010.     u64 elapsedTSC = endTSC - startTSC;

    1011. 

  1011. 

    1012. 

  1012.     return int(elapsedTSC * frequencyPC / elapsedPC / 1000000);

    1013. 

  1013. }

    1014. 

  1014. 

    1015. 

  1015. 

    1016. 

  1016. static int getFrequency() {

    1017. 

  1017.     return measureFrequency(50);

    1018. 

  1018. }

    1019. 

  1019. 

    1020. 

  1020. 

    1021. 

  1021. static int getClassicalFrequency(const CPUInfo& info) {

    1022. 

  1022.     static const u32 LOOP_LENGTH = 10000000;

    1023. 

  1023. 

    1024. 

  1024.     u64 start = getHPCounter();

    1025. 

  1025.     classicalTimingLoop(LOOP_LENGTH);

    1026. 

  1026.     u64 end   = getHPCounter();

    1027. 

  1027. 

    1028. 

  1028.     u64 countsPerSecond = getHPFrequency();

    1029. 

  1029. 

    1030. 

  1030.     // Calculate loop running time in seconds.

    1031. 

  1031.     double duration = double(end - start) / countsPerSecond;

    1032. 

  1032. 

    1033. 

  1033.     // Calculate the clock speed.

    1034. 

  1034.     if (info.identity.family == 3) {

    1035. 

  1035.         // 80386 processors....  Loop time is 115 cycles!

    1036. 

  1036.         return int(((LOOP_LENGTH * 115.0) / duration) / 1000000);

    1037. 

  1037.     } else if (info.identity.family == 4) {

    1038. 

  1038.         // 80486 processors....  Loop time is 47 cycles!

    1039. 

  1039.         return int(((LOOP_LENGTH * 47.0) / duration) / 1000000);

    1040. 

  1040.     } else if (info.identity.family == 5) {

    1041. 

  1041.         // Pentium processors....  Loop time is 43 cycles!

    1042. 

  1042.         return int(((LOOP_LENGTH * 43.0) / duration) / 1000000);

    1043. 

  1043.     } else {

    1044. 

  1044.         // Unknown cycle count.

    1045. 

  1045.         return 0;

    1046. 

  1046.     }

    1047. 

  1047. }

    1048. 

  1048. 

    1049. 

  1049. 

    1050. 

  1050. static int getCPUFrequency(const CPUInfo& info) {

    1051. 

  1051.     if (info.features.tsc) {

    1052. 

  1052.         return getFrequency();

    1053. 

  1053.     } else {

    1054. 

  1054.         return getClassicalFrequency(info);

    1055. 

  1055.     }

    1056. 

  1056. }

    1057. 

  1057. 

    1058. 

  1058. 

    1059. 

  1059. void getCPUInfo(CPUInfo& info) {

    1060. 

  1060.     // CPUID support.

    1061. 

  1061.     info.supportsCPUID = getCPUIDSupport();

    1062. 

  1062. 

    1063. 

  1063.     if (info.supportsCPUID) {

    1064. 

  1064.         // Identity.

    1065. 

  1065.         getIdentity(info.identity);

    1066. 

  1066.         getExtendedIdentity(info.identity);

    1067. 

  1067. 

    1068. 

  1068.         // Features.

    1069. 

  1069.         getFeatures(info.features);

    1070. 

  1070.         getExtendedFeatures(info.identity, info.features);

    1071. 

  1071.         if (info.features.serial) {

    1072. 

  1072.             getSerialNumber(info);

    1073. 

  1073.         }

    1074. 

  1074. 

    1075. 

  1075.         // Cache.

    1076. 

  1076.         if (!getCacheDetails(info.identity, info.cache)) {

    1077. 

  1077.             getClassicalCacheDetails(info.cache);

    1078. 

  1078.         }

    1079. 

  1079. 

    1080. 

  1080.         // Power management.

    1081. 

  1081.         getPowerManagement(info.identity, info.powerManagement);

    1082. 

  1082. 

    1083. 

  1083.         info.frequency = getCPUFrequency(info);

    1084. 

  1084.     }

    1085. 

  1085. }

    1086. 

  1086. 

    1087. 

  1087. 

    1088. 

  1088. #if defined(_MSC_VER) || defined(__CYGWIN__)

    1089. 

  1089. 

    1090. 

  1090. int getCPUCount() {

    1091. 

  1091.     SYSTEM_INFO info;

    1092. 

  1092.     GetSystemInfo(&info);

    1093. 

  1093.     return info.dwNumberOfProcessors;

    1094. 

  1094. }

    1095. 

  1095. 

    1096. 

  1096. static DWORD WINAPI retrieverThreadProc(LPVOID parameter) {

    1097. 

  1097.     CPUInfo* info = (CPUInfo*)parameter;

    1098. 

  1098.     getCPUInfo(*info);

    1099. 

  1099.     return 0;

    1100. 

  1100. }

    1101. 

  1101. 

    1102. 

  1102. 

    1103. 

  1103. int getMultipleCPUInfo(CPUInfo* array) {

    1104. 

  1104.     DWORD processAffinityMask;

    1105. 

  1105.     DWORD systemAffinityMask;

    1106. 

  1106.     GetProcessAffinityMask(

    1107. 

  1107.         GetCurrentProcess(),

    1108. 

  1108.         &processAffinityMask,

    1109. 

  1109.         &systemAffinityMask);

    1110. 

  1110. 

    1111. 

  1111.     int totalQueried = 0;

    1112. 

  1112. 

    1113. 

  1113.     int processorCount = getCPUCount();

    1114. 

  1114.     HANDLE* handles = new HANDLE[processorCount];

    1115. 

  1115. 

    1116. 

  1116.     for (int i = 0; i < processorCount; ++i) {

    1117. 

  1117.         // Skip if processor is disabled.

    1118. 

  1118.         int currentMask = (1 << i);

    1119. 

  1119.         if (!(processAffinityMask & currentMask)) {

    1120. 

  1120.             continue;

    1121. 

  1121.         }

    1122. 

  1122. 

    1123. 

  1123.         HANDLE& handle = handles[totalQueried];

    1124. 

  1124. 

    1125. 

  1125.         DWORD dummy;

    1126. 

  1126.         handle = CreateThread(

    1127. 

  1127.             NULL, 0, retrieverThreadProc, array + totalQueried,

    1128. 

  1128.             CREATE_SUSPENDED, &dummy);

    1129. 

  1129.         if (!handle) {

    1130. 

  1130.             continue;

    1131. 

  1131.         }

    1132. 

  1132. 

    1133. 

  1133.         if (0 == SetThreadAffinityMask(handle, currentMask)) {

    1134. 

  1134.             CloseHandle(handle);

    1135. 

  1135.             continue;

    1136. 

  1136.         }

    1137. 

  1137. 

    1138. 

  1138.         ResumeThread(handle);

    1139. 

  1139.         ++totalQueried;

    1140. 

  1140.     }

    1141. 

  1141. 

    1142. 

  1142.     WaitForMultipleObjects(totalQueried, handles, TRUE, INFINITE);

    1143. 

  1143.     for (int i = 0; i < totalQueried; ++i) {

    1144. 

  1144.         CloseHandle(handles[i]);

    1145. 

  1145.     }

    1146. 

  1146.     delete[] handles;

    1147. 

  1147.     return totalQueried;

    1148. 

  1148. }

    1149. 

  1149. 

    1150. 

  1150. #elif defined(__APPLE__)

    1151. 

  1151. 

    1152. 

  1152. #include <sys/param.h>

    1153. 

  1153. #include <sys/sysctl.h>

    1154. 

  1154. 

    1155. 

  1155. // http://alienryderflex.com/processor_count.html

    1156. 

  1156. int getCPUCount() {

    1157. 

  1157.     int count;

    1158. 

  1158.     size_t size = sizeof(count);

    1159. 

  1159.     if (sysctlbyname("hw.ncpu", &count, &size, NULL, 0)) {

    1160. 

  1160. 	return 1;

    1161. 

  1161.     }

    1162. 

  1162.     return count;

    1163. 

  1163. }

    1164. 

  1164. 

    1165. 

  1165. int getMultipleCPUInfo(CPUInfo* array) {

    1166. 

  1166.     int cpuCount = getCPUCount();

    1167. 

  1167.     for (int i = 0; i < cpuCount; ++i) {

    1168. 

  1168.         // Do we need to yield to make sure we're actually going to run on that

    1169. 

  1169.         // processor?  Not according to the online docs...  affinity changes

    1170. 

  1170.         // should happen immediately.

    1171. 

  1171.         // sched_yield();

    1172. 

  1172. 

    1173. 

  1173.         getCPUInfo(array[i]);

    1174. 

  1174.     }

    1175. 

  1175.     return cpuCount;

    1176. 

  1176. }

    1177. 

  1177. 

    1178. 

  1178. #else  // Linux

    1179. 

  1179. 

    1180. 

  1180. #include <sched.h>

    1181. 

  1181. 

    1182. 

  1182. int getCPUCount() {

    1183. 

  1183.     cpu_set_t mask;

    1184. 

  1184.     int res = sched_getaffinity(0, sizeof(mask), &mask);

    1185. 

  1185.     if (res == -1) {

    1186. 

  1186.         return 0;

    1187. 

  1187.     }

    1188. 

  1188. 

    1189. 

  1189.     int cpuCount = 0;

    1190. 

  1190.     for (int i = 0; i < CPU_SETSIZE; ++i) {

    1191. 

  1191.         if (CPU_ISSET(i, &mask)) {

    1192. 

  1192.             ++cpuCount;

    1193. 

  1193.         }

    1194. 

  1194.     }

    1195. 

  1195.     return cpuCount;

    1196. 

  1196. }

    1197. 

  1197. 

    1198. 

  1198. 

    1199. 

  1199. int getMultipleCPUInfo(CPUInfo* array) {

    1200. 

  1200.     cpu_set_t oldMask;

    1201. 

  1201.     int res = sched_getaffinity(0, sizeof(oldMask), &oldMask);

    1202. 

  1202.     if (res == -1) {

    1203. 

  1203.         return 0;

    1204. 

  1204.     }

    1205. 

  1205. 

    1206. 

  1206.     int cpuCount = getCPUCount();

    1207. 

  1207.     int totalQueried = 0;

    1208. 

  1208.     for (int i = 0; i < cpuCount; ++i) {

    1209. 

  1209.         cpu_set_t mask;

    1210. 

  1210.         CPU_ZERO(&mask);

    1211. 

  1211.         CPU_SET(i, &mask);

    1212. 

  1212.         res = sched_setaffinity(0, sizeof(mask), &mask);

    1213. 

  1213.         if (res == -1) {

    1214. 

  1214.             continue;

    1215. 

  1215.         }

    1216. 

  1216. 

    1217. 

  1217.         // Do we need to yield to make sure we're actually going to run on that

    1218. 

  1218.         // processor?  Not according to the online docs...  affinity changes

    1219. 

  1219.         // should happen immediately.

    1220. 

  1220.         // sched_yield();

    1221. 

  1221. 

    1222. 

  1222.         getCPUInfo(array[totalQueried]);

    1223. 

  1223.         ++totalQueried;

    1224. 

  1224.     }

    1225. 

  1225. 

    1226. 

  1226.     // Make sure we restore the original affinity.

    1227. 

  1227.     sched_setaffinity(0, sizeof(oldMask), &oldMask);

    1228. 

  1228. 

    1229. 

  1229.     return totalQueried;

    1230. 

  1230. }

    1231. 

  1231. 

    1232. 

  1232. #endif

    1233. 

  1233.