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/arch/arm/mach-davinci/board-dm365-evm.c

https://github.com/kingklick/kk-incredible-kernel
C | 491 lines | 350 code | 70 blank | 71 comment | 20 complexity | b1eb81cef6d837090eb8c7262f9c510b MD5 | raw file
  1. /*
  2. * TI DaVinci DM365 EVM board support
  3. *
  4. * Copyright (C) 2009 Texas Instruments Incorporated
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/i2c.h>
  20. #include <linux/io.h>
  21. #include <linux/clk.h>
  22. #include <linux/i2c/at24.h>
  23. #include <linux/leds.h>
  24. #include <linux/mtd/mtd.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <linux/mtd/nand.h>
  27. #include <asm/setup.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/mach/arch.h>
  30. #include <asm/mach/map.h>
  31. #include <mach/mux.h>
  32. #include <mach/hardware.h>
  33. #include <mach/dm365.h>
  34. #include <mach/psc.h>
  35. #include <mach/common.h>
  36. #include <mach/i2c.h>
  37. #include <mach/serial.h>
  38. #include <mach/mmc.h>
  39. #include <mach/nand.h>
  40. static inline int have_imager(void)
  41. {
  42. /* REVISIT when it's supported, trigger via Kconfig */
  43. return 0;
  44. }
  45. static inline int have_tvp7002(void)
  46. {
  47. /* REVISIT when it's supported, trigger via Kconfig */
  48. return 0;
  49. }
  50. #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
  51. #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
  52. #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
  53. #define DM365_EVM_PHY_MASK (0x2)
  54. #define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
  55. /*
  56. * A MAX-II CPLD is used for various board control functions.
  57. */
  58. #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
  59. #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
  60. #define CPLD_TEST CPLD_OFFSET(0,1)
  61. #define CPLD_LEDS CPLD_OFFSET(0,2)
  62. #define CPLD_MUX CPLD_OFFSET(0,3)
  63. #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
  64. #define CPLD_POWER CPLD_OFFSET(1,1)
  65. #define CPLD_VIDEO CPLD_OFFSET(1,2)
  66. #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
  67. #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
  68. #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
  69. #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
  70. #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
  71. #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
  72. #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
  73. #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
  74. #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
  75. #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
  76. #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
  77. #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
  78. #define CPLD_RESETS CPLD_OFFSET(4,3)
  79. #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
  80. #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
  81. #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
  82. #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
  83. #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
  84. #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
  85. static void __iomem *cpld;
  86. /* NOTE: this is geared for the standard config, with a socketed
  87. * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
  88. * swap chips with a different block size, partitioning will
  89. * need to be changed. This NAND chip MT29F16G08FAA is the default
  90. * NAND shipped with the Spectrum Digital DM365 EVM
  91. */
  92. #define NAND_BLOCK_SIZE SZ_128K
  93. static struct mtd_partition davinci_nand_partitions[] = {
  94. {
  95. /* UBL (a few copies) plus U-Boot */
  96. .name = "bootloader",
  97. .offset = 0,
  98. .size = 28 * NAND_BLOCK_SIZE,
  99. .mask_flags = MTD_WRITEABLE, /* force read-only */
  100. }, {
  101. /* U-Boot environment */
  102. .name = "params",
  103. .offset = MTDPART_OFS_APPEND,
  104. .size = 2 * NAND_BLOCK_SIZE,
  105. .mask_flags = 0,
  106. }, {
  107. .name = "kernel",
  108. .offset = MTDPART_OFS_APPEND,
  109. .size = SZ_4M,
  110. .mask_flags = 0,
  111. }, {
  112. .name = "filesystem1",
  113. .offset = MTDPART_OFS_APPEND,
  114. .size = SZ_512M,
  115. .mask_flags = 0,
  116. }, {
  117. .name = "filesystem2",
  118. .offset = MTDPART_OFS_APPEND,
  119. .size = MTDPART_SIZ_FULL,
  120. .mask_flags = 0,
  121. }
  122. /* two blocks with bad block table (and mirror) at the end */
  123. };
  124. static struct davinci_nand_pdata davinci_nand_data = {
  125. .mask_chipsel = BIT(14),
  126. .parts = davinci_nand_partitions,
  127. .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
  128. .ecc_mode = NAND_ECC_HW,
  129. .options = NAND_USE_FLASH_BBT,
  130. };
  131. static struct resource davinci_nand_resources[] = {
  132. {
  133. .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
  134. .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
  135. .flags = IORESOURCE_MEM,
  136. }, {
  137. .start = DM365_ASYNC_EMIF_CONTROL_BASE,
  138. .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
  139. .flags = IORESOURCE_MEM,
  140. },
  141. };
  142. static struct platform_device davinci_nand_device = {
  143. .name = "davinci_nand",
  144. .id = 0,
  145. .num_resources = ARRAY_SIZE(davinci_nand_resources),
  146. .resource = davinci_nand_resources,
  147. .dev = {
  148. .platform_data = &davinci_nand_data,
  149. },
  150. };
  151. static struct at24_platform_data eeprom_info = {
  152. .byte_len = (256*1024) / 8,
  153. .page_size = 64,
  154. .flags = AT24_FLAG_ADDR16,
  155. .setup = davinci_get_mac_addr,
  156. .context = (void *)0x7f00,
  157. };
  158. static struct i2c_board_info i2c_info[] = {
  159. {
  160. I2C_BOARD_INFO("24c256", 0x50),
  161. .platform_data = &eeprom_info,
  162. },
  163. };
  164. static struct davinci_i2c_platform_data i2c_pdata = {
  165. .bus_freq = 400 /* kHz */,
  166. .bus_delay = 0 /* usec */,
  167. };
  168. static int cpld_mmc_get_cd(int module)
  169. {
  170. if (!cpld)
  171. return -ENXIO;
  172. /* low == card present */
  173. return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
  174. }
  175. static int cpld_mmc_get_ro(int module)
  176. {
  177. if (!cpld)
  178. return -ENXIO;
  179. /* high == card's write protect switch active */
  180. return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
  181. }
  182. static struct davinci_mmc_config dm365evm_mmc_config = {
  183. .get_cd = cpld_mmc_get_cd,
  184. .get_ro = cpld_mmc_get_ro,
  185. .wires = 4,
  186. .max_freq = 50000000,
  187. .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
  188. .version = MMC_CTLR_VERSION_2,
  189. };
  190. static void dm365evm_emac_configure(void)
  191. {
  192. /*
  193. * EMAC pins are multiplexed with GPIO and UART
  194. * Further details are available at the DM365 ARM
  195. * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
  196. */
  197. davinci_cfg_reg(DM365_EMAC_TX_EN);
  198. davinci_cfg_reg(DM365_EMAC_TX_CLK);
  199. davinci_cfg_reg(DM365_EMAC_COL);
  200. davinci_cfg_reg(DM365_EMAC_TXD3);
  201. davinci_cfg_reg(DM365_EMAC_TXD2);
  202. davinci_cfg_reg(DM365_EMAC_TXD1);
  203. davinci_cfg_reg(DM365_EMAC_TXD0);
  204. davinci_cfg_reg(DM365_EMAC_RXD3);
  205. davinci_cfg_reg(DM365_EMAC_RXD2);
  206. davinci_cfg_reg(DM365_EMAC_RXD1);
  207. davinci_cfg_reg(DM365_EMAC_RXD0);
  208. davinci_cfg_reg(DM365_EMAC_RX_CLK);
  209. davinci_cfg_reg(DM365_EMAC_RX_DV);
  210. davinci_cfg_reg(DM365_EMAC_RX_ER);
  211. davinci_cfg_reg(DM365_EMAC_CRS);
  212. davinci_cfg_reg(DM365_EMAC_MDIO);
  213. davinci_cfg_reg(DM365_EMAC_MDCLK);
  214. /*
  215. * EMAC interrupts are multiplexed with GPIO interrupts
  216. * Details are available at the DM365 ARM
  217. * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
  218. */
  219. davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
  220. davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
  221. davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
  222. davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
  223. }
  224. static void dm365evm_mmc_configure(void)
  225. {
  226. /*
  227. * MMC/SD pins are multiplexed with GPIO and EMIF
  228. * Further details are available at the DM365 ARM
  229. * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
  230. */
  231. davinci_cfg_reg(DM365_SD1_CLK);
  232. davinci_cfg_reg(DM365_SD1_CMD);
  233. davinci_cfg_reg(DM365_SD1_DATA3);
  234. davinci_cfg_reg(DM365_SD1_DATA2);
  235. davinci_cfg_reg(DM365_SD1_DATA1);
  236. davinci_cfg_reg(DM365_SD1_DATA0);
  237. }
  238. static void __init evm_init_i2c(void)
  239. {
  240. davinci_init_i2c(&i2c_pdata);
  241. i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
  242. }
  243. static struct platform_device *dm365_evm_nand_devices[] __initdata = {
  244. &davinci_nand_device,
  245. };
  246. static inline int have_leds(void)
  247. {
  248. #ifdef CONFIG_LEDS_CLASS
  249. return 1;
  250. #else
  251. return 0;
  252. #endif
  253. }
  254. struct cpld_led {
  255. struct led_classdev cdev;
  256. u8 mask;
  257. };
  258. static const struct {
  259. const char *name;
  260. const char *trigger;
  261. } cpld_leds[] = {
  262. { "dm365evm::ds2", },
  263. { "dm365evm::ds3", },
  264. { "dm365evm::ds4", },
  265. { "dm365evm::ds5", },
  266. { "dm365evm::ds6", "nand-disk", },
  267. { "dm365evm::ds7", "mmc1", },
  268. { "dm365evm::ds8", "mmc0", },
  269. { "dm365evm::ds9", "heartbeat", },
  270. };
  271. static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
  272. {
  273. struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
  274. u8 reg = __raw_readb(cpld + CPLD_LEDS);
  275. if (b != LED_OFF)
  276. reg &= ~led->mask;
  277. else
  278. reg |= led->mask;
  279. __raw_writeb(reg, cpld + CPLD_LEDS);
  280. }
  281. static enum led_brightness cpld_led_get(struct led_classdev *cdev)
  282. {
  283. struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
  284. u8 reg = __raw_readb(cpld + CPLD_LEDS);
  285. return (reg & led->mask) ? LED_OFF : LED_FULL;
  286. }
  287. static int __init cpld_leds_init(void)
  288. {
  289. int i;
  290. if (!have_leds() || !cpld)
  291. return 0;
  292. /* setup LEDs */
  293. __raw_writeb(0xff, cpld + CPLD_LEDS);
  294. for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
  295. struct cpld_led *led;
  296. led = kzalloc(sizeof(*led), GFP_KERNEL);
  297. if (!led)
  298. break;
  299. led->cdev.name = cpld_leds[i].name;
  300. led->cdev.brightness_set = cpld_led_set;
  301. led->cdev.brightness_get = cpld_led_get;
  302. led->cdev.default_trigger = cpld_leds[i].trigger;
  303. led->mask = BIT(i);
  304. if (led_classdev_register(NULL, &led->cdev) < 0) {
  305. kfree(led);
  306. break;
  307. }
  308. }
  309. return 0;
  310. }
  311. /* run after subsys_initcall() for LEDs */
  312. fs_initcall(cpld_leds_init);
  313. static void __init evm_init_cpld(void)
  314. {
  315. u8 mux, resets;
  316. const char *label;
  317. struct clk *aemif_clk;
  318. /* Make sure we can configure the CPLD through CS1. Then
  319. * leave it on for later access to MMC and LED registers.
  320. */
  321. aemif_clk = clk_get(NULL, "aemif");
  322. if (IS_ERR(aemif_clk))
  323. return;
  324. clk_enable(aemif_clk);
  325. if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
  326. "cpld") == NULL)
  327. goto fail;
  328. cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
  329. if (!cpld) {
  330. release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
  331. SECTION_SIZE);
  332. fail:
  333. pr_err("ERROR: can't map CPLD\n");
  334. clk_disable(aemif_clk);
  335. return;
  336. }
  337. /* External muxing for some signals */
  338. mux = 0;
  339. /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
  340. * NOTE: SW4 bus width setting must match!
  341. */
  342. if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
  343. /* external keypad mux */
  344. mux |= BIT(7);
  345. platform_add_devices(dm365_evm_nand_devices,
  346. ARRAY_SIZE(dm365_evm_nand_devices));
  347. } else {
  348. /* no OneNAND support yet */
  349. }
  350. /* Leave external chips in reset when unused. */
  351. resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
  352. /* Static video input config with SN74CBT16214 1-of-3 mux:
  353. * - port b1 == tvp7002 (mux lowbits == 1 or 6)
  354. * - port b2 == imager (mux lowbits == 2 or 7)
  355. * - port b3 == tvp5146 (mux lowbits == 5)
  356. *
  357. * Runtime switching could work too, with limitations.
  358. */
  359. if (have_imager()) {
  360. label = "HD imager";
  361. mux |= 1;
  362. /* externally mux MMC1/ENET/AIC33 to imager */
  363. mux |= BIT(6) | BIT(5) | BIT(3);
  364. } else {
  365. struct davinci_soc_info *soc_info = &davinci_soc_info;
  366. /* we can use MMC1 ... */
  367. dm365evm_mmc_configure();
  368. davinci_setup_mmc(1, &dm365evm_mmc_config);
  369. /* ... and ENET ... */
  370. dm365evm_emac_configure();
  371. soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
  372. soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
  373. resets &= ~BIT(3);
  374. /* ... and AIC33 */
  375. resets &= ~BIT(1);
  376. if (have_tvp7002()) {
  377. mux |= 2;
  378. resets &= ~BIT(2);
  379. label = "tvp7002 HD";
  380. } else {
  381. /* default to tvp5146 */
  382. mux |= 5;
  383. resets &= ~BIT(0);
  384. label = "tvp5146 SD";
  385. }
  386. }
  387. __raw_writeb(mux, cpld + CPLD_MUX);
  388. __raw_writeb(resets, cpld + CPLD_RESETS);
  389. pr_info("EVM: %s video input\n", label);
  390. /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
  391. }
  392. static struct davinci_uart_config uart_config __initdata = {
  393. .enabled_uarts = (1 << 0),
  394. };
  395. static void __init dm365_evm_map_io(void)
  396. {
  397. dm365_init();
  398. }
  399. static __init void dm365_evm_init(void)
  400. {
  401. evm_init_i2c();
  402. davinci_serial_init(&uart_config);
  403. dm365evm_emac_configure();
  404. dm365evm_mmc_configure();
  405. davinci_setup_mmc(0, &dm365evm_mmc_config);
  406. /* maybe setup mmc1/etc ... _after_ mmc0 */
  407. evm_init_cpld();
  408. }
  409. static __init void dm365_evm_irq_init(void)
  410. {
  411. davinci_irq_init();
  412. }
  413. MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
  414. .phys_io = IO_PHYS,
  415. .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
  416. .boot_params = (0x80000100),
  417. .map_io = dm365_evm_map_io,
  418. .init_irq = dm365_evm_irq_init,
  419. .timer = &davinci_timer,
  420. .init_machine = dm365_evm_init,
  421. MACHINE_END