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/arch/x86/kernel/cpu/intel.c

https://github.com/erasmux/cm-kernel
C | 531 lines | 360 code | 65 blank | 106 comment | 125 complexity | 7616ecc6bf66527ce1ebae77c650f7c5 MD5 | raw file
  1. #include <linux/init.h>
  2. #include <linux/kernel.h>
  3. #include <linux/string.h>
  4. #include <linux/bitops.h>
  5. #include <linux/smp.h>
  6. #include <linux/sched.h>
  7. #include <linux/thread_info.h>
  8. #include <linux/module.h>
  9. #include <linux/uaccess.h>
  10. #include <asm/processor.h>
  11. #include <asm/pgtable.h>
  12. #include <asm/msr.h>
  13. #include <asm/bugs.h>
  14. #include <asm/cpu.h>
  15. #ifdef CONFIG_X86_64
  16. #include <linux/topology.h>
  17. #include <asm/numa_64.h>
  18. #endif
  19. #include "cpu.h"
  20. #ifdef CONFIG_X86_LOCAL_APIC
  21. #include <asm/mpspec.h>
  22. #include <asm/apic.h>
  23. #endif
  24. static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  25. {
  26. /* Unmask CPUID levels if masked: */
  27. if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
  28. u64 misc_enable;
  29. rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  30. if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
  31. misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
  32. wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  33. c->cpuid_level = cpuid_eax(0);
  34. get_cpu_cap(c);
  35. }
  36. }
  37. if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  38. (c->x86 == 0x6 && c->x86_model >= 0x0e))
  39. set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  40. /*
  41. * Atom erratum AAE44/AAF40/AAG38/AAH41:
  42. *
  43. * A race condition between speculative fetches and invalidating
  44. * a large page. This is worked around in microcode, but we
  45. * need the microcode to have already been loaded... so if it is
  46. * not, recommend a BIOS update and disable large pages.
  47. */
  48. if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
  49. u32 ucode, junk;
  50. wrmsr(MSR_IA32_UCODE_REV, 0, 0);
  51. sync_core();
  52. rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
  53. if (ucode < 0x20e) {
  54. printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
  55. clear_cpu_cap(c, X86_FEATURE_PSE);
  56. }
  57. }
  58. #ifdef CONFIG_X86_64
  59. set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  60. #else
  61. /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  62. if (c->x86 == 15 && c->x86_cache_alignment == 64)
  63. c->x86_cache_alignment = 128;
  64. #endif
  65. /* CPUID workaround for 0F33/0F34 CPU */
  66. if (c->x86 == 0xF && c->x86_model == 0x3
  67. && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
  68. c->x86_phys_bits = 36;
  69. /*
  70. * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  71. * with P/T states and does not stop in deep C-states.
  72. *
  73. * It is also reliable across cores and sockets. (but not across
  74. * cabinets - we turn it off in that case explicitly.)
  75. */
  76. if (c->x86_power & (1 << 8)) {
  77. set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  78. set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
  79. if (!check_tsc_unstable())
  80. sched_clock_stable = 1;
  81. }
  82. /*
  83. * There is a known erratum on Pentium III and Core Solo
  84. * and Core Duo CPUs.
  85. * " Page with PAT set to WC while associated MTRR is UC
  86. * may consolidate to UC "
  87. * Because of this erratum, it is better to stick with
  88. * setting WC in MTRR rather than using PAT on these CPUs.
  89. *
  90. * Enable PAT WC only on P4, Core 2 or later CPUs.
  91. */
  92. if (c->x86 == 6 && c->x86_model < 15)
  93. clear_cpu_cap(c, X86_FEATURE_PAT);
  94. #ifdef CONFIG_KMEMCHECK
  95. /*
  96. * P4s have a "fast strings" feature which causes single-
  97. * stepping REP instructions to only generate a #DB on
  98. * cache-line boundaries.
  99. *
  100. * Ingo Molnar reported a Pentium D (model 6) and a Xeon
  101. * (model 2) with the same problem.
  102. */
  103. if (c->x86 == 15) {
  104. u64 misc_enable;
  105. rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  106. if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
  107. printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
  108. misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
  109. wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  110. }
  111. }
  112. #endif
  113. }
  114. #ifdef CONFIG_X86_32
  115. /*
  116. * Early probe support logic for ppro memory erratum #50
  117. *
  118. * This is called before we do cpu ident work
  119. */
  120. int __cpuinit ppro_with_ram_bug(void)
  121. {
  122. /* Uses data from early_cpu_detect now */
  123. if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  124. boot_cpu_data.x86 == 6 &&
  125. boot_cpu_data.x86_model == 1 &&
  126. boot_cpu_data.x86_mask < 8) {
  127. printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  128. return 1;
  129. }
  130. return 0;
  131. }
  132. #ifdef CONFIG_X86_F00F_BUG
  133. static void __cpuinit trap_init_f00f_bug(void)
  134. {
  135. __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
  136. /*
  137. * Update the IDT descriptor and reload the IDT so that
  138. * it uses the read-only mapped virtual address.
  139. */
  140. idt_descr.address = fix_to_virt(FIX_F00F_IDT);
  141. load_idt(&idt_descr);
  142. }
  143. #endif
  144. static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
  145. {
  146. #ifdef CONFIG_SMP
  147. /* calling is from identify_secondary_cpu() ? */
  148. if (c->cpu_index == boot_cpu_id)
  149. return;
  150. /*
  151. * Mask B, Pentium, but not Pentium MMX
  152. */
  153. if (c->x86 == 5 &&
  154. c->x86_mask >= 1 && c->x86_mask <= 4 &&
  155. c->x86_model <= 3) {
  156. /*
  157. * Remember we have B step Pentia with bugs
  158. */
  159. WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
  160. "with B stepping processors.\n");
  161. }
  162. #endif
  163. }
  164. static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
  165. {
  166. unsigned long lo, hi;
  167. #ifdef CONFIG_X86_F00F_BUG
  168. /*
  169. * All current models of Pentium and Pentium with MMX technology CPUs
  170. * have the F0 0F bug, which lets nonprivileged users lock up the
  171. * system.
  172. * Note that the workaround only should be initialized once...
  173. */
  174. c->f00f_bug = 0;
  175. if (!paravirt_enabled() && c->x86 == 5) {
  176. static int f00f_workaround_enabled;
  177. c->f00f_bug = 1;
  178. if (!f00f_workaround_enabled) {
  179. trap_init_f00f_bug();
  180. printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
  181. f00f_workaround_enabled = 1;
  182. }
  183. }
  184. #endif
  185. /*
  186. * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
  187. * model 3 mask 3
  188. */
  189. if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
  190. clear_cpu_cap(c, X86_FEATURE_SEP);
  191. /*
  192. * P4 Xeon errata 037 workaround.
  193. * Hardware prefetcher may cause stale data to be loaded into the cache.
  194. */
  195. if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
  196. rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
  197. if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
  198. printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
  199. printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
  200. lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
  201. wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
  202. }
  203. }
  204. /*
  205. * See if we have a good local APIC by checking for buggy Pentia,
  206. * i.e. all B steppings and the C2 stepping of P54C when using their
  207. * integrated APIC (see 11AP erratum in "Pentium Processor
  208. * Specification Update").
  209. */
  210. if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
  211. (c->x86_mask < 0x6 || c->x86_mask == 0xb))
  212. set_cpu_cap(c, X86_FEATURE_11AP);
  213. #ifdef CONFIG_X86_INTEL_USERCOPY
  214. /*
  215. * Set up the preferred alignment for movsl bulk memory moves
  216. */
  217. switch (c->x86) {
  218. case 4: /* 486: untested */
  219. break;
  220. case 5: /* Old Pentia: untested */
  221. break;
  222. case 6: /* PII/PIII only like movsl with 8-byte alignment */
  223. movsl_mask.mask = 7;
  224. break;
  225. case 15: /* P4 is OK down to 8-byte alignment */
  226. movsl_mask.mask = 7;
  227. break;
  228. }
  229. #endif
  230. #ifdef CONFIG_X86_NUMAQ
  231. numaq_tsc_disable();
  232. #endif
  233. intel_smp_check(c);
  234. }
  235. #else
  236. static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
  237. {
  238. }
  239. #endif
  240. static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
  241. {
  242. #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
  243. unsigned node;
  244. int cpu = smp_processor_id();
  245. int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
  246. /* Don't do the funky fallback heuristics the AMD version employs
  247. for now. */
  248. node = apicid_to_node[apicid];
  249. if (node == NUMA_NO_NODE)
  250. node = first_node(node_online_map);
  251. else if (!node_online(node)) {
  252. /* reuse the value from init_cpu_to_node() */
  253. node = cpu_to_node(cpu);
  254. }
  255. numa_set_node(cpu, node);
  256. #endif
  257. }
  258. /*
  259. * find out the number of processor cores on the die
  260. */
  261. static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
  262. {
  263. unsigned int eax, ebx, ecx, edx;
  264. if (c->cpuid_level < 4)
  265. return 1;
  266. /* Intel has a non-standard dependency on %ecx for this CPUID level. */
  267. cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
  268. if (eax & 0x1f)
  269. return (eax >> 26) + 1;
  270. else
  271. return 1;
  272. }
  273. static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
  274. {
  275. /* Intel VMX MSR indicated features */
  276. #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
  277. #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
  278. #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
  279. #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
  280. #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
  281. #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
  282. u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
  283. clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
  284. clear_cpu_cap(c, X86_FEATURE_VNMI);
  285. clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
  286. clear_cpu_cap(c, X86_FEATURE_EPT);
  287. clear_cpu_cap(c, X86_FEATURE_VPID);
  288. rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
  289. msr_ctl = vmx_msr_high | vmx_msr_low;
  290. if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
  291. set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
  292. if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
  293. set_cpu_cap(c, X86_FEATURE_VNMI);
  294. if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
  295. rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
  296. vmx_msr_low, vmx_msr_high);
  297. msr_ctl2 = vmx_msr_high | vmx_msr_low;
  298. if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
  299. (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
  300. set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
  301. if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
  302. set_cpu_cap(c, X86_FEATURE_EPT);
  303. if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
  304. set_cpu_cap(c, X86_FEATURE_VPID);
  305. }
  306. }
  307. static void __cpuinit init_intel(struct cpuinfo_x86 *c)
  308. {
  309. unsigned int l2 = 0;
  310. early_init_intel(c);
  311. intel_workarounds(c);
  312. /*
  313. * Detect the extended topology information if available. This
  314. * will reinitialise the initial_apicid which will be used
  315. * in init_intel_cacheinfo()
  316. */
  317. detect_extended_topology(c);
  318. l2 = init_intel_cacheinfo(c);
  319. if (c->cpuid_level > 9) {
  320. unsigned eax = cpuid_eax(10);
  321. /* Check for version and the number of counters */
  322. if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
  323. set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
  324. }
  325. if (cpu_has_xmm2)
  326. set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
  327. if (cpu_has_ds) {
  328. unsigned int l1;
  329. rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
  330. if (!(l1 & (1<<11)))
  331. set_cpu_cap(c, X86_FEATURE_BTS);
  332. if (!(l1 & (1<<12)))
  333. set_cpu_cap(c, X86_FEATURE_PEBS);
  334. }
  335. if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
  336. set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
  337. #ifdef CONFIG_X86_64
  338. if (c->x86 == 15)
  339. c->x86_cache_alignment = c->x86_clflush_size * 2;
  340. if (c->x86 == 6)
  341. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  342. #else
  343. /*
  344. * Names for the Pentium II/Celeron processors
  345. * detectable only by also checking the cache size.
  346. * Dixon is NOT a Celeron.
  347. */
  348. if (c->x86 == 6) {
  349. char *p = NULL;
  350. switch (c->x86_model) {
  351. case 5:
  352. if (c->x86_mask == 0) {
  353. if (l2 == 0)
  354. p = "Celeron (Covington)";
  355. else if (l2 == 256)
  356. p = "Mobile Pentium II (Dixon)";
  357. }
  358. break;
  359. case 6:
  360. if (l2 == 128)
  361. p = "Celeron (Mendocino)";
  362. else if (c->x86_mask == 0 || c->x86_mask == 5)
  363. p = "Celeron-A";
  364. break;
  365. case 8:
  366. if (l2 == 128)
  367. p = "Celeron (Coppermine)";
  368. break;
  369. }
  370. if (p)
  371. strcpy(c->x86_model_id, p);
  372. }
  373. if (c->x86 == 15)
  374. set_cpu_cap(c, X86_FEATURE_P4);
  375. if (c->x86 == 6)
  376. set_cpu_cap(c, X86_FEATURE_P3);
  377. #endif
  378. if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
  379. /*
  380. * let's use the legacy cpuid vector 0x1 and 0x4 for topology
  381. * detection.
  382. */
  383. c->x86_max_cores = intel_num_cpu_cores(c);
  384. #ifdef CONFIG_X86_32
  385. detect_ht(c);
  386. #endif
  387. }
  388. /* Work around errata */
  389. srat_detect_node(c);
  390. if (cpu_has(c, X86_FEATURE_VMX))
  391. detect_vmx_virtcap(c);
  392. }
  393. #ifdef CONFIG_X86_32
  394. static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
  395. {
  396. /*
  397. * Intel PIII Tualatin. This comes in two flavours.
  398. * One has 256kb of cache, the other 512. We have no way
  399. * to determine which, so we use a boottime override
  400. * for the 512kb model, and assume 256 otherwise.
  401. */
  402. if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
  403. size = 256;
  404. return size;
  405. }
  406. #endif
  407. static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
  408. .c_vendor = "Intel",
  409. .c_ident = { "GenuineIntel" },
  410. #ifdef CONFIG_X86_32
  411. .c_models = {
  412. { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
  413. {
  414. [0] = "486 DX-25/33",
  415. [1] = "486 DX-50",
  416. [2] = "486 SX",
  417. [3] = "486 DX/2",
  418. [4] = "486 SL",
  419. [5] = "486 SX/2",
  420. [7] = "486 DX/2-WB",
  421. [8] = "486 DX/4",
  422. [9] = "486 DX/4-WB"
  423. }
  424. },
  425. { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
  426. {
  427. [0] = "Pentium 60/66 A-step",
  428. [1] = "Pentium 60/66",
  429. [2] = "Pentium 75 - 200",
  430. [3] = "OverDrive PODP5V83",
  431. [4] = "Pentium MMX",
  432. [7] = "Mobile Pentium 75 - 200",
  433. [8] = "Mobile Pentium MMX"
  434. }
  435. },
  436. { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
  437. {
  438. [0] = "Pentium Pro A-step",
  439. [1] = "Pentium Pro",
  440. [3] = "Pentium II (Klamath)",
  441. [4] = "Pentium II (Deschutes)",
  442. [5] = "Pentium II (Deschutes)",
  443. [6] = "Mobile Pentium II",
  444. [7] = "Pentium III (Katmai)",
  445. [8] = "Pentium III (Coppermine)",
  446. [10] = "Pentium III (Cascades)",
  447. [11] = "Pentium III (Tualatin)",
  448. }
  449. },
  450. { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
  451. {
  452. [0] = "Pentium 4 (Unknown)",
  453. [1] = "Pentium 4 (Willamette)",
  454. [2] = "Pentium 4 (Northwood)",
  455. [4] = "Pentium 4 (Foster)",
  456. [5] = "Pentium 4 (Foster)",
  457. }
  458. },
  459. },
  460. .c_size_cache = intel_size_cache,
  461. #endif
  462. .c_early_init = early_init_intel,
  463. .c_init = init_intel,
  464. .c_x86_vendor = X86_VENDOR_INTEL,
  465. };
  466. cpu_dev_register(intel_cpu_dev);