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/drivers/spi/xilinx_spi.c

https://github.com/gnarlyc/desirec_2.6.29
C | 463 lines | 304 code | 86 blank | 73 comment | 37 complexity | 27670570b8a41b9a2de8b40301aa2300 MD5 | raw file
  1. /*
  2. * xilinx_spi.c
  3. *
  4. * Xilinx SPI controller driver (master mode only)
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * source@mvista.com
  8. *
  9. * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is licensed
  11. * "as is" without any warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/of_device.h>
  19. #include <linux/of_spi.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/spi/spi_bitbang.h>
  22. #include <linux/io.h>
  23. #define XILINX_SPI_NAME "xilinx_spi"
  24. /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
  25. * Product Specification", DS464
  26. */
  27. #define XSPI_CR_OFFSET 0x62 /* 16-bit Control Register */
  28. #define XSPI_CR_ENABLE 0x02
  29. #define XSPI_CR_MASTER_MODE 0x04
  30. #define XSPI_CR_CPOL 0x08
  31. #define XSPI_CR_CPHA 0x10
  32. #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
  33. #define XSPI_CR_TXFIFO_RESET 0x20
  34. #define XSPI_CR_RXFIFO_RESET 0x40
  35. #define XSPI_CR_MANUAL_SSELECT 0x80
  36. #define XSPI_CR_TRANS_INHIBIT 0x100
  37. #define XSPI_SR_OFFSET 0x67 /* 8-bit Status Register */
  38. #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
  39. #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
  40. #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
  41. #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
  42. #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
  43. #define XSPI_TXD_OFFSET 0x6b /* 8-bit Data Transmit Register */
  44. #define XSPI_RXD_OFFSET 0x6f /* 8-bit Data Receive Register */
  45. #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
  46. /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
  47. * IPIF registers are 32 bit
  48. */
  49. #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
  50. #define XIPIF_V123B_GINTR_ENABLE 0x80000000
  51. #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
  52. #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
  53. #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
  54. #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
  55. * disabled */
  56. #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
  57. #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
  58. #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
  59. #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
  60. #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
  61. #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
  62. struct xilinx_spi {
  63. /* bitbang has to be first */
  64. struct spi_bitbang bitbang;
  65. struct completion done;
  66. void __iomem *regs; /* virt. address of the control registers */
  67. u32 irq;
  68. u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
  69. u8 *rx_ptr; /* pointer in the Tx buffer */
  70. const u8 *tx_ptr; /* pointer in the Rx buffer */
  71. int remaining_bytes; /* the number of bytes left to transfer */
  72. };
  73. static void xspi_init_hw(void __iomem *regs_base)
  74. {
  75. /* Reset the SPI device */
  76. out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET,
  77. XIPIF_V123B_RESET_MASK);
  78. /* Disable all the interrupts just in case */
  79. out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
  80. /* Enable the global IPIF interrupt */
  81. out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET,
  82. XIPIF_V123B_GINTR_ENABLE);
  83. /* Deselect the slave on the SPI bus */
  84. out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff);
  85. /* Disable the transmitter, enable Manual Slave Select Assertion,
  86. * put SPI controller into master mode, and enable it */
  87. out_be16(regs_base + XSPI_CR_OFFSET,
  88. XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT
  89. | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE);
  90. }
  91. static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
  92. {
  93. struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
  94. if (is_on == BITBANG_CS_INACTIVE) {
  95. /* Deselect the slave on the SPI bus */
  96. out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff);
  97. } else if (is_on == BITBANG_CS_ACTIVE) {
  98. /* Set the SPI clock phase and polarity */
  99. u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET)
  100. & ~XSPI_CR_MODE_MASK;
  101. if (spi->mode & SPI_CPHA)
  102. cr |= XSPI_CR_CPHA;
  103. if (spi->mode & SPI_CPOL)
  104. cr |= XSPI_CR_CPOL;
  105. out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
  106. /* We do not check spi->max_speed_hz here as the SPI clock
  107. * frequency is not software programmable (the IP block design
  108. * parameter)
  109. */
  110. /* Activate the chip select */
  111. out_be32(xspi->regs + XSPI_SSR_OFFSET,
  112. ~(0x0001 << spi->chip_select));
  113. }
  114. }
  115. /* spi_bitbang requires custom setup_transfer() to be defined if there is a
  116. * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
  117. * supports just 8 bits per word, and SPI clock can't be changed in software.
  118. * Check for 8 bits per word. Chip select delay calculations could be
  119. * added here as soon as bitbang_work() can be made aware of the delay value.
  120. */
  121. static int xilinx_spi_setup_transfer(struct spi_device *spi,
  122. struct spi_transfer *t)
  123. {
  124. u8 bits_per_word;
  125. bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
  126. if (bits_per_word != 8) {
  127. dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
  128. __func__, bits_per_word);
  129. return -EINVAL;
  130. }
  131. return 0;
  132. }
  133. /* the spi->mode bits understood by this driver: */
  134. #define MODEBITS (SPI_CPOL | SPI_CPHA)
  135. static int xilinx_spi_setup(struct spi_device *spi)
  136. {
  137. struct spi_bitbang *bitbang;
  138. struct xilinx_spi *xspi;
  139. int retval;
  140. xspi = spi_master_get_devdata(spi->master);
  141. bitbang = &xspi->bitbang;
  142. if (!spi->bits_per_word)
  143. spi->bits_per_word = 8;
  144. if (spi->mode & ~MODEBITS) {
  145. dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
  146. __func__, spi->mode & ~MODEBITS);
  147. return -EINVAL;
  148. }
  149. retval = xilinx_spi_setup_transfer(spi, NULL);
  150. if (retval < 0)
  151. return retval;
  152. dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
  153. __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
  154. return 0;
  155. }
  156. static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
  157. {
  158. u8 sr;
  159. /* Fill the Tx FIFO with as many bytes as possible */
  160. sr = in_8(xspi->regs + XSPI_SR_OFFSET);
  161. while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
  162. if (xspi->tx_ptr) {
  163. out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
  164. } else {
  165. out_8(xspi->regs + XSPI_TXD_OFFSET, 0);
  166. }
  167. xspi->remaining_bytes--;
  168. sr = in_8(xspi->regs + XSPI_SR_OFFSET);
  169. }
  170. }
  171. static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
  172. {
  173. struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
  174. u32 ipif_ier;
  175. u16 cr;
  176. /* We get here with transmitter inhibited */
  177. xspi->tx_ptr = t->tx_buf;
  178. xspi->rx_ptr = t->rx_buf;
  179. xspi->remaining_bytes = t->len;
  180. INIT_COMPLETION(xspi->done);
  181. xilinx_spi_fill_tx_fifo(xspi);
  182. /* Enable the transmit empty interrupt, which we use to determine
  183. * progress on the transmission.
  184. */
  185. ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET);
  186. out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET,
  187. ipif_ier | XSPI_INTR_TX_EMPTY);
  188. /* Start the transfer by not inhibiting the transmitter any longer */
  189. cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
  190. out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
  191. wait_for_completion(&xspi->done);
  192. /* Disable the transmit empty interrupt */
  193. out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier);
  194. return t->len - xspi->remaining_bytes;
  195. }
  196. /* This driver supports single master mode only. Hence Tx FIFO Empty
  197. * is the only interrupt we care about.
  198. * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
  199. * Fault are not to happen.
  200. */
  201. static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
  202. {
  203. struct xilinx_spi *xspi = dev_id;
  204. u32 ipif_isr;
  205. /* Get the IPIF interrupts, and clear them immediately */
  206. ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET);
  207. out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr);
  208. if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
  209. u16 cr;
  210. u8 sr;
  211. /* A transmit has just completed. Process received data and
  212. * check for more data to transmit. Always inhibit the
  213. * transmitter while the Isr refills the transmit register/FIFO,
  214. * or make sure it is stopped if we're done.
  215. */
  216. cr = in_be16(xspi->regs + XSPI_CR_OFFSET);
  217. out_be16(xspi->regs + XSPI_CR_OFFSET,
  218. cr | XSPI_CR_TRANS_INHIBIT);
  219. /* Read out all the data from the Rx FIFO */
  220. sr = in_8(xspi->regs + XSPI_SR_OFFSET);
  221. while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
  222. u8 data;
  223. data = in_8(xspi->regs + XSPI_RXD_OFFSET);
  224. if (xspi->rx_ptr) {
  225. *xspi->rx_ptr++ = data;
  226. }
  227. sr = in_8(xspi->regs + XSPI_SR_OFFSET);
  228. }
  229. /* See if there is more data to send */
  230. if (xspi->remaining_bytes > 0) {
  231. xilinx_spi_fill_tx_fifo(xspi);
  232. /* Start the transfer by not inhibiting the
  233. * transmitter any longer
  234. */
  235. out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
  236. } else {
  237. /* No more data to send.
  238. * Indicate the transfer is completed.
  239. */
  240. complete(&xspi->done);
  241. }
  242. }
  243. return IRQ_HANDLED;
  244. }
  245. static int __init xilinx_spi_of_probe(struct of_device *ofdev,
  246. const struct of_device_id *match)
  247. {
  248. struct spi_master *master;
  249. struct xilinx_spi *xspi;
  250. struct resource r_irq_struct;
  251. struct resource r_mem_struct;
  252. struct resource *r_irq = &r_irq_struct;
  253. struct resource *r_mem = &r_mem_struct;
  254. int rc = 0;
  255. const u32 *prop;
  256. int len;
  257. /* Get resources(memory, IRQ) associated with the device */
  258. master = spi_alloc_master(&ofdev->dev, sizeof(struct xilinx_spi));
  259. if (master == NULL) {
  260. return -ENOMEM;
  261. }
  262. dev_set_drvdata(&ofdev->dev, master);
  263. rc = of_address_to_resource(ofdev->node, 0, r_mem);
  264. if (rc) {
  265. dev_warn(&ofdev->dev, "invalid address\n");
  266. goto put_master;
  267. }
  268. rc = of_irq_to_resource(ofdev->node, 0, r_irq);
  269. if (rc == NO_IRQ) {
  270. dev_warn(&ofdev->dev, "no IRQ found\n");
  271. goto put_master;
  272. }
  273. xspi = spi_master_get_devdata(master);
  274. xspi->bitbang.master = spi_master_get(master);
  275. xspi->bitbang.chipselect = xilinx_spi_chipselect;
  276. xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
  277. xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
  278. xspi->bitbang.master->setup = xilinx_spi_setup;
  279. init_completion(&xspi->done);
  280. xspi->irq = r_irq->start;
  281. if (!request_mem_region(r_mem->start,
  282. r_mem->end - r_mem->start + 1, XILINX_SPI_NAME)) {
  283. rc = -ENXIO;
  284. dev_warn(&ofdev->dev, "memory request failure\n");
  285. goto put_master;
  286. }
  287. xspi->regs = ioremap(r_mem->start, r_mem->end - r_mem->start + 1);
  288. if (xspi->regs == NULL) {
  289. rc = -ENOMEM;
  290. dev_warn(&ofdev->dev, "ioremap failure\n");
  291. goto put_master;
  292. }
  293. xspi->irq = r_irq->start;
  294. /* dynamic bus assignment */
  295. master->bus_num = -1;
  296. /* number of slave select bits is required */
  297. prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len);
  298. if (!prop || len < sizeof(*prop)) {
  299. dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n");
  300. goto put_master;
  301. }
  302. master->num_chipselect = *prop;
  303. /* SPI controller initializations */
  304. xspi_init_hw(xspi->regs);
  305. /* Register for SPI Interrupt */
  306. rc = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
  307. if (rc != 0) {
  308. dev_warn(&ofdev->dev, "irq request failure: %d\n", xspi->irq);
  309. goto unmap_io;
  310. }
  311. rc = spi_bitbang_start(&xspi->bitbang);
  312. if (rc != 0) {
  313. dev_err(&ofdev->dev, "spi_bitbang_start FAILED\n");
  314. goto free_irq;
  315. }
  316. dev_info(&ofdev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
  317. (unsigned int)r_mem->start, (u32)xspi->regs, xspi->irq);
  318. /* Add any subnodes on the SPI bus */
  319. of_register_spi_devices(master, ofdev->node);
  320. return rc;
  321. free_irq:
  322. free_irq(xspi->irq, xspi);
  323. unmap_io:
  324. iounmap(xspi->regs);
  325. put_master:
  326. spi_master_put(master);
  327. return rc;
  328. }
  329. static int __devexit xilinx_spi_remove(struct of_device *ofdev)
  330. {
  331. struct xilinx_spi *xspi;
  332. struct spi_master *master;
  333. master = platform_get_drvdata(ofdev);
  334. xspi = spi_master_get_devdata(master);
  335. spi_bitbang_stop(&xspi->bitbang);
  336. free_irq(xspi->irq, xspi);
  337. iounmap(xspi->regs);
  338. dev_set_drvdata(&ofdev->dev, 0);
  339. spi_master_put(xspi->bitbang.master);
  340. return 0;
  341. }
  342. /* work with hotplug and coldplug */
  343. MODULE_ALIAS("platform:" XILINX_SPI_NAME);
  344. static int __exit xilinx_spi_of_remove(struct of_device *op)
  345. {
  346. return xilinx_spi_remove(op);
  347. }
  348. static struct of_device_id xilinx_spi_of_match[] = {
  349. { .compatible = "xlnx,xps-spi-2.00.a", },
  350. { .compatible = "xlnx,xps-spi-2.00.b", },
  351. {}
  352. };
  353. MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
  354. static struct of_platform_driver xilinx_spi_of_driver = {
  355. .owner = THIS_MODULE,
  356. .name = "xilinx-xps-spi",
  357. .match_table = xilinx_spi_of_match,
  358. .probe = xilinx_spi_of_probe,
  359. .remove = __exit_p(xilinx_spi_of_remove),
  360. .driver = {
  361. .name = "xilinx-xps-spi",
  362. .owner = THIS_MODULE,
  363. },
  364. };
  365. static int __init xilinx_spi_init(void)
  366. {
  367. return of_register_platform_driver(&xilinx_spi_of_driver);
  368. }
  369. module_init(xilinx_spi_init);
  370. static void __exit xilinx_spi_exit(void)
  371. {
  372. of_unregister_platform_driver(&xilinx_spi_of_driver);
  373. }
  374. module_exit(xilinx_spi_exit);
  375. MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
  376. MODULE_DESCRIPTION("Xilinx SPI driver");
  377. MODULE_LICENSE("GPL");