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/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c

https://github.com/robclark/kernel-omap4
C | 420 lines | 336 code | 52 blank | 32 comment | 22 complexity | 665a6611c45b306e3d67e77beb8b1bde MD5 | raw file
  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <core/os.h>
  25. #include <core/client.h>
  26. #include <core/engctx.h>
  27. #include <core/ramht.h>
  28. #include <core/class.h>
  29. #include <core/math.h>
  30. #include <subdev/timer.h>
  31. #include <subdev/bar.h>
  32. #include <engine/dmaobj.h>
  33. #include <engine/fifo.h>
  34. #include "nv50.h"
  35. /*******************************************************************************
  36. * FIFO channel objects
  37. ******************************************************************************/
  38. static int
  39. nv84_fifo_context_attach(struct nouveau_object *parent,
  40. struct nouveau_object *object)
  41. {
  42. struct nouveau_bar *bar = nouveau_bar(parent);
  43. struct nv50_fifo_base *base = (void *)parent->parent;
  44. struct nouveau_gpuobj *ectx = (void *)object;
  45. u64 limit = ectx->addr + ectx->size - 1;
  46. u64 start = ectx->addr;
  47. u32 addr;
  48. switch (nv_engidx(object->engine)) {
  49. case NVDEV_ENGINE_SW : return 0;
  50. case NVDEV_ENGINE_GR : addr = 0x0020; break;
  51. case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
  52. case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
  53. case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
  54. default:
  55. return -EINVAL;
  56. }
  57. nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  58. nv_wo32(base->eng, addr + 0x00, 0x00190000);
  59. nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  60. nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  61. nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  62. upper_32_bits(start));
  63. nv_wo32(base->eng, addr + 0x10, 0x00000000);
  64. nv_wo32(base->eng, addr + 0x14, 0x00000000);
  65. bar->flush(bar);
  66. return 0;
  67. }
  68. static int
  69. nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
  70. struct nouveau_object *object)
  71. {
  72. struct nouveau_bar *bar = nouveau_bar(parent);
  73. struct nv50_fifo_priv *priv = (void *)parent->engine;
  74. struct nv50_fifo_base *base = (void *)parent->parent;
  75. struct nv50_fifo_chan *chan = (void *)parent;
  76. u32 addr, save, engn;
  77. bool done;
  78. switch (nv_engidx(object->engine)) {
  79. case NVDEV_ENGINE_SW : return 0;
  80. case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
  81. case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
  82. case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
  83. case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
  84. default:
  85. return -EINVAL;
  86. }
  87. save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
  88. nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
  89. done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
  90. nv_wr32(priv, 0x002520, save);
  91. if (!done) {
  92. nv_error(priv, "channel %d unload timeout\n", chan->base.chid);
  93. if (suspend)
  94. return -EBUSY;
  95. }
  96. nv_wo32(base->eng, addr + 0x00, 0x00000000);
  97. nv_wo32(base->eng, addr + 0x04, 0x00000000);
  98. nv_wo32(base->eng, addr + 0x08, 0x00000000);
  99. nv_wo32(base->eng, addr + 0x0c, 0x00000000);
  100. nv_wo32(base->eng, addr + 0x10, 0x00000000);
  101. nv_wo32(base->eng, addr + 0x14, 0x00000000);
  102. bar->flush(bar);
  103. return 0;
  104. }
  105. static int
  106. nv84_fifo_object_attach(struct nouveau_object *parent,
  107. struct nouveau_object *object, u32 handle)
  108. {
  109. struct nv50_fifo_chan *chan = (void *)parent;
  110. u32 context;
  111. if (nv_iclass(object, NV_GPUOBJ_CLASS))
  112. context = nv_gpuobj(object)->node->offset >> 4;
  113. else
  114. context = 0x00000004; /* just non-zero */
  115. switch (nv_engidx(object->engine)) {
  116. case NVDEV_ENGINE_DMAOBJ:
  117. case NVDEV_ENGINE_SW : context |= 0x00000000; break;
  118. case NVDEV_ENGINE_GR : context |= 0x00100000; break;
  119. case NVDEV_ENGINE_MPEG :
  120. case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
  121. case NVDEV_ENGINE_ME :
  122. case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
  123. case NVDEV_ENGINE_VP : context |= 0x00400000; break;
  124. case NVDEV_ENGINE_CRYPT :
  125. case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
  126. case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
  127. default:
  128. return -EINVAL;
  129. }
  130. return nouveau_ramht_insert(chan->ramht, 0, handle, context);
  131. }
  132. static int
  133. nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
  134. struct nouveau_object *engine,
  135. struct nouveau_oclass *oclass, void *data, u32 size,
  136. struct nouveau_object **pobject)
  137. {
  138. struct nouveau_bar *bar = nouveau_bar(parent);
  139. struct nv50_fifo_base *base = (void *)parent;
  140. struct nv50_fifo_chan *chan;
  141. struct nv03_channel_dma_class *args = data;
  142. int ret;
  143. if (size < sizeof(*args))
  144. return -EINVAL;
  145. ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
  146. 0x2000, args->pushbuf,
  147. (1ULL << NVDEV_ENGINE_DMAOBJ) |
  148. (1ULL << NVDEV_ENGINE_SW) |
  149. (1ULL << NVDEV_ENGINE_GR) |
  150. (1ULL << NVDEV_ENGINE_MPEG) |
  151. (1ULL << NVDEV_ENGINE_ME) |
  152. (1ULL << NVDEV_ENGINE_VP) |
  153. (1ULL << NVDEV_ENGINE_CRYPT) |
  154. (1ULL << NVDEV_ENGINE_BSP) |
  155. (1ULL << NVDEV_ENGINE_PPP) |
  156. (1ULL << NVDEV_ENGINE_COPY0) |
  157. (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
  158. *pobject = nv_object(chan);
  159. if (ret)
  160. return ret;
  161. ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
  162. if (ret)
  163. return ret;
  164. nv_parent(chan)->context_attach = nv84_fifo_context_attach;
  165. nv_parent(chan)->context_detach = nv84_fifo_context_detach;
  166. nv_parent(chan)->object_attach = nv84_fifo_object_attach;
  167. nv_parent(chan)->object_detach = nv50_fifo_object_detach;
  168. nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
  169. nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
  170. nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
  171. nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
  172. nv_wo32(base->ramfc, 0x3c, 0x003f6078);
  173. nv_wo32(base->ramfc, 0x44, 0x01003fff);
  174. nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
  175. nv_wo32(base->ramfc, 0x4c, 0xffffffff);
  176. nv_wo32(base->ramfc, 0x60, 0x7fffffff);
  177. nv_wo32(base->ramfc, 0x78, 0x00000000);
  178. nv_wo32(base->ramfc, 0x7c, 0x30000001);
  179. nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
  180. (4 << 24) /* SEARCH_FULL */ |
  181. (chan->ramht->base.node->offset >> 4));
  182. nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
  183. nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
  184. bar->flush(bar);
  185. return 0;
  186. }
  187. static int
  188. nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
  189. struct nouveau_object *engine,
  190. struct nouveau_oclass *oclass, void *data, u32 size,
  191. struct nouveau_object **pobject)
  192. {
  193. struct nouveau_bar *bar = nouveau_bar(parent);
  194. struct nv50_fifo_base *base = (void *)parent;
  195. struct nv50_fifo_chan *chan;
  196. struct nv50_channel_ind_class *args = data;
  197. u64 ioffset, ilength;
  198. int ret;
  199. if (size < sizeof(*args))
  200. return -EINVAL;
  201. ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
  202. 0x2000, args->pushbuf,
  203. (1ULL << NVDEV_ENGINE_DMAOBJ) |
  204. (1ULL << NVDEV_ENGINE_SW) |
  205. (1ULL << NVDEV_ENGINE_GR) |
  206. (1ULL << NVDEV_ENGINE_MPEG) |
  207. (1ULL << NVDEV_ENGINE_ME) |
  208. (1ULL << NVDEV_ENGINE_VP) |
  209. (1ULL << NVDEV_ENGINE_CRYPT) |
  210. (1ULL << NVDEV_ENGINE_BSP) |
  211. (1ULL << NVDEV_ENGINE_PPP) |
  212. (1ULL << NVDEV_ENGINE_COPY0) |
  213. (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
  214. *pobject = nv_object(chan);
  215. if (ret)
  216. return ret;
  217. ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
  218. if (ret)
  219. return ret;
  220. nv_parent(chan)->context_attach = nv84_fifo_context_attach;
  221. nv_parent(chan)->context_detach = nv84_fifo_context_detach;
  222. nv_parent(chan)->object_attach = nv84_fifo_object_attach;
  223. nv_parent(chan)->object_detach = nv50_fifo_object_detach;
  224. ioffset = args->ioffset;
  225. ilength = log2i(args->ilength / 8);
  226. nv_wo32(base->ramfc, 0x3c, 0x403f6078);
  227. nv_wo32(base->ramfc, 0x44, 0x01003fff);
  228. nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
  229. nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
  230. nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
  231. nv_wo32(base->ramfc, 0x60, 0x7fffffff);
  232. nv_wo32(base->ramfc, 0x78, 0x00000000);
  233. nv_wo32(base->ramfc, 0x7c, 0x30000001);
  234. nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
  235. (4 << 24) /* SEARCH_FULL */ |
  236. (chan->ramht->base.node->offset >> 4));
  237. nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
  238. nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
  239. bar->flush(bar);
  240. return 0;
  241. }
  242. static int
  243. nv84_fifo_chan_init(struct nouveau_object *object)
  244. {
  245. struct nv50_fifo_priv *priv = (void *)object->engine;
  246. struct nv50_fifo_base *base = (void *)object->parent;
  247. struct nv50_fifo_chan *chan = (void *)object;
  248. struct nouveau_gpuobj *ramfc = base->ramfc;
  249. u32 chid = chan->base.chid;
  250. int ret;
  251. ret = nouveau_fifo_channel_init(&chan->base);
  252. if (ret)
  253. return ret;
  254. nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
  255. nv50_fifo_playlist_update(priv);
  256. return 0;
  257. }
  258. static struct nouveau_ofuncs
  259. nv84_fifo_ofuncs_dma = {
  260. .ctor = nv84_fifo_chan_ctor_dma,
  261. .dtor = nv50_fifo_chan_dtor,
  262. .init = nv84_fifo_chan_init,
  263. .fini = nv50_fifo_chan_fini,
  264. .rd32 = _nouveau_fifo_channel_rd32,
  265. .wr32 = _nouveau_fifo_channel_wr32,
  266. };
  267. static struct nouveau_ofuncs
  268. nv84_fifo_ofuncs_ind = {
  269. .ctor = nv84_fifo_chan_ctor_ind,
  270. .dtor = nv50_fifo_chan_dtor,
  271. .init = nv84_fifo_chan_init,
  272. .fini = nv50_fifo_chan_fini,
  273. .rd32 = _nouveau_fifo_channel_rd32,
  274. .wr32 = _nouveau_fifo_channel_wr32,
  275. };
  276. static struct nouveau_oclass
  277. nv84_fifo_sclass[] = {
  278. { NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma },
  279. { NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind },
  280. {}
  281. };
  282. /*******************************************************************************
  283. * FIFO context - basically just the instmem reserved for the channel
  284. ******************************************************************************/
  285. static int
  286. nv84_fifo_context_ctor(struct nouveau_object *parent,
  287. struct nouveau_object *engine,
  288. struct nouveau_oclass *oclass, void *data, u32 size,
  289. struct nouveau_object **pobject)
  290. {
  291. struct nv50_fifo_base *base;
  292. int ret;
  293. ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
  294. 0x1000, NVOBJ_FLAG_HEAP, &base);
  295. *pobject = nv_object(base);
  296. if (ret)
  297. return ret;
  298. ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0200, 0,
  299. NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
  300. if (ret)
  301. return ret;
  302. ret = nouveau_gpuobj_new(parent, nv_object(base), 0x4000, 0,
  303. 0, &base->pgd);
  304. if (ret)
  305. return ret;
  306. ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
  307. if (ret)
  308. return ret;
  309. ret = nouveau_gpuobj_new(parent, nv_object(base), 0x1000, 0x400,
  310. NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
  311. if (ret)
  312. return ret;
  313. ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0100, 0x100,
  314. NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
  315. if (ret)
  316. return ret;
  317. return 0;
  318. }
  319. static struct nouveau_oclass
  320. nv84_fifo_cclass = {
  321. .handle = NV_ENGCTX(FIFO, 0x84),
  322. .ofuncs = &(struct nouveau_ofuncs) {
  323. .ctor = nv84_fifo_context_ctor,
  324. .dtor = nv50_fifo_context_dtor,
  325. .init = _nouveau_fifo_context_init,
  326. .fini = _nouveau_fifo_context_fini,
  327. .rd32 = _nouveau_fifo_context_rd32,
  328. .wr32 = _nouveau_fifo_context_wr32,
  329. },
  330. };
  331. /*******************************************************************************
  332. * PFIFO engine
  333. ******************************************************************************/
  334. static int
  335. nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  336. struct nouveau_oclass *oclass, void *data, u32 size,
  337. struct nouveau_object **pobject)
  338. {
  339. struct nv50_fifo_priv *priv;
  340. int ret;
  341. ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
  342. *pobject = nv_object(priv);
  343. if (ret)
  344. return ret;
  345. ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
  346. &priv->playlist[0]);
  347. if (ret)
  348. return ret;
  349. ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
  350. &priv->playlist[1]);
  351. if (ret)
  352. return ret;
  353. nv_subdev(priv)->unit = 0x00000100;
  354. nv_subdev(priv)->intr = nv04_fifo_intr;
  355. nv_engine(priv)->cclass = &nv84_fifo_cclass;
  356. nv_engine(priv)->sclass = nv84_fifo_sclass;
  357. return 0;
  358. }
  359. struct nouveau_oclass
  360. nv84_fifo_oclass = {
  361. .handle = NV_ENGINE(FIFO, 0x84),
  362. .ofuncs = &(struct nouveau_ofuncs) {
  363. .ctor = nv84_fifo_ctor,
  364. .dtor = nv50_fifo_dtor,
  365. .init = nv50_fifo_init,
  366. .fini = _nouveau_fifo_fini,
  367. },
  368. };