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    33. 

  33. <h1>stm32f10x_map.h</h1><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************</span>
    34. 

  34. <a name="l00002"></a>00002 <span class="comment">* File Name          : stm32f10x_map.h</span>
    35. 

  35. <a name="l00003"></a>00003 <span class="comment">* Author             : MCD Application Team</span>
    36. 

  36. <a name="l00004"></a>00004 <span class="comment">* Version            : V2.0.3</span>
    37. 

  37. <a name="l00005"></a>00005 <span class="comment">* Date               : 09/22/2008</span>
    38. 

  38. <a name="l00006"></a>00006 <span class="comment">* Description        : This file contains all the peripheral register&apos;s definitions,</span>
    39. 

  39. <a name="l00007"></a>00007 <span class="comment">*                      bits definitions and memory mapping.</span>
    40. 

  40. <a name="l00008"></a>00008 <span class="comment">********************************************************************************</span>
    41. 

  41. <a name="l00009"></a>00009 <span class="comment">* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS</span>
    42. 

  42. <a name="l00010"></a>00010 <span class="comment">* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.</span>
    43. 

  43. <a name="l00011"></a>00011 <span class="comment">* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,</span>
    44. 

  44. <a name="l00012"></a>00012 <span class="comment">* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE</span>
    45. 

  45. <a name="l00013"></a>00013 <span class="comment">* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING</span>
    46. 

  46. <a name="l00014"></a>00014 <span class="comment">* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.</span>
    47. 

  47. <a name="l00015"></a>00015 <span class="comment">*******************************************************************************/</span>
    48. 

  48. <a name="l00016"></a>00016 
    49. 

  49. <a name="l00017"></a>00017 <span class="comment">/* Define to prevent recursive inclusion -------------------------------------*/</span>
    50. 

  50. <a name="l00018"></a>00018 <span class="preprocessor">#ifndef __STM32F10x_MAP_H</span>
    51. 

  51. <a name="l00019"></a>00019 <span class="preprocessor"></span><span class="preprocessor">#define __STM32F10x_MAP_H</span>
    52. 

  52. <a name="l00020"></a>00020 <span class="preprocessor"></span>
    53. 

  53. <a name="l00021"></a>00021 <span class="preprocessor">#ifndef EXT</span>
    54. 

  54. <a name="l00022"></a>00022 <span class="preprocessor"></span><span class="preprocessor">  #define EXT extern</span>
    55. 

  55. <a name="l00023"></a>00023 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/* EXT */</span>
    56. 

  56. <a name="l00024"></a>00024 
    57. 

  57. <a name="l00025"></a>00025 <span class="comment">/* Includes ------------------------------------------------------------------*/</span>
    58. 

  58. <a name="l00026"></a>00026 <span class="preprocessor">#include &quot;stm32f10x_conf.h&quot;</span>
    59. 

  59. <a name="l00027"></a>00027 <span class="preprocessor">#include &quot;stm32f10x_type.h&quot;</span>
    60. 

  60. <a name="l00028"></a>00028 <span class="preprocessor">#include &quot;cortexm3_macro.h&quot;</span>
    61. 

  61. <a name="l00029"></a>00029 
    62. 

  62. <a name="l00030"></a>00030 <span class="comment">/* Exported types ------------------------------------------------------------*/</span>
    63. 

  63. <a name="l00031"></a>00031 <span class="comment">/******************************************************************************/</span>
    64. 

  64. <a name="l00032"></a>00032 <span class="comment">/*                         Peripheral registers structures                    */</span>
    65. 

  65. <a name="l00033"></a>00033 <span class="comment">/******************************************************************************/</span>
    66. 

  66. <a name="l00034"></a>00034 
    67. 

  67. <a name="l00035"></a>00035 <span class="comment">/*------------------------ Analog to Digital Converter -----------------------*/</span>
    68. 

  68. <a name="l00036"></a>00036 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    69. 

  69. <a name="l00037"></a>00037 {
    70. 

  70. <a name="l00038"></a>00038   vu32 SR;
    71. 

  71. <a name="l00039"></a>00039   vu32 CR1;
    72. 

  72. <a name="l00040"></a>00040   vu32 CR2;
    73. 

  73. <a name="l00041"></a>00041   vu32 SMPR1;
    74. 

  74. <a name="l00042"></a>00042   vu32 SMPR2;
    75. 

  75. <a name="l00043"></a>00043   vu32 JOFR1;
    76. 

  76. <a name="l00044"></a>00044   vu32 JOFR2;
    77. 

  77. <a name="l00045"></a>00045   vu32 JOFR3;
    78. 

  78. <a name="l00046"></a>00046   vu32 JOFR4;
    79. 

  79. <a name="l00047"></a>00047   vu32 HTR;
    80. 

  80. <a name="l00048"></a>00048   vu32 LTR;
    81. 

  81. <a name="l00049"></a>00049   vu32 SQR1;
    82. 

  82. <a name="l00050"></a>00050   vu32 SQR2;
    83. 

  83. <a name="l00051"></a>00051   vu32 SQR3;
    84. 

  84. <a name="l00052"></a>00052   vu32 JSQR;
    85. 

  85. <a name="l00053"></a>00053   vu32 JDR1;
    86. 

  86. <a name="l00054"></a>00054   vu32 JDR2;
    87. 

  87. <a name="l00055"></a>00055   vu32 JDR3;
    88. 

  88. <a name="l00056"></a>00056   vu32 JDR4;
    89. 

  89. <a name="l00057"></a>00057   vu32 DR;
    90. 

  90. <a name="l00058"></a>00058 } ADC_TypeDef;
    91. 

  91. <a name="l00059"></a>00059 
    92. 

  92. <a name="l00060"></a>00060 <span class="comment">/*------------------------ Backup Registers ----------------------------------*/</span>
    93. 

  93. <a name="l00061"></a>00061 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    94. 

  94. <a name="l00062"></a>00062 {
    95. 

  95. <a name="l00063"></a>00063   u32  RESERVED0;
    96. 

  96. <a name="l00064"></a>00064   vu16 DR1;
    97. 

  97. <a name="l00065"></a>00065   u16  RESERVED1;
    98. 

  98. <a name="l00066"></a>00066   vu16 DR2;
    99. 

  99. <a name="l00067"></a>00067   u16  RESERVED2;
    100. 

  100. <a name="l00068"></a>00068   vu16 DR3;
    101. 

  101. <a name="l00069"></a>00069   u16  RESERVED3;
    102. 

  102. <a name="l00070"></a>00070   vu16 DR4;
    103. 

  103. <a name="l00071"></a>00071   u16  RESERVED4;
    104. 

  104. <a name="l00072"></a>00072   vu16 DR5;
    105. 

  105. <a name="l00073"></a>00073   u16  RESERVED5;
    106. 

  106. <a name="l00074"></a>00074   vu16 DR6;
    107. 

  107. <a name="l00075"></a>00075   u16  RESERVED6;
    108. 

  108. <a name="l00076"></a>00076   vu16 DR7;
    109. 

  109. <a name="l00077"></a>00077   u16  RESERVED7;
    110. 

  110. <a name="l00078"></a>00078   vu16 DR8;
    111. 

  111. <a name="l00079"></a>00079   u16  RESERVED8;
    112. 

  112. <a name="l00080"></a>00080   vu16 DR9;
    113. 

  113. <a name="l00081"></a>00081   u16  RESERVED9;
    114. 

  114. <a name="l00082"></a>00082   vu16 DR10;
    115. 

  115. <a name="l00083"></a>00083   u16  RESERVED10; 
    116. 

  116. <a name="l00084"></a>00084   vu16 RTCCR;
    117. 

  117. <a name="l00085"></a>00085   u16  RESERVED11;
    118. 

  118. <a name="l00086"></a>00086   vu16 CR;
    119. 

  119. <a name="l00087"></a>00087   u16  RESERVED12;
    120. 

  120. <a name="l00088"></a>00088   vu16 CSR;
    121. 

  121. <a name="l00089"></a>00089   u16  RESERVED13[5];
    122. 

  122. <a name="l00090"></a>00090   vu16 DR11;
    123. 

  123. <a name="l00091"></a>00091   u16  RESERVED14;
    124. 

  124. <a name="l00092"></a>00092   vu16 DR12;
    125. 

  125. <a name="l00093"></a>00093   u16  RESERVED15;
    126. 

  126. <a name="l00094"></a>00094   vu16 DR13;
    127. 

  127. <a name="l00095"></a>00095   u16  RESERVED16;
    128. 

  128. <a name="l00096"></a>00096   vu16 DR14;
    129. 

  129. <a name="l00097"></a>00097   u16  RESERVED17;
    130. 

  130. <a name="l00098"></a>00098   vu16 DR15;
    131. 

  131. <a name="l00099"></a>00099   u16  RESERVED18;
    132. 

  132. <a name="l00100"></a>00100   vu16 DR16;
    133. 

  133. <a name="l00101"></a>00101   u16  RESERVED19;
    134. 

  134. <a name="l00102"></a>00102   vu16 DR17;
    135. 

  135. <a name="l00103"></a>00103   u16  RESERVED20;
    136. 

  136. <a name="l00104"></a>00104   vu16 DR18;
    137. 

  137. <a name="l00105"></a>00105   u16  RESERVED21;
    138. 

  138. <a name="l00106"></a>00106   vu16 DR19;
    139. 

  139. <a name="l00107"></a>00107   u16  RESERVED22;
    140. 

  140. <a name="l00108"></a>00108   vu16 DR20;
    141. 

  141. <a name="l00109"></a>00109   u16  RESERVED23;
    142. 

  142. <a name="l00110"></a>00110   vu16 DR21;
    143. 

  143. <a name="l00111"></a>00111   u16  RESERVED24;
    144. 

  144. <a name="l00112"></a>00112   vu16 DR22;
    145. 

  145. <a name="l00113"></a>00113   u16  RESERVED25;
    146. 

  146. <a name="l00114"></a>00114   vu16 DR23;
    147. 

  147. <a name="l00115"></a>00115   u16  RESERVED26;
    148. 

  148. <a name="l00116"></a>00116   vu16 DR24;
    149. 

  149. <a name="l00117"></a>00117   u16  RESERVED27;
    150. 

  150. <a name="l00118"></a>00118   vu16 DR25;
    151. 

  151. <a name="l00119"></a>00119   u16  RESERVED28;
    152. 

  152. <a name="l00120"></a>00120   vu16 DR26;
    153. 

  153. <a name="l00121"></a>00121   u16  RESERVED29;
    154. 

  154. <a name="l00122"></a>00122   vu16 DR27;
    155. 

  155. <a name="l00123"></a>00123   u16  RESERVED30;
    156. 

  156. <a name="l00124"></a>00124   vu16 DR28;
    157. 

  157. <a name="l00125"></a>00125   u16  RESERVED31;
    158. 

  158. <a name="l00126"></a>00126   vu16 DR29;
    159. 

  159. <a name="l00127"></a>00127   u16  RESERVED32;
    160. 

  160. <a name="l00128"></a>00128   vu16 DR30;
    161. 

  161. <a name="l00129"></a>00129   u16  RESERVED33; 
    162. 

  162. <a name="l00130"></a>00130   vu16 DR31;
    163. 

  163. <a name="l00131"></a>00131   u16  RESERVED34;
    164. 

  164. <a name="l00132"></a>00132   vu16 DR32;
    165. 

  165. <a name="l00133"></a>00133   u16  RESERVED35;
    166. 

  166. <a name="l00134"></a>00134   vu16 DR33;
    167. 

  167. <a name="l00135"></a>00135   u16  RESERVED36;
    168. 

  168. <a name="l00136"></a>00136   vu16 DR34;
    169. 

  169. <a name="l00137"></a>00137   u16  RESERVED37;
    170. 

  170. <a name="l00138"></a>00138   vu16 DR35;
    171. 

  171. <a name="l00139"></a>00139   u16  RESERVED38;
    172. 

  172. <a name="l00140"></a>00140   vu16 DR36;
    173. 

  173. <a name="l00141"></a>00141   u16  RESERVED39;
    174. 

  174. <a name="l00142"></a>00142   vu16 DR37;
    175. 

  175. <a name="l00143"></a>00143   u16  RESERVED40;
    176. 

  176. <a name="l00144"></a>00144   vu16 DR38;
    177. 

  177. <a name="l00145"></a>00145   u16  RESERVED41;
    178. 

  178. <a name="l00146"></a>00146   vu16 DR39;
    179. 

  179. <a name="l00147"></a>00147   u16  RESERVED42;
    180. 

  180. <a name="l00148"></a>00148   vu16 DR40;
    181. 

  181. <a name="l00149"></a>00149   u16  RESERVED43;
    182. 

  182. <a name="l00150"></a>00150   vu16 DR41;
    183. 

  183. <a name="l00151"></a>00151   u16  RESERVED44;
    184. 

  184. <a name="l00152"></a>00152   vu16 DR42;
    185. 

  185. <a name="l00153"></a>00153   u16  RESERVED45;    
    186. 

  186. <a name="l00154"></a>00154 } BKP_TypeDef;
    187. 

  187. <a name="l00155"></a>00155 
    188. 

  188. <a name="l00156"></a>00156 <span class="comment">/*------------------------ Controller Area Network ---------------------------*/</span>
    189. 

  189. <a name="l00157"></a>00157 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    190. 

  190. <a name="l00158"></a>00158 {
    191. 

  191. <a name="l00159"></a>00159   vu32 TIR;
    192. 

  192. <a name="l00160"></a>00160   vu32 TDTR;
    193. 

  193. <a name="l00161"></a>00161   vu32 TDLR;
    194. 

  194. <a name="l00162"></a>00162   vu32 TDHR;
    195. 

  195. <a name="l00163"></a>00163 } CAN_TxMailBox_TypeDef;
    196. 

  196. <a name="l00164"></a>00164 
    197. 

  197. <a name="l00165"></a>00165 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    198. 

  198. <a name="l00166"></a>00166 {
    199. 

  199. <a name="l00167"></a>00167   vu32 RIR;
    200. 

  200. <a name="l00168"></a>00168   vu32 RDTR;
    201. 

  201. <a name="l00169"></a>00169   vu32 RDLR;
    202. 

  202. <a name="l00170"></a>00170   vu32 RDHR;
    203. 

  203. <a name="l00171"></a>00171 } CAN_FIFOMailBox_TypeDef;
    204. 

  204. <a name="l00172"></a>00172 
    205. 

  205. <a name="l00173"></a>00173 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    206. 

  206. <a name="l00174"></a>00174 {
    207. 

  207. <a name="l00175"></a>00175   vu32 FR1;
    208. 

  208. <a name="l00176"></a>00176   vu32 FR2;
    209. 

  209. <a name="l00177"></a>00177 } CAN_FilterRegister_TypeDef;
    210. 

  210. <a name="l00178"></a>00178 
    211. 

  211. <a name="l00179"></a>00179 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    212. 

  212. <a name="l00180"></a>00180 {
    213. 

  213. <a name="l00181"></a>00181   vu32 MCR;
    214. 

  214. <a name="l00182"></a>00182   vu32 MSR;
    215. 

  215. <a name="l00183"></a>00183   vu32 TSR;
    216. 

  216. <a name="l00184"></a>00184   vu32 RF0R;
    217. 

  217. <a name="l00185"></a>00185   vu32 RF1R;
    218. 

  218. <a name="l00186"></a>00186   vu32 IER;
    219. 

  219. <a name="l00187"></a>00187   vu32 ESR;
    220. 

  220. <a name="l00188"></a>00188   vu32 BTR;
    221. 

  221. <a name="l00189"></a>00189   u32  RESERVED0[88];
    222. 

  222. <a name="l00190"></a>00190   CAN_TxMailBox_TypeDef sTxMailBox[3];
    223. 

  223. <a name="l00191"></a>00191   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
    224. 

  224. <a name="l00192"></a>00192   u32  RESERVED1[12];
    225. 

  225. <a name="l00193"></a>00193   vu32 FMR;
    226. 

  226. <a name="l00194"></a>00194   vu32 FM1R;
    227. 

  227. <a name="l00195"></a>00195   u32  RESERVED2;
    228. 

  228. <a name="l00196"></a>00196   vu32 FS1R;
    229. 

  229. <a name="l00197"></a>00197   u32  RESERVED3;
    230. 

  230. <a name="l00198"></a>00198   vu32 FFA1R;
    231. 

  231. <a name="l00199"></a>00199   u32  RESERVED4;
    232. 

  232. <a name="l00200"></a>00200   vu32 FA1R;
    233. 

  233. <a name="l00201"></a>00201   u32  RESERVED5[8];
    234. 

  234. <a name="l00202"></a>00202   CAN_FilterRegister_TypeDef sFilterRegister[14];
    235. 

  235. <a name="l00203"></a>00203 } CAN_TypeDef;
    236. 

  236. <a name="l00204"></a>00204 
    237. 

  237. <a name="l00205"></a>00205 <span class="comment">/*------------------------ CRC calculation unit ------------------------------*/</span>
    238. 

  238. <a name="l00206"></a>00206 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    239. 

  239. <a name="l00207"></a>00207 {
    240. 

  240. <a name="l00208"></a>00208   vu32 DR;
    241. 

  241. <a name="l00209"></a>00209   vu8  IDR;
    242. 

  242. <a name="l00210"></a>00210   u8   RESERVED0;
    243. 

  243. <a name="l00211"></a>00211   u16  RESERVED1;
    244. 

  244. <a name="l00212"></a>00212   vu32 CR;
    245. 

  245. <a name="l00213"></a>00213 } CRC_TypeDef;
    246. 

  246. <a name="l00214"></a>00214 
    247. 

  247. <a name="l00215"></a>00215 
    248. 

  248. <a name="l00216"></a>00216 <span class="comment">/*------------------------ Digital to Analog Converter -----------------------*/</span>
    249. 

  249. <a name="l00217"></a>00217 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    250. 

  250. <a name="l00218"></a>00218 {
    251. 

  251. <a name="l00219"></a>00219   vu32 CR;
    252. 

  252. <a name="l00220"></a>00220   vu32 SWTRIGR;
    253. 

  253. <a name="l00221"></a>00221   vu32 DHR12R1;
    254. 

  254. <a name="l00222"></a>00222   vu32 DHR12L1;
    255. 

  255. <a name="l00223"></a>00223   vu32 DHR8R1;
    256. 

  256. <a name="l00224"></a>00224   vu32 DHR12R2;
    257. 

  257. <a name="l00225"></a>00225   vu32 DHR12L2;
    258. 

  258. <a name="l00226"></a>00226   vu32 DHR8R2;
    259. 

  259. <a name="l00227"></a>00227   vu32 DHR12RD;
    260. 

  260. <a name="l00228"></a>00228   vu32 DHR12LD;
    261. 

  261. <a name="l00229"></a>00229   vu32 DHR8RD;
    262. 

  262. <a name="l00230"></a>00230   vu32 DOR1;
    263. 

  263. <a name="l00231"></a>00231   vu32 DOR2;
    264. 

  264. <a name="l00232"></a>00232 } DAC_TypeDef;
    265. 

  265. <a name="l00233"></a>00233 
    266. 

  266. <a name="l00234"></a>00234 <span class="comment">/*------------------------ Debug MCU -----------------------------------------*/</span>
    267. 

  267. <a name="l00235"></a>00235 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    268. 

  268. <a name="l00236"></a>00236 {
    269. 

  269. <a name="l00237"></a>00237   vu32 IDCODE;
    270. 

  270. <a name="l00238"></a>00238   vu32 CR;      
    271. 

  271. <a name="l00239"></a>00239 }DBGMCU_TypeDef;
    272. 

  272. <a name="l00240"></a>00240 
    273. 

  273. <a name="l00241"></a>00241 <span class="comment">/*------------------------ DMA Controller ------------------------------------*/</span>
    274. 

  274. <a name="l00242"></a>00242 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    275. 

  275. <a name="l00243"></a>00243 {
    276. 

  276. <a name="l00244"></a>00244   vu32 CCR;
    277. 

  277. <a name="l00245"></a>00245   vu32 CNDTR;
    278. 

  278. <a name="l00246"></a>00246   vu32 CPAR;
    279. 

  279. <a name="l00247"></a>00247   vu32 CMAR;
    280. 

  280. <a name="l00248"></a>00248 } DMA_Channel_TypeDef;
    281. 

  281. <a name="l00249"></a>00249 
    282. 

  282. <a name="l00250"></a>00250 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    283. 

  283. <a name="l00251"></a>00251 {
    284. 

  284. <a name="l00252"></a>00252   vu32 <a class="code" href="a01646.html#ga28bf4c54d9527b4a20eb142b6cf3d66a" title="USB general interrupt subroutine.">ISR</a>;
    285. 

  285. <a name="l00253"></a>00253   vu32 IFCR;
    286. 

  286. <a name="l00254"></a>00254 } DMA_TypeDef;
    287. 

  287. <a name="l00255"></a>00255 
    288. 

  288. <a name="l00256"></a>00256 <span class="comment">/*------------------------ External Interrupt/Event Controller ---------------*/</span>
    289. 

  289. <a name="l00257"></a>00257 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    290. 

  290. <a name="l00258"></a>00258 {
    291. 

  291. <a name="l00259"></a>00259   vu32 IMR;
    292. 

  292. <a name="l00260"></a>00260   vu32 EMR;
    293. 

  293. <a name="l00261"></a>00261   vu32 RTSR;
    294. 

  294. <a name="l00262"></a>00262   vu32 FTSR;
    295. 

  295. <a name="l00263"></a>00263   vu32 SWIER;
    296. 

  296. <a name="l00264"></a>00264   vu32 PR;
    297. 

  297. <a name="l00265"></a>00265 } EXTI_TypeDef;
    298. 

  298. <a name="l00266"></a>00266 
    299. 

  299. <a name="l00267"></a>00267 <span class="comment">/*------------------------ FLASH and Option Bytes Registers ------------------*/</span>
    300. 

  300. <a name="l00268"></a>00268 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    301. 

  301. <a name="l00269"></a>00269 {
    302. 

  302. <a name="l00270"></a>00270   vu32 ACR;
    303. 

  303. <a name="l00271"></a>00271   vu32 KEYR;
    304. 

  304. <a name="l00272"></a>00272   vu32 OPTKEYR;
    305. 

  305. <a name="l00273"></a>00273   vu32 SR;
    306. 

  306. <a name="l00274"></a>00274   vu32 CR;
    307. 

  307. <a name="l00275"></a>00275   vu32 AR;
    308. 

  308. <a name="l00276"></a>00276   vu32 RESERVED;
    309. 

  309. <a name="l00277"></a>00277   vu32 OBR;
    310. 

  310. <a name="l00278"></a>00278   vu32 WRPR;
    311. 

  311. <a name="l00279"></a>00279 } FLASH_TypeDef;
    312. 

  312. <a name="l00280"></a>00280 
    313. 

  313. <a name="l00281"></a>00281 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    314. 

  314. <a name="l00282"></a>00282 {
    315. 

  315. <a name="l00283"></a>00283   vu16 RDP;
    316. 

  316. <a name="l00284"></a>00284   vu16 USER;
    317. 

  317. <a name="l00285"></a>00285   vu16 Data0;
    318. 

  318. <a name="l00286"></a>00286   vu16 Data1;
    319. 

  319. <a name="l00287"></a>00287   vu16 WRP0;
    320. 

  320. <a name="l00288"></a>00288   vu16 WRP1;
    321. 

  321. <a name="l00289"></a>00289   vu16 WRP2;
    322. 

  322. <a name="l00290"></a>00290   vu16 WRP3;
    323. 

  323. <a name="l00291"></a>00291 } OB_TypeDef;
    324. 

  324. <a name="l00292"></a>00292 
    325. 

  325. <a name="l00293"></a>00293 <span class="comment">/*------------------------ Flexible Static Memory Controller -----------------*/</span>
    326. 

  326. <a name="l00294"></a>00294 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    327. 

  327. <a name="l00295"></a>00295 {
    328. 

  328. <a name="l00296"></a>00296   vu32 BTCR[8];   
    329. 

  329. <a name="l00297"></a>00297 } FSMC_Bank1_TypeDef; 
    330. 

  330. <a name="l00298"></a>00298 
    331. 

  331. <a name="l00299"></a>00299 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    332. 

  332. <a name="l00300"></a>00300 {
    333. 

  333. <a name="l00301"></a>00301   vu32 BWTR[7];
    334. 

  334. <a name="l00302"></a>00302 } FSMC_Bank1E_TypeDef;
    335. 

  335. <a name="l00303"></a>00303 
    336. 

  336. <a name="l00304"></a>00304 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    337. 

  337. <a name="l00305"></a>00305 {
    338. 

  338. <a name="l00306"></a>00306   vu32 PCR2;
    339. 

  339. <a name="l00307"></a>00307   vu32 SR2;
    340. 

  340. <a name="l00308"></a>00308   vu32 PMEM2;
    341. 

  341. <a name="l00309"></a>00309   vu32 PATT2;
    342. 

  342. <a name="l00310"></a>00310   u32  RESERVED0;   
    343. 

  343. <a name="l00311"></a>00311   vu32 ECCR2; 
    344. 

  344. <a name="l00312"></a>00312 } FSMC_Bank2_TypeDef;  
    345. 

  345. <a name="l00313"></a>00313 
    346. 

  346. <a name="l00314"></a>00314 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    347. 

  347. <a name="l00315"></a>00315 {
    348. 

  348. <a name="l00316"></a>00316   vu32 PCR3;
    349. 

  349. <a name="l00317"></a>00317   vu32 SR3;
    350. 

  350. <a name="l00318"></a>00318   vu32 PMEM3;
    351. 

  351. <a name="l00319"></a>00319   vu32 PATT3;
    352. 

  352. <a name="l00320"></a>00320   u32  RESERVED0;   
    353. 

  353. <a name="l00321"></a>00321   vu32 ECCR3; 
    354. 

  354. <a name="l00322"></a>00322 } FSMC_Bank3_TypeDef; 
    355. 

  355. <a name="l00323"></a>00323 
    356. 

  356. <a name="l00324"></a>00324 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    357. 

  357. <a name="l00325"></a>00325 {
    358. 

  358. <a name="l00326"></a>00326   vu32 PCR4;
    359. 

  359. <a name="l00327"></a>00327   vu32 SR4;
    360. 

  360. <a name="l00328"></a>00328   vu32 PMEM4;
    361. 

  361. <a name="l00329"></a>00329   vu32 PATT4;
    362. 

  362. <a name="l00330"></a>00330   vu32 PIO4; 
    363. 

  363. <a name="l00331"></a>00331 } FSMC_Bank4_TypeDef; 
    364. 

  364. <a name="l00332"></a>00332 
    365. 

  365. <a name="l00333"></a>00333 <span class="comment">/*------------------------ General Purpose and Alternate Function IO ---------*/</span>
    366. 

  366. <a name="l00334"></a>00334 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    367. 

  367. <a name="l00335"></a>00335 {
    368. 

  368. <a name="l00336"></a>00336   vu32 CRL;
    369. 

  369. <a name="l00337"></a>00337   vu32 CRH;
    370. 

  370. <a name="l00338"></a>00338   vu32 IDR;
    371. 

  371. <a name="l00339"></a>00339   vu32 ODR;
    372. 

  372. <a name="l00340"></a>00340   vu32 BSRR;
    373. 

  373. <a name="l00341"></a>00341   vu32 BRR;
    374. 

  374. <a name="l00342"></a>00342   vu32 LCKR;
    375. 

  375. <a name="l00343"></a>00343 } GPIO_TypeDef;
    376. 

  376. <a name="l00344"></a>00344 
    377. 

  377. <a name="l00345"></a>00345 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    378. 

  378. <a name="l00346"></a>00346 {
    379. 

  379. <a name="l00347"></a>00347   vu32 EVCR;
    380. 

  380. <a name="l00348"></a>00348   vu32 MAPR;
    381. 

  381. <a name="l00349"></a>00349   vu32 EXTICR[4];
    382. 

  382. <a name="l00350"></a>00350 } AFIO_TypeDef;
    383. 

  383. <a name="l00351"></a>00351 
    384. 

  384. <a name="l00352"></a>00352 <span class="comment">/*------------------------ Inter-integrated Circuit Interface ----------------*/</span>
    385. 

  385. <a name="l00353"></a>00353 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    386. 

  386. <a name="l00354"></a>00354 {
    387. 

  387. <a name="l00355"></a>00355   vu16 CR1;
    388. 

  388. <a name="l00356"></a>00356   u16  RESERVED0;
    389. 

  389. <a name="l00357"></a>00357   vu16 CR2;
    390. 

  390. <a name="l00358"></a>00358   u16  RESERVED1;
    391. 

  391. <a name="l00359"></a>00359   vu16 OAR1;
    392. 

  392. <a name="l00360"></a>00360   u16  RESERVED2;
    393. 

  393. <a name="l00361"></a>00361   vu16 OAR2;
    394. 

  394. <a name="l00362"></a>00362   u16  RESERVED3;
    395. 

  395. <a name="l00363"></a>00363   vu16 DR;
    396. 

  396. <a name="l00364"></a>00364   u16  RESERVED4;
    397. 

  397. <a name="l00365"></a>00365   vu16 SR1;
    398. 

  398. <a name="l00366"></a>00366   u16  RESERVED5;
    399. 

  399. <a name="l00367"></a>00367   vu16 SR2;
    400. 

  400. <a name="l00368"></a>00368   u16  RESERVED6;
    401. 

  401. <a name="l00369"></a>00369   vu16 CCR;
    402. 

  402. <a name="l00370"></a>00370   u16  RESERVED7;
    403. 

  403. <a name="l00371"></a>00371   vu16 TRISE;
    404. 

  404. <a name="l00372"></a>00372   u16  RESERVED8;
    405. 

  405. <a name="l00373"></a>00373 } I2C_TypeDef;
    406. 

  406. <a name="l00374"></a>00374 
    407. 

  407. <a name="l00375"></a>00375 <span class="comment">/*------------------------ Independent WATCHDOG ------------------------------*/</span>
    408. 

  408. <a name="l00376"></a>00376 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    409. 

  409. <a name="l00377"></a>00377 {
    410. 

  410. <a name="l00378"></a>00378   vu32 KR;
    411. 

  411. <a name="l00379"></a>00379   vu32 PR;
    412. 

  412. <a name="l00380"></a>00380   vu32 RLR;
    413. 

  413. <a name="l00381"></a>00381   vu32 SR;
    414. 

  414. <a name="l00382"></a>00382 } IWDG_TypeDef;
    415. 

  415. <a name="l00383"></a>00383 
    416. 

  416. <a name="l00384"></a>00384 <span class="comment">/*------------------------ Nested Vectored Interrupt Controller --------------*/</span>
    417. 

  417. <a name="l00385"></a>00385 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    418. 

  418. <a name="l00386"></a>00386 {
    419. 

  419. <a name="l00387"></a>00387   vu32 ISER[2];
    420. 

  420. <a name="l00388"></a>00388   u32  RESERVED0[30];
    421. 

  421. <a name="l00389"></a>00389   vu32 ICER[2];
    422. 

  422. <a name="l00390"></a>00390   u32  RSERVED1[30];
    423. 

  423. <a name="l00391"></a>00391   vu32 ISPR[2];
    424. 

  424. <a name="l00392"></a>00392   u32  RESERVED2[30];
    425. 

  425. <a name="l00393"></a>00393   vu32 ICPR[2];
    426. 

  426. <a name="l00394"></a>00394   u32  RESERVED3[30];
    427. 

  427. <a name="l00395"></a>00395   vu32 IABR[2];
    428. 

  428. <a name="l00396"></a>00396   u32  RESERVED4[62];
    429. 

  429. <a name="l00397"></a>00397   vu32 IPR[15];
    430. 

  430. <a name="l00398"></a>00398 } NVIC_TypeDef;
    431. 

  431. <a name="l00399"></a>00399 
    432. 

  432. <a name="l00400"></a>00400 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    433. 

  433. <a name="l00401"></a>00401 {
    434. 

  434. <a name="l00402"></a>00402   vuc32 CPUID;
    435. 

  435. <a name="l00403"></a>00403   vu32 ICSR;
    436. 

  436. <a name="l00404"></a>00404   vu32 VTOR;
    437. 

  437. <a name="l00405"></a>00405   vu32 AIRCR;
    438. 

  438. <a name="l00406"></a>00406   vu32 SCR;
    439. 

  439. <a name="l00407"></a>00407   vu32 CCR;
    440. 

  440. <a name="l00408"></a>00408   vu32 SHPR[3];
    441. 

  441. <a name="l00409"></a>00409   vu32 SHCSR;
    442. 

  442. <a name="l00410"></a>00410   vu32 CFSR;
    443. 

  443. <a name="l00411"></a>00411   vu32 HFSR;
    444. 

  444. <a name="l00412"></a>00412   vu32 DFSR;
    445. 

  445. <a name="l00413"></a>00413   vu32 MMFAR;
    446. 

  446. <a name="l00414"></a>00414   vu32 BFAR;
    447. 

  447. <a name="l00415"></a>00415   vu32 AFSR;
    448. 

  448. <a name="l00416"></a>00416 } SCB_TypeDef;
    449. 

  449. <a name="l00417"></a>00417 
    450. 

  450. <a name="l00418"></a>00418 <span class="comment">/*------------------------ Power Control -------------------------------------*/</span>
    451. 

  451. <a name="l00419"></a>00419 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    452. 

  452. <a name="l00420"></a>00420 {
    453. 

  453. <a name="l00421"></a>00421   vu32 CR;
    454. 

  454. <a name="l00422"></a>00422   vu32 CSR;
    455. 

  455. <a name="l00423"></a>00423 } PWR_TypeDef;
    456. 

  456. <a name="l00424"></a>00424 
    457. 

  457. <a name="l00425"></a>00425 <span class="comment">/*------------------------ Reset and Clock Control ---------------------------*/</span>
    458. 

  458. <a name="l00426"></a>00426 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    459. 

  459. <a name="l00427"></a>00427 {
    460. 

  460. <a name="l00428"></a>00428   vu32 CR;
    461. 

  461. <a name="l00429"></a>00429   vu32 CFGR;
    462. 

  462. <a name="l00430"></a>00430   vu32 CIR;
    463. 

  463. <a name="l00431"></a>00431   vu32 APB2RSTR;
    464. 

  464. <a name="l00432"></a>00432   vu32 APB1RSTR;
    465. 

  465. <a name="l00433"></a>00433   vu32 AHBENR;
    466. 

  466. <a name="l00434"></a>00434   vu32 APB2ENR;
    467. 

  467. <a name="l00435"></a>00435   vu32 APB1ENR;
    468. 

  468. <a name="l00436"></a>00436   vu32 BDCR;
    469. 

  469. <a name="l00437"></a>00437   vu32 CSR;
    470. 

  470. <a name="l00438"></a>00438 } RCC_TypeDef;
    471. 

  471. <a name="l00439"></a>00439 
    472. 

  472. <a name="l00440"></a>00440 <span class="comment">/*------------------------ Real-Time Clock -----------------------------------*/</span>
    473. 

  473. <a name="l00441"></a>00441 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    474. 

  474. <a name="l00442"></a>00442 {
    475. 

  475. <a name="l00443"></a>00443   vu16 CRH;
    476. 

  476. <a name="l00444"></a>00444   u16  RESERVED0;
    477. 

  477. <a name="l00445"></a>00445   vu16 CRL;
    478. 

  478. <a name="l00446"></a>00446   u16  RESERVED1;
    479. 

  479. <a name="l00447"></a>00447   vu16 PRLH;
    480. 

  480. <a name="l00448"></a>00448   u16  RESERVED2;
    481. 

  481. <a name="l00449"></a>00449   vu16 PRLL;
    482. 

  482. <a name="l00450"></a>00450   u16  RESERVED3;
    483. 

  483. <a name="l00451"></a>00451   vu16 DIVH;
    484. 

  484. <a name="l00452"></a>00452   u16  RESERVED4;
    485. 

  485. <a name="l00453"></a>00453   vu16 DIVL;
    486. 

  486. <a name="l00454"></a>00454   u16  RESERVED5;
    487. 

  487. <a name="l00455"></a>00455   vu16 CNTH;
    488. 

  488. <a name="l00456"></a>00456   u16  RESERVED6;
    489. 

  489. <a name="l00457"></a>00457   vu16 CNTL;
    490. 

  490. <a name="l00458"></a>00458   u16  RESERVED7;
    491. 

  491. <a name="l00459"></a>00459   vu16 ALRH;
    492. 

  492. <a name="l00460"></a>00460   u16  RESERVED8;
    493. 

  493. <a name="l00461"></a>00461   vu16 ALRL;
    494. 

  494. <a name="l00462"></a>00462   u16  RESERVED9;
    495. 

  495. <a name="l00463"></a>00463 } RTC_TypeDef;
    496. 

  496. <a name="l00464"></a>00464 
    497. 

  497. <a name="l00465"></a>00465 <span class="comment">/*------------------------ SD host Interface ---------------------------------*/</span>
    498. 

  498. <a name="l00466"></a>00466 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    499. 

  499. <a name="l00467"></a>00467 {
    500. 

  500. <a name="l00468"></a>00468   vu32 POWER;
    501. 

  501. <a name="l00469"></a>00469   vu32 CLKCR;
    502. 

  502. <a name="l00470"></a>00470   vu32 ARG;
    503. 

  503. <a name="l00471"></a>00471   vu32 CMD;
    504. 

  504. <a name="l00472"></a>00472   vuc32 RESPCMD;
    505. 

  505. <a name="l00473"></a>00473   vuc32 RESP1;
    506. 

  506. <a name="l00474"></a>00474   vuc32 RESP2;
    507. 

  507. <a name="l00475"></a>00475   vuc32 RESP3;
    508. 

  508. <a name="l00476"></a>00476   vuc32 RESP4;
    509. 

  509. <a name="l00477"></a>00477   vu32 DTIMER;
    510. 

  510. <a name="l00478"></a>00478   vu32 DLEN;
    511. 

  511. <a name="l00479"></a>00479   vu32 DCTRL;
    512. 

  512. <a name="l00480"></a>00480   vuc32 DCOUNT;
    513. 

  513. <a name="l00481"></a>00481   vuc32 STA;
    514. 

  514. <a name="l00482"></a>00482   vu32 ICR;
    515. 

  515. <a name="l00483"></a>00483   vu32 MASK;
    516. 

  516. <a name="l00484"></a>00484   u32  RESERVED0[2];
    517. 

  517. <a name="l00485"></a>00485   vuc32 FIFOCNT;
    518. 

  518. <a name="l00486"></a>00486   u32  RESERVED1[13];
    519. 

  519. <a name="l00487"></a>00487   vu32 FIFO;
    520. 

  520. <a name="l00488"></a>00488 } SDIO_TypeDef;
    521. 

  521. <a name="l00489"></a>00489 
    522. 

  522. <a name="l00490"></a>00490 <span class="comment">/*------------------------ Serial Peripheral Interface -----------------------*/</span>
    523. 

  523. <a name="l00491"></a>00491 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    524. 

  524. <a name="l00492"></a>00492 {
    525. 

  525. <a name="l00493"></a>00493   vu16 CR1;
    526. 

  526. <a name="l00494"></a>00494   u16  RESERVED0;
    527. 

  527. <a name="l00495"></a>00495   vu16 CR2;
    528. 

  528. <a name="l00496"></a>00496   u16  RESERVED1;
    529. 

  529. <a name="l00497"></a>00497   vu16 SR;
    530. 

  530. <a name="l00498"></a>00498   u16  RESERVED2;
    531. 

  531. <a name="l00499"></a>00499   vu16 DR;
    532. 

  532. <a name="l00500"></a>00500   u16  RESERVED3;
    533. 

  533. <a name="l00501"></a>00501   vu16 CRCPR;
    534. 

  534. <a name="l00502"></a>00502   u16  RESERVED4;
    535. 

  535. <a name="l00503"></a>00503   vu16 RXCRCR;
    536. 

  536. <a name="l00504"></a>00504   u16  RESERVED5;
    537. 

  537. <a name="l00505"></a>00505   vu16 TXCRCR;
    538. 

  538. <a name="l00506"></a>00506   u16  RESERVED6;
    539. 

  539. <a name="l00507"></a>00507   vu16 I2SCFGR;
    540. 

  540. <a name="l00508"></a>00508   u16  RESERVED7;
    541. 

  541. <a name="l00509"></a>00509   vu16 I2SPR;
    542. 

  542. <a name="l00510"></a>00510   u16  RESERVED8;  
    543. 

  543. <a name="l00511"></a>00511 } SPI_TypeDef;
    544. 

  544. <a name="l00512"></a>00512 
    545. 

  545. <a name="l00513"></a>00513 <span class="comment">/*------------------------ SystemTick ----------------------------------------*/</span>
    546. 

  546. <a name="l00514"></a>00514 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    547. 

  547. <a name="l00515"></a>00515 {
    548. 

  548. <a name="l00516"></a>00516   vu32 CTRL;
    549. 

  549. <a name="l00517"></a>00517   vu32 LOAD;
    550. 

  550. <a name="l00518"></a>00518   vu32 VAL;
    551. 

  551. <a name="l00519"></a>00519   vuc32 CALIB;
    552. 

  552. <a name="l00520"></a>00520 } SysTick_TypeDef;
    553. 

  553. <a name="l00521"></a>00521 
    554. 

  554. <a name="l00522"></a>00522 <span class="comment">/*------------------------ TIM -----------------------------------------------*/</span>
    555. 

  555. <a name="l00523"></a>00523 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    556. 

  556. <a name="l00524"></a>00524 {
    557. 

  557. <a name="l00525"></a>00525   vu16 CR1;
    558. 

  558. <a name="l00526"></a>00526   u16  RESERVED0;
    559. 

  559. <a name="l00527"></a>00527   vu16 CR2;
    560. 

  560. <a name="l00528"></a>00528   u16  RESERVED1;
    561. 

  561. <a name="l00529"></a>00529   vu16 SMCR;
    562. 

  562. <a name="l00530"></a>00530   u16  RESERVED2;
    563. 

  563. <a name="l00531"></a>00531   vu16 DIER;
    564. 

  564. <a name="l00532"></a>00532   u16  RESERVED3;
    565. 

  565. <a name="l00533"></a>00533   vu16 SR;
    566. 

  566. <a name="l00534"></a>00534   u16  RESERVED4;
    567. 

  567. <a name="l00535"></a>00535   vu16 EGR;
    568. 

  568. <a name="l00536"></a>00536   u16  RESERVED5;
    569. 

  569. <a name="l00537"></a>00537   vu16 CCMR1;
    570. 

  570. <a name="l00538"></a>00538   u16  RESERVED6;
    571. 

  571. <a name="l00539"></a>00539   vu16 CCMR2;
    572. 

  572. <a name="l00540"></a>00540   u16  RESERVED7;
    573. 

  573. <a name="l00541"></a>00541   vu16 CCER;
    574. 

  574. <a name="l00542"></a>00542   u16  RESERVED8;
    575. 

  575. <a name="l00543"></a>00543   vu16 CNT;
    576. 

  576. <a name="l00544"></a>00544   u16  RESERVED9;
    577. 

  577. <a name="l00545"></a>00545   vu16 PSC;
    578. 

  578. <a name="l00546"></a>00546   u16  RESERVED10;
    579. 

  579. <a name="l00547"></a>00547   vu16 ARR;
    580. 

  580. <a name="l00548"></a>00548   u16  RESERVED11;
    581. 

  581. <a name="l00549"></a>00549   vu16 RCR;
    582. 

  582. <a name="l00550"></a>00550   u16  RESERVED12;
    583. 

  583. <a name="l00551"></a>00551   vu16 CCR1;
    584. 

  584. <a name="l00552"></a>00552   u16  RESERVED13;
    585. 

  585. <a name="l00553"></a>00553   vu16 CCR2;
    586. 

  586. <a name="l00554"></a>00554   u16  RESERVED14;
    587. 

  587. <a name="l00555"></a>00555   vu16 CCR3;
    588. 

  588. <a name="l00556"></a>00556   u16  RESERVED15;
    589. 

  589. <a name="l00557"></a>00557   vu16 CCR4;
    590. 

  590. <a name="l00558"></a>00558   u16  RESERVED16;
    591. 

  591. <a name="l00559"></a>00559   vu16 BDTR;
    592. 

  592. <a name="l00560"></a>00560   u16  RESERVED17;
    593. 

  593. <a name="l00561"></a>00561   vu16 DCR;
    594. 

  594. <a name="l00562"></a>00562   u16  RESERVED18;
    595. 

  595. <a name="l00563"></a>00563   vu16 DMAR;
    596. 

  596. <a name="l00564"></a>00564   u16  RESERVED19;
    597. 

  597. <a name="l00565"></a>00565 } TIM_TypeDef;
    598. 

  598. <a name="l00566"></a>00566 
    599. 

  599. <a name="l00567"></a>00567 <span class="comment">/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/</span>
    600. 

  600. <a name="l00568"></a>00568 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    601. 

  601. <a name="l00569"></a>00569 {
    602. 

  602. <a name="l00570"></a>00570   vu16 SR;
    603. 

  603. <a name="l00571"></a>00571   u16  RESERVED0;
    604. 

  604. <a name="l00572"></a>00572   vu16 DR;
    605. 

  605. <a name="l00573"></a>00573   u16  RESERVED1;
    606. 

  606. <a name="l00574"></a>00574   vu16 BRR;
    607. 

  607. <a name="l00575"></a>00575   u16  RESERVED2;
    608. 

  608. <a name="l00576"></a>00576   vu16 CR1;
    609. 

  609. <a name="l00577"></a>00577   u16  RESERVED3;
    610. 

  610. <a name="l00578"></a>00578   vu16 CR2;
    611. 

  611. <a name="l00579"></a>00579   u16  RESERVED4;
    612. 

  612. <a name="l00580"></a>00580   vu16 CR3;
    613. 

  613. <a name="l00581"></a>00581   u16  RESERVED5;
    614. 

  614. <a name="l00582"></a>00582   vu16 GTPR;
    615. 

  615. <a name="l00583"></a>00583   u16  RESERVED6;
    616. 

  616. <a name="l00584"></a>00584 } USART_TypeDef;
    617. 

  617. <a name="l00585"></a>00585 
    618. 

  618. <a name="l00586"></a>00586 <span class="comment">/*------------------------ Window WATCHDOG -----------------------------------*/</span>
    619. 

  619. <a name="l00587"></a>00587 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    620. 

  620. <a name="l00588"></a>00588 {
    621. 

  621. <a name="l00589"></a>00589   vu32 CR;
    622. 

  622. <a name="l00590"></a>00590   vu32 CFR;
    623. 

  623. <a name="l00591"></a>00591   vu32 SR;
    624. 

  624. <a name="l00592"></a>00592 } WWDG_TypeDef;
    625. 

  625. <a name="l00593"></a>00593 
    626. 

  626. <a name="l00594"></a>00594 <span class="comment">/******************************************************************************/</span>
    627. 

  627. <a name="l00595"></a>00595 <span class="comment">/*                         Peripheral memory map                              */</span>
    628. 

  628. <a name="l00596"></a>00596 <span class="comment">/******************************************************************************/</span>
    629. 

  629. <a name="l00597"></a>00597 <span class="comment">/* Peripheral and SRAM base address in the alias region */</span>
    630. 

  630. <a name="l00598"></a>00598 <span class="preprocessor">#define PERIPH_BB_BASE        ((u32)0x42000000)</span>
    631. 

  631. <a name="l00599"></a>00599 <span class="preprocessor"></span><span class="preprocessor">#define SRAM_BB_BASE          ((u32)0x22000000)</span>
    632. 

  632. <a name="l00600"></a>00600 <span class="preprocessor"></span>
    633. 

  633. <a name="l00601"></a>00601 <span class="comment">/* Peripheral and SRAM base address in the bit-band region */</span>
    634. 

  634. <a name="l00602"></a>00602 <span class="preprocessor">#define SRAM_BASE             ((u32)0x20000000)</span>
    635. 

  635. <a name="l00603"></a>00603 <span class="preprocessor"></span><span class="preprocessor">#define PERIPH_BASE           ((u32)0x40000000)</span>
    636. 

  636. <a name="l00604"></a>00604 <span class="preprocessor"></span>
    637. 

  637. <a name="l00605"></a>00605 <span class="comment">/* FSMC registers base address */</span>
    638. 

  638. <a name="l00606"></a>00606 <span class="preprocessor">#define FSMC_R_BASE           ((u32)0xA0000000)</span>
    639. 

  639. <a name="l00607"></a>00607 <span class="preprocessor"></span>
    640. 

  640. <a name="l00608"></a>00608 <span class="comment">/* Peripheral memory map */</span>
    641. 

  641. <a name="l00609"></a>00609 <span class="preprocessor">#define APB1PERIPH_BASE       PERIPH_BASE</span>
    642. 

  642. <a name="l00610"></a>00610 <span class="preprocessor"></span><span class="preprocessor">#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)</span>
    643. 

  643. <a name="l00611"></a>00611 <span class="preprocessor"></span><span class="preprocessor">#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)</span>
    644. 

  644. <a name="l00612"></a>00612 <span class="preprocessor"></span>
    645. 

  645. <a name="l00613"></a>00613 <span class="preprocessor">#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)</span>
    646. 

  646. <a name="l00614"></a>00614 <span class="preprocessor"></span><span class="preprocessor">#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)</span>
    647. 

  647. <a name="l00615"></a>00615 <span class="preprocessor"></span><span class="preprocessor">#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)</span>
    648. 

  648. <a name="l00616"></a>00616 <span class="preprocessor"></span><span class="preprocessor">#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)</span>
    649. 

  649. <a name="l00617"></a>00617 <span class="preprocessor"></span><span class="preprocessor">#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)</span>
    650. 

  650. <a name="l00618"></a>00618 <span class="preprocessor"></span><span class="preprocessor">#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)</span>
    651. 

  651. <a name="l00619"></a>00619 <span class="preprocessor"></span><span class="preprocessor">#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)</span>
    652. 

  652. <a name="l00620"></a>00620 <span class="preprocessor"></span><span class="preprocessor">#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)</span>
    653. 

  653. <a name="l00621"></a>00621 <span class="preprocessor"></span><span class="preprocessor">#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)</span>
    654. 

  654. <a name="l00622"></a>00622 <span class="preprocessor"></span><span class="preprocessor">#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)</span>
    655. 

  655. <a name="l00623"></a>00623 <span class="preprocessor"></span><span class="preprocessor">#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)</span>
    656. 

  656. <a name="l00624"></a>00624 <span class="preprocessor"></span><span class="preprocessor">#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)</span>
    657. 

  657. <a name="l00625"></a>00625 <span class="preprocessor"></span><span class="preprocessor">#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)</span>
    658. 

  658. <a name="l00626"></a>00626 <span class="preprocessor"></span><span class="preprocessor">#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)</span>
    659. 

  659. <a name="l00627"></a>00627 <span class="preprocessor"></span><span class="preprocessor">#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)</span>
    660. 

  660. <a name="l00628"></a>00628 <span class="preprocessor"></span><span class="preprocessor">#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)</span>
    661. 

  661. <a name="l00629"></a>00629 <span class="preprocessor"></span><span class="preprocessor">#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)</span>
    662. 

  662. <a name="l00630"></a>00630 <span class="preprocessor"></span><span class="preprocessor">#define CAN_BASE              (APB1PERIPH_BASE + 0x6400)</span>
    663. 

  663. <a name="l00631"></a>00631 <span class="preprocessor"></span><span class="preprocessor">#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)</span>
    664. 

  664. <a name="l00632"></a>00632 <span class="preprocessor"></span><span class="preprocessor">#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)</span>
    665. 

  665. <a name="l00633"></a>00633 <span class="preprocessor"></span><span class="preprocessor">#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)</span>
    666. 

  666. <a name="l00634"></a>00634 <span class="preprocessor"></span>
    667. 

  667. <a name="l00635"></a>00635 <span class="preprocessor">#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)</span>
    668. 

  668. <a name="l00636"></a>00636 <span class="preprocessor"></span><span class="preprocessor">#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)</span>
    669. 

  669. <a name="l00637"></a>00637 <span class="preprocessor"></span><span class="preprocessor">#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)</span>
    670. 

  670. <a name="l00638"></a>00638 <span class="preprocessor"></span><span class="preprocessor">#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)</span>
    671. 

  671. <a name="l00639"></a>00639 <span class="preprocessor"></span><span class="preprocessor">#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)</span>
    672. 

  672. <a name="l00640"></a>00640 <span class="preprocessor"></span><span class="preprocessor">#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)</span>
    673. 

  673. <a name="l00641"></a>00641 <span class="preprocessor"></span><span class="preprocessor">#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)</span>
    674. 

  674. <a name="l00642"></a>00642 <span class="preprocessor"></span><span class="preprocessor">#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)</span>
    675. 

  675. <a name="l00643"></a>00643 <span class="preprocessor"></span><span class="preprocessor">#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)</span>
    676. 

  676. <a name="l00644"></a>00644 <span class="preprocessor"></span><span class="preprocessor">#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)</span>
    677. 

  677. <a name="l00645"></a>00645 <span class="preprocessor"></span><span class="preprocessor">#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)</span>
    678. 

  678. <a name="l00646"></a>00646 <span class="preprocessor"></span><span class="preprocessor">#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)</span>
    679. 

  679. <a name="l00647"></a>00647 <span class="preprocessor"></span><span class="preprocessor">#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)</span>
    680. 

  680. <a name="l00648"></a>00648 <span class="preprocessor"></span><span class="preprocessor">#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)</span>
    681. 

  681. <a name="l00649"></a>00649 <span class="preprocessor"></span><span class="preprocessor">#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)</span>
    682. 

  682. <a name="l00650"></a>00650 <span class="preprocessor"></span><span class="preprocessor">#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)</span>
    683. 

  683. <a name="l00651"></a>00651 <span class="preprocessor"></span>
    684. 

  684. <a name="l00652"></a>00652 <span class="preprocessor">#define SDIO_BASE             (PERIPH_BASE + 0x18000)</span>
    685. 

  685. <a name="l00653"></a>00653 <span class="preprocessor"></span>
    686. 

  686. <a name="l00654"></a>00654 <span class="preprocessor">#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)</span>
    687. 

  687. <a name="l00655"></a>00655 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)</span>
    688. 

  688. <a name="l00656"></a>00656 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)</span>
    689. 

  689. <a name="l00657"></a>00657 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)</span>
    690. 

  690. <a name="l00658"></a>00658 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)</span>
    691. 

  691. <a name="l00659"></a>00659 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)</span>
    692. 

  692. <a name="l00660"></a>00660 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)</span>
    693. 

  693. <a name="l00661"></a>00661 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)</span>
    694. 

  694. <a name="l00662"></a>00662 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)</span>
    695. 

  695. <a name="l00663"></a>00663 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)</span>
    696. 

  696. <a name="l00664"></a>00664 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)</span>
    697. 

  697. <a name="l00665"></a>00665 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)</span>
    698. 

  698. <a name="l00666"></a>00666 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)</span>
    699. 

  699. <a name="l00667"></a>00667 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)</span>
    700. 

  700. <a name="l00668"></a>00668 <span class="preprocessor"></span><span class="preprocessor">#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)</span>
    701. 

  701. <a name="l00669"></a>00669 <span class="preprocessor"></span><span class="preprocessor">#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)</span>
    702. 

  702. <a name="l00670"></a>00670 <span class="preprocessor"></span>
    703. 

  703. <a name="l00671"></a>00671 <span class="comment">/* Flash registers base address */</span>
    704. 

  704. <a name="l00672"></a>00672 <span class="preprocessor">#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000)</span>
    705. 

  705. <a name="l00673"></a>00673 <span class="preprocessor"></span><span class="comment">/* Flash Option Bytes base address */</span>
    706. 

  706. <a name="l00674"></a>00674 <span class="preprocessor">#define OB_BASE               ((u32)0x1FFFF800)</span>
    707. 

  707. <a name="l00675"></a>00675 <span class="preprocessor"></span>
    708. 

  708. <a name="l00676"></a>00676 <span class="comment">/* FSMC Bankx registers base address */</span>
    709. 

  709. <a name="l00677"></a>00677 <span class="preprocessor">#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)</span>
    710. 

  710. <a name="l00678"></a>00678 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)</span>
    711. 

  711. <a name="l00679"></a>00679 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)</span>
    712. 

  712. <a name="l00680"></a>00680 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)</span>
    713. 

  713. <a name="l00681"></a>00681 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)</span>
    714. 

  714. <a name="l00682"></a>00682 <span class="preprocessor"></span>
    715. 

  715. <a name="l00683"></a>00683 <span class="comment">/* Debug MCU registers base address */</span>
    716. 

  716. <a name="l00684"></a>00684 <span class="preprocessor">#define DBGMCU_BASE          ((u32)0xE0042000)</span>
    717. 

  717. <a name="l00685"></a>00685 <span class="preprocessor"></span>
    718. 

  718. <a name="l00686"></a>00686 <span class="comment">/* System Control Space memory map */</span>
    719. 

  719. <a name="l00687"></a>00687 <span class="preprocessor">#define SCS_BASE              ((u32)0xE000E000)</span>
    720. 

  720. <a name="l00688"></a>00688 <span class="preprocessor"></span>
    721. 

  721. <a name="l00689"></a>00689 <span class="preprocessor">#define SysTick_BASE          (SCS_BASE + 0x0010)</span>
    722. 

  722. <a name="l00690"></a>00690 <span class="preprocessor"></span><span class="preprocessor">#define NVIC_BASE             (SCS_BASE + 0x0100)</span>
    723. 

  723. <a name="l00691"></a>00691 <span class="preprocessor"></span><span class="preprocessor">#define SCB_BASE              (SCS_BASE + 0x0D00)</span>
    724. 

  724. <a name="l00692"></a>00692 <span class="preprocessor"></span>
    725. 

  725. <a name="l00693"></a>00693 <span class="comment">/******************************************************************************/</span>
    726. 

  726. <a name="l00694"></a>00694 <span class="comment">/*                         Peripheral declaration                             */</span>
    727. 

  727. <a name="l00695"></a>00695 <span class="comment">/******************************************************************************/</span>
    728. 

  728. <a name="l00696"></a>00696 
    729. 

  729. <a name="l00697"></a>00697 <span class="comment">/*------------------------ Non Debug Mode ------------------------------------*/</span>
    730. 

  730. <a name="l00698"></a>00698 <span class="preprocessor">#ifndef DEBUG</span>
    731. 

  731. <a name="l00699"></a>00699 <span class="preprocessor"></span><span class="preprocessor">#ifdef _TIM2</span>
    732. 

  732. <a name="l00700"></a>00700 <span class="preprocessor"></span><span class="preprocessor">  #define TIM2                ((TIM_TypeDef *) TIM2_BASE)</span>
    733. 

  733. <a name="l00701"></a>00701 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM2 */</span>
    734. 

  734. <a name="l00702"></a>00702 
    735. 

  735. <a name="l00703"></a>00703 <span class="preprocessor">#ifdef _TIM3</span>
    736. 

  736. <a name="l00704"></a>00704 <span class="preprocessor"></span><span class="preprocessor">  #define TIM3                ((TIM_TypeDef *) TIM3_BASE)</span>
    737. 

  737. <a name="l00705"></a>00705 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM3 */</span>
    738. 

  738. <a name="l00706"></a>00706 
    739. 

  739. <a name="l00707"></a>00707 <span class="preprocessor">#ifdef _TIM4</span>
    740. 

  740. <a name="l00708"></a>00708 <span class="preprocessor"></span><span class="preprocessor">  #define TIM4                ((TIM_TypeDef *) TIM4_BASE)</span>
    741. 

  741. <a name="l00709"></a>00709 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM4 */</span>
    742. 

  742. <a name="l00710"></a>00710 
    743. 

  743. <a name="l00711"></a>00711 <span class="preprocessor">#ifdef _TIM5</span>
    744. 

  744. <a name="l00712"></a>00712 <span class="preprocessor"></span><span class="preprocessor">  #define TIM5                ((TIM_TypeDef *) TIM5_BASE)</span>
    745. 

  745. <a name="l00713"></a>00713 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM5 */</span>
    746. 

  746. <a name="l00714"></a>00714 
    747. 

  747. <a name="l00715"></a>00715 <span class="preprocessor">#ifdef _TIM6</span>
    748. 

  748. <a name="l00716"></a>00716 <span class="preprocessor"></span><span class="preprocessor">  #define TIM6                ((TIM_TypeDef *) TIM6_BASE)</span>
    749. 

  749. <a name="l00717"></a>00717 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM6 */</span>
    750. 

  750. <a name="l00718"></a>00718 
    751. 

  751. <a name="l00719"></a>00719 <span class="preprocessor">#ifdef _TIM7</span>
    752. 

  752. <a name="l00720"></a>00720 <span class="preprocessor"></span><span class="preprocessor">  #define TIM7                ((TIM_TypeDef *) TIM7_BASE)</span>
    753. 

  753. <a name="l00721"></a>00721 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM7 */</span>
    754. 

  754. <a name="l00722"></a>00722 
    755. 

  755. <a name="l00723"></a>00723 <span class="preprocessor">#ifdef _RTC</span>
    756. 

  756. <a name="l00724"></a>00724 <span class="preprocessor"></span><span class="preprocessor">  #define RTC                 ((RTC_TypeDef *) RTC_BASE)</span>
    757. 

  757. <a name="l00725"></a>00725 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_RTC */</span>
    758. 

  758. <a name="l00726"></a>00726 
    759. 

  759. <a name="l00727"></a>00727 <span class="preprocessor">#ifdef _WWDG</span>
    760. 

  760. <a name="l00728"></a>00728 <span class="preprocessor"></span><span class="preprocessor">  #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)</span>
    761. 

  761. <a name="l00729"></a>00729 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_WWDG */</span>
    762. 

  762. <a name="l00730"></a>00730 
    763. 

  763. <a name="l00731"></a>00731 <span class="preprocessor">#ifdef _IWDG</span>
    764. 

  764. <a name="l00732"></a>00732 <span class="preprocessor"></span><span class="preprocessor">  #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)</span>
    765. 

  765. <a name="l00733"></a>00733 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_IWDG */</span>
    766. 

  766. <a name="l00734"></a>00734 
    767. 

  767. <a name="l00735"></a>00735 <span class="preprocessor">#ifdef _SPI2</span>
    768. 

  768. <a name="l00736"></a>00736 <span class="preprocessor"></span><span class="preprocessor">  #define SPI2                ((SPI_TypeDef *) SPI2_BASE)</span>
    769. 

  769. <a name="l00737"></a>00737 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_SPI2 */</span>
    770. 

  770. <a name="l00738"></a>00738 
    771. 

  771. <a name="l00739"></a>00739 <span class="preprocessor">#ifdef _SPI3</span>
    772. 

  772. <a name="l00740"></a>00740 <span class="preprocessor"></span><span class="preprocessor">  #define SPI3                ((SPI_TypeDef *) SPI3_BASE)</span>
    773. 

  773. <a name="l00741"></a>00741 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_SPI3 */</span>
    774. 

  774. <a name…
    775.