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/arch/powerpc/kernel/setup_32.c

https://bitbucket.org/MikeC84/shooter-ics-crc-3.0.16-3a7b522
C | 350 lines | 234 code | 65 blank | 51 comment | 23 complexity | fedc3a1e6db9bf0d3bf919dcb4b38da8 MD5 | raw file
  1. /*
  2. * Common prep/pmac/chrp boot and setup code.
  3. */
  4. #include <linux/module.h>
  5. #include <linux/string.h>
  6. #include <linux/sched.h>
  7. #include <linux/init.h>
  8. #include <linux/kernel.h>
  9. #include <linux/reboot.h>
  10. #include <linux/delay.h>
  11. #include <linux/initrd.h>
  12. #include <linux/tty.h>
  13. #include <linux/bootmem.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/root_dev.h>
  16. #include <linux/cpu.h>
  17. #include <linux/console.h>
  18. #include <linux/memblock.h>
  19. #include <asm/io.h>
  20. #include <asm/prom.h>
  21. #include <asm/processor.h>
  22. #include <asm/pgtable.h>
  23. #include <asm/setup.h>
  24. #include <asm/smp.h>
  25. #include <asm/elf.h>
  26. #include <asm/cputable.h>
  27. #include <asm/bootx.h>
  28. #include <asm/btext.h>
  29. #include <asm/machdep.h>
  30. #include <asm/uaccess.h>
  31. #include <asm/system.h>
  32. #include <asm/pmac_feature.h>
  33. #include <asm/sections.h>
  34. #include <asm/nvram.h>
  35. #include <asm/xmon.h>
  36. #include <asm/time.h>
  37. #include <asm/serial.h>
  38. #include <asm/udbg.h>
  39. #include <asm/mmu_context.h>
  40. #include "setup.h"
  41. #define DBG(fmt...)
  42. extern void bootx_init(unsigned long r4, unsigned long phys);
  43. int boot_cpuid = -1;
  44. EXPORT_SYMBOL_GPL(boot_cpuid);
  45. int __initdata boot_cpu_count;
  46. int boot_cpuid_phys;
  47. int smp_hw_index[NR_CPUS];
  48. unsigned long ISA_DMA_THRESHOLD;
  49. unsigned int DMA_MODE_READ;
  50. unsigned int DMA_MODE_WRITE;
  51. #ifdef CONFIG_VGA_CONSOLE
  52. unsigned long vgacon_remap_base;
  53. EXPORT_SYMBOL(vgacon_remap_base);
  54. #endif
  55. /*
  56. * These are used in binfmt_elf.c to put aux entries on the stack
  57. * for each elf executable being started.
  58. */
  59. int dcache_bsize;
  60. int icache_bsize;
  61. int ucache_bsize;
  62. /*
  63. * We're called here very early in the boot. We determine the machine
  64. * type and call the appropriate low-level setup functions.
  65. * -- Cort <cort@fsmlabs.com>
  66. *
  67. * Note that the kernel may be running at an address which is different
  68. * from the address that it was linked at, so we must use RELOC/PTRRELOC
  69. * to access static data (including strings). -- paulus
  70. */
  71. notrace unsigned long __init early_init(unsigned long dt_ptr)
  72. {
  73. unsigned long offset = reloc_offset();
  74. struct cpu_spec *spec;
  75. /* First zero the BSS -- use memset_io, some platforms don't have
  76. * caches on yet */
  77. memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
  78. __bss_stop - __bss_start);
  79. /*
  80. * Identify the CPU type and fix up code sections
  81. * that depend on which cpu we have.
  82. */
  83. spec = identify_cpu(offset, mfspr(SPRN_PVR));
  84. do_feature_fixups(spec->cpu_features,
  85. PTRRELOC(&__start___ftr_fixup),
  86. PTRRELOC(&__stop___ftr_fixup));
  87. do_feature_fixups(spec->mmu_features,
  88. PTRRELOC(&__start___mmu_ftr_fixup),
  89. PTRRELOC(&__stop___mmu_ftr_fixup));
  90. do_lwsync_fixups(spec->cpu_features,
  91. PTRRELOC(&__start___lwsync_fixup),
  92. PTRRELOC(&__stop___lwsync_fixup));
  93. do_final_fixups();
  94. return KERNELBASE + offset;
  95. }
  96. /*
  97. * Find out what kind of machine we're on and save any data we need
  98. * from the early boot process (devtree is copied on pmac by prom_init()).
  99. * This is called very early on the boot process, after a minimal
  100. * MMU environment has been set up but before MMU_init is called.
  101. */
  102. notrace void __init machine_init(unsigned long dt_ptr)
  103. {
  104. lockdep_init();
  105. /* Enable early debugging if any specified (see udbg.h) */
  106. udbg_early_init();
  107. /* Do some early initialization based on the flat device tree */
  108. early_init_devtree(__va(dt_ptr));
  109. probe_machine();
  110. setup_kdump_trampoline();
  111. #ifdef CONFIG_6xx
  112. if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
  113. cpu_has_feature(CPU_FTR_CAN_NAP))
  114. ppc_md.power_save = ppc6xx_idle;
  115. #endif
  116. #ifdef CONFIG_E500
  117. if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
  118. cpu_has_feature(CPU_FTR_CAN_NAP))
  119. ppc_md.power_save = e500_idle;
  120. #endif
  121. if (ppc_md.progress)
  122. ppc_md.progress("id mach(): done", 0x200);
  123. }
  124. #ifdef CONFIG_BOOKE_WDT
  125. /* Checks wdt=x and wdt_period=xx command-line option */
  126. notrace int __init early_parse_wdt(char *p)
  127. {
  128. if (p && strncmp(p, "0", 1) != 0)
  129. booke_wdt_enabled = 1;
  130. return 0;
  131. }
  132. early_param("wdt", early_parse_wdt);
  133. int __init early_parse_wdt_period (char *p)
  134. {
  135. if (p)
  136. booke_wdt_period = simple_strtoul(p, NULL, 0);
  137. return 0;
  138. }
  139. early_param("wdt_period", early_parse_wdt_period);
  140. #endif /* CONFIG_BOOKE_WDT */
  141. /* Checks "l2cr=xxxx" command-line option */
  142. int __init ppc_setup_l2cr(char *str)
  143. {
  144. if (cpu_has_feature(CPU_FTR_L2CR)) {
  145. unsigned long val = simple_strtoul(str, NULL, 0);
  146. printk(KERN_INFO "l2cr set to %lx\n", val);
  147. _set_L2CR(0); /* force invalidate by disable cache */
  148. _set_L2CR(val); /* and enable it */
  149. }
  150. return 1;
  151. }
  152. __setup("l2cr=", ppc_setup_l2cr);
  153. /* Checks "l3cr=xxxx" command-line option */
  154. int __init ppc_setup_l3cr(char *str)
  155. {
  156. if (cpu_has_feature(CPU_FTR_L3CR)) {
  157. unsigned long val = simple_strtoul(str, NULL, 0);
  158. printk(KERN_INFO "l3cr set to %lx\n", val);
  159. _set_L3CR(val); /* and enable it */
  160. }
  161. return 1;
  162. }
  163. __setup("l3cr=", ppc_setup_l3cr);
  164. #ifdef CONFIG_GENERIC_NVRAM
  165. /* Generic nvram hooks used by drivers/char/gen_nvram.c */
  166. unsigned char nvram_read_byte(int addr)
  167. {
  168. if (ppc_md.nvram_read_val)
  169. return ppc_md.nvram_read_val(addr);
  170. return 0xff;
  171. }
  172. EXPORT_SYMBOL(nvram_read_byte);
  173. void nvram_write_byte(unsigned char val, int addr)
  174. {
  175. if (ppc_md.nvram_write_val)
  176. ppc_md.nvram_write_val(addr, val);
  177. }
  178. EXPORT_SYMBOL(nvram_write_byte);
  179. ssize_t nvram_get_size(void)
  180. {
  181. if (ppc_md.nvram_size)
  182. return ppc_md.nvram_size();
  183. return -1;
  184. }
  185. EXPORT_SYMBOL(nvram_get_size);
  186. void nvram_sync(void)
  187. {
  188. if (ppc_md.nvram_sync)
  189. ppc_md.nvram_sync();
  190. }
  191. EXPORT_SYMBOL(nvram_sync);
  192. #endif /* CONFIG_NVRAM */
  193. int __init ppc_init(void)
  194. {
  195. /* clear the progress line */
  196. if (ppc_md.progress)
  197. ppc_md.progress(" ", 0xffff);
  198. /* call platform init */
  199. if (ppc_md.init != NULL) {
  200. ppc_md.init();
  201. }
  202. return 0;
  203. }
  204. arch_initcall(ppc_init);
  205. static void __init irqstack_early_init(void)
  206. {
  207. unsigned int i;
  208. /* interrupt stacks must be in lowmem, we get that for free on ppc32
  209. * as the memblock is limited to lowmem by default */
  210. for_each_possible_cpu(i) {
  211. softirq_ctx[i] = (struct thread_info *)
  212. __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
  213. hardirq_ctx[i] = (struct thread_info *)
  214. __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
  215. }
  216. }
  217. #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
  218. static void __init exc_lvl_early_init(void)
  219. {
  220. unsigned int i, hw_cpu;
  221. /* interrupt stacks must be in lowmem, we get that for free on ppc32
  222. * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
  223. for_each_possible_cpu(i) {
  224. hw_cpu = get_hard_smp_processor_id(i);
  225. critirq_ctx[hw_cpu] = (struct thread_info *)
  226. __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
  227. #ifdef CONFIG_BOOKE
  228. dbgirq_ctx[hw_cpu] = (struct thread_info *)
  229. __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
  230. mcheckirq_ctx[hw_cpu] = (struct thread_info *)
  231. __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
  232. #endif
  233. }
  234. }
  235. #else
  236. #define exc_lvl_early_init()
  237. #endif
  238. /* Warning, IO base is not yet inited */
  239. void __init setup_arch(char **cmdline_p)
  240. {
  241. *cmdline_p = cmd_line;
  242. /* so udelay does something sensible, assume <= 1000 bogomips */
  243. loops_per_jiffy = 500000000 / HZ;
  244. unflatten_device_tree();
  245. check_for_initrd();
  246. if (ppc_md.init_early)
  247. ppc_md.init_early();
  248. find_legacy_serial_ports();
  249. smp_setup_cpu_maps();
  250. /* Register early console */
  251. register_early_udbg_console();
  252. xmon_setup();
  253. /*
  254. * Set cache line size based on type of cpu as a default.
  255. * Systems with OF can look in the properties on the cpu node(s)
  256. * for a possibly more accurate value.
  257. */
  258. dcache_bsize = cur_cpu_spec->dcache_bsize;
  259. icache_bsize = cur_cpu_spec->icache_bsize;
  260. ucache_bsize = 0;
  261. if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
  262. ucache_bsize = icache_bsize = dcache_bsize;
  263. /* reboot on panic */
  264. panic_timeout = 180;
  265. if (ppc_md.panic)
  266. setup_panic();
  267. init_mm.start_code = (unsigned long)_stext;
  268. init_mm.end_code = (unsigned long) _etext;
  269. init_mm.end_data = (unsigned long) _edata;
  270. init_mm.brk = klimit;
  271. exc_lvl_early_init();
  272. irqstack_early_init();
  273. /* set up the bootmem stuff with available memory */
  274. do_init_bootmem();
  275. if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
  276. #ifdef CONFIG_DUMMY_CONSOLE
  277. conswitchp = &dummy_con;
  278. #endif
  279. if (ppc_md.setup_arch)
  280. ppc_md.setup_arch();
  281. if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
  282. paging_init();
  283. /* Initialize the MMU context management stuff */
  284. mmu_context_init();
  285. }