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  3.         <title>core.cpuid</title>

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  4.         </head><body>

    5. 

  5.         <h1>core.cpuid</h1>

    6. 

  6.         <!-- Generated by Ddoc from src\core\cpuid.d -->

    7. 

  7. Identify the characteristics of the host CPU, providing information

    8. 

  8.  about cache sizes and assembly optimisation hints.

    9. 

  9. <br><br>

    10. 

  10. <b>References:</b><br>

    11. 

  11. Some of this information was extremely difficult to track down. Some of the

    12. 

  12.  documents below were found only in cached versions stored by search engines!

    13. 

  13.  This code relies on information found in:

    14. 

  14. <br><br>

    15. 

  15. 

    16. 

  16.  <ul><li>"Intel(R) 64 and IA-32 Architectures Software Developers Manual,

    17. 

  17.     Volume 2A: Instruction Set Reference, A-M" (2007).

    18. 

  18.  </li>

    19. 

  19.  <li>"AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).

    20. 

  20.  </li>

    21. 

  21.  <li>"AMD Processor Recognition Application Note For Processors Prior to AMD

    22. 

  22.     Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).

    23. 

  23.  </li>

    24. 

  24.  <li>"AMD Geode(TM) GX Processors Data Book",

    25. 

  25.     Advanced Micro Devices, Publication ID 31505E, (2005).

    26. 

  26.  </li>

    27. 

  27.  <li>"AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).

    28. 

  28.  </li>

    29. 

  29.  <li>"Application note 106: Software Customization for the 6x86 Family",

    30. 

  30.     Cyrix Corporation, Rev 1.5 (1998)

    31. 

  31.  </li>

    32. 

  32.  <li><a href="www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf">www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf</a></li>

    33. 

  33.  <li>"Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution",

    34. 

  34.    National Semiconductor, (2002)

    35. 

  35.  </li>

    36. 

  36.  <li>"The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).

    37. 

  37.  </li>

    38. 

  38.  <li><a href="http://www.sandpile.org/ia32/cpuid.htm">http://www.sandpile.org/ia32/cpuid.htm</a></li>

    39. 

  39.  <li><a href="www.akkadia.org/drepper/cpumemory.pdf">www.akkadia.org/drepper/cpumemory.pdf</a></li>

    40. 

  40.  <li>"What every programmer should know about memory",

    41. 

  41.     Ulrich Depper, Red Hat, Inc., (2007).

    42. 

  42.  </li>

    43. 

  43.  <li>"CPU Identification by the Windows Kernel", G. Chappell (2009).

    44. 

  44.    <a href="http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm">http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm</a>

    45. 

  45.  </li>

    46. 

  46.  <li>"Intel(R) Processor Identification and the CPUID Instruction, Application

    47. 

  47.     Note 485" (2009).

    48. 

  48.  </li>

    49. 

  49.  </ul>

    50. 

  50. 

    51. 

  51. <br><br>

    52. 

  52. <font color=red>BUGS:</font><br>

    53. 

  53. Currently only works on x86 and Itanium CPUs.

    54. 

  54.       Many processors have bugs in their microcode for the CPUID instruction,

    55. 

  55.       so sometimes the cache information may be incorrect.

    56. 

  56. 

    57. 

  57. <br><br>

    58. 

  58. <b>License:</b><br>

    59. 

  59. <a href="http://www.boost.org/LICENSE_1_0.txt">Boost License 1.0</a>

    60. 

  60. <br><br>

    61. 

  61. <b>Authors:</b><br>

    62. 

  62. Don Clugston, Tomas Lindquist Olsen &lt;tomas@famolsen.dk&gt;

    63. 

  63. <br><br>

    64. 

  64. <b>Source:</b><br>

    65. 

  65. <br><br>

    66. 

  66. 

    67. 

  67. <dl><dt><big>struct <u>CacheInfo</u>;

    68. 

  68. </big></dt>

    69. 

  69. <dd>Cache size and behaviour<br><br>

    70. 

  70. 

    71. 

  71. <dl><dt><big>uint <u>size</u>;

    72. 

  72. </big></dt>

    73. 

  73. <dd>Size of the cache, in kilobytes, per CPU.

    74. 

  74.  For L1 unified (data + code) caches, this <u>size</u> is half the physical <u>size</u>.

    75. 

  75.  (we don't halve it for larger sizes, since normally

    76. 

  76.  data <u>size</u> is much greater than code <u>size</u> for critical loops).<br><br>

    77. 

  77. 

    78. 

  78. </dd>

    79. 

  79. <dt><big>ubyte <u>associativity</u>;

    80. 

  80. </big></dt>

    81. 

  81. <dd>Number of ways of <u>associativity</u>, eg:

    82. 

  82.  1 = direct mapped

    83. 

  83.  2 = 2-way set associative

    84. 

  84.  3 = 3-way set associative

    85. 

  85.  ubyte.max = fully associative<br><br>

    86. 

  86. 

    87. 

  87. </dd>

    88. 

  88. <dt><big>uint <u>lineSize</u>;

    89. 

  89. </big></dt>

    90. 

  90. <dd>Number of bytes read into the cache when a cache miss occurs.<br><br>

    91. 

  91. 

    92. 

  92. </dd>

    93. 

  93. </dl>

    94. 

  94. </dd>

    95. 

  95. <dt><big>string <u>vendor</u>();

    96. 

  96. </big></dt>

    97. 

  97. <dd>Returns <u>vendor</u> string, for display purposes only.

    98. 

  98.  Do NOT use this to determine features!

    99. 

  99.  Note that some CPUs have programmable vendorIDs.<br><br>

    100. 

  100. 

    101. 

  101. </dd>

    102. 

  102. <dt><big>string <u>processor</u>();

    103. 

  103. </big></dt>

    104. 

  104. <dd>Returns <u>processor</u> string, for display purposes only<br><br>

    105. 

  105. 

    106. 

  106. </dd>

    107. 

  107. <dt><big>CacheInfo[5u] <u>datacache</u>;

    108. 

  108. </big></dt>

    109. 

  109. <dd>The data caches. If there are fewer than 5 physical caches levels,

    110. 

  110.  the remaining levels are set to uint.max (== entire memory space)<br><br>

    111. 

  111. 

    112. 

  112. </dd>

    113. 

  113. <dt><big>@property bool <u>x87onChip</u>();

    114. 

  114. </big></dt>

    115. 

  115. <dd>Does it have an x87 FPU on-chip?<br><br>

    116. 

  116. 

    117. 

  117. </dd>

    118. 

  118. <dt><big>@property bool <u>mmx</u>();

    119. 

  119. </big></dt>

    120. 

  120. <dd>Is MMX supported?<br><br>

    121. 

  121. 

    122. 

  122. </dd>

    123. 

  123. <dt><big>@property bool <u>sse</u>();

    124. 

  124. </big></dt>

    125. 

  125. <dd>Is SSE supported?<br><br>

    126. 

  126. 

    127. 

  127. </dd>

    128. 

  128. <dt><big>@property bool <u>sse2</u>();

    129. 

  129. </big></dt>

    130. 

  130. <dd>Is SSE2 supported?<br><br>

    131. 

  131. 

    132. 

  132. </dd>

    133. 

  133. <dt><big>@property bool <u>sse3</u>();

    134. 

  134. </big></dt>

    135. 

  135. <dd>Is SSE3 supported?<br><br>

    136. 

  136. 

    137. 

  137. </dd>

    138. 

  138. <dt><big>@property bool <u>ssse3</u>();

    139. 

  139. </big></dt>

    140. 

  140. <dd>Is SSSE3 supported?<br><br>

    141. 

  141. 

    142. 

  142. </dd>

    143. 

  143. <dt><big>@property bool <u>sse41</u>();

    144. 

  144. </big></dt>

    145. 

  145. <dd>Is SSE4.1 supported?<br><br>

    146. 

  146. 

    147. 

  147. </dd>

    148. 

  148. <dt><big>@property bool <u>sse42</u>();

    149. 

  149. </big></dt>

    150. 

  150. <dd>Is SSE4.2 supported?<br><br>

    151. 

  151. 

    152. 

  152. </dd>

    153. 

  153. <dt><big>@property bool <u>sse4a</u>();

    154. 

  154. </big></dt>

    155. 

  155. <dd>Is SSE4a supported?<br><br>

    156. 

  156. 

    157. 

  157. </dd>

    158. 

  158. <dt><big>@property bool <u>amd3dnow</u>();

    159. 

  159. </big></dt>

    160. 

  160. <dd>Is AMD 3DNOW supported?<br><br>

    161. 

  161. 

    162. 

  162. </dd>

    163. 

  163. <dt><big>@property bool <u>amd3dnowExt</u>();

    164. 

  164. </big></dt>

    165. 

  165. <dd>Is AMD 3DNOW Ext supported?<br><br>

    166. 

  166. 

    167. 

  167. </dd>

    168. 

  168. <dt><big>@property bool <u>amdMmx</u>();

    169. 

  169. </big></dt>

    170. 

  170. <dd>Are AMD extensions to MMX supported?<br><br>

    171. 

  171. 

    172. 

  172. </dd>

    173. 

  173. <dt><big>@property bool <u>hasFxsr</u>();

    174. 

  174. </big></dt>

    175. 

  175. <dd>Is fxsave/fxrstor supported?<br><br>

    176. 

  176. 

    177. 

  177. </dd>

    178. 

  178. <dt><big>@property bool <u>hasCmov</u>();

    179. 

  179. </big></dt>

    180. 

  180. <dd>Is cmov supported?<br><br>

    181. 

  181. 

    182. 

  182. </dd>

    183. 

  183. <dt><big>@property bool <u>hasRdtsc</u>();

    184. 

  184. </big></dt>

    185. 

  185. <dd>Is rdtsc supported?<br><br>

    186. 

  186. 

    187. 

  187. </dd>

    188. 

  188. <dt><big>@property bool <u>hasCmpxchg8b</u>();

    189. 

  189. </big></dt>

    190. 

  190. <dd>Is cmpxchg8b supported?<br><br>

    191. 

  191. 

    192. 

  192. </dd>

    193. 

  193. <dt><big>@property bool <u>hasCmpxchg16b</u>();

    194. 

  194. </big></dt>

    195. 

  195. <dd>Is cmpxchg8b supported?<br><br>

    196. 

  196. 

    197. 

  197. </dd>

    198. 

  198. <dt><big>@property bool <u>hasSysEnterSysExit</u>();

    199. 

  199. </big></dt>

    200. 

  200. <dd>Is SYSENTER/SYSEXIT supported?<br><br>

    201. 

  201. 

    202. 

  202. </dd>

    203. 

  203. <dt><big>@property bool <u>has3dnowPrefetch</u>();

    204. 

  204. </big></dt>

    205. 

  205. <dd>Is 3DNow prefetch supported?<br><br>

    206. 

  206. 

    207. 

  207. </dd>

    208. 

  208. <dt><big>@property bool <u>hasLahfSahf</u>();

    209. 

  209. </big></dt>

    210. 

  210. <dd>Are LAHF and SAHF supported in 64-bit mode?<br><br>

    211. 

  211. 

    212. 

  212. </dd>

    213. 

  213. <dt><big>@property bool <u>hasPopcnt</u>();

    214. 

  214. </big></dt>

    215. 

  215. <dd>Is POPCNT supported?<br><br>

    216. 

  216. 

    217. 

  217. </dd>

    218. 

  218. <dt><big>@property bool <u>hasLzcnt</u>();

    219. 

  219. </big></dt>

    220. 

  220. <dd>Is LZCNT supported?<br><br>

    221. 

  221. 

    222. 

  222. </dd>

    223. 

  223. <dt><big>@property bool <u>isX86_64</u>();

    224. 

  224. </big></dt>

    225. 

  225. <dd>Is this an Intel64 or AMD 64?<br><br>

    226. 

  226. 

    227. 

  227. </dd>

    228. 

  228. <dt><big>@property bool <u>isItanium</u>();

    229. 

  229. </big></dt>

    230. 

  230. <dd>Is this an IA64 (Itanium) processor?<br><br>

    231. 

  231. 

    232. 

  232. </dd>

    233. 

  233. <dt><big>@property bool <u>hyperThreading</u>();

    234. 

  234. </big></dt>

    235. 

  235. <dd>Is hyperthreading supported?<br><br>

    236. 

  236. 

    237. 

  237. </dd>

    238. 

  238. <dt><big>@property uint <u>threadsPerCPU</u>();

    239. 

  239. </big></dt>

    240. 

  240. <dd>Returns number of threads per CPU<br><br>

    241. 

  241. 

    242. 

  242. </dd>

    243. 

  243. <dt><big>@property uint <u>coresPerCPU</u>();

    244. 

  244. </big></dt>

    245. 

  245. <dd>Returns number of cores in CPU<br><br>

    246. 

  246. 

    247. 

  247. </dd>

    248. 

  248. <dt><big>@property bool <u>preferAthlon</u>();

    249. 

  249. </big></dt>

    250. 

  250. <dd>Optimisation hints for assembly code.

    251. 

  251.  For forward compatibility, the CPU is compared against different

    252. 

  252.  microarchitectures. For 32-bit X86, comparisons are made against

    253. 

  253.  the Intel PPro/PII/PIII/PM family.

    254. 

  254. <br><br>

    255. 

  255. The major 32-bit x86 microarchitecture 'dynasties' have been:

    256. 

  256.  (1) Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2).

    257. 

  257.  (2) AMD Athlon (K7, K8, K10).

    258. 

  258.  (3) Intel NetBurst (Pentium 4, Pentium D).

    259. 

  259.  (4) In-order Pentium (Pentium1, PMMX, Atom)

    260. 

  260.  Other early CPUs (Nx586, AMD K5, K6, Centaur C3, Transmeta,

    261. 

  261.    Cyrix, Rise) were mostly in-order.

    262. 

  262.  Some new processors do not fit into the existing categories:

    263. 

  263.  Intel Atom 230/330 (family 6, model 0x1C) is an in-order core.

    264. 

  264.  Centaur Isiah = VIA Nano (family 6, model F) is an out-of-order core.

    265. 

  265. <br><br>

    266. 

  266. 

    267. 

  267.  Within each dynasty, the optimisation techniques are largely

    268. 

  268.  identical (eg, use instruction pairing for group 4). Major

    269. 

  269.  instruction set improvements occur within each dynasty.

    270. 

  270.  Does this CPU perform better on AMD K7 code than PentiumPro..Core2 code?<br><br>

    271. 

  271. 

    272. 

  272. </dd>

    273. 

  273. <dt><big>@property bool <u>preferPentium4</u>();

    274. 

  274. </big></dt>

    275. 

  275. <dd>Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?<br><br>

    276. 

  276. 

    277. 

  277. </dd>

    278. 

  278. <dt><big>@property bool <u>preferPentium1</u>();

    279. 

  279. </big></dt>

    280. 

  280. <dd>Does this CPU perform better on Pentium I code than Pentium Pro code?<br><br>

    281. 

  281. 

    282. 

  282. </dd>

    283. 

  283. <dt><big>uint <u>stepping</u>;

    284. 

  284. </big></dt>

    285. 

  285. <dd>Processor type (vendor-dependent).

    286. 

  286.  This should be visible ONLY for display purposes.<br><br>

    287. 

  287. 

    288. 

  288. </dd>

    289. 

  289. <dt><big>uint <u>model</u>;

    290. 

  290. </big></dt>

    291. 

  291. <dd>Processor type (vendor-dependent).

    292. 

  292.  This should be visible ONLY for display purposes.<br><br>

    293. 

  293. 

    294. 

  294. </dd>

    295. 

  295. <dt><big>uint <u>family</u>;

    296. 

  296. </big></dt>

    297. 

  297. <dd>Processor type (vendor-dependent).

    298. 

  298.  This should be visible ONLY for display purposes.<br><br>

    299. 

  299. 

    300. 

  300. </dd>

    301. 

  301. </dl>

    302. 

  302. 

    303. 

  303.         <hr><small>Page generated by <a href="http://www.digitalmars.com/d/2.0/ddoc.html">Ddoc</a>. Copyright Don Clugston 2007 - 2009.

    304. 

  304. </small>

    305. 

  305.         </body></html>

    306. 

  306.