/lib/kruntime/doc/core_cpuid.html
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- <title>core.cpuid</title>
- </head><body>
- <h1>core.cpuid</h1>
- <!-- Generated by Ddoc from src\core\cpuid.d -->
- Identify the characteristics of the host CPU, providing information
- about cache sizes and assembly optimisation hints.
- <br><br>
- <b>References:</b><br>
- Some of this information was extremely difficult to track down. Some of the
- documents below were found only in cached versions stored by search engines!
- This code relies on information found in:
- <br><br>
-
- <ul><li>"Intel(R) 64 and IA-32 Architectures Software Developers Manual,
- Volume 2A: Instruction Set Reference, A-M" (2007).
- </li>
- <li>"AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
- </li>
- <li>"AMD Processor Recognition Application Note For Processors Prior to AMD
- Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).
- </li>
- <li>"AMD Geode(TM) GX Processors Data Book",
- Advanced Micro Devices, Publication ID 31505E, (2005).
- </li>
- <li>"AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
- </li>
- <li>"Application note 106: Software Customization for the 6x86 Family",
- Cyrix Corporation, Rev 1.5 (1998)
- </li>
- <li><a href="www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf">www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf</a></li>
- <li>"Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution",
- National Semiconductor, (2002)
- </li>
- <li>"The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
- </li>
- <li><a href="http://www.sandpile.org/ia32/cpuid.htm">http://www.sandpile.org/ia32/cpuid.htm</a></li>
- <li><a href="www.akkadia.org/drepper/cpumemory.pdf">www.akkadia.org/drepper/cpumemory.pdf</a></li>
- <li>"What every programmer should know about memory",
- Ulrich Depper, Red Hat, Inc., (2007).
- </li>
- <li>"CPU Identification by the Windows Kernel", G. Chappell (2009).
- <a href="http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm">http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm</a>
- </li>
- <li>"Intel(R) Processor Identification and the CPUID Instruction, Application
- Note 485" (2009).
- </li>
- </ul>
-
- <br><br>
- <font color=red>BUGS:</font><br>
- Currently only works on x86 and Itanium CPUs.
- Many processors have bugs in their microcode for the CPUID instruction,
- so sometimes the cache information may be incorrect.
-
- <br><br>
- <b>License:</b><br>
- <a href="http://www.boost.org/LICENSE_1_0.txt">Boost License 1.0</a>
- <br><br>
- <b>Authors:</b><br>
- Don Clugston, Tomas Lindquist Olsen <tomas@famolsen.dk>
- <br><br>
- <b>Source:</b><br>
- <br><br>
-
- <dl><dt><big>struct <u>CacheInfo</u>;
- </big></dt>
- <dd>Cache size and behaviour<br><br>
-
- <dl><dt><big>uint <u>size</u>;
- </big></dt>
- <dd>Size of the cache, in kilobytes, per CPU.
- For L1 unified (data + code) caches, this <u>size</u> is half the physical <u>size</u>.
- (we don't halve it for larger sizes, since normally
- data <u>size</u> is much greater than code <u>size</u> for critical loops).<br><br>
-
- </dd>
- <dt><big>ubyte <u>associativity</u>;
- </big></dt>
- <dd>Number of ways of <u>associativity</u>, eg:
- 1 = direct mapped
- 2 = 2-way set associative
- 3 = 3-way set associative
- ubyte.max = fully associative<br><br>
-
- </dd>
- <dt><big>uint <u>lineSize</u>;
- </big></dt>
- <dd>Number of bytes read into the cache when a cache miss occurs.<br><br>
-
- </dd>
- </dl>
- </dd>
- <dt><big>string <u>vendor</u>();
- </big></dt>
- <dd>Returns <u>vendor</u> string, for display purposes only.
- Do NOT use this to determine features!
- Note that some CPUs have programmable vendorIDs.<br><br>
-
- </dd>
- <dt><big>string <u>processor</u>();
- </big></dt>
- <dd>Returns <u>processor</u> string, for display purposes only<br><br>
-
- </dd>
- <dt><big>CacheInfo[5u] <u>datacache</u>;
- </big></dt>
- <dd>The data caches. If there are fewer than 5 physical caches levels,
- the remaining levels are set to uint.max (== entire memory space)<br><br>
-
- </dd>
- <dt><big>@property bool <u>x87onChip</u>();
- </big></dt>
- <dd>Does it have an x87 FPU on-chip?<br><br>
-
- </dd>
- <dt><big>@property bool <u>mmx</u>();
- </big></dt>
- <dd>Is MMX supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>sse</u>();
- </big></dt>
- <dd>Is SSE supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>sse2</u>();
- </big></dt>
- <dd>Is SSE2 supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>sse3</u>();
- </big></dt>
- <dd>Is SSE3 supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>ssse3</u>();
- </big></dt>
- <dd>Is SSSE3 supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>sse41</u>();
- </big></dt>
- <dd>Is SSE4.1 supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>sse42</u>();
- </big></dt>
- <dd>Is SSE4.2 supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>sse4a</u>();
- </big></dt>
- <dd>Is SSE4a supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>amd3dnow</u>();
- </big></dt>
- <dd>Is AMD 3DNOW supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>amd3dnowExt</u>();
- </big></dt>
- <dd>Is AMD 3DNOW Ext supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>amdMmx</u>();
- </big></dt>
- <dd>Are AMD extensions to MMX supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasFxsr</u>();
- </big></dt>
- <dd>Is fxsave/fxrstor supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasCmov</u>();
- </big></dt>
- <dd>Is cmov supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasRdtsc</u>();
- </big></dt>
- <dd>Is rdtsc supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasCmpxchg8b</u>();
- </big></dt>
- <dd>Is cmpxchg8b supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasCmpxchg16b</u>();
- </big></dt>
- <dd>Is cmpxchg8b supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasSysEnterSysExit</u>();
- </big></dt>
- <dd>Is SYSENTER/SYSEXIT supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>has3dnowPrefetch</u>();
- </big></dt>
- <dd>Is 3DNow prefetch supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasLahfSahf</u>();
- </big></dt>
- <dd>Are LAHF and SAHF supported in 64-bit mode?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasPopcnt</u>();
- </big></dt>
- <dd>Is POPCNT supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hasLzcnt</u>();
- </big></dt>
- <dd>Is LZCNT supported?<br><br>
-
- </dd>
- <dt><big>@property bool <u>isX86_64</u>();
- </big></dt>
- <dd>Is this an Intel64 or AMD 64?<br><br>
-
- </dd>
- <dt><big>@property bool <u>isItanium</u>();
- </big></dt>
- <dd>Is this an IA64 (Itanium) processor?<br><br>
-
- </dd>
- <dt><big>@property bool <u>hyperThreading</u>();
- </big></dt>
- <dd>Is hyperthreading supported?<br><br>
-
- </dd>
- <dt><big>@property uint <u>threadsPerCPU</u>();
- </big></dt>
- <dd>Returns number of threads per CPU<br><br>
-
- </dd>
- <dt><big>@property uint <u>coresPerCPU</u>();
- </big></dt>
- <dd>Returns number of cores in CPU<br><br>
-
- </dd>
- <dt><big>@property bool <u>preferAthlon</u>();
- </big></dt>
- <dd>Optimisation hints for assembly code.
- For forward compatibility, the CPU is compared against different
- microarchitectures. For 32-bit X86, comparisons are made against
- the Intel PPro/PII/PIII/PM family.
- <br><br>
- The major 32-bit x86 microarchitecture 'dynasties' have been:
- (1) Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2).
- (2) AMD Athlon (K7, K8, K10).
- (3) Intel NetBurst (Pentium 4, Pentium D).
- (4) In-order Pentium (Pentium1, PMMX, Atom)
- Other early CPUs (Nx586, AMD K5, K6, Centaur C3, Transmeta,
- Cyrix, Rise) were mostly in-order.
- Some new processors do not fit into the existing categories:
- Intel Atom 230/330 (family 6, model 0x1C) is an in-order core.
- Centaur Isiah = VIA Nano (family 6, model F) is an out-of-order core.
- <br><br>
-
- Within each dynasty, the optimisation techniques are largely
- identical (eg, use instruction pairing for group 4). Major
- instruction set improvements occur within each dynasty.
- Does this CPU perform better on AMD K7 code than PentiumPro..Core2 code?<br><br>
-
- </dd>
- <dt><big>@property bool <u>preferPentium4</u>();
- </big></dt>
- <dd>Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?<br><br>
-
- </dd>
- <dt><big>@property bool <u>preferPentium1</u>();
- </big></dt>
- <dd>Does this CPU perform better on Pentium I code than Pentium Pro code?<br><br>
-
- </dd>
- <dt><big>uint <u>stepping</u>;
- </big></dt>
- <dd>Processor type (vendor-dependent).
- This should be visible ONLY for display purposes.<br><br>
-
- </dd>
- <dt><big>uint <u>model</u>;
- </big></dt>
- <dd>Processor type (vendor-dependent).
- This should be visible ONLY for display purposes.<br><br>
-
- </dd>
- <dt><big>uint <u>family</u>;
- </big></dt>
- <dd>Processor type (vendor-dependent).
- This should be visible ONLY for display purposes.<br><br>
-
- </dd>
- </dl>
-
- <hr><small>Page generated by <a href="http://www.digitalmars.com/d/2.0/ddoc.html">Ddoc</a>. Copyright Don Clugston 2007 - 2009.
- </small>
- </body></html>