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/src/kernel/drivers/net/ixgbe/ixgbe_dcb_82598.c

https://github.com/ccampos784/sch-i500-gingerbread
C | 401 lines | 214 code | 59 blank | 128 comment | 37 complexity | 7967d927587b2838bfe58a42a196a386 MD5 | raw file
  1. /*******************************************************************************
  2. Intel 10 Gigabit PCI Express Linux driver
  3. Copyright(c) 1999 - 2010 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20. *******************************************************************************/
  21. #include "ixgbe.h"
  22. #include "ixgbe_type.h"
  23. #include "ixgbe_dcb.h"
  24. #include "ixgbe_dcb_82598.h"
  25. /**
  26. * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
  27. * @hw: pointer to hardware structure
  28. * @stats: pointer to statistics structure
  29. * @tc_count: Number of elements in bwg_array.
  30. *
  31. * This function returns the status data for each of the Traffic Classes in use.
  32. */
  33. s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
  34. struct ixgbe_hw_stats *stats,
  35. u8 tc_count)
  36. {
  37. int tc;
  38. if (tc_count > MAX_TRAFFIC_CLASS)
  39. return DCB_ERR_PARAM;
  40. /* Statistics pertaining to each traffic class */
  41. for (tc = 0; tc < tc_count; tc++) {
  42. /* Transmitted Packets */
  43. stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
  44. /* Transmitted Bytes */
  45. stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
  46. /* Received Packets */
  47. stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
  48. /* Received Bytes */
  49. stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
  50. }
  51. return 0;
  52. }
  53. /**
  54. * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
  55. * @hw: pointer to hardware structure
  56. * @stats: pointer to statistics structure
  57. * @tc_count: Number of elements in bwg_array.
  58. *
  59. * This function returns the CBFC status data for each of the Traffic Classes.
  60. */
  61. s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
  62. struct ixgbe_hw_stats *stats,
  63. u8 tc_count)
  64. {
  65. int tc;
  66. if (tc_count > MAX_TRAFFIC_CLASS)
  67. return DCB_ERR_PARAM;
  68. for (tc = 0; tc < tc_count; tc++) {
  69. /* Priority XOFF Transmitted */
  70. stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
  71. /* Priority XOFF Received */
  72. stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
  73. }
  74. return 0;
  75. }
  76. /**
  77. * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
  78. * @hw: pointer to hardware structure
  79. * @dcb_config: pointer to ixgbe_dcb_config structure
  80. *
  81. * Configure packet buffers for DCB mode.
  82. */
  83. static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
  84. struct ixgbe_dcb_config *dcb_config)
  85. {
  86. s32 ret_val = 0;
  87. u32 value = IXGBE_RXPBSIZE_64KB;
  88. u8 i = 0;
  89. /* Setup Rx packet buffer sizes */
  90. switch (dcb_config->rx_pba_cfg) {
  91. case pba_80_48:
  92. /* Setup the first four at 80KB */
  93. value = IXGBE_RXPBSIZE_80KB;
  94. for (; i < 4; i++)
  95. IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
  96. /* Setup the last four at 48KB...don't re-init i */
  97. value = IXGBE_RXPBSIZE_48KB;
  98. /* Fall Through */
  99. case pba_equal:
  100. default:
  101. for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
  102. IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
  103. /* Setup Tx packet buffer sizes */
  104. for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
  105. IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
  106. IXGBE_TXPBSIZE_40KB);
  107. }
  108. break;
  109. }
  110. return ret_val;
  111. }
  112. /**
  113. * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
  114. * @hw: pointer to hardware structure
  115. * @dcb_config: pointer to ixgbe_dcb_config structure
  116. *
  117. * Configure Rx Data Arbiter and credits for each traffic class.
  118. */
  119. s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
  120. struct ixgbe_dcb_config *dcb_config)
  121. {
  122. struct tc_bw_alloc *p;
  123. u32 reg = 0;
  124. u32 credit_refill = 0;
  125. u32 credit_max = 0;
  126. u8 i = 0;
  127. reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
  128. IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
  129. reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
  130. /* Enable Arbiter */
  131. reg &= ~IXGBE_RMCS_ARBDIS;
  132. /* Enable Receive Recycle within the BWG */
  133. reg |= IXGBE_RMCS_RRM;
  134. /* Enable Deficit Fixed Priority arbitration*/
  135. reg |= IXGBE_RMCS_DFP;
  136. IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
  137. /* Configure traffic class credits and priority */
  138. for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  139. p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
  140. credit_refill = p->data_credits_refill;
  141. credit_max = p->data_credits_max;
  142. reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
  143. if (p->prio_type == prio_link)
  144. reg |= IXGBE_RT2CR_LSP;
  145. IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
  146. }
  147. reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
  148. reg |= IXGBE_RDRXCTL_RDMTS_1_2;
  149. reg |= IXGBE_RDRXCTL_MPBEN;
  150. reg |= IXGBE_RDRXCTL_MCEN;
  151. IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
  152. reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
  153. /* Make sure there is enough descriptors before arbitration */
  154. reg &= ~IXGBE_RXCTRL_DMBYPS;
  155. IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
  156. return 0;
  157. }
  158. /**
  159. * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
  160. * @hw: pointer to hardware structure
  161. * @dcb_config: pointer to ixgbe_dcb_config structure
  162. *
  163. * Configure Tx Descriptor Arbiter and credits for each traffic class.
  164. */
  165. s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
  166. struct ixgbe_dcb_config *dcb_config)
  167. {
  168. struct tc_bw_alloc *p;
  169. u32 reg, max_credits;
  170. u8 i;
  171. reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
  172. /* Enable arbiter */
  173. reg &= ~IXGBE_DPMCS_ARBDIS;
  174. if (!(dcb_config->round_robin_enable)) {
  175. /* Enable DFP and Recycle mode */
  176. reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
  177. }
  178. reg |= IXGBE_DPMCS_TSOEF;
  179. /* Configure Max TSO packet size 34KB including payload and headers */
  180. reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
  181. IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
  182. /* Configure traffic class credits and priority */
  183. for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  184. p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
  185. max_credits = dcb_config->tc_config[i].desc_credits_max;
  186. reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
  187. reg |= p->data_credits_refill;
  188. reg |= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
  189. if (p->prio_type == prio_group)
  190. reg |= IXGBE_TDTQ2TCCR_GSP;
  191. if (p->prio_type == prio_link)
  192. reg |= IXGBE_TDTQ2TCCR_LSP;
  193. IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
  194. }
  195. return 0;
  196. }
  197. /**
  198. * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
  199. * @hw: pointer to hardware structure
  200. * @dcb_config: pointer to ixgbe_dcb_config structure
  201. *
  202. * Configure Tx Data Arbiter and credits for each traffic class.
  203. */
  204. s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
  205. struct ixgbe_dcb_config *dcb_config)
  206. {
  207. struct tc_bw_alloc *p;
  208. u32 reg;
  209. u8 i;
  210. reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
  211. /* Enable Data Plane Arbiter */
  212. reg &= ~IXGBE_PDPMCS_ARBDIS;
  213. /* Enable DFP and Transmit Recycle Mode */
  214. reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
  215. IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
  216. /* Configure traffic class credits and priority */
  217. for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  218. p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
  219. reg = p->data_credits_refill;
  220. reg |= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT;
  221. reg |= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;
  222. if (p->prio_type == prio_group)
  223. reg |= IXGBE_TDPT2TCCR_GSP;
  224. if (p->prio_type == prio_link)
  225. reg |= IXGBE_TDPT2TCCR_LSP;
  226. IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
  227. }
  228. /* Enable Tx packet buffer division */
  229. reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
  230. reg |= IXGBE_DTXCTL_ENDBUBD;
  231. IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
  232. return 0;
  233. }
  234. /**
  235. * ixgbe_dcb_config_pfc_82598 - Config priority flow control
  236. * @hw: pointer to hardware structure
  237. * @dcb_config: pointer to ixgbe_dcb_config structure
  238. *
  239. * Configure Priority Flow Control for each traffic class.
  240. */
  241. s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
  242. struct ixgbe_dcb_config *dcb_config)
  243. {
  244. u32 reg, rx_pba_size;
  245. u8 i;
  246. if (!dcb_config->pfc_mode_enable)
  247. goto out;
  248. /* Enable Transmit Priority Flow Control */
  249. reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
  250. reg &= ~IXGBE_RMCS_TFCE_802_3X;
  251. /* correct the reporting of our flow control status */
  252. reg |= IXGBE_RMCS_TFCE_PRIORITY;
  253. IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
  254. /* Enable Receive Priority Flow Control */
  255. reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
  256. reg &= ~IXGBE_FCTRL_RFCE;
  257. reg |= IXGBE_FCTRL_RPFCE;
  258. IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
  259. /*
  260. * Configure flow control thresholds and enable priority flow control
  261. * for each traffic class.
  262. */
  263. for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  264. if (dcb_config->rx_pba_cfg == pba_equal) {
  265. rx_pba_size = IXGBE_RXPBSIZE_64KB;
  266. } else {
  267. rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB
  268. : IXGBE_RXPBSIZE_48KB;
  269. }
  270. reg = ((rx_pba_size >> 5) & 0xFFF0);
  271. if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
  272. dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
  273. reg |= IXGBE_FCRTL_XONE;
  274. IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
  275. reg = ((rx_pba_size >> 2) & 0xFFF0);
  276. if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
  277. dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
  278. reg |= IXGBE_FCRTH_FCEN;
  279. IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
  280. }
  281. /* Configure pause time */
  282. for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
  283. IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
  284. /* Configure flow control refresh threshold value */
  285. IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
  286. out:
  287. return 0;
  288. }
  289. /**
  290. * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
  291. * @hw: pointer to hardware structure
  292. *
  293. * Configure queue statistics registers, all queues belonging to same traffic
  294. * class uses a single set of queue statistics counters.
  295. */
  296. s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
  297. {
  298. u32 reg = 0;
  299. u8 i = 0;
  300. u8 j = 0;
  301. /* Receive Queues stats setting - 8 queues per statistics reg */
  302. for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
  303. reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
  304. reg |= ((0x1010101) * j);
  305. IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
  306. reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
  307. reg |= ((0x1010101) * j);
  308. IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
  309. }
  310. /* Transmit Queues stats setting - 4 queues per statistics reg */
  311. for (i = 0; i < 8; i++) {
  312. reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
  313. reg |= ((0x1010101) * i);
  314. IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
  315. }
  316. return 0;
  317. }
  318. /**
  319. * ixgbe_dcb_hw_config_82598 - Config and enable DCB
  320. * @hw: pointer to hardware structure
  321. * @dcb_config: pointer to ixgbe_dcb_config structure
  322. *
  323. * Configure dcb settings and enable dcb mode.
  324. */
  325. s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
  326. struct ixgbe_dcb_config *dcb_config)
  327. {
  328. ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config);
  329. ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
  330. ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
  331. ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
  332. ixgbe_dcb_config_pfc_82598(hw, dcb_config);
  333. ixgbe_dcb_config_tc_stats_82598(hw);
  334. return 0;
  335. }