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/SYS_V1.50/include/Config.h

https://github.com/fredcooke/DSOQuad_SourceCode
C Header | 220 lines | 167 code | 31 blank | 22 comment | 0 complexity | 812b7b5333623ebf944a40b6e900c2fc MD5 | raw file
    

  1. /********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ********************
    2. 

  2.  File Name : Config.h       
    3. 

  3.  Version   : DS203_SYS Ver 1.2x                                 Author : bure
    4. 

  4. *******************************************************************************/
    5. 

  5. #ifndef __CONFIG_H
    6. 

  6. #define __CONFIG_H
    7. 

  7. 

  8. #include "stm32f10x_lib.h"
    9. 

  9. 

  10. //============================================================================//
    11. 

  11. 

  12. #define BULK_MAX_PACKET_SIZE  0x00000040
    13. 

  13. 

  14. #define FSMC_BCR1   (*((vu32 *)(0xA0000000+0x00)))   
    15. 

  15. #define FSMC_BTR1   (*((vu32 *)(0xA0000000+0x04)))
    16. 

  16. #define FSMC_BWTR1  (*((vu32 *)(0xA0000000+0x104)))
    17. 

  17. #define FSMC_BCR2   (*((vu32 *)(0xA0000008+0x00)))   
    18. 

  18. #define FSMC_BTR2   (*((vu32 *)(0xA0000008+0x04)))
    19. 

  19. #define FSMC_BWTR2  (*((vu32 *)(0xA0000008+0x104)))
    20. 

  20. 

  21. #define FPGA_PORT   (*((vu16 *)(0x64000000+0x00)))
    22. 

  22. #define FPGA_PORT_ADDR         (0x64000000+0x00)
    23. 

  23. 

  24. #define LCD_PORT    (*((vu16 *)(0x60000000+0x00)))
    25. 

  25. #define LCD_PORT_ADDR          (0x60000000+0x00)
    26. 

  26. 

  27. 

  28. #define RCC_AHBENR  (*((vu32 *)(0x40021000+0x14)))
    29. 

  29. #define RCC_APB2ENR (*((vu32 *)(0x40021000+0x18)))
    30. 

  30. #define RCC_APB1ENR (*((vu32 *)(0x40021000+0x1C)))
    31. 

  31. #define RCC_CFGR    (*((vu32 *)(0x40021000+0x04)))
    32. 

  32. 

  33. #define TIM1_CR1    (*((vu32 *)(0x40012C00+0x00)))
    34. 

  34. #define TIM1_CR2    (*((vu32 *)(0x40012C00+0x04)))
    35. 

  35. #define TIM1_DIER   (*((vu32 *)(0x40012C00+0x0C)))
    36. 

  36. #define TIM1_SR     (*((vu32 *)(0x40012C00+0x10)))
    37. 

  37. #define TIM1_CCMR1  (*((vu32 *)(0x40012C00+0x18)))
    38. 

  38. #define TIM1_CCER   (*((vu32 *)(0x40012C00+0x20)))
    39. 

  39. #define TIM1_PSC    (*((vu32 *)(0x40012C00+0x28)))
    40. 

  40. #define TIM1_ARR    (*((vu32 *)(0x40012C00+0x2C)))
    41. 

  41. #define TIM1_RCR    (*((vu32 *)(0x40012C00+0x30)))
    42. 

  42. #define TIM1_CCR1   (*((vu32 *)(0x40012C00+0x34)))
    43. 

  43. #define TIM1_BDTR   (*((vu32 *)(0x40012C00+0x44)))
    44. 

  44. 

  45. #define TIM8_CR1    (*((vu32 *)(0x40013400+0x00)))
    46. 

  46. #define TIM8_CR2    (*((vu32 *)(0x40013400+0x04)))
    47. 

  47. #define TIM8_DIER   (*((vu32 *)(0x40013400+0x0C)))
    48. 

  48. #define TIM8_SR     (*((vu32 *)(0x40013400+0x10)))
    49. 

  49. #define TIM8_CCMR1  (*((vu32 *)(0x40013400+0x18)))
    50. 

  50. #define TIM8_CCER   (*((vu32 *)(0x40013400+0x20)))
    51. 

  51. #define TIM8_PSC    (*((vu32 *)(0x40013400+0x28)))
    52. 

  52. #define TIM8_ARR    (*((vu32 *)(0x40013400+0x2C)))
    53. 

  53. #define TIM8_RCR    (*((vu32 *)(0x40013400+0x30)))
    54. 

  54. #define TIM8_CCR1   (*((vu32 *)(0x40013400+0x34)))
    55. 

  55. #define TIM8_CCR2   (*((vu32 *)(0x40013400+0x38)))
    56. 

  56. #define TIM8_BDTR   (*((vu32 *)(0x40013400+0x44)))
    57. 

  57. 

  58. #define TIM2_CR1    (*((vu32 *)(0x40000000+0x00)))
    59. 

  59. #define TIM2_DIER   (*((vu32 *)(0x40000000+0x0C)))
    60. 

  60. #define TIM2_SR     (*((vu32 *)(0x40000000+0x10)))
    61. 

  61. #define TIM2_CCMR1  (*((vu32 *)(0x40000000+0x18)))
    62. 

  62. #define TIM2_CCMR2  (*((vu32 *)(0x40000000+0x1C)))
    63. 

  63. #define TIM2_CCER   (*((vu32 *)(0x40000000+0x20)))
    64. 

  64. #define TIM2_PSC    (*((vu32 *)(0x40000000+0x28)))
    65. 

  65. #define TIM2_ARR    (*((vu32 *)(0x40000000+0x2C)))
    66. 

  66. #define TIM2_CCR1   (*((vu32 *)(0x40000000+0x34)))
    67. 

  67. #define TIM2_CCR2   (*((vu32 *)(0x40000000+0x38)))
    68. 

  68. #define TIM2_CCR3   (*((vu32 *)(0x40000000+0x3C)))
    69. 

  69. 

  70. #define TIM5_CR1    (*((vu32 *)(0x40000C00+0x00)))
    71. 

  71. #define TIM5_CR2    (*((vu32 *)(0x40000C00+0x04)))
    72. 

  72. //#define TIM5_DIER   (*((vu32 *)(0x40000C00+0x0C)))
    73. 

  73. #define TIM5_CCMR1  (*((vu32 *)(0x40000C00+0x18)))
    74. 

  74. #define TIM5_CCMR2  (*((vu32 *)(0x40000C00+0x1C)))
    75. 

  75. #define TIM5_CCER   (*((vu32 *)(0x40000C00+0x20)))
    76. 

  76. #define TIM5_PSC    (*((vu32 *)(0x40000C00+0x28)))
    77. 

  77. #define TIM5_ARR    (*((vu32 *)(0x40000C00+0x2C)))
    78. 

  78. #define TIM5_CCR1   (*((vu32 *)(0x40000C00+0x34)))
    79. 

  79. #define TIM5_CCR2   (*((vu32 *)(0x40000C00+0x38)))
    80. 

  80. #define TIM5_CCR3   (*((vu32 *)(0x40000C00+0x3C)))
    81. 

  81. //#define TIM5_CCR4   (*((vu32 *)(0x40000C00+0x40)))
    82. 

  82. 

  83. #define TIM7_CR1    (*((vu32 *)(0x40001400+0x00)))
    84. 

  84. #define TIM7_CR2    (*((vu32 *)(0x40001400+0x04)))
    85. 

  85. #define TIM7_DIER   (*((vu32 *)(0x40001400+0x0C)))
    86. 

  86. //#define TIM7_CCER   (*((vu32 *)(0x40001400+0x20)))
    87. 

  87. #define TIM7_PSC    (*((vu32 *)(0x40001400+0x28)))
    88. 

  88. #define TIM7_ARR    (*((vu32 *)(0x40001400+0x2C)))
    89. 

  89. //#define TIM7_CCR1   (*((vu32 *)(0x40001400+0x34)))
    90. 

  90. //#define TIM7_CCR2   (*((vu32 *)(0x40001400+0x38)))
    91. 

  91. 

  92. #define TIM3_CR1    (*((vu32 *)(0x40000400+0x00)))
    93. 

  93. //#define TIM3_SMCR   (*((vu32 *)(0x40000400+0x08)))
    94. 

  94. #define TIM3_DIER   (*((vu32 *)(0x40000400+0x0C)))
    95. 

  95. #define TIM3_SR     (*((vu32 *)(0x40000400+0x10)))
    96. 

  96. //#define TIM3_CCMR1  (*((vu32 *)(0x40000400+0x18)))
    97. 

  97. //#define TIM3_CCER   (*((vu32 *)(0x40000400+0x20)))
    98. 

  98. #define TIM3_PSC    (*((vu32 *)(0x40000400+0x28)))
    99. 

  99. #define TIM3_ARR    (*((vu32 *)(0x40000400+0x2C)))
    100. 

  100. //#define TIM3_CCR2   (*((vu32 *)(0x40000400+0x38)))
    101. 

  101. 

  102. #define TIM4_CR1    (*((vu32 *)(0x40000800+0x00)))
    103. 

  103. //#define TIM4_DIER   (*((vu32 *)(0x40000800+0x0C)))
    104. 

  104. //#define TIM4_SR     (*((vu32 *)(0x40000800+0x10)))
    105. 

  105. #define TIM4_CCMR1  (*((vu32 *)(0x40000800+0x18)))
    106. 

  106. //#define TIM4_CCMR2  (*((vu32 *)(0x40000800+0x1C)))
    107. 

  107. #define TIM4_CCER   (*((vu32 *)(0x40000800+0x20)))
    108. 

  108. #define TIM4_PSC    (*((vu32 *)(0x40000800+0x28)))
    109. 

  109. #define TIM4_ARR    (*((vu32 *)(0x40000800+0x2C)))
    110. 

  110. #define TIM4_CCR1   (*((vu32 *)(0x40000800+0x34)))
    111. 

  111. //#define TIM4_CCR2   (*((vu32 *)(0x40000800+0x38)))
    112. 

  112. //#define TIM4_CCR3   (*((vu32 *)(0x40000800+0x3C)))
    113. 

  113. //#define TIM4_CCR4   (*((vu32 *)(0x40000800+0x40)))
    114. 

  114. 

  115. #define DAC_CR      (*((vu32 *)(0x40007400+0x00)))
    116. 

  116. #define DAC_DHR12R1 (*((vu32 *)(0x40007400+0x08)))
    117. 

  117. #define DAC_DHR12R1_ADDR ((vu32)(0x40007400+0x08))
    118. 

  118. 

  119. #define ADC3_CR1    (*((vu32 *)(0x40013C00+0x04)))
    120. 

  120. #define ADC3_CR2    (*((vu32 *)(0x40013C00+0x08)))
    121. 

  121. #define ADC3_SMPR1  (*((vu32 *)(0x40013C00+0x0C)))
    122. 

  122. #define ADC3_SMPR2  (*((vu32 *)(0x40013C00+0x10)))
    123. 

  123. #define ADC3_SQR1   (*((vu32 *)(0x40013C00+0x2C)))
    124. 

  124. #define ADC3_SQR3   (*((vu32 *)(0x40013C00+0x34)))
    125. 

  125. #define ADC3_DR     (*((vu32 *)(0x40013C00+0x4C)))
    126. 

  126. 

  127. #define ADC2_CR1    (*((vu32 *)(0x40012800+0x04)))
    128. 

  128. #define ADC2_CR2    (*((vu32 *)(0x40012800+0x08)))
    129. 

  129. #define ADC2_SMPR1  (*((vu32 *)(0x40012800+0x0C)))
    130. 

  130. #define ADC2_SMPR2  (*((vu32 *)(0x40012800+0x10)))
    131. 

  131. #define ADC2_SQR1   (*((vu32 *)(0x40012800+0x2C)))
    132. 

  132. #define ADC2_SQR3   (*((vu32 *)(0x40012800+0x34)))
    133. 

  133. 

  134. #define ADC1_CR1    (*((vu32 *)(0x40012400+0x04)))
    135. 

  135. #define ADC1_CR2    (*((vu32 *)(0x40012400+0x08)))
    136. 

  136. #define ADC1_SMPR1  (*((vu32 *)(0x40012400+0x0C)))
    137. 

  137. #define ADC1_SMPR2  (*((vu32 *)(0x40012400+0x10)))
    138. 

  138. #define ADC1_SQR1   (*((vu32 *)(0x40012400+0x2C)))
    139. 

  139. #define ADC1_SQR3   (*((vu32 *)(0x40012400+0x34)))
    140. 

  140. #define ADC1_DR     (*((vu32 *)(0x40012400+0x4C)))
    141. 

  141. #define ADC1_DR_ADDR  ((u32)0x4001244C)
    142. 

  142. 

  143. #define DMA_ISR     (*((vu32 *)(0x40020000+0x00)))
    144. 

  144. #define DMA_IFCR    (*((vu32 *)(0x40020000+0x04)))
    145. 

  145. #define DMA1_CCR1   (*((vu32 *)(0x40020000+0x08)))
    146. 

  146. #define DMA1_CNDTR1 (*((vu32 *)(0x40020000+0x0C)))
    147. 

  147. #define DMA1_CPAR1  (*((vu32 *)(0x40020000+0x10)))
    148. 

  148. #define DMA1_CMAR1  (*((vu32 *)(0x40020000+0x14)))
    149. 

  149. #define DMA1_CCR2   (*((vu32 *)(0x40020000+0x1C)))
    150. 

  150. #define DMA1_CNDTR2 (*((vu32 *)(0x40020000+0x20)))
    151. 

  151. #define DMA1_CPAR2  (*((vu32 *)(0x40020000+0x24)))
    152. 

  152. #define DMA1_CMAR2  (*((vu32 *)(0x40020000+0x28)))
    153. 

  153. 

  154. #define DMA2_CCR1   (*((vu32 *)(0x40020400+0x08)))
    155. 

  155. #define DMA2_CNDTR1 (*((vu32 *)(0x40020400+0x0C)))
    156. 

  156. #define DMA2_CPAR1  (*((vu32 *)(0x40020400+0x10)))
    157. 

  157. #define DMA2_CMAR1  (*((vu32 *)(0x40020400+0x14)))
    158. 

  158. #define DMA2_CCR2   (*((vu32 *)(0x40020400+0x1C)))
    159. 

  159. #define DMA2_CNDTR2 (*((vu32 *)(0x40020400+0x20)))
    160. 

  160. #define DMA2_CPAR2  (*((vu32 *)(0x40020400+0x24)))
    161. 

  161. #define DMA2_CMAR2  (*((vu32 *)(0x40020400+0x28)))
    162. 

  162. #define DMA2_CCR4   (*((vu32 *)(0x40020400+0x44)))
    163. 

  163. #define DMA2_CNDTR4 (*((vu32 *)(0x40020400+0x48)))
    164. 

  164. #define DMA2_CPAR4  (*((vu32 *)(0x40020400+0x4C)))
    165. 

  165. #define DMA2_CMAR4  (*((vu32 *)(0x40020400+0x50)))
    166. 

  166. 

  167. 

  168. #define GPIOA_CRL   (*((vu32 *)(0x40010800+0x00)))
    169. 

  169. #define GPIOA_CRH   (*((vu32 *)(0x40010800+0x04)))
    170. 

  170. #define GPIOA_IDR   (*((vu32 *)(0x40010800+0x08)))
    171. 

  171. #define GPIOA_ODR   (*((vu32 *)(0x40010800+0x0C)))
    172. 

  172. #define GPIOA_BSRR  (*((vu32 *)(0x40010800+0x10)))
    173. 

  173. #define GPIOA_BRR   (*((vu32 *)(0x40010800+0x14)))
    174. 

  174. 

  175. #define GPIOB_CRL   (*((vu32 *)(0x40010C00+0x00)))
    176. 

  176. #define GPIOB_CRH   (*((vu32 *)(0x40010C00+0x04)))
    177. 

  177. #define GPIOB_IDR   (*((vu32 *)(0x40010C00+0x08)))
    178. 

  178. #define GPIOB_ODR   (*((vu32 *)(0x40010C00+0x0C)))
    179. 

  179. #define GPIOB_BSRR  (*((vu32 *)(0x40010C00+0x10)))
    180. 

  180. #define GPIOB_BRR   (*((vu32 *)(0x40010C00+0x14)))
    181. 

  181. 

  182. #define GPIOC_CRL   (*((vu32 *)(0x40011000+0x00)))
    183. 

  183. #define GPIOC_CRH   (*((vu32 *)(0x40011000+0x04)))
    184. 

  184. #define GPIOC_ODR   (*((vu32 *)(0x40011000+0x0C)))
    185. 

  185. #define GPIOC_IDR   (*((vu32 *)(0x40011000+0x08)))
    186. 

  186. #define GPIOC_BSRR  (*((vu32 *)(0x40011000+0x10)))
    187. 

  187. #define GPIOC_BRR   (*((vu32 *)(0x40011000+0x14)))
    188. 

  188. 

  189. #define GPIOD_CRL   (*((vu32 *)(0x40011400+0x00)))
    190. 

  190. #define GPIOD_CRH   (*((vu32 *)(0x40011400+0x04)))
    191. 

  191. #define GPIOD_ODR   (*((vu32 *)(0x40011400+0x0C)))
    192. 

  192. #define GPIOD_IDR   (*((vu32 *)(0x40011400+0x08)))
    193. 

  193. #define GPIOD_BSRR  (*((vu32 *)(0x40011400+0x10)))
    194. 

  194. #define GPIOD_BRR   (*((vu32 *)(0x40011400+0x14)))
    195. 

  195. 

  196. #define GPIOE_CRL   (*((vu32 *)(0x40011800+0x00)))
    197. 

  197. #define GPIOE_CRH   (*((vu32 *)(0x40011800+0x04)))
    198. 

  198. #define GPIOE_ODR   (*((vu32 *)(0x40011800+0x0C)))
    199. 

  199. #define GPIOE_IDR   (*((vu32 *)(0x40011800+0x08)))
    200. 

  200. #define GPIOE_BSRR  (*((vu32 *)(0x40011800+0x10)))
    201. 

  201. #define GPIOE_BRR   (*((vu32 *)(0x40011800+0x14)))
    202. 

  202. 

  203. #define AFIO_MAPR   (*((vu32 *)(0x40010000+0x04)))
    204. 

  204. 

  205. /*************************   For hardware version 2.3 *************************/
    206. 

  206. void Set_System(void);
    207. 

  207. void NVIC_Config(void);
    208. 

  208. void GPIO_Config(void);
    209. 

  209. void GPIO_Config2(void);
    210. 

  210. void FSMC_Config(void);
    211. 

  211. void DMA_Config(void);
    212. 

  212. void SPI_Config(void);
    213. 

  213. void DAC_Config(void);
    214. 

  214. void ADC_Config(void);
    215. 

  215. void Timer_Config(void);
    216. 

  216. void Get_SerialNum(void);
    217. 

  217. 

  218. #endif  
    219. 

  219. 

  220. /*******************************  END OF FILE  ********************************/
    221. 

  221.