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/drivers/gpu/drm/radeon/r100_track.h

https://github.com/mstsirkin/linux
C Header | 197 lines | 174 code | 20 blank | 3 comment | 11 complexity | ee296d1d8b664b073f37da10ce85deea MD5 | raw file
  1. #define R100_TRACK_MAX_TEXTURE 3
  2. #define R200_TRACK_MAX_TEXTURE 6
  3. #define R300_TRACK_MAX_TEXTURE 16
  4. #define R100_MAX_CB 1
  5. #define R300_MAX_CB 4
  6. /*
  7. * CS functions
  8. */
  9. struct r100_cs_track_cb {
  10. struct radeon_bo *robj;
  11. unsigned pitch;
  12. unsigned cpp;
  13. unsigned offset;
  14. };
  15. struct r100_cs_track_array {
  16. struct radeon_bo *robj;
  17. unsigned esize;
  18. };
  19. struct r100_cs_cube_info {
  20. struct radeon_bo *robj;
  21. unsigned offset;
  22. unsigned width;
  23. unsigned height;
  24. };
  25. #define R100_TRACK_COMP_NONE 0
  26. #define R100_TRACK_COMP_DXT1 1
  27. #define R100_TRACK_COMP_DXT35 2
  28. struct r100_cs_track_texture {
  29. struct radeon_bo *robj;
  30. struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
  31. unsigned pitch;
  32. unsigned width;
  33. unsigned height;
  34. unsigned num_levels;
  35. unsigned cpp;
  36. unsigned tex_coord_type;
  37. unsigned txdepth;
  38. unsigned width_11;
  39. unsigned height_11;
  40. bool use_pitch;
  41. bool enabled;
  42. bool lookup_disable;
  43. bool roundup_w;
  44. bool roundup_h;
  45. unsigned compress_format;
  46. };
  47. struct r100_cs_track {
  48. unsigned num_cb;
  49. unsigned num_texture;
  50. unsigned maxy;
  51. unsigned vtx_size;
  52. unsigned vap_vf_cntl;
  53. unsigned vap_alt_nverts;
  54. unsigned immd_dwords;
  55. unsigned num_arrays;
  56. unsigned max_indx;
  57. unsigned color_channel_mask;
  58. struct r100_cs_track_array arrays[16];
  59. struct r100_cs_track_cb cb[R300_MAX_CB];
  60. struct r100_cs_track_cb zb;
  61. struct r100_cs_track_cb aa;
  62. struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
  63. bool z_enabled;
  64. bool separate_cube;
  65. bool zb_cb_clear;
  66. bool blend_read_enable;
  67. bool cb_dirty;
  68. bool zb_dirty;
  69. bool tex_dirty;
  70. bool aa_dirty;
  71. bool aaresolve;
  72. };
  73. int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
  74. void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
  75. int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
  76. struct radeon_cs_reloc **cs_reloc);
  77. void r100_cs_dump_packet(struct radeon_cs_parser *p,
  78. struct radeon_cs_packet *pkt);
  79. int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
  80. int r200_packet0_check(struct radeon_cs_parser *p,
  81. struct radeon_cs_packet *pkt,
  82. unsigned idx, unsigned reg);
  83. static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
  84. struct radeon_cs_packet *pkt,
  85. unsigned idx,
  86. unsigned reg)
  87. {
  88. int r;
  89. u32 tile_flags = 0;
  90. u32 tmp;
  91. struct radeon_cs_reloc *reloc;
  92. u32 value;
  93. r = r100_cs_packet_next_reloc(p, &reloc);
  94. if (r) {
  95. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  96. idx, reg);
  97. r100_cs_dump_packet(p, pkt);
  98. return r;
  99. }
  100. value = radeon_get_ib_value(p, idx);
  101. tmp = value & 0x003fffff;
  102. tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
  103. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
  104. tile_flags |= RADEON_DST_TILE_MACRO;
  105. if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
  106. if (reg == RADEON_SRC_PITCH_OFFSET) {
  107. DRM_ERROR("Cannot src blit from microtiled surface\n");
  108. r100_cs_dump_packet(p, pkt);
  109. return -EINVAL;
  110. }
  111. tile_flags |= RADEON_DST_TILE_MICRO;
  112. }
  113. tmp |= tile_flags;
  114. p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
  115. return 0;
  116. }
  117. static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
  118. struct radeon_cs_packet *pkt,
  119. int idx)
  120. {
  121. unsigned c, i;
  122. struct radeon_cs_reloc *reloc;
  123. struct r100_cs_track *track;
  124. int r = 0;
  125. volatile uint32_t *ib;
  126. u32 idx_value;
  127. ib = p->ib->ptr;
  128. track = (struct r100_cs_track *)p->track;
  129. c = radeon_get_ib_value(p, idx++) & 0x1F;
  130. if (c > 16) {
  131. DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
  132. pkt->opcode);
  133. r100_cs_dump_packet(p, pkt);
  134. return -EINVAL;
  135. }
  136. track->num_arrays = c;
  137. for (i = 0; i < (c - 1); i+=2, idx+=3) {
  138. r = r100_cs_packet_next_reloc(p, &reloc);
  139. if (r) {
  140. DRM_ERROR("No reloc for packet3 %d\n",
  141. pkt->opcode);
  142. r100_cs_dump_packet(p, pkt);
  143. return r;
  144. }
  145. idx_value = radeon_get_ib_value(p, idx);
  146. ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
  147. track->arrays[i + 0].esize = idx_value >> 8;
  148. track->arrays[i + 0].robj = reloc->robj;
  149. track->arrays[i + 0].esize &= 0x7F;
  150. r = r100_cs_packet_next_reloc(p, &reloc);
  151. if (r) {
  152. DRM_ERROR("No reloc for packet3 %d\n",
  153. pkt->opcode);
  154. r100_cs_dump_packet(p, pkt);
  155. return r;
  156. }
  157. ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
  158. track->arrays[i + 1].robj = reloc->robj;
  159. track->arrays[i + 1].esize = idx_value >> 24;
  160. track->arrays[i + 1].esize &= 0x7F;
  161. }
  162. if (c & 1) {
  163. r = r100_cs_packet_next_reloc(p, &reloc);
  164. if (r) {
  165. DRM_ERROR("No reloc for packet3 %d\n",
  166. pkt->opcode);
  167. r100_cs_dump_packet(p, pkt);
  168. return r;
  169. }
  170. idx_value = radeon_get_ib_value(p, idx);
  171. ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
  172. track->arrays[i + 0].robj = reloc->robj;
  173. track->arrays[i + 0].esize = idx_value >> 8;
  174. track->arrays[i + 0].esize &= 0x7F;
  175. }
  176. return r;
  177. }