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/drivers/video/aty/atyfb_base.c

https://github.com/mstsirkin/linux
C | 1631 lines | 1255 code | 199 blank | 177 comment | 169 complexity | def674e294f81689722f612f46ca2ea4 MD5 | raw file
    

  1. /*
    2. 

  2.  *  ATI Frame Buffer Device Driver Core
    3. 

  3.  *
    4. 

  4.  *	Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
    5. 

  5.  *	Copyright (C) 1997-2001  Geert Uytterhoeven
    6. 

  6.  *	Copyright (C) 1998  Bernd Harries
    7. 

  7.  *	Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
    8. 

  8.  *
    9. 

  9.  *  This driver supports the following ATI graphics chips:
    10. 

  10.  *    - ATI Mach64
    11. 

  11.  *
    12. 

  12.  *  To do: add support for
    13. 

  13.  *    - ATI Rage128 (from aty128fb.c)
    14. 

  14.  *    - ATI Radeon (from radeonfb.c)
    15. 

  15.  *
    16. 

  16.  *  This driver is partly based on the PowerMac console driver:
    17. 

  17.  *
    18. 

  18.  *	Copyright (C) 1996 Paul Mackerras
    19. 

  19.  *
    20. 

  20.  *  and on the PowerMac ATI/mach64 display driver:
    21. 

  21.  *
    22. 

  22.  *	Copyright (C) 1997 Michael AK Tesch
    23. 

  23.  *
    24. 

  24.  *	      with work by Jon Howell
    25. 

  25.  *			   Harry AC Eaton
    26. 

  26.  *			   Anthony Tong <atong@uiuc.edu>
    27. 

  27.  *
    28. 

  28.  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
    29. 

  29.  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
    30. 

  30.  *
    31. 

  31.  *  This file is subject to the terms and conditions of the GNU General Public
    32. 

  32.  *  License. See the file COPYING in the main directory of this archive for
    33. 

  33.  *  more details.
    34. 

  34.  *
    35. 

  35.  *  Many thanks to Nitya from ATI devrel for support and patience !
    36. 

  36.  */
    37. 

  37. 

  38. /******************************************************************************
    39. 

    40. 

  40.   TODO:
    41. 

    42. 

  42.     - cursor support on all cards and all ramdacs.
    43. 

  43.     - cursor parameters controlable via ioctl()s.
    44. 

  44.     - guess PLL and MCLK based on the original PLL register values initialized
    45. 

  45.       by Open Firmware (if they are initialized). BIOS is done
    46. 

    47. 

  47.     (Anyone with Mac to help with this?)
    48. 

    49. 

  49. ******************************************************************************/
    50. 

  50. 

  51. 

  52. #include <linux/module.h>
    53. 

  53. #include <linux/moduleparam.h>
    54. 

  54. #include <linux/kernel.h>
    55. 

  55. #include <linux/errno.h>
    56. 

  56. #include <linux/string.h>
    57. 

  57. #include <linux/mm.h>
    58. 

  58. #include <linux/slab.h>
    59. 

  59. #include <linux/vmalloc.h>
    60. 

  60. #include <linux/delay.h>
    61. 

  61. #include <linux/console.h>
    62. 

  62. #include <linux/fb.h>
    63. 

  63. #include <linux/init.h>
    64. 

  64. #include <linux/pci.h>
    65. 

  65. #include <linux/interrupt.h>
    66. 

  66. #include <linux/spinlock.h>
    67. 

  67. #include <linux/wait.h>
    68. 

  68. #include <linux/backlight.h>
    69. 

  69. #include <linux/reboot.h>
    70. 

  70. #include <linux/dmi.h>
    71. 

  71. 

  72. #include <asm/io.h>
    73. 

  73. #include <linux/uaccess.h>
    74. 

  74. 

  75. #include <video/mach64.h>
    76. 

  76. #include "atyfb.h"
    77. 

  77. #include "ati_ids.h"
    78. 

  78. 

  79. #ifdef __powerpc__
    80. 

  80. #include <asm/machdep.h>
    81. 

  81. #include <asm/prom.h>
    82. 

  82. #include "../macmodes.h"
    83. 

  83. #endif
    84. 

  84. #ifdef __sparc__
    85. 

  85. #include <asm/fbio.h>
    86. 

  86. #include <asm/oplib.h>
    87. 

  87. #include <asm/prom.h>
    88. 

  88. #endif
    89. 

  89. 

  90. #ifdef CONFIG_ADB_PMU
    91. 

  91. #include <linux/adb.h>
    92. 

  92. #include <linux/pmu.h>
    93. 

  93. #endif
    94. 

  94. #ifdef CONFIG_BOOTX_TEXT
    95. 

  95. #include <asm/btext.h>
    96. 

  96. #endif
    97. 

  97. #ifdef CONFIG_PMAC_BACKLIGHT
    98. 

  98. #include <asm/backlight.h>
    99. 

  99. #endif
    100. 

  100. #ifdef CONFIG_MTRR
    101. 

  101. #include <asm/mtrr.h>
    102. 

  102. #endif
    103. 

  103. 

  104. /*
    105. 

  105.  * Debug flags.
    106. 

  106.  */
    107. 

  107. #undef DEBUG
    108. 

  108. /*#define DEBUG*/
    109. 

  109. 

  110. /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
    111. 

  111. /*  - must be large enough to catch all GUI-Regs   */
    112. 

  112. /*  - must be aligned to a PAGE boundary           */
    113. 

  113. #define GUI_RESERVE	(1 * PAGE_SIZE)
    114. 

  114. 

  115. /* FIXME: remove the FAIL definition */
    116. 

  116. #define FAIL(msg) do { \
    117. 

  117. 	if (!(var->activate & FB_ACTIVATE_TEST)) \
    118. 

  118. 		printk(KERN_CRIT "atyfb: " msg "\n"); \
    119. 

  119. 	return -EINVAL; \
    120. 

  120. } while (0)
    121. 

  121. #define FAIL_MAX(msg, x, _max_) do { \
    122. 

  122. 	if (x > _max_) { \
    123. 

  123. 		if (!(var->activate & FB_ACTIVATE_TEST)) \
    124. 

  124. 			printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
    125. 

  125. 		return -EINVAL; \
    126. 

  126. 	} \
    127. 

  127. } while (0)
    128. 

  128. #ifdef DEBUG
    129. 

  129. #define DPRINTK(fmt, args...)	printk(KERN_DEBUG "atyfb: " fmt, ## args)
    130. 

  130. #else
    131. 

  131. #define DPRINTK(fmt, args...)
    132. 

  132. #endif
    133. 

  133. 

  134. #define PRINTKI(fmt, args...)	printk(KERN_INFO "atyfb: " fmt, ## args)
    135. 

  135. #define PRINTKE(fmt, args...)	printk(KERN_ERR "atyfb: " fmt, ## args)
    136. 

  136. 

  137. #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
    138. 

  138. defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
    139. 

  139. static const u32 lt_lcd_regs[] = {
    140. 

  140. 	CNFG_PANEL_LG,
    141. 

  141. 	LCD_GEN_CNTL_LG,
    142. 

  142. 	DSTN_CONTROL_LG,
    143. 

  143. 	HFB_PITCH_ADDR_LG,
    144. 

  144. 	HORZ_STRETCHING_LG,
    145. 

  145. 	VERT_STRETCHING_LG,
    146. 

  146. 	0, /* EXT_VERT_STRETCH */
    147. 

  147. 	LT_GIO_LG,
    148. 

  148. 	POWER_MANAGEMENT_LG
    149. 

  149. };
    150. 

  150. 

  151. void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
    152. 

  152. {
    153. 

  153. 	if (M64_HAS(LT_LCD_REGS)) {
    154. 

  154. 		aty_st_le32(lt_lcd_regs[index], val, par);
    155. 

  155. 	} else {
    156. 

  156. 		unsigned long temp;
    157. 

  157. 

  158. 		/* write addr byte */
    159. 

  159. 		temp = aty_ld_le32(LCD_INDEX, par);
    160. 

  160. 		aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
    161. 

  161. 		/* write the register value */
    162. 

  162. 		aty_st_le32(LCD_DATA, val, par);
    163. 

  163. 	}
    164. 

  164. }
    165. 

  165. 

  166. u32 aty_ld_lcd(int index, const struct atyfb_par *par)
    167. 

  167. {
    168. 

  168. 	if (M64_HAS(LT_LCD_REGS)) {
    169. 

  169. 		return aty_ld_le32(lt_lcd_regs[index], par);
    170. 

  170. 	} else {
    171. 

  171. 		unsigned long temp;
    172. 

  172. 

  173. 		/* write addr byte */
    174. 

  174. 		temp = aty_ld_le32(LCD_INDEX, par);
    175. 

  175. 		aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
    176. 

  176. 		/* read the register value */
    177. 

  177. 		return aty_ld_le32(LCD_DATA, par);
    178. 

  178. 	}
    179. 

  179. }
    180. 

  180. #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
    181. 

  181. 

  182. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    183. 

  183. /*
    184. 

  184.  * ATIReduceRatio --
    185. 

  185.  *
    186. 

  186.  * Reduce a fraction by factoring out the largest common divider of the
    187. 

  187.  * fraction's numerator and denominator.
    188. 

  188.  */
    189. 

  189. static void ATIReduceRatio(int *Numerator, int *Denominator)
    190. 

  190. {
    191. 

  191. 	int Multiplier, Divider, Remainder;
    192. 

  192. 

  193. 	Multiplier = *Numerator;
    194. 

  194. 	Divider = *Denominator;
    195. 

  195. 

  196. 	while ((Remainder = Multiplier % Divider)) {
    197. 

  197. 		Multiplier = Divider;
    198. 

  198. 		Divider = Remainder;
    199. 

  199. 	}
    200. 

  200. 

  201. 	*Numerator /= Divider;
    202. 

  202. 	*Denominator /= Divider;
    203. 

  203. }
    204. 

  204. #endif
    205. 

  205. /*
    206. 

  206.  * The Hardware parameters for each card
    207. 

  207.  */
    208. 

  208. 

  209. struct pci_mmap_map {
    210. 

  210. 	unsigned long voff;
    211. 

  211. 	unsigned long poff;
    212. 

  212. 	unsigned long size;
    213. 

  213. 	unsigned long prot_flag;
    214. 

  214. 	unsigned long prot_mask;
    215. 

  215. };
    216. 

  216. 

  217. static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
    218. 

  218. 	.id		= "ATY Mach64",
    219. 

  219. 	.type		= FB_TYPE_PACKED_PIXELS,
    220. 

  220. 	.visual		= FB_VISUAL_PSEUDOCOLOR,
    221. 

  221. 	.xpanstep	= 8,
    222. 

  222. 	.ypanstep	= 1,
    223. 

  223. };
    224. 

  224. 

  225. /*
    226. 

  226.  * Frame buffer device API
    227. 

  227.  */
    228. 

  228. 

  229. static int atyfb_open(struct fb_info *info, int user);
    230. 

  230. static int atyfb_release(struct fb_info *info, int user);
    231. 

  231. static int atyfb_check_var(struct fb_var_screeninfo *var,
    232. 

  232. 			   struct fb_info *info);
    233. 

  233. static int atyfb_set_par(struct fb_info *info);
    234. 

  234. static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
    235. 

  235. 			   u_int transp, struct fb_info *info);
    236. 

  236. static int atyfb_pan_display(struct fb_var_screeninfo *var,
    237. 

  237. 			     struct fb_info *info);
    238. 

  238. static int atyfb_blank(int blank, struct fb_info *info);
    239. 

  239. static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
    240. 

  240. #ifdef __sparc__
    241. 

  241. static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
    242. 

  242. #endif
    243. 

  243. static int atyfb_sync(struct fb_info *info);
    244. 

  244. 

  245. /*
    246. 

  246.  * Internal routines
    247. 

  247.  */
    248. 

  248. 

  249. static int aty_init(struct fb_info *info);
    250. 

  250. 

  251. static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
    252. 

  252. 

  253. static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
    254. 

  254. static int aty_var_to_crtc(const struct fb_info *info,
    255. 

  255. 			   const struct fb_var_screeninfo *var,
    256. 

  256. 			   struct crtc *crtc);
    257. 

  257. static int aty_crtc_to_var(const struct crtc *crtc,
    258. 

  258. 			   struct fb_var_screeninfo *var);
    259. 

  259. static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
    260. 

  260. #ifdef CONFIG_PPC
    261. 

  261. static int read_aty_sense(const struct atyfb_par *par);
    262. 

  262. #endif
    263. 

  263. 

  264. static DEFINE_MUTEX(reboot_lock);
    265. 

  265. static struct fb_info *reboot_info;
    266. 

  266. 

  267. /*
    268. 

  268.  * Interface used by the world
    269. 

  269.  */
    270. 

  270. 

  271. static struct fb_var_screeninfo default_var = {
    272. 

  272. 	/* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
    273. 

  273. 	640, 480, 640, 480, 0, 0, 8, 0,
    274. 

  274. 	{0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
    275. 

  275. 	0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
    276. 

  276. 	0, FB_VMODE_NONINTERLACED
    277. 

  277. };
    278. 

  278. 

  279. static struct fb_videomode defmode = {
    280. 

  280. 	/* 640x480 @ 60 Hz, 31.5 kHz hsync */
    281. 

  281. 	NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
    282. 

  282. 	0, FB_VMODE_NONINTERLACED
    283. 

  283. };
    284. 

  284. 

  285. static struct fb_ops atyfb_ops = {
    286. 

  286. 	.owner		= THIS_MODULE,
    287. 

  287. 	.fb_open	= atyfb_open,
    288. 

  288. 	.fb_release	= atyfb_release,
    289. 

  289. 	.fb_check_var	= atyfb_check_var,
    290. 

  290. 	.fb_set_par	= atyfb_set_par,
    291. 

  291. 	.fb_setcolreg	= atyfb_setcolreg,
    292. 

  292. 	.fb_pan_display	= atyfb_pan_display,
    293. 

  293. 	.fb_blank	= atyfb_blank,
    294. 

  294. 	.fb_ioctl	= atyfb_ioctl,
    295. 

  295. 	.fb_fillrect	= atyfb_fillrect,
    296. 

  296. 	.fb_copyarea	= atyfb_copyarea,
    297. 

  297. 	.fb_imageblit	= atyfb_imageblit,
    298. 

  298. #ifdef __sparc__
    299. 

  299. 	.fb_mmap	= atyfb_mmap,
    300. 

  300. #endif
    301. 

  301. 	.fb_sync	= atyfb_sync,
    302. 

  302. };
    303. 

  303. 

  304. static int noaccel;
    305. 

  305. #ifdef CONFIG_MTRR
    306. 

  306. static int nomtrr;
    307. 

  307. #endif
    308. 

  308. static int vram;
    309. 

  309. static int pll;
    310. 

  310. static int mclk;
    311. 

  311. static int xclk;
    312. 

  312. static int comp_sync __devinitdata = -1;
    313. 

  313. static char *mode;
    314. 

  314. 

  315. #ifdef CONFIG_PMAC_BACKLIGHT
    316. 

  316. static int backlight __devinitdata = 1;
    317. 

  317. #else
    318. 

  318. static int backlight __devinitdata = 0;
    319. 

  319. #endif
    320. 

  320. 

  321. #ifdef CONFIG_PPC
    322. 

  322. static int default_vmode __devinitdata = VMODE_CHOOSE;
    323. 

  323. static int default_cmode __devinitdata = CMODE_CHOOSE;
    324. 

  324. 

  325. module_param_named(vmode, default_vmode, int, 0);
    326. 

  326. MODULE_PARM_DESC(vmode, "int: video mode for mac");
    327. 

  327. module_param_named(cmode, default_cmode, int, 0);
    328. 

  328. MODULE_PARM_DESC(cmode, "int: color mode for mac");
    329. 

  329. #endif
    330. 

  330. 

  331. #ifdef CONFIG_ATARI
    332. 

  332. static unsigned int mach64_count __devinitdata = 0;
    333. 

  333. static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
    334. 

  334. static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
    335. 

  335. static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
    336. 

  336. #endif
    337. 

  337. 

  338. /* top -> down is an evolution of mach64 chipset, any corrections? */
    339. 

  339. #define ATI_CHIP_88800GX   (M64F_GX)
    340. 

  340. #define ATI_CHIP_88800CX   (M64F_GX)
    341. 

  341. 

  342. #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
    343. 

  343. #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
    344. 

  344. 

  345. #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
    346. 

  346. #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
    347. 

  347. 

  348. #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
    349. 

  349. #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
    350. 

  350. #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
    351. 

  351. 

  352. /* FIXME what is this chip? */
    353. 

  353. #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
    354. 

  354. 

  355. /* make sets shorter */
    356. 

  356. #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
    357. 

  357. 

  358. #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
    359. 

  359. /*#define ATI_CHIP_264GTDVD  ?*/
    360. 

  360. #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
    361. 

  361. 

  362. #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
    363. 

  363. #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
    364. 

  364. #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
    365. 

  365. 

  366. #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM)
    367. 

  367. #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM | M64F_MOBIL_BUS)
    368. 

  368. 

  369. static struct {
    370. 

  370. 	u16 pci_id;
    371. 

  371. 	const char *name;
    372. 

  372. 	int pll, mclk, xclk, ecp_max;
    373. 

  373. 	u32 features;
    374. 

  374. } aty_chips[] __devinitdata = {
    375. 

  375. #ifdef CONFIG_FB_ATY_GX
    376. 

  376. 	/* Mach64 GX */
    377. 

  377. 	{ PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
    378. 

  378. 	{ PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
    379. 

  379. #endif /* CONFIG_FB_ATY_GX */
    380. 

  380. 

  381. #ifdef CONFIG_FB_ATY_CT
    382. 

  382. 	{ PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
    383. 

  383. 	{ PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
    384. 

  384. 

  385. 	/* FIXME what is this chip? */
    386. 

  386. 	{ PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
    387. 

  387. 

  388. 	{ PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
    389. 

  389. 	{ PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
    390. 

  390. 

  391. 	{ PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
    392. 

  392. 	{ PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
    393. 

  393. 

  394. 	{ PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
    395. 

  395. 

  396. 	{ PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
    397. 

  397. 

  398. 	{ PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
    399. 

  399. 	{ PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
    400. 

  400. 	{ PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
    401. 

  401. 	{ PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
    402. 

  402. 

  403. 	{ PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
    404. 

  404. 	{ PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
    405. 

  405. 	{ PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
    406. 

  406. 	{ PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
    407. 

  407. 	{ PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
    408. 

  408. 

  409. 	{ PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
    410. 

  410. 	{ PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
    411. 

  411. 	{ PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
    412. 

  412. 	{ PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
    413. 

  413. 	{ PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
    414. 

  414. 

  415. 	{ PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
    416. 

  416. 	{ PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
    417. 

  417. 	{ PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
    418. 

  418. 	{ PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
    419. 

  419. 	{ PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
    420. 

  420. 	{ PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
    421. 

  421. 

  422. 	{ PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
    423. 

  423. 	{ PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
    424. 

  424. 	{ PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
    425. 

  425. 	{ PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
    426. 

  426. #endif /* CONFIG_FB_ATY_CT */
    427. 

  427. };
    428. 

  428. 

  429. static int __devinit correct_chipset(struct atyfb_par *par)
    430. 

  430. {
    431. 

  431. 	u8 rev;
    432. 

  432. 	u16 type;
    433. 

  433. 	u32 chip_id;
    434. 

  434. 	const char *name;
    435. 

  435. 	int i;
    436. 

  436. 

  437. 	for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
    438. 

  438. 		if (par->pci_id == aty_chips[i].pci_id)
    439. 

  439. 			break;
    440. 

  440. 

  441. 	if (i < 0)
    442. 

  442. 		return -ENODEV;
    443. 

  443. 

  444. 	name = aty_chips[i].name;
    445. 

  445. 	par->pll_limits.pll_max = aty_chips[i].pll;
    446. 

  446. 	par->pll_limits.mclk = aty_chips[i].mclk;
    447. 

  447. 	par->pll_limits.xclk = aty_chips[i].xclk;
    448. 

  448. 	par->pll_limits.ecp_max = aty_chips[i].ecp_max;
    449. 

  449. 	par->features = aty_chips[i].features;
    450. 

  450. 

  451. 	chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
    452. 

  452. 	type = chip_id & CFG_CHIP_TYPE;
    453. 

  453. 	rev = (chip_id & CFG_CHIP_REV) >> 24;
    454. 

  454. 

  455. 	switch (par->pci_id) {
    456. 

  456. #ifdef CONFIG_FB_ATY_GX
    457. 

  457. 	case PCI_CHIP_MACH64GX:
    458. 

  458. 		if (type != 0x00d7)
    459. 

  459. 			return -ENODEV;
    460. 

  460. 		break;
    461. 

  461. 	case PCI_CHIP_MACH64CX:
    462. 

  462. 		if (type != 0x0057)
    463. 

  463. 			return -ENODEV;
    464. 

  464. 		break;
    465. 

  465. #endif
    466. 

  466. #ifdef CONFIG_FB_ATY_CT
    467. 

  467. 	case PCI_CHIP_MACH64VT:
    468. 

  468. 		switch (rev & 0x07) {
    469. 

  469. 		case 0x00:
    470. 

  470. 			switch (rev & 0xc0) {
    471. 

  471. 			case 0x00:
    472. 

  472. 				name = "ATI264VT (A3) (Mach64 VT)";
    473. 

  473. 				par->pll_limits.pll_max = 170;
    474. 

  474. 				par->pll_limits.mclk = 67;
    475. 

  475. 				par->pll_limits.xclk = 67;
    476. 

  476. 				par->pll_limits.ecp_max = 80;
    477. 

  477. 				par->features = ATI_CHIP_264VT;
    478. 

  478. 				break;
    479. 

  479. 			case 0x40:
    480. 

  480. 				name = "ATI264VT2 (A4) (Mach64 VT)";
    481. 

  481. 				par->pll_limits.pll_max = 200;
    482. 

  482. 				par->pll_limits.mclk = 67;
    483. 

  483. 				par->pll_limits.xclk = 67;
    484. 

  484. 				par->pll_limits.ecp_max = 80;
    485. 

  485. 				par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
    486. 

  486. 				break;
    487. 

  487. 			}
    488. 

  488. 			break;
    489. 

  489. 		case 0x01:
    490. 

  490. 			name = "ATI264VT3 (B1) (Mach64 VT)";
    491. 

  491. 			par->pll_limits.pll_max = 200;
    492. 

  492. 			par->pll_limits.mclk = 67;
    493. 

  493. 			par->pll_limits.xclk = 67;
    494. 

  494. 			par->pll_limits.ecp_max = 80;
    495. 

  495. 			par->features = ATI_CHIP_264VTB;
    496. 

  496. 			break;
    497. 

  497. 		case 0x02:
    498. 

  498. 			name = "ATI264VT3 (B2) (Mach64 VT)";
    499. 

  499. 			par->pll_limits.pll_max = 200;
    500. 

  500. 			par->pll_limits.mclk = 67;
    501. 

  501. 			par->pll_limits.xclk = 67;
    502. 

  502. 			par->pll_limits.ecp_max = 80;
    503. 

  503. 			par->features = ATI_CHIP_264VT3;
    504. 

  504. 			break;
    505. 

  505. 		}
    506. 

  506. 		break;
    507. 

  507. 	case PCI_CHIP_MACH64GT:
    508. 

  508. 		switch (rev & 0x07) {
    509. 

  509. 		case 0x01:
    510. 

  510. 			name = "3D RAGE II (Mach64 GT)";
    511. 

  511. 			par->pll_limits.pll_max = 170;
    512. 

  512. 			par->pll_limits.mclk = 67;
    513. 

  513. 			par->pll_limits.xclk = 67;
    514. 

  514. 			par->pll_limits.ecp_max = 80;
    515. 

  515. 			par->features = ATI_CHIP_264GTB;
    516. 

  516. 			break;
    517. 

  517. 		case 0x02:
    518. 

  518. 			name = "3D RAGE II+ (Mach64 GT)";
    519. 

  519. 			par->pll_limits.pll_max = 200;
    520. 

  520. 			par->pll_limits.mclk = 67;
    521. 

  521. 			par->pll_limits.xclk = 67;
    522. 

  522. 			par->pll_limits.ecp_max = 100;
    523. 

  523. 			par->features = ATI_CHIP_264GTB;
    524. 

  524. 			break;
    525. 

  525. 		}
    526. 

  526. 		break;
    527. 

  527. #endif
    528. 

  528. 	}
    529. 

  529. 

  530. 	PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
    531. 

  531. 	return 0;
    532. 

  532. }
    533. 

  533. 

  534. static char ram_dram[] __devinitdata = "DRAM";
    535. 

  535. static char ram_resv[] __devinitdata = "RESV";
    536. 

  536. #ifdef CONFIG_FB_ATY_GX
    537. 

  537. static char ram_vram[] __devinitdata = "VRAM";
    538. 

  538. #endif /* CONFIG_FB_ATY_GX */
    539. 

  539. #ifdef CONFIG_FB_ATY_CT
    540. 

  540. static char ram_edo[] __devinitdata = "EDO";
    541. 

  541. static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
    542. 

  542. static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
    543. 

  543. static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
    544. 

  544. static char ram_wram[] __devinitdata = "WRAM";
    545. 

  545. static char ram_off[] __devinitdata = "OFF";
    546. 

  546. #endif /* CONFIG_FB_ATY_CT */
    547. 

  547. 

  548. 

  549. #ifdef CONFIG_FB_ATY_GX
    550. 

  550. static char *aty_gx_ram[8] __devinitdata = {
    551. 

  551. 	ram_dram, ram_vram, ram_vram, ram_dram,
    552. 

  552. 	ram_dram, ram_vram, ram_vram, ram_resv
    553. 

  553. };
    554. 

  554. #endif /* CONFIG_FB_ATY_GX */
    555. 

  555. 

  556. #ifdef CONFIG_FB_ATY_CT
    557. 

  557. static char *aty_ct_ram[8] __devinitdata = {
    558. 

  558. 	ram_off, ram_dram, ram_edo, ram_edo,
    559. 

  559. 	ram_sdram, ram_sgram, ram_wram, ram_resv
    560. 

  560. };
    561. 

  561. static char *aty_xl_ram[8] __devinitdata = {
    562. 

  562. 	ram_off, ram_dram, ram_edo, ram_edo,
    563. 

  563. 	ram_sdram, ram_sgram, ram_sdram32, ram_resv
    564. 

  564. };
    565. 

  565. #endif /* CONFIG_FB_ATY_CT */
    566. 

  566. 

  567. static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var,
    568. 

  568. 			      struct atyfb_par *par)
    569. 

  569. {
    570. 

  570. 	u32 pixclock = var->pixclock;
    571. 

  571. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    572. 

  572. 	u32 lcd_on_off;
    573. 

  573. 	par->pll.ct.xres = 0;
    574. 

  574. 	if (par->lcd_table != 0) {
    575. 

  575. 		lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
    576. 

  576. 		if (lcd_on_off & LCD_ON) {
    577. 

  577. 			par->pll.ct.xres = var->xres;
    578. 

  578. 			pixclock = par->lcd_pixclock;
    579. 

  579. 		}
    580. 

  580. 	}
    581. 

  581. #endif
    582. 

  582. 	return pixclock;
    583. 

  583. }
    584. 

  584. 

  585. #if defined(CONFIG_PPC)
    586. 

  586. 

  587. /*
    588. 

  588.  * Apple monitor sense
    589. 

  589.  */
    590. 

  590. 

  591. static int __devinit read_aty_sense(const struct atyfb_par *par)
    592. 

  592. {
    593. 

  593. 	int sense, i;
    594. 

  594. 

  595. 	aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
    596. 

  596. 	__delay(200);
    597. 

  597. 	aty_st_le32(GP_IO, 0, par); /* turn off outputs */
    598. 

  598. 	__delay(2000);
    599. 

  599. 	i = aty_ld_le32(GP_IO, par); /* get primary sense value */
    600. 

  600. 	sense = ((i & 0x3000) >> 3) | (i & 0x100);
    601. 

  601. 

  602. 	/* drive each sense line low in turn and collect the other 2 */
    603. 

  603. 	aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
    604. 

  604. 	__delay(2000);
    605. 

  605. 	i = aty_ld_le32(GP_IO, par);
    606. 

  606. 	sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
    607. 

  607. 	aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
    608. 

  608. 	__delay(200);
    609. 

  609. 

  610. 	aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
    611. 

  611. 	__delay(2000);
    612. 

  612. 	i = aty_ld_le32(GP_IO, par);
    613. 

  613. 	sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
    614. 

  614. 	aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
    615. 

  615. 	__delay(200);
    616. 

  616. 

  617. 	aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
    618. 

  618. 	__delay(2000);
    619. 

  619. 	sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
    620. 

  620. 	aty_st_le32(GP_IO, 0, par); /* turn off outputs */
    621. 

  621. 	return sense;
    622. 

  622. }
    623. 

  623. 

  624. #endif /* defined(CONFIG_PPC) */
    625. 

  625. 

  626. /* ------------------------------------------------------------------------- */
    627. 

  627. 

  628. /*
    629. 

  629.  * CRTC programming
    630. 

  630.  */
    631. 

  631. 

  632. static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
    633. 

  633. {
    634. 

  634. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    635. 

  635. 	if (par->lcd_table != 0) {
    636. 

  636. 		if (!M64_HAS(LT_LCD_REGS)) {
    637. 

  637. 			crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
    638. 

  638. 			aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
    639. 

  639. 		}
    640. 

  640. 		crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
    641. 

  641. 		crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
    642. 

  642. 

  643. 

  644. 		/* switch to non shadow registers */
    645. 

  645. 		aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
    646. 

  646. 			   ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
    647. 

  647. 

  648. 		/* save stretching */
    649. 

  649. 		crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
    650. 

  650. 		crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
    651. 

  651. 		if (!M64_HAS(LT_LCD_REGS))
    652. 

  652. 			crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
    653. 

  653. 	}
    654. 

  654. #endif
    655. 

  655. 	crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
    656. 

  656. 	crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
    657. 

  657. 	crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
    658. 

  658. 	crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
    659. 

  659. 	crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
    660. 

  660. 	crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
    661. 

  661. 	crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
    662. 

  662. 

  663. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    664. 

  664. 	if (par->lcd_table != 0) {
    665. 

  665. 		/* switch to shadow registers */
    666. 

  666. 		aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
    667. 

  667. 			   SHADOW_EN | SHADOW_RW_EN, par);
    668. 

  668. 

  669. 		crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
    670. 

  670. 		crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
    671. 

  671. 		crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
    672. 

  672. 		crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
    673. 

  673. 

  674. 		aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
    675. 

  675. 	}
    676. 

  676. #endif /* CONFIG_FB_ATY_GENERIC_LCD */
    677. 

  677. }
    678. 

  678. 

  679. static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
    680. 

  680. {
    681. 

  681. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    682. 

  682. 	if (par->lcd_table != 0) {
    683. 

  683. 		/* stop CRTC */
    684. 

  684. 		aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl &
    685. 

  685. 			    ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
    686. 

  686. 

  687. 		/* update non-shadow registers first */
    688. 

  688. 		aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
    689. 

  689. 		aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
    690. 

  690. 			   ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
    691. 

  691. 

  692. 		/* temporarily disable stretching */
    693. 

  693. 		aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching &
    694. 

  694. 			   ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
    695. 

  695. 		aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching &
    696. 

  696. 			   ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
    697. 

  697. 			     VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
    698. 

  698. 	}
    699. 

  699. #endif
    700. 

  700. 	/* turn off CRT */
    701. 

  701. 	aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
    702. 

  702. 

  703. 	DPRINTK("setting up CRTC\n");
    704. 

  704. 	DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
    705. 

  705. 		((((crtc->h_tot_disp >> 16) & 0xff) + 1) << 3),
    706. 

  706. 		(((crtc->v_tot_disp >> 16) & 0x7ff) + 1),
    707. 

  707. 		(crtc->h_sync_strt_wid & 0x200000) ? 'N' : 'P',
    708. 

  708. 		(crtc->v_sync_strt_wid & 0x200000) ? 'N' : 'P',
    709. 

  709. 		(crtc->gen_cntl & CRTC_CSYNC_EN) ? 'P' : 'N');
    710. 

  710. 

  711. 	DPRINTK("CRTC_H_TOTAL_DISP: %x\n", crtc->h_tot_disp);
    712. 

  712. 	DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n", crtc->h_sync_strt_wid);
    713. 

  713. 	DPRINTK("CRTC_V_TOTAL_DISP: %x\n", crtc->v_tot_disp);
    714. 

  714. 	DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n", crtc->v_sync_strt_wid);
    715. 

  715. 	DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
    716. 

  716. 	DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
    717. 

  717. 	DPRINTK("CRTC_GEN_CNTL: %x\n", crtc->gen_cntl);
    718. 

  718. 

  719. 	aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
    720. 

  720. 	aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
    721. 

  721. 	aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
    722. 

  722. 	aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
    723. 

  723. 	aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
    724. 

  724. 	aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
    725. 

  725. 

  726. 	aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
    727. 

  727. #if 0
    728. 

  728. 	FIXME
    729. 

  729. 	if (par->accel_flags & FB_ACCELF_TEXT)
    730. 

  730. 		aty_init_engine(par, info);
    731. 

  731. #endif
    732. 

  732. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    733. 

  733. 	/* after setting the CRTC registers we should set the LCD registers. */
    734. 

  734. 	if (par->lcd_table != 0) {
    735. 

  735. 		/* switch to shadow registers */
    736. 

  736. 		aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
    737. 

  737. 			   SHADOW_EN | SHADOW_RW_EN, par);
    738. 

  738. 

  739. 		DPRINTK("set shadow CRT to %ix%i %c%c\n",
    740. 

  740. 			((((crtc->shadow_h_tot_disp >> 16) & 0xff) + 1) << 3),
    741. 

  741. 			(((crtc->shadow_v_tot_disp >> 16) & 0x7ff) + 1),
    742. 

  742. 			(crtc->shadow_h_sync_strt_wid & 0x200000) ? 'N' : 'P',
    743. 

  743. 			(crtc->shadow_v_sync_strt_wid & 0x200000) ? 'N' : 'P');
    744. 

  744. 

  745. 		DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n",
    746. 

  746. 			crtc->shadow_h_tot_disp);
    747. 

  747. 		DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n",
    748. 

  748. 			crtc->shadow_h_sync_strt_wid);
    749. 

  749. 		DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n",
    750. 

  750. 			crtc->shadow_v_tot_disp);
    751. 

  751. 		DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n",
    752. 

  752. 			crtc->shadow_v_sync_strt_wid);
    753. 

  753. 

  754. 		aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
    755. 

  755. 		aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
    756. 

  756. 		aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
    757. 

  757. 		aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
    758. 

  758. 

  759. 		/* restore CRTC selection & shadow state and enable stretching */
    760. 

  760. 		DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
    761. 

  761. 		DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
    762. 

  762. 		DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
    763. 

  763. 		if (!M64_HAS(LT_LCD_REGS))
    764. 

  764. 			DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
    765. 

  765. 

  766. 		aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
    767. 

  767. 		aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
    768. 

  768. 		aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
    769. 

  769. 		if (!M64_HAS(LT_LCD_REGS)) {
    770. 

  770. 			aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
    771. 

  771. 			aty_ld_le32(LCD_INDEX, par);
    772. 

  772. 			aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
    773. 

  773. 		}
    774. 

  774. 	}
    775. 

  775. #endif /* CONFIG_FB_ATY_GENERIC_LCD */
    776. 

  776. }
    777. 

  777. 

  778. static u32 calc_line_length(struct atyfb_par *par, u32 vxres, u32 bpp)
    779. 

  779. {
    780. 

  780. 	u32 line_length = vxres * bpp / 8;
    781. 

  781. 

  782. 	if (par->ram_type == SGRAM ||
    783. 

  783. 	    (!M64_HAS(XL_MEM) && par->ram_type == WRAM))
    784. 

  784. 		line_length = (line_length + 63) & ~63;
    785. 

  785. 

  786. 	return line_length;
    787. 

  787. }
    788. 

  788. 

  789. static int aty_var_to_crtc(const struct fb_info *info,
    790. 

  790. 			   const struct fb_var_screeninfo *var,
    791. 

  791. 			   struct crtc *crtc)
    792. 

  792. {
    793. 

  793. 	struct atyfb_par *par = (struct atyfb_par *) info->par;
    794. 

  794. 	u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
    795. 

  795. 	u32 sync, vmode, vdisplay;
    796. 

  796. 	u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
    797. 

  797. 	u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
    798. 

  798. 	u32 pix_width, dp_pix_width, dp_chain_mask;
    799. 

  799. 	u32 line_length;
    800. 

  800. 

  801. 	/* input */
    802. 

  802. 	xres = (var->xres + 7) & ~7;
    803. 

  803. 	yres = var->yres;
    804. 

  804. 	vxres = (var->xres_virtual + 7) & ~7;
    805. 

  805. 	vyres = var->yres_virtual;
    806. 

  806. 	xoffset = (var->xoffset + 7) & ~7;
    807. 

  807. 	yoffset = var->yoffset;
    808. 

  808. 	bpp = var->bits_per_pixel;
    809. 

  809. 	if (bpp == 16)
    810. 

  810. 		bpp = (var->green.length == 5) ? 15 : 16;
    811. 

  811. 	sync = var->sync;
    812. 

  812. 	vmode = var->vmode;
    813. 

  813. 

  814. 	/* convert (and round up) and validate */
    815. 

  815. 	if (vxres < xres + xoffset)
    816. 

  816. 		vxres = xres + xoffset;
    817. 

  817. 	h_disp = xres;
    818. 

  818. 

  819. 	if (vyres < yres + yoffset)
    820. 

  820. 		vyres = yres + yoffset;
    821. 

  821. 	v_disp = yres;
    822. 

  822. 

  823. 	if (bpp <= 8) {
    824. 

  824. 		bpp = 8;
    825. 

  825. 		pix_width = CRTC_PIX_WIDTH_8BPP;
    826. 

  826. 		dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
    827. 

  827. 			BYTE_ORDER_LSB_TO_MSB;
    828. 

  828. 		dp_chain_mask = DP_CHAIN_8BPP;
    829. 

  829. 	} else if (bpp <= 15) {
    830. 

  830. 		bpp = 16;
    831. 

  831. 		pix_width = CRTC_PIX_WIDTH_15BPP;
    832. 

  832. 		dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
    833. 

  833. 			BYTE_ORDER_LSB_TO_MSB;
    834. 

  834. 		dp_chain_mask = DP_CHAIN_15BPP;
    835. 

  835. 	} else if (bpp <= 16) {
    836. 

  836. 		bpp = 16;
    837. 

  837. 		pix_width = CRTC_PIX_WIDTH_16BPP;
    838. 

  838. 		dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
    839. 

  839. 			BYTE_ORDER_LSB_TO_MSB;
    840. 

  840. 		dp_chain_mask = DP_CHAIN_16BPP;
    841. 

  841. 	} else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
    842. 

  842. 		bpp = 24;
    843. 

  843. 		pix_width = CRTC_PIX_WIDTH_24BPP;
    844. 

  844. 		dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
    845. 

  845. 			BYTE_ORDER_LSB_TO_MSB;
    846. 

  846. 		dp_chain_mask = DP_CHAIN_24BPP;
    847. 

  847. 	} else if (bpp <= 32) {
    848. 

  848. 		bpp = 32;
    849. 

  849. 		pix_width = CRTC_PIX_WIDTH_32BPP;
    850. 

  850. 		dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
    851. 

  851. 			BYTE_ORDER_LSB_TO_MSB;
    852. 

  852. 		dp_chain_mask = DP_CHAIN_32BPP;
    853. 

  853. 	} else
    854. 

  854. 		FAIL("invalid bpp");
    855. 

  855. 

  856. 	line_length = calc_line_length(par, vxres, bpp);
    857. 

  857. 

  858. 	if (vyres * line_length > info->fix.smem_len)
    859. 

  859. 		FAIL("not enough video RAM");
    860. 

  860. 

  861. 	h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
    862. 

  862. 	v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
    863. 

  863. 

  864. 	if ((xres > 1600) || (yres > 1200)) {
    865. 

  865. 		FAIL("MACH64 chips are designed for max 1600x1200\n"
    866. 

  866. 		     "select anoter resolution.");
    867. 

  867. 	}
    868. 

  868. 	h_sync_strt = h_disp + var->right_margin;
    869. 

  869. 	h_sync_end = h_sync_strt + var->hsync_len;
    870. 

  870. 	h_sync_dly  = var->right_margin & 7;
    871. 

  871. 	h_total = h_sync_end + h_sync_dly + var->left_margin;
    872. 

  872. 

  873. 	v_sync_strt = v_disp + var->lower_margin;
    874. 

  874. 	v_sync_end = v_sync_strt + var->vsync_len;
    875. 

  875. 	v_total = v_sync_end + var->upper_margin;
    876. 

  876. 

  877. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    878. 

  878. 	if (par->lcd_table != 0) {
    879. 

  879. 		if (!M64_HAS(LT_LCD_REGS)) {
    880. 

  880. 			u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
    881. 

  881. 			crtc->lcd_index = lcd_index &
    882. 

  882. 				~(LCD_INDEX_MASK | LCD_DISPLAY_DIS |
    883. 

  883. 				  LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
    884. 

  884. 			aty_st_le32(LCD_INDEX, lcd_index, par);
    885. 

  885. 		}
    886. 

  886. 

  887. 		if (!M64_HAS(MOBIL_BUS))
    888. 

  888. 			crtc->lcd_index |= CRTC2_DISPLAY_DIS;
    889. 

  889. 

  890. 		crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
    891. 

  891. 		crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
    892. 

  892. 

  893. 		crtc->lcd_gen_cntl &=
    894. 

  894. 			~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
    895. 

  895. 			/*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
    896. 

  896. 			USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
    897. 

  897. 		crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
    898. 

  898. 

  899. 		if ((crtc->lcd_gen_cntl & LCD_ON) &&
    900. 

  900. 		    ((xres > par->lcd_width) || (yres > par->lcd_height))) {
    901. 

  901. 			/*
    902. 

  902. 			 * We cannot display the mode on the LCD. If the CRT is
    903. 

  903. 			 * enabled we can turn off the LCD.
    904. 

  904. 			 * If the CRT is off, it isn't a good idea to switch it
    905. 

  905. 			 * on; we don't know if one is connected. So it's better
    906. 

  906. 			 * to fail then.
    907. 

  907. 			 */
    908. 

  908. 			if (crtc->lcd_gen_cntl & CRT_ON) {
    909. 

  909. 				if (!(var->activate & FB_ACTIVATE_TEST))
    910. 

  910. 					PRINTKI("Disable LCD panel, because video mode does not fit.\n");
    911. 

  911. 				crtc->lcd_gen_cntl &= ~LCD_ON;
    912. 

  912. 				/*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
    913. 

  913. 			} else {
    914. 

  914. 				if (!(var->activate & FB_ACTIVATE_TEST))
    915. 

  915. 					PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
    916. 

  916. 				return -EINVAL;
    917. 

  917. 			}
    918. 

  918. 		}
    919. 

  919. 	}
    920. 

  920. 

  921. 	if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
    922. 

  922. 		int VScan = 1;
    923. 

  923. 		/* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
    924. 

  924. 		const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
    925. 

  925. 		const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
    926. 

  926. 

  927. 		vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
    928. 

  928. 

  929. 		/*
    930. 

  930. 		 * This is horror! When we simulate, say 640x480 on an 800x600
    931. 

  931. 		 * LCD monitor, the CRTC should be programmed 800x600 values for
    932. 

  932. 		 * the non visible part, but 640x480 for the visible part.
    933. 

  933. 		 * This code has been tested on a laptop with it's 1400x1050 LCD
    934. 

  934. 		 * monitor and a conventional monitor both switched on.
    935. 

  935. 		 * Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
    936. 

  936. 		 * works with little glitches also with DOUBLESCAN modes
    937. 

  937. 		 */
    938. 

  938. 		if (yres < par->lcd_height) {
    939. 

  939. 			VScan = par->lcd_height / yres;
    940. 

  940. 			if (VScan > 1) {
    941. 

  941. 				VScan = 2;
    942. 

  942. 				vmode |= FB_VMODE_DOUBLE;
    943. 

  943. 			}
    944. 

  944. 		}
    945. 

  945. 

  946. 		h_sync_strt = h_disp + par->lcd_right_margin;
    947. 

  947. 		h_sync_end = h_sync_strt + par->lcd_hsync_len;
    948. 

  948. 		h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
    949. 

  949. 		h_total = h_disp + par->lcd_hblank_len;
    950. 

  950. 

  951. 		v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
    952. 

  952. 		v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
    953. 

  953. 		v_total = v_disp + par->lcd_vblank_len / VScan;
    954. 

  954. 	}
    955. 

  955. #endif /* CONFIG_FB_ATY_GENERIC_LCD */
    956. 

  956. 

  957. 	h_disp = (h_disp >> 3) - 1;
    958. 

  958. 	h_sync_strt = (h_sync_strt >> 3) - 1;
    959. 

  959. 	h_sync_end = (h_sync_end >> 3) - 1;
    960. 

  960. 	h_total = (h_total >> 3) - 1;
    961. 

  961. 	h_sync_wid = h_sync_end - h_sync_strt;
    962. 

  962. 

  963. 	FAIL_MAX("h_disp too large", h_disp, 0xff);
    964. 

  964. 	FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
    965. 

  965. 	/*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
    966. 

  966. 	if (h_sync_wid > 0x1f)
    967. 

  967. 		h_sync_wid = 0x1f;
    968. 

  968. 	FAIL_MAX("h_total too large", h_total, 0x1ff);
    969. 

  969. 

  970. 	if (vmode & FB_VMODE_DOUBLE) {
    971. 

  971. 		v_disp <<= 1;
    972. 

  972. 		v_sync_strt <<= 1;
    973. 

  973. 		v_sync_end <<= 1;
    974. 

  974. 		v_total <<= 1;
    975. 

  975. 	}
    976. 

  976. 

  977. 	vdisplay = yres;
    978. 

  978. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    979. 

  979. 	if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
    980. 

  980. 		vdisplay  = par->lcd_height;
    981. 

  981. #endif
    982. 

  982. 

  983. 	v_disp--;
    984. 

  984. 	v_sync_strt--;
    985. 

  985. 	v_sync_end--;
    986. 

  986. 	v_total--;
    987. 

  987. 	v_sync_wid = v_sync_end - v_sync_strt;
    988. 

  988. 

  989. 	FAIL_MAX("v_disp too large", v_disp, 0x7ff);
    990. 

  990. 	FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
    991. 

  991. 	/*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
    992. 

  992. 	if (v_sync_wid > 0x1f)
    993. 

  993. 		v_sync_wid = 0x1f;
    994. 

  994. 	FAIL_MAX("v_total too large", v_total, 0x7ff);
    995. 

  995. 

  996. 	c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
    997. 

  997. 

  998. 	/* output */
    999. 

  999. 	crtc->vxres = vxres;
    1000. 

  1000. 	crtc->vyres = vyres;
    1001. 

  1001. 	crtc->xoffset = xoffset;
    1002. 

  1002. 	crtc->yoffset = yoffset;
    1003. 

  1003. 	crtc->bpp = bpp;
    1004. 

  1004. 	crtc->off_pitch =
    1005. 

  1005. 		((yoffset * line_length + xoffset * bpp / 8) / 8) |
    1006. 

  1006. 		((line_length / bpp) << 22);
    1007. 

  1007. 	crtc->vline_crnt_vline = 0;
    1008. 

  1008. 

  1009. 	crtc->h_tot_disp = h_total | (h_disp << 16);
    1010. 

  1010. 	crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly << 8) |
    1011. 

  1011. 		((h_sync_strt & 0x100) << 4) | (h_sync_wid << 16) |
    1012. 

  1012. 		(h_sync_pol << 21);
    1013. 

  1013. 	crtc->v_tot_disp = v_total | (v_disp << 16);
    1014. 

  1014. 	crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
    1015. 

  1015. 		(v_sync_pol << 21);
    1016. 

  1016. 

  1017. 	/* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
    1018. 

  1018. 	crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
    1019. 

  1019. 	crtc->gen_cntl |= CRTC_VGA_LINEAR;
    1020. 

  1020. 

  1021. 	/* Enable doublescan mode if requested */
    1022. 

  1022. 	if (vmode & FB_VMODE_DOUBLE)
    1023. 

  1023. 		crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
    1024. 

  1024. 	/* Enable interlaced mode if requested */
    1025. 

  1025. 	if (vmode & FB_VMODE_INTERLACED)
    1026. 

  1026. 		crtc->gen_cntl |= CRTC_INTERLACE_EN;
    1027. 

  1027. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    1028. 

  1028. 	if (par->lcd_table != 0) {
    1029. 

  1029. 		vdisplay = yres;
    1030. 

  1030. 		if (vmode & FB_VMODE_DOUBLE)
    1031. 

  1031. 			vdisplay <<= 1;
    1032. 

  1032. 		crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
    1033. 

  1033. 		crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
    1034. 

  1034. 					/*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
    1035. 

  1035. 					USE_SHADOWED_VEND |
    1036. 

  1036. 					USE_SHADOWED_ROWCUR |
    1037. 

  1037. 					SHADOW_EN | SHADOW_RW_EN);
    1038. 

  1038. 		crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR/* | LOCK_8DOT*/;
    1039. 

  1039. 

  1040. 		/* MOBILITY M1 tested, FIXME: LT */
    1041. 

  1041. 		crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
    1042. 

  1042. 		if (!M64_HAS(LT_LCD_REGS))
    1043. 

  1043. 			crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
    1044. 

  1044. 				~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
    1045. 

  1045. 

  1046. 		crtc->horz_stretching &= ~(HORZ_STRETCH_RATIO |
    1047. 

  1047. 					   HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
    1048. 

  1048. 					   HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
    1049. 

  1049. 		if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
    1050. 

  1050. 			do {
    1051. 

  1051. 				/*
    1052. 

  1052. 				 * The horizontal blender misbehaves when
    1053. 

  1053. 				 * HDisplay is less than a certain threshold
    1054. 

  1054. 				 * (440 for a 1024-wide panel).  It doesn't
    1055. 

  1055. 				 * stretch such modes enough.  Use pixel
    1056. 

  1056. 				 * replication instead of blending to stretch
    1057. 

  1057. 				 * modes that can be made to exactly fit the
    1058. 

  1058. 				 * panel width.  The undocumented "NoLCDBlend"
    1059. 

  1059. 				 * option allows the pixel-replicated mode to
    1060. 

  1060. 				 * be slightly wider or narrower than the
    1061. 

  1061. 				 * panel width.  It also causes a mode that is
    1062. 

  1062. 				 * exactly half as wide as the panel to be
    1063. 

  1063. 				 * pixel-replicated, rather than blended.
    1064. 

  1064. 				 */
    1065. 

  1065. 				int HDisplay  = xres & ~7;
    1066. 

  1066. 				int nStretch  = par->lcd_width / HDisplay;
    1067. 

  1067. 				int Remainder = par->lcd_width % HDisplay;
    1068. 

  1068. 

  1069. 				if ((!Remainder && ((nStretch > 2))) ||
    1070. 

  1070. 				    (((HDisplay * 16) / par->lcd_width) < 7)) {
    1071. 

  1071. 					static const char StretchLoops[] = { 10, 12, 13, 15, 16 };
    1072. 

  1072. 					int horz_stretch_loop = -1, BestRemainder;
    1073. 

  1073. 					int Numerator = HDisplay, Denominator = par->lcd_width;
    1074. 

  1074. 					int Index = 5;
    1075. 

  1075. 					ATIReduceRatio(&Numerator, &Denominator);
    1076. 

  1076. 

  1077. 					BestRemainder = (Numerator * 16) / Denominator;
    1078. 

  1078. 					while (--Index >= 0) {
    1079. 

  1079. 						Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
    1080. 

  1080. 							Denominator;
    1081. 

  1081. 						if (Remainder < BestRemainder) {
    1082. 

  1082. 							horz_stretch_loop = Index;
    1083. 

  1083. 							if (!(BestRemainder = Remainder))
    1084. 

  1084. 								break;
    1085. 

  1085. 						}
    1086. 

  1086. 					}
    1087. 

  1087. 

  1088. 					if ((horz_stretch_loop >= 0) && !BestRemainder) {
    1089. 

  1089. 						int horz_stretch_ratio = 0, Accumulator = 0;
    1090. 

  1090. 						int reuse_previous = 1;
    1091. 

  1091. 

  1092. 						Index = StretchLoops[horz_stretch_loop];
    1093. 

  1093. 

  1094. 						while (--Index >= 0) {
    1095. 

  1095. 							if (Accumulator > 0)
    1096. 

  1096. 								horz_stretch_ratio |= reuse_previous;
    1097. 

  1097. 							else
    1098. 

  1098. 								Accumulator += Denominator;
    1099. 

  1099. 							Accumulator -= Numerator;
    1100. 

  1100. 							reuse_previous <<= 1;
    1101. 

  1101. 						}
    1102. 

  1102. 

  1103. 						crtc->horz_stretching |= (HORZ_STRETCH_EN |
    1104. 

  1104. 							((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
    1105. 

  1105. 							(horz_stretch_ratio & HORZ_STRETCH_RATIO));
    1106. 

  1106. 						break;      /* Out of the do { ... } while (0) */
    1107. 

  1107. 					}
    1108. 

  1108. 				}
    1109. 

  1109. 

  1110. 				crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
    1111. 

  1111. 					(((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
    1112. 

  1112. 			} while (0);
    1113. 

  1113. 		}
    1114. 

  1114. 

  1115. 		if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
    1116. 

  1116. 			crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
    1117. 

  1117. 				(((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
    1118. 

  1118. 

  1119. 			if (!M64_HAS(LT_LCD_REGS) &&
    1120. 

  1120. 			    xres <= (M64_HAS(MOBIL_BUS) ? 1024 : 800))
    1121. 

  1121. 				crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
    1122. 

  1122. 		} else {
    1123. 

  1123. 			/*
    1124. 

  1124. 			 * Don't use vertical blending if the mode is too wide
    1125. 

  1125. 			 * or not vertically stretched.
    1126. 

  1126. 			 */
    1127. 

  1127. 			crtc->vert_stretching = 0;
    1128. 

  1128. 		}
    1129. 

  1129. 		/* copy to shadow crtc */
    1130. 

  1130. 		crtc->shadow_h_tot_disp = crtc->h_tot_disp;
    1131. 

  1131. 		crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
    1132. 

  1132. 		crtc->shadow_v_tot_disp = crtc->v_tot_disp;
    1133. 

  1133. 		crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
    1134. 

  1134. 	}
    1135. 

  1135. #endif /* CONFIG_FB_ATY_GENERIC_LCD */
    1136. 

  1136. 

  1137. 	if (M64_HAS(MAGIC_FIFO)) {
    1138. 

  1138. 		/* FIXME: display FIFO low watermark values */
    1139. 

  1139. 		crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
    1140. 

  1140. 	}
    1141. 

  1141. 	crtc->dp_pix_width = dp_pix_width;
    1142. 

  1142. 	crtc->dp_chain_mask = dp_chain_mask;
    1143. 

  1143. 

  1144. 	return 0;
    1145. 

  1145. }
    1146. 

  1146. 

  1147. static int aty_crtc_to_var(const struct crtc *crtc,
    1148. 

  1148. 			   struct fb_var_screeninfo *var)
    1149. 

  1149. {
    1150. 

  1150. 	u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
    1151. 

  1151. 	u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
    1152. 

  1152. 	u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
    1153. 

  1153. 	u32 pix_width;
    1154. 

  1154. 	u32 double_scan, interlace;
    1155. 

  1155. 

  1156. 	/* input */
    1157. 

  1157. 	h_total = crtc->h_tot_disp & 0x1ff;
    1158. 

  1158. 	h_disp = (crtc->h_tot_disp >> 16) & 0xff;
    1159. 

  1159. 	h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
    1160. 

  1160. 	h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
    1161. 

  1161. 	h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
    1162. 

  1162. 	h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
    1163. 

  1163. 	v_total = crtc->v_tot_disp & 0x7ff;
    1164. 

  1164. 	v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
    1165. 

  1165. 	v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
    1166. 

  1166. 	v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
    1167. 

  1167. 	v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
    1168. 

  1168. 	c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
    1169. 

  1169. 	pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
    1170. 

  1170. 	double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
    1171. 

  1171. 	interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
    1172. 

  1172. 

  1173. 	/* convert */
    1174. 

  1174. 	xres = (h_disp + 1) * 8;
    1175. 

  1175. 	yres = v_disp + 1;
    1176. 

  1176. 	left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
    1177. 

  1177. 	right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
    1178. 

  1178. 	hslen = h_sync_wid * 8;
    1179. 

  1179. 	upper = v_total - v_sync_strt - v_sync_wid;
    1180. 

  1180. 	lower = v_sync_strt - v_disp;
    1181. 

  1181. 	vslen = v_sync_wid;
    1182. 

  1182. 	sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
    1183. 

  1183. 		(v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
    1184. 

  1184. 		(c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
    1185. 

  1185. 

  1186. 	switch (pix_width) {
    1187. 

  1187. #if 0
    1188. 

  1188. 	case CRTC_PIX_WIDTH_4BPP:
    1189. 

  1189. 		bpp = 4;
    1190. 

  1190. 		var->red.offset = 0;
    1191. 

  1191. 		var->red.length = 8;
    1192. 

  1192. 		var->green.offset = 0;
    1193. 

  1193. 		var->green.length = 8;
    1194. 

  1194. 		var->blue.offset = 0;
    1195. 

  1195. 		var->blue.length = 8;
    1196. 

  1196. 		var->transp.offset = 0;
    1197. 

  1197. 		var->transp.length = 0;
    1198. 

  1198. 		break;
    1199. 

  1199. #endif
    1200. 

  1200. 	case CRTC_PIX_WIDTH_8BPP:
    1201. 

  1201. 		bpp = 8;
    1202. 

  1202. 		var->red.offset = 0;
    1203. 

  1203. 		var->red.length = 8;
    1204. 

  1204. 		var->green.offset = 0;
    1205. 

  1205. 		var->green.length = 8;
    1206. 

  1206. 		var->blue.offset = 0;
    1207. 

  1207. 		var->blue.length = 8;
    1208. 

  1208. 		var->transp.offset = 0;
    1209. 

  1209. 		var->transp.length = 0;
    1210. 

  1210. 		break;
    1211. 

  1211. 	case CRTC_PIX_WIDTH_15BPP:	/* RGB 555 */
    1212. 

  1212. 		bpp = 16;
    1213. 

  1213. 		var->red.offset = 10;
    1214. 

  1214. 		var->red.length = 5;
    1215. 

  1215. 		var->green.offset = 5;
    1216. 

  1216. 		var->green.length = 5;
    1217. 

  1217. 		var->blue.offset = 0;
    1218. 

  1218. 		var->blue.length = 5;
    1219. 

  1219. 		var->transp.offset = 0;
    1220. 

  1220. 		var->transp.length = 0;
    1221. 

  1221. 		break;
    1222. 

  1222. 	case CRTC_PIX_WIDTH_16BPP:	/* RGB 565 */
    1223. 

  1223. 		bpp = 16;
    1224. 

  1224. 		var->red.offset = 11;
    1225. 

  1225. 		var->red.length = 5;
    1226. 

  1226. 		var->green.offset = 5;
    1227. 

  1227. 		var->green.length = 6;
    1228. 

  1228. 		var->blue.offset = 0;
    1229. 

  1229. 		var->blue.length = 5;
    1230. 

  1230. 		var->transp.offset = 0;
    1231. 

  1231. 		var->transp.length = 0;
    1232. 

  1232. 		break;
    1233. 

  1233. 	case CRTC_PIX_WIDTH_24BPP:	/* RGB 888 */
    1234. 

  1234. 		bpp = 24;
    1235. 

  1235. 		var->red.offset = 16;
    1236. 

  1236. 		var->red.length = 8;
    1237. 

  1237. 		var->green.offset = 8;
    1238. 

  1238. 		var->green.length = 8;
    1239. 

  1239. 		var->blue.offset = 0;
    1240. 

  1240. 		var->blue.length = 8;
    1241. 

  1241. 		var->transp.offset = 0;
    1242. 

  1242. 		var->transp.length = 0;
    1243. 

  1243. 		break;
    1244. 

  1244. 	case CRTC_PIX_WIDTH_32BPP:	/* ARGB 8888 */
    1245. 

  1245. 		bpp = 32;
    1246. 

  1246. 		var->red.offset = 16;
    1247. 

  1247. 		var->red.length = 8;
    1248. 

  1248. 		var->green.offset = 8;
    1249. 

  1249. 		var->green.length = 8;
    1250. 

  1250. 		var->blue.offset = 0;
    1251. 

  1251. 		var->blue.length = 8;
    1252. 

  1252. 		var->transp.offset = 24;
    1253. 

  1253. 		var->transp.length = 8;
    1254. 

  1254. 		break;
    1255. 

  1255. 	default:
    1256. 

  1256. 		PRINTKE("Invalid pixel width\n");
    1257. 

  1257. 		return -EINVAL;
    1258. 

  1258. 	}
    1259. 

  1259. 

  1260. 	/* output */
    1261. 

  1261. 	var->xres = xres;
    1262. 

  1262. 	var->yres = yres;
    1263. 

  1263. 	var->xres_virtual = crtc->vxres;
    1264. 

  1264. 	var->yres_virtual = crtc->vyres;
    1265. 

  1265. 	var->bits_per_pixel = bpp;
    1266. 

  1266. 	var->left_margin = left;
    1267. 

  1267. 	var->right_margin = right;
    1268. 

  1268. 	var->upper_margin = upper;
    1269. 

  1269. 	var->lower_margin = lower;
    1270. 

  1270. 	var->hsync_len = hslen;
    1271. 

  1271. 	var->vsync_len = vslen;
    1272. 

  1272. 	var->sync = sync;
    1273. 

  1273. 	var->vmode = FB_VMODE_NONINTERLACED;
    1274. 

  1274. 	/*
    1275. 

  1275. 	 * In double scan mode, the vertical parameters are doubled,
    1276. 

  1276. 	 * so we need to halve them to get the right values.
    1277. 

  1277. 	 * In interlaced mode the values are already correct,
    1278. 

  1278. 	 * so no correction is necessary.
    1279. 

  1279. 	 */
    1280. 

  1280. 	if (interlace)
    1281. 

  1281. 		var->vmode = FB_VMODE_INTERLACED;
    1282. 

  1282. 

  1283. 	if (double_scan) {
    1284. 

  1284. 		var->vmode = FB_VMODE_DOUBLE;
    1285. 

  1285. 		var->yres >>= 1;
    1286. 

  1286. 		var->upper_margin >>= 1;
    1287. 

  1287. 		var->lower_margin >>= 1;
    1288. 

  1288. 		var->vsync_len >>= 1;
    1289. 

  1289. 	}
    1290. 

  1290. 

  1291. 	return 0;
    1292. 

  1292. }
    1293. 

  1293. 

  1294. /* ------------------------------------------------------------------------- */
    1295. 

  1295. 

  1296. static int atyfb_set_par(struct fb_info *info)
    1297. 

  1297. {
    1298. 

  1298. 	struct atyfb_par *par = (struct atyfb_par *) info->par;
    1299. 

  1299. 	struct fb_var_screeninfo *var = &info->var;
    1300. 

  1300. 	u32 tmp, pixclock;
    1301. 

  1301. 	int err;
    1302. 

  1302. #ifdef DEBUG
    1303. 

  1303. 	struct fb_var_screeninfo debug;
    1304. 

  1304. 	u32 pixclock_in_ps;
    1305. 

  1305. #endif
    1306. 

  1306. 	if (par->asleep)
    1307. 

  1307. 		return 0;
    1308. 

  1308. 

  1309. 	err = aty_var_to_crtc(info, var, &par->crtc);
    1310. 

  1310. 	if (err)
    1311. 

  1311. 		return err;
    1312. 

  1312. 

  1313. 	pixclock = atyfb_get_pixclock(var, par);
    1314. 

  1314. 

  1315. 	if (pixclock == 0) {
    1316. 

  1316. 		PRINTKE("Invalid pixclock\n");
    1317. 

  1317. 		return -EINVAL;
    1318. 

  1318. 	} else {
    1319. 

  1319. 		err = par->pll_ops->var_to_pll(info, pixclock,
    1320. 

  1320. 					       var->bits_per_pixel, &par->pll);
    1321. 

  1321. 		if (err)
    1322. 

  1322. 			return err;
    1323. 

  1323. 	}
    1324. 

  1324. 

  1325. 	par->accel_flags = var->accel_flags; /* hack */
    1326. 

  1326. 

  1327. 	if (var->accel_flags) {
    1328. 

  1328. 		info->fbops->fb_sync = atyfb_sync;
    1329. 

  1329. 		info->flags &= ~FBINFO_HWACCEL_DISABLED;
    1330. 

  1330. 	} else {
    1331. 

  1331. 		info->fbops->fb_sync = NULL;
    1332. 

  1332. 		info->flags |= FBINFO_HWACCEL_DISABLED;
    1333. 

  1333. 	}
    1334. 

  1334. 

  1335. 	if (par->blitter_may_be_busy)
    1336. 

  1336. 		wait_for_idle(par);
    1337. 

  1337. 

  1338. 	aty_set_crtc(par, &par->crtc);
    1339. 

  1339. 	par->dac_ops->set_dac(info, &par->pll,
    1340. 

  1340. 			      var->bits_per_pixel, par->accel_flags);
    1341. 

  1341. 	par->pll_ops->set_pll(info, &par->pll);
    1342. 

  1342. 

  1343. #ifdef DEBUG
    1344. 

  1344. 	if (par->pll_ops && par->pll_ops->pll_to_var)
    1345. 

  1345. 		pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll);
    1346. 

  1346. 	else
    1347. 

  1347. 		pixclock_in_ps = 0;
    1348. 

  1348. 

  1349. 	if (0 == pixclock_in_ps) {
    1350. 

  1350. 		PRINTKE("ALERT ops->pll_to_var get 0\n");
    1351. 

  1351. 		pixclock_in_ps = pixclock;
    1352. 

  1352. 	}
    1353. 

  1353. 

  1354. 	memset(&debug, 0, sizeof(debug));
    1355. 

  1355. 	if (!aty_crtc_to_var(&par->crtc, &debug)) {
    1356. 

  1356. 		u32 hSync, vRefresh;
    1357. 

  1357. 		u32 h_disp, h_sync_strt, h_sync_end, h_total;
    1358. 

  1358. 		u32 v_disp, v_sync_strt, v_sync_end, v_total;
    1359. 

  1359. 

  1360. 		h_disp = debug.xres;
    1361. 

  1361. 		h_sync_strt = h_disp + debug.right_margin;
    1362. 

  1362. 		h_sync_end = h_sync_strt + debug.hsync_len;
    1363. 

  1363. 		h_total = h_sync_end + debug.left_margin;
    1364. 

  1364. 		v_disp = debug.yres;
    1365. 

  1365. 		v_sync_strt = v_disp + debug.lower_margin;
    1366. 

  1366. 		v_sync_end = v_sync_strt + debug.vsync_len;
    1367. 

  1367. 		v_total = v_sync_end + debug.upper_margin;
    1368. 

  1368. 

  1369. 		hSync = 1000000000 / (pixclock_in_ps * h_total);
    1370. 

  1370. 		vRefresh = (hSync * 1000) / v_total;
    1371. 

  1371. 		if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
    1372. 

  1372. 			vRefresh *= 2;
    1373. 

  1373. 		if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
    1374. 

  1374. 			vRefresh /= 2;
    1375. 

  1375. 

  1376. 		DPRINTK("atyfb_set_par\n");
    1377. 

  1377. 		DPRINTK(" Set Visible Mode to %ix%i-%i\n",
    1378. 

  1378. 			var->xres, var->yres, var->bits_per_pixel);
    1379. 

  1379. 		DPRINTK(" Virtual resolution %ix%i, "
    1380. 

  1380. 			"pixclock_in_ps %i (calculated %i)\n",
    1381. 

  1381. 			var->xres_virtual, var->yres_virtual,
    1382. 

  1382. 			pixclock, pixclock_in_ps);
    1383. 

  1383. 		DPRINTK(" Dot clock:           %i MHz\n",
    1384. 

  1384. 			1000000 / pixclock_in_ps);
    1385. 

  1385. 		DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
    1386. 

  1386. 		DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
    1387. 

  1387. 		DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
    1388. 

  1388. 			1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
    1389. 

  1389. 			h_disp, h_sync_strt, h_sync_end, h_total,
    1390. 

  1390. 			v_disp, v_sync_strt, v_sync_end, v_total);
    1391. 

  1391. 		DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
    1392. 

  1392. 			pixclock_in_ps,
    1393. 

  1393. 			debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
    1394. 

  1394. 			debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
    1395. 

  1395. 	}
    1396. 

  1396. #endif /* DEBUG */
    1397. 

  1397. 

  1398. 	if (!M64_HAS(INTEGRATED)) {
    1399. 

  1399. 		/* Don't forget MEM_CNTL */
    1400. 

  1400. 		tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
    1401. 

  1401. 		switch (var->bits_per_pixel) {
    1402. 

  1402. 		case 8:
    1403. 

  1403. 			tmp |= 0x02000000;
    1404. 

  1404. 			break;
    1405. 

  1405. 		case 16:
    1406. 

  1406. 			tmp |= 0x03000000;
    1407. 

  1407. 			break;
    1408. 

  1408. 		case 32:
    1409. 

  1409. 			tmp |= 0x06000000;
    1410. 

  1410. 			break;
    1411. 

  1411. 		}
    1412. 

  1412. 		aty_st_le32(MEM_CNTL, tmp, par);
    1413. 

  1413. 	} else {
    1414. 

  1414. 		tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
    1415. 

  1415. 		if (!M64_HAS(MAGIC_POSTDIV))
    1416. 

  1416. 			tmp |= par->mem_refresh_rate << 20;
    1417. 

  1417. 		switch (var->bits_per_pixel) {
    1418. 

  1418. 		case 8:
    1419. 

  1419. 		case 24:
    1420. 

  1420. 			tmp |= 0x00000000;
    1421. 

  1421. 			break;
    1422. 

  1422. 		case 16:
    1423. 

  1423. 			tmp |= 0x04000000;
    1424. 

  1424. 			break;
    1425. 

  1425. 		case 32:
    1426. 

  1426. 			tmp |= 0x08000000;
    1427. 

  1427. 			break;
    1428. 

  1428. 		}
    1429. 

  1429. 		if (M64_HAS(CT_BUS)) {
    1430. 

  1430. 			aty_st_le32(DAC_CNTL, 0x87010184, par);
    1431. 

  1431. 			aty_st_le32(BUS_CNTL, 0x680000f9, par);
    1432. 

  1432. 		} else if (M64_HAS(VT_BUS)) {
    1433. 

  1433. 			aty_st_le32(DAC_CNTL, 0x87010184, par);
    1434. 

  1434. 			aty_st_le32(BUS_CNTL, 0x680000f9, par);
    1435. 

  1435. 		} else if (M64_HAS(MOBIL_BUS)) {
    1436. 

  1436. 			aty_st_le32(DAC_CNTL, 0x80010102, par);
    1437. 

  1437. 			aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
    1438. 

  1438. 		} else {
    1439. 

  1439. 			/* GT */
    1440. 

  1440. 			aty_st_le32(DAC_CNTL, 0x86010102, par);
    1441. 

  1441. 			aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
    1442. 

  1442. 			aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
    1443. 

  1443. 		}
    1444. 

  1444. 		aty_st_le32(MEM_CNTL, tmp, par);
    1445. 

  1445. 	}
    1446. 

  1446. 	aty_st_8(DAC_MASK, 0xff, par);
    1447. 

  1447. 

  1448. 	info->fix.line_length = calc_line_length(par, var->xres_virtual,
    1449. 

  1449. 						 var->bits_per_pixel);
    1450. 

  1450. 

  1451. 	info->fix.visual = var->bits_per_pixel <= 8 ?
    1452. 

  1452. 		FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
    1453. 

  1453. 

  1454. 	/* Initialize the graphics engine */
    1455. 

  1455. 	if (par->accel_flags & FB_ACCELF_TEXT)
    1456. 

  1456. 		aty_init_engine(par, info);
    1457. 

  1457. 

  1458. #ifdef CONFIG_BOOTX_TEXT
    1459. 

  1459. 	btext_update_display(info->fix.smem_start,
    1460. 

  1460. 		(((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
    1461. 

  1461. 		((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
    1462. 

  1462. 		var->bits_per_pixel,
    1463. 

  1463. 		par->crtc.vxres * var->bits_per_pixel / 8);
    1464. 

  1464. #endif /* CONFIG_BOOTX_TEXT */
    1465. 

  1465. #if 0
    1466. 

  1466. 	/* switch to accelerator mode */
    1467. 

  1467. 	if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
    1468. 

  1468. 		aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
    1469. 

  1469. #endif
    1470. 

  1470. #ifdef DEBUG
    1471. 

  1471. {
    1472. 

  1472. 	/* dump non shadow CRTC, pll, LCD registers */
    1473. 

  1473. 	int i; u32 base;
    1474. 

  1474. 

  1475. 	/* CRTC registers */
    1476. 

  1476. 	base = 0x2000;
    1477. 

  1477. 	printk("debug atyfb: Mach64 non-shadow register values:");
    1478. 

  1478. 	for (i = 0; i < 256; i = i+4) {
    1479. 

  1479. 		if (i % 16 == 0)
    1480. 

  1480. 			printk("\ndebug atyfb: 0x%04X: ", base + i);
    1481. 

  1481. 		printk(" %08X", aty_ld_le32(i, par));
    1482. 

  1482. 	}
    1483. 

  1483. 	printk("\n\n");
    1484. 

  1484. 

  1485. #ifdef CONFIG_FB_ATY_CT
    1486. 

  1486. 	/* PLL registers */
    1487. 

  1487. 	base = 0x00;
    1488. 

  1488. 	printk("debug atyfb: Mach64 PLL register values:");
    1489. 

  1489. 	for (i = 0; i < 64; i++) {
    1490. 

  1490. 		if (i % 16 == 0)
    1491. 

  1491. 			printk("\ndebug atyfb: 0x%02X: ", base + i);
    1492. 

  1492. 		if (i % 4 == 0)
    1493. 

  1493. 			printk(" ");
    1494. 

  1494. 		printk("%02X", aty_ld_pll_ct(i, par));
    1495. 

  1495. 	}
    1496. 

  1496. 	printk("\n\n");
    1497. 

  1497. #endif	/* CONFIG_FB_ATY_CT */
    1498. 

  1498. 

  1499. #ifdef CONFIG_FB_ATY_GENERIC_LCD
    1500. 

  1500. 	if (par->lcd_table != 0) {
    1501. 

  1501. 		/* LCD registers */
    1502. 

  1502. 		base = 0x00;
    1503. 

  1503. 		printk("debug atyfb: LCD register values:");
    1504. 

  1504. 		if (M64_HAS(LT_LCD_REGS)) {
    1505. 

  1505. 			for (i = 0; i <= POWER_MANAGEMENT; i++) {
    1506. 

  1506. 				if (i == EXT_VERT_STRETCH)
    1507. 

  1507. 					continue;
    1508. 

  1508. 				printk("\ndebug atyfb: 0x%04X: ",
    1509. 

  1509. 				       lt_lcd_regs[i]);
    1510. 

  1510. 				printk(" %08X", aty_ld_lcd(i, par));
    1511. 

  1511. 			}
    1512. 

  1512. 		} else {
    1513. 

  1513. 			for (i = 0; i < 64; i++) {
    1514. 

  1514. 				if (i % 4 == 0)
    1515. 

  1515. 					printk("\ndebug atyfb: 0x%02X: ",
    1516. 

  1516. 					       base + i);
    1517. 

  1517. 				printk(" %08X", aty_ld_lcd(i, par));
    1518. 

  1518. 			}
    1519. 

  1519. 		}
    1520. 

  1520. 		printk("\n\n");
    1521. 

  1521. 	}
    1522. 

  1522. #endif /* CONFIG_FB_ATY_GENERIC_LCD */
    1523. 

  1523. }
    1524. 

  1524. #endif /* DEBUG */
    1525. 

  1525. 	return 0;
    1526. 

  1526. }
    1527. 

  1527. 

  1528. static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
    1529. 

  1529. {
    1530. 

  1530. 	struct atyfb_par *par = (struct atyfb_par *) info->par;
    1531. 

  1531. 	int err;
    1532. 

  1532. 	struct crtc crtc;
    1533. 

  1533. 	union aty_pll pll;
    1534. 

  1534. 	u32 pixclock;
    1535. 

  1535. 

  1536. 	memcpy(&pll, &par->pll, sizeof(pll));
    1537. 

  1537. 

  1538. 	err = aty_var_to_crtc(info, var, &crtc);
    1539. 

  1539. 	if (err)
    1540. 

  1540. 		return err;
    1541. 

  1541. 

  1542. 	pixclock = atyfb_get_pixclock(var, par);
    1543. 

  1543. 

  1544. 	if (pixclock == 0) {
    1545. 

  1545. 		if (!(var->activate & FB_ACTIVATE_TEST))
    1546. 

  1546. 			PRINTKE("Invalid pixclock\n");
    1547. 

  1547. 		return -EINVAL;
    1548. 

  1548. 	} else {
    1549. 

  1549. 		err = par->pll_ops->var_to_pll(info, pixclock,
    1550. 

  1550. 					       var->bits_per_pixel, &pll);
    1551. 

  1551. 		if (err)
    1552. 

  1552. 			return err;
    1553. 

  1553. 	}
    1554. 

  1554. 

  1555. 	if (var->accel_flags & FB_ACCELF_TEXT)
    1556. 

  1556. 		info->var.accel_flags = FB_ACCELF_TEXT;
    1557. 

  1557. 	else
    1558. 

  1558. 		info->var.accel_flags = 0;
    1559. 

  1559. 

  1560. 	aty_crtc_to_var(&crtc, var);
    1561. 

  1561. 	var->pixclock = par->pll_ops->pll_to_var(info, &pll);
    1562. 

  1562. 	return 0;
    1563. 

  1563. }
    1564. 

  1564. 

  1565. static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
    1566. 

  1566. {
    1567. 

  1567. 	u32 xoffset = info->var.xoffset;
    1568. 

  1568. 	u32 yoffset = info->var.yoffset;
    1569. 

  1569. 	u32 line_length = info->fix.line_length;
    1570. 

  1570. 	u32 bpp = info->var.bits_per_pixel;
    1571. 

  1571. 

  1572. 	par->crtc.off_pitch =
    1573. 

  1573. 		((yoffset * line_length + xoffset * bpp / 8) / 8) |
    1574. 

  1574. 		((line_length / bpp) << 22);
    1575. 

  1575. }
    1576. 

  1576. 

  1577. 

  1578. /*
    1579. 

  1579.  * Open/Release the frame buffer device
    1580. 

  1580.  */
    1581. 

  1581. 

  1582. static int atyfb_open(struct fb_info *info, int user)
    1583. 

  1583. {
    1584. 

  1584. 	struct atyfb_par *par = (struct atyfb_par *) info->par;
    1585. 

  1585. 

  1586. 	if (user) {
    1587. 

  1587. 		par->open++;
    1588. 

  1588. #ifdef __sparc__
    1589. 

  1589. 		par->mmaped = 0;
    1590. 

  1590. #endif
    1591. 

  1591. 	}
    1592. 

  1592. 	return 0;
    1593. 

  1593. }
    1594. 

  1594. 

  1595. static irqreturn_t aty_irq(int irq, void *dev_id)
    1596. 

  1596. {
    1597. 

  1597. 	struct atyfb_par *par = dev_id;
    1598. 

  1598. 	int handled = 0;
    1599. 

  1599. 	u32 int_cntl;
    1600. 

  1600. 

  1601. 	spin_lock(&par->int_lock);
    1602. 

  1602. 

  1603. 	int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
    1604. 

  1604. 

  1605. 	if (int_cntl & CRTC_VBLANK_INT) {
    1606. 

  1606. 		/* clear interrupt */
    1607. 

  1607. 		aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) |
    1608. 

  1608. 			    CRTC_VBLANK_INT_AK, par);
    1609. 

  1609. 		par->vblank.count++;
    1610. 

  1610. 		if (par->vblank.pan_display) {
    1611. 

  1611. 			par->vblank.pan_display = 0;
    1612. 

  1612. 			aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
    1613. 

  1613. 		}
    1614. 

  1614. 		wake_up_interruptible(&par->vblank.wait);
    1615. 

  1615. 		handled = 1;
    1616. 

  1616. 	}
    1617. 

  1617. 

  1618. 	spin_unlock(&par->int_lock);
    1619. 

  1619. 

  1620. 	return IRQ_RETVAL(handled);
    1621. 

  1621. }
    1622. 

  1622. 

  1623. static int aty_enable_irq(struct atyfb_par *par, int reenable)
    1624. 

  1624. {
    1625. 

  1625. 	u32 int_cntl;
    1626. 

  1626. 

  1627. 	if (!test_and_set_bit(0, &par->irq_flags)) {
    1628. 

  1628. 		if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
    1629. 

  1629. 			clear_bit(0, &par->irq_flags);
    1630. 

  1630. 			return -EINVAL;
    1631. 

  1631. 		
    1632.