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/sound/atmel/ac97c.c

https://github.com/Mengqi/linux-2.6
C | 1202 lines | 981 code | 178 blank | 43 comment | 140 complexity | 8a4546dc140628534dda78ae6b079352 MD5 | raw file
  1. /*
  2. * Driver for Atmel AC97C
  3. *
  4. * Copyright (C) 2005-2009 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/bitmap.h>
  13. #include <linux/device.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/atmel_pdc.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/mutex.h>
  22. #include <linux/gpio.h>
  23. #include <linux/io.h>
  24. #include <sound/core.h>
  25. #include <sound/initval.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/ac97_codec.h>
  29. #include <sound/atmel-ac97c.h>
  30. #include <sound/memalloc.h>
  31. #include <linux/dw_dmac.h>
  32. #include <mach/cpu.h>
  33. #include <mach/gpio.h>
  34. #ifdef CONFIG_ARCH_AT91
  35. #include <mach/hardware.h>
  36. #endif
  37. #include "ac97c.h"
  38. enum {
  39. DMA_TX_READY = 0,
  40. DMA_RX_READY,
  41. DMA_TX_CHAN_PRESENT,
  42. DMA_RX_CHAN_PRESENT,
  43. };
  44. /* Serialize access to opened variable */
  45. static DEFINE_MUTEX(opened_mutex);
  46. struct atmel_ac97c_dma {
  47. struct dma_chan *rx_chan;
  48. struct dma_chan *tx_chan;
  49. };
  50. struct atmel_ac97c {
  51. struct clk *pclk;
  52. struct platform_device *pdev;
  53. struct atmel_ac97c_dma dma;
  54. struct snd_pcm_substream *playback_substream;
  55. struct snd_pcm_substream *capture_substream;
  56. struct snd_card *card;
  57. struct snd_pcm *pcm;
  58. struct snd_ac97 *ac97;
  59. struct snd_ac97_bus *ac97_bus;
  60. u64 cur_format;
  61. unsigned int cur_rate;
  62. unsigned long flags;
  63. int playback_period, capture_period;
  64. /* Serialize access to opened variable */
  65. spinlock_t lock;
  66. void __iomem *regs;
  67. int irq;
  68. int opened;
  69. int reset_pin;
  70. };
  71. #define get_chip(card) ((struct atmel_ac97c *)(card)->private_data)
  72. #define ac97c_writel(chip, reg, val) \
  73. __raw_writel((val), (chip)->regs + AC97C_##reg)
  74. #define ac97c_readl(chip, reg) \
  75. __raw_readl((chip)->regs + AC97C_##reg)
  76. /* This function is called by the DMA driver. */
  77. static void atmel_ac97c_dma_playback_period_done(void *arg)
  78. {
  79. struct atmel_ac97c *chip = arg;
  80. snd_pcm_period_elapsed(chip->playback_substream);
  81. }
  82. static void atmel_ac97c_dma_capture_period_done(void *arg)
  83. {
  84. struct atmel_ac97c *chip = arg;
  85. snd_pcm_period_elapsed(chip->capture_substream);
  86. }
  87. static int atmel_ac97c_prepare_dma(struct atmel_ac97c *chip,
  88. struct snd_pcm_substream *substream,
  89. enum dma_data_direction direction)
  90. {
  91. struct dma_chan *chan;
  92. struct dw_cyclic_desc *cdesc;
  93. struct snd_pcm_runtime *runtime = substream->runtime;
  94. unsigned long buffer_len, period_len;
  95. /*
  96. * We don't do DMA on "complex" transfers, i.e. with
  97. * non-halfword-aligned buffers or lengths.
  98. */
  99. if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
  100. dev_dbg(&chip->pdev->dev, "too complex transfer\n");
  101. return -EINVAL;
  102. }
  103. if (direction == DMA_TO_DEVICE)
  104. chan = chip->dma.tx_chan;
  105. else
  106. chan = chip->dma.rx_chan;
  107. buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
  108. period_len = frames_to_bytes(runtime, runtime->period_size);
  109. cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
  110. period_len, direction);
  111. if (IS_ERR(cdesc)) {
  112. dev_dbg(&chip->pdev->dev, "could not prepare cyclic DMA\n");
  113. return PTR_ERR(cdesc);
  114. }
  115. if (direction == DMA_TO_DEVICE) {
  116. cdesc->period_callback = atmel_ac97c_dma_playback_period_done;
  117. set_bit(DMA_TX_READY, &chip->flags);
  118. } else {
  119. cdesc->period_callback = atmel_ac97c_dma_capture_period_done;
  120. set_bit(DMA_RX_READY, &chip->flags);
  121. }
  122. cdesc->period_callback_param = chip;
  123. return 0;
  124. }
  125. static struct snd_pcm_hardware atmel_ac97c_hw = {
  126. .info = (SNDRV_PCM_INFO_MMAP
  127. | SNDRV_PCM_INFO_MMAP_VALID
  128. | SNDRV_PCM_INFO_INTERLEAVED
  129. | SNDRV_PCM_INFO_BLOCK_TRANSFER
  130. | SNDRV_PCM_INFO_JOINT_DUPLEX
  131. | SNDRV_PCM_INFO_RESUME
  132. | SNDRV_PCM_INFO_PAUSE),
  133. .formats = (SNDRV_PCM_FMTBIT_S16_BE
  134. | SNDRV_PCM_FMTBIT_S16_LE),
  135. .rates = (SNDRV_PCM_RATE_CONTINUOUS),
  136. .rate_min = 4000,
  137. .rate_max = 48000,
  138. .channels_min = 1,
  139. .channels_max = 2,
  140. .buffer_bytes_max = 2 * 2 * 64 * 2048,
  141. .period_bytes_min = 4096,
  142. .period_bytes_max = 4096,
  143. .periods_min = 6,
  144. .periods_max = 64,
  145. };
  146. static int atmel_ac97c_playback_open(struct snd_pcm_substream *substream)
  147. {
  148. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  149. struct snd_pcm_runtime *runtime = substream->runtime;
  150. mutex_lock(&opened_mutex);
  151. chip->opened++;
  152. runtime->hw = atmel_ac97c_hw;
  153. if (chip->cur_rate) {
  154. runtime->hw.rate_min = chip->cur_rate;
  155. runtime->hw.rate_max = chip->cur_rate;
  156. }
  157. if (chip->cur_format)
  158. runtime->hw.formats = (1ULL << chip->cur_format);
  159. mutex_unlock(&opened_mutex);
  160. chip->playback_substream = substream;
  161. return 0;
  162. }
  163. static int atmel_ac97c_capture_open(struct snd_pcm_substream *substream)
  164. {
  165. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  166. struct snd_pcm_runtime *runtime = substream->runtime;
  167. mutex_lock(&opened_mutex);
  168. chip->opened++;
  169. runtime->hw = atmel_ac97c_hw;
  170. if (chip->cur_rate) {
  171. runtime->hw.rate_min = chip->cur_rate;
  172. runtime->hw.rate_max = chip->cur_rate;
  173. }
  174. if (chip->cur_format)
  175. runtime->hw.formats = (1ULL << chip->cur_format);
  176. mutex_unlock(&opened_mutex);
  177. chip->capture_substream = substream;
  178. return 0;
  179. }
  180. static int atmel_ac97c_playback_close(struct snd_pcm_substream *substream)
  181. {
  182. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  183. mutex_lock(&opened_mutex);
  184. chip->opened--;
  185. if (!chip->opened) {
  186. chip->cur_rate = 0;
  187. chip->cur_format = 0;
  188. }
  189. mutex_unlock(&opened_mutex);
  190. chip->playback_substream = NULL;
  191. return 0;
  192. }
  193. static int atmel_ac97c_capture_close(struct snd_pcm_substream *substream)
  194. {
  195. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  196. mutex_lock(&opened_mutex);
  197. chip->opened--;
  198. if (!chip->opened) {
  199. chip->cur_rate = 0;
  200. chip->cur_format = 0;
  201. }
  202. mutex_unlock(&opened_mutex);
  203. chip->capture_substream = NULL;
  204. return 0;
  205. }
  206. static int atmel_ac97c_playback_hw_params(struct snd_pcm_substream *substream,
  207. struct snd_pcm_hw_params *hw_params)
  208. {
  209. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  210. int retval;
  211. retval = snd_pcm_lib_malloc_pages(substream,
  212. params_buffer_bytes(hw_params));
  213. if (retval < 0)
  214. return retval;
  215. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  216. if (cpu_is_at32ap7000()) {
  217. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  218. if (retval == 1)
  219. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  220. dw_dma_cyclic_free(chip->dma.tx_chan);
  221. }
  222. /* Set restrictions to params. */
  223. mutex_lock(&opened_mutex);
  224. chip->cur_rate = params_rate(hw_params);
  225. chip->cur_format = params_format(hw_params);
  226. mutex_unlock(&opened_mutex);
  227. return retval;
  228. }
  229. static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream,
  230. struct snd_pcm_hw_params *hw_params)
  231. {
  232. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  233. int retval;
  234. retval = snd_pcm_lib_malloc_pages(substream,
  235. params_buffer_bytes(hw_params));
  236. if (retval < 0)
  237. return retval;
  238. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  239. if (cpu_is_at32ap7000()) {
  240. if (retval < 0)
  241. return retval;
  242. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  243. if (retval == 1)
  244. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  245. dw_dma_cyclic_free(chip->dma.rx_chan);
  246. }
  247. /* Set restrictions to params. */
  248. mutex_lock(&opened_mutex);
  249. chip->cur_rate = params_rate(hw_params);
  250. chip->cur_format = params_format(hw_params);
  251. mutex_unlock(&opened_mutex);
  252. return retval;
  253. }
  254. static int atmel_ac97c_playback_hw_free(struct snd_pcm_substream *substream)
  255. {
  256. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  257. if (cpu_is_at32ap7000()) {
  258. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  259. dw_dma_cyclic_free(chip->dma.tx_chan);
  260. }
  261. return snd_pcm_lib_free_pages(substream);
  262. }
  263. static int atmel_ac97c_capture_hw_free(struct snd_pcm_substream *substream)
  264. {
  265. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  266. if (cpu_is_at32ap7000()) {
  267. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  268. dw_dma_cyclic_free(chip->dma.rx_chan);
  269. }
  270. return snd_pcm_lib_free_pages(substream);
  271. }
  272. static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
  273. {
  274. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  275. struct snd_pcm_runtime *runtime = substream->runtime;
  276. int block_size = frames_to_bytes(runtime, runtime->period_size);
  277. unsigned long word = ac97c_readl(chip, OCA);
  278. int retval;
  279. chip->playback_period = 0;
  280. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  281. /* assign channels to AC97C channel A */
  282. switch (runtime->channels) {
  283. case 1:
  284. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  285. break;
  286. case 2:
  287. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  288. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  289. break;
  290. default:
  291. /* TODO: support more than two channels */
  292. return -EINVAL;
  293. }
  294. ac97c_writel(chip, OCA, word);
  295. /* configure sample format and size */
  296. word = ac97c_readl(chip, CAMR);
  297. if (chip->opened <= 1)
  298. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  299. else
  300. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  301. switch (runtime->format) {
  302. case SNDRV_PCM_FORMAT_S16_LE:
  303. if (cpu_is_at32ap7000())
  304. word |= AC97C_CMR_CEM_LITTLE;
  305. break;
  306. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  307. word &= ~(AC97C_CMR_CEM_LITTLE);
  308. break;
  309. default:
  310. word = ac97c_readl(chip, OCA);
  311. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  312. ac97c_writel(chip, OCA, word);
  313. return -EINVAL;
  314. }
  315. /* Enable underrun interrupt on channel A */
  316. word |= AC97C_CSR_UNRUN;
  317. ac97c_writel(chip, CAMR, word);
  318. /* Enable channel A event interrupt */
  319. word = ac97c_readl(chip, IMR);
  320. word |= AC97C_SR_CAEVT;
  321. ac97c_writel(chip, IER, word);
  322. /* set variable rate if needed */
  323. if (runtime->rate != 48000) {
  324. word = ac97c_readl(chip, MR);
  325. word |= AC97C_MR_VRA;
  326. ac97c_writel(chip, MR, word);
  327. } else {
  328. word = ac97c_readl(chip, MR);
  329. word &= ~(AC97C_MR_VRA);
  330. ac97c_writel(chip, MR, word);
  331. }
  332. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE,
  333. runtime->rate);
  334. if (retval)
  335. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  336. runtime->rate);
  337. if (cpu_is_at32ap7000()) {
  338. if (!test_bit(DMA_TX_READY, &chip->flags))
  339. retval = atmel_ac97c_prepare_dma(chip, substream,
  340. DMA_TO_DEVICE);
  341. } else {
  342. /* Initialize and start the PDC */
  343. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
  344. writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
  345. writel(runtime->dma_addr + block_size,
  346. chip->regs + ATMEL_PDC_TNPR);
  347. writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
  348. }
  349. return retval;
  350. }
  351. static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream)
  352. {
  353. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  354. struct snd_pcm_runtime *runtime = substream->runtime;
  355. int block_size = frames_to_bytes(runtime, runtime->period_size);
  356. unsigned long word = ac97c_readl(chip, ICA);
  357. int retval;
  358. chip->capture_period = 0;
  359. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  360. /* assign channels to AC97C channel A */
  361. switch (runtime->channels) {
  362. case 1:
  363. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  364. break;
  365. case 2:
  366. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  367. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  368. break;
  369. default:
  370. /* TODO: support more than two channels */
  371. return -EINVAL;
  372. }
  373. ac97c_writel(chip, ICA, word);
  374. /* configure sample format and size */
  375. word = ac97c_readl(chip, CAMR);
  376. if (chip->opened <= 1)
  377. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  378. else
  379. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  380. switch (runtime->format) {
  381. case SNDRV_PCM_FORMAT_S16_LE:
  382. if (cpu_is_at32ap7000())
  383. word |= AC97C_CMR_CEM_LITTLE;
  384. break;
  385. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  386. word &= ~(AC97C_CMR_CEM_LITTLE);
  387. break;
  388. default:
  389. word = ac97c_readl(chip, ICA);
  390. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  391. ac97c_writel(chip, ICA, word);
  392. return -EINVAL;
  393. }
  394. /* Enable overrun interrupt on channel A */
  395. word |= AC97C_CSR_OVRUN;
  396. ac97c_writel(chip, CAMR, word);
  397. /* Enable channel A event interrupt */
  398. word = ac97c_readl(chip, IMR);
  399. word |= AC97C_SR_CAEVT;
  400. ac97c_writel(chip, IER, word);
  401. /* set variable rate if needed */
  402. if (runtime->rate != 48000) {
  403. word = ac97c_readl(chip, MR);
  404. word |= AC97C_MR_VRA;
  405. ac97c_writel(chip, MR, word);
  406. } else {
  407. word = ac97c_readl(chip, MR);
  408. word &= ~(AC97C_MR_VRA);
  409. ac97c_writel(chip, MR, word);
  410. }
  411. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE,
  412. runtime->rate);
  413. if (retval)
  414. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  415. runtime->rate);
  416. if (cpu_is_at32ap7000()) {
  417. if (!test_bit(DMA_RX_READY, &chip->flags))
  418. retval = atmel_ac97c_prepare_dma(chip, substream,
  419. DMA_FROM_DEVICE);
  420. } else {
  421. /* Initialize and start the PDC */
  422. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
  423. writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
  424. writel(runtime->dma_addr + block_size,
  425. chip->regs + ATMEL_PDC_RNPR);
  426. writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
  427. }
  428. return retval;
  429. }
  430. static int
  431. atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  432. {
  433. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  434. unsigned long camr, ptcr = 0;
  435. int retval = 0;
  436. camr = ac97c_readl(chip, CAMR);
  437. switch (cmd) {
  438. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  439. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  440. case SNDRV_PCM_TRIGGER_START:
  441. if (cpu_is_at32ap7000()) {
  442. retval = dw_dma_cyclic_start(chip->dma.tx_chan);
  443. if (retval)
  444. goto out;
  445. } else {
  446. ptcr = ATMEL_PDC_TXTEN;
  447. }
  448. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX;
  449. break;
  450. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  451. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  452. case SNDRV_PCM_TRIGGER_STOP:
  453. if (cpu_is_at32ap7000())
  454. dw_dma_cyclic_stop(chip->dma.tx_chan);
  455. else
  456. ptcr |= ATMEL_PDC_TXTDIS;
  457. if (chip->opened <= 1)
  458. camr &= ~AC97C_CMR_CENA;
  459. break;
  460. default:
  461. retval = -EINVAL;
  462. goto out;
  463. }
  464. ac97c_writel(chip, CAMR, camr);
  465. if (!cpu_is_at32ap7000())
  466. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  467. out:
  468. return retval;
  469. }
  470. static int
  471. atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  472. {
  473. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  474. unsigned long camr, ptcr = 0;
  475. int retval = 0;
  476. camr = ac97c_readl(chip, CAMR);
  477. ptcr = readl(chip->regs + ATMEL_PDC_PTSR);
  478. switch (cmd) {
  479. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  480. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  481. case SNDRV_PCM_TRIGGER_START:
  482. if (cpu_is_at32ap7000()) {
  483. retval = dw_dma_cyclic_start(chip->dma.rx_chan);
  484. if (retval)
  485. goto out;
  486. } else {
  487. ptcr = ATMEL_PDC_RXTEN;
  488. }
  489. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDRX;
  490. break;
  491. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  492. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  493. case SNDRV_PCM_TRIGGER_STOP:
  494. if (cpu_is_at32ap7000())
  495. dw_dma_cyclic_stop(chip->dma.rx_chan);
  496. else
  497. ptcr |= (ATMEL_PDC_RXTDIS);
  498. if (chip->opened <= 1)
  499. camr &= ~AC97C_CMR_CENA;
  500. break;
  501. default:
  502. retval = -EINVAL;
  503. break;
  504. }
  505. ac97c_writel(chip, CAMR, camr);
  506. if (!cpu_is_at32ap7000())
  507. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  508. out:
  509. return retval;
  510. }
  511. static snd_pcm_uframes_t
  512. atmel_ac97c_playback_pointer(struct snd_pcm_substream *substream)
  513. {
  514. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  515. struct snd_pcm_runtime *runtime = substream->runtime;
  516. snd_pcm_uframes_t frames;
  517. unsigned long bytes;
  518. if (cpu_is_at32ap7000())
  519. bytes = dw_dma_get_src_addr(chip->dma.tx_chan);
  520. else
  521. bytes = readl(chip->regs + ATMEL_PDC_TPR);
  522. bytes -= runtime->dma_addr;
  523. frames = bytes_to_frames(runtime, bytes);
  524. if (frames >= runtime->buffer_size)
  525. frames -= runtime->buffer_size;
  526. return frames;
  527. }
  528. static snd_pcm_uframes_t
  529. atmel_ac97c_capture_pointer(struct snd_pcm_substream *substream)
  530. {
  531. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  532. struct snd_pcm_runtime *runtime = substream->runtime;
  533. snd_pcm_uframes_t frames;
  534. unsigned long bytes;
  535. if (cpu_is_at32ap7000())
  536. bytes = dw_dma_get_dst_addr(chip->dma.rx_chan);
  537. else
  538. bytes = readl(chip->regs + ATMEL_PDC_RPR);
  539. bytes -= runtime->dma_addr;
  540. frames = bytes_to_frames(runtime, bytes);
  541. if (frames >= runtime->buffer_size)
  542. frames -= runtime->buffer_size;
  543. return frames;
  544. }
  545. static struct snd_pcm_ops atmel_ac97_playback_ops = {
  546. .open = atmel_ac97c_playback_open,
  547. .close = atmel_ac97c_playback_close,
  548. .ioctl = snd_pcm_lib_ioctl,
  549. .hw_params = atmel_ac97c_playback_hw_params,
  550. .hw_free = atmel_ac97c_playback_hw_free,
  551. .prepare = atmel_ac97c_playback_prepare,
  552. .trigger = atmel_ac97c_playback_trigger,
  553. .pointer = atmel_ac97c_playback_pointer,
  554. };
  555. static struct snd_pcm_ops atmel_ac97_capture_ops = {
  556. .open = atmel_ac97c_capture_open,
  557. .close = atmel_ac97c_capture_close,
  558. .ioctl = snd_pcm_lib_ioctl,
  559. .hw_params = atmel_ac97c_capture_hw_params,
  560. .hw_free = atmel_ac97c_capture_hw_free,
  561. .prepare = atmel_ac97c_capture_prepare,
  562. .trigger = atmel_ac97c_capture_trigger,
  563. .pointer = atmel_ac97c_capture_pointer,
  564. };
  565. static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev)
  566. {
  567. struct atmel_ac97c *chip = (struct atmel_ac97c *)dev;
  568. irqreturn_t retval = IRQ_NONE;
  569. u32 sr = ac97c_readl(chip, SR);
  570. u32 casr = ac97c_readl(chip, CASR);
  571. u32 cosr = ac97c_readl(chip, COSR);
  572. u32 camr = ac97c_readl(chip, CAMR);
  573. if (sr & AC97C_SR_CAEVT) {
  574. struct snd_pcm_runtime *runtime;
  575. int offset, next_period, block_size;
  576. dev_dbg(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
  577. casr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  578. casr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  579. casr & AC97C_CSR_UNRUN ? " UNRUN" : "",
  580. casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  581. casr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  582. !casr ? " NONE" : "");
  583. if (!cpu_is_at32ap7000()) {
  584. if ((casr & camr) & AC97C_CSR_ENDTX) {
  585. runtime = chip->playback_substream->runtime;
  586. block_size = frames_to_bytes(runtime,
  587. runtime->period_size);
  588. chip->playback_period++;
  589. if (chip->playback_period == runtime->periods)
  590. chip->playback_period = 0;
  591. next_period = chip->playback_period + 1;
  592. if (next_period == runtime->periods)
  593. next_period = 0;
  594. offset = block_size * next_period;
  595. writel(runtime->dma_addr + offset,
  596. chip->regs + ATMEL_PDC_TNPR);
  597. writel(block_size / 2,
  598. chip->regs + ATMEL_PDC_TNCR);
  599. snd_pcm_period_elapsed(
  600. chip->playback_substream);
  601. }
  602. if ((casr & camr) & AC97C_CSR_ENDRX) {
  603. runtime = chip->capture_substream->runtime;
  604. block_size = frames_to_bytes(runtime,
  605. runtime->period_size);
  606. chip->capture_period++;
  607. if (chip->capture_period == runtime->periods)
  608. chip->capture_period = 0;
  609. next_period = chip->capture_period + 1;
  610. if (next_period == runtime->periods)
  611. next_period = 0;
  612. offset = block_size * next_period;
  613. writel(runtime->dma_addr + offset,
  614. chip->regs + ATMEL_PDC_RNPR);
  615. writel(block_size / 2,
  616. chip->regs + ATMEL_PDC_RNCR);
  617. snd_pcm_period_elapsed(chip->capture_substream);
  618. }
  619. }
  620. retval = IRQ_HANDLED;
  621. }
  622. if (sr & AC97C_SR_COEVT) {
  623. dev_info(&chip->pdev->dev, "codec channel event%s%s%s%s%s\n",
  624. cosr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  625. cosr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  626. cosr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  627. cosr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  628. !cosr ? " NONE" : "");
  629. retval = IRQ_HANDLED;
  630. }
  631. if (retval == IRQ_NONE) {
  632. dev_err(&chip->pdev->dev, "spurious interrupt sr 0x%08x "
  633. "casr 0x%08x cosr 0x%08x\n", sr, casr, cosr);
  634. }
  635. return retval;
  636. }
  637. static struct ac97_pcm at91_ac97_pcm_defs[] __devinitdata = {
  638. /* Playback */
  639. {
  640. .exclusive = 1,
  641. .r = { {
  642. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  643. | (1 << AC97_SLOT_PCM_RIGHT)),
  644. } },
  645. },
  646. /* PCM in */
  647. {
  648. .stream = 1,
  649. .exclusive = 1,
  650. .r = { {
  651. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  652. | (1 << AC97_SLOT_PCM_RIGHT)),
  653. } }
  654. },
  655. /* Mic in */
  656. {
  657. .stream = 1,
  658. .exclusive = 1,
  659. .r = { {
  660. .slots = (1<<AC97_SLOT_MIC),
  661. } }
  662. },
  663. };
  664. static int __devinit atmel_ac97c_pcm_new(struct atmel_ac97c *chip)
  665. {
  666. struct snd_pcm *pcm;
  667. struct snd_pcm_hardware hw = atmel_ac97c_hw;
  668. int capture, playback, retval, err;
  669. capture = test_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  670. playback = test_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  671. if (!cpu_is_at32ap7000()) {
  672. err = snd_ac97_pcm_assign(chip->ac97_bus,
  673. ARRAY_SIZE(at91_ac97_pcm_defs),
  674. at91_ac97_pcm_defs);
  675. if (err)
  676. return err;
  677. }
  678. retval = snd_pcm_new(chip->card, chip->card->shortname,
  679. chip->pdev->id, playback, capture, &pcm);
  680. if (retval)
  681. return retval;
  682. if (capture)
  683. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  684. &atmel_ac97_capture_ops);
  685. if (playback)
  686. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  687. &atmel_ac97_playback_ops);
  688. retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  689. &chip->pdev->dev, hw.periods_min * hw.period_bytes_min,
  690. hw.buffer_bytes_max);
  691. if (retval)
  692. return retval;
  693. pcm->private_data = chip;
  694. pcm->info_flags = 0;
  695. strcpy(pcm->name, chip->card->shortname);
  696. chip->pcm = pcm;
  697. return 0;
  698. }
  699. static int atmel_ac97c_mixer_new(struct atmel_ac97c *chip)
  700. {
  701. struct snd_ac97_template template;
  702. memset(&template, 0, sizeof(template));
  703. template.private_data = chip;
  704. return snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
  705. }
  706. static void atmel_ac97c_write(struct snd_ac97 *ac97, unsigned short reg,
  707. unsigned short val)
  708. {
  709. struct atmel_ac97c *chip = get_chip(ac97);
  710. unsigned long word;
  711. int timeout = 40;
  712. word = (reg & 0x7f) << 16 | val;
  713. do {
  714. if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
  715. ac97c_writel(chip, COTHR, word);
  716. return;
  717. }
  718. udelay(1);
  719. } while (--timeout);
  720. dev_dbg(&chip->pdev->dev, "codec write timeout\n");
  721. }
  722. static unsigned short atmel_ac97c_read(struct snd_ac97 *ac97,
  723. unsigned short reg)
  724. {
  725. struct atmel_ac97c *chip = get_chip(ac97);
  726. unsigned long word;
  727. int timeout = 40;
  728. int write = 10;
  729. word = (0x80 | (reg & 0x7f)) << 16;
  730. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
  731. ac97c_readl(chip, CORHR);
  732. retry_write:
  733. timeout = 40;
  734. do {
  735. if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
  736. ac97c_writel(chip, COTHR, word);
  737. goto read_reg;
  738. }
  739. udelay(10);
  740. } while (--timeout);
  741. if (!--write)
  742. goto timed_out;
  743. goto retry_write;
  744. read_reg:
  745. do {
  746. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
  747. unsigned short val = ac97c_readl(chip, CORHR);
  748. return val;
  749. }
  750. udelay(10);
  751. } while (--timeout);
  752. if (!--write)
  753. goto timed_out;
  754. goto retry_write;
  755. timed_out:
  756. dev_dbg(&chip->pdev->dev, "codec read timeout\n");
  757. return 0xffff;
  758. }
  759. static bool filter(struct dma_chan *chan, void *slave)
  760. {
  761. struct dw_dma_slave *dws = slave;
  762. if (dws->dma_dev == chan->device->dev) {
  763. chan->private = dws;
  764. return true;
  765. } else
  766. return false;
  767. }
  768. static void atmel_ac97c_reset(struct atmel_ac97c *chip)
  769. {
  770. ac97c_writel(chip, MR, 0);
  771. ac97c_writel(chip, MR, AC97C_MR_ENA);
  772. ac97c_writel(chip, CAMR, 0);
  773. ac97c_writel(chip, COMR, 0);
  774. if (gpio_is_valid(chip->reset_pin)) {
  775. gpio_set_value(chip->reset_pin, 0);
  776. /* AC97 v2.2 specifications says minimum 1 us. */
  777. udelay(2);
  778. gpio_set_value(chip->reset_pin, 1);
  779. }
  780. }
  781. static int __devinit atmel_ac97c_probe(struct platform_device *pdev)
  782. {
  783. struct snd_card *card;
  784. struct atmel_ac97c *chip;
  785. struct resource *regs;
  786. struct ac97c_platform_data *pdata;
  787. struct clk *pclk;
  788. static struct snd_ac97_bus_ops ops = {
  789. .write = atmel_ac97c_write,
  790. .read = atmel_ac97c_read,
  791. };
  792. int retval;
  793. int irq;
  794. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  795. if (!regs) {
  796. dev_dbg(&pdev->dev, "no memory resource\n");
  797. return -ENXIO;
  798. }
  799. pdata = pdev->dev.platform_data;
  800. if (!pdata) {
  801. dev_dbg(&pdev->dev, "no platform data\n");
  802. return -ENXIO;
  803. }
  804. irq = platform_get_irq(pdev, 0);
  805. if (irq < 0) {
  806. dev_dbg(&pdev->dev, "could not get irq\n");
  807. return -ENXIO;
  808. }
  809. if (cpu_is_at32ap7000()) {
  810. pclk = clk_get(&pdev->dev, "pclk");
  811. } else {
  812. pclk = clk_get(&pdev->dev, "ac97_clk");
  813. }
  814. if (IS_ERR(pclk)) {
  815. dev_dbg(&pdev->dev, "no peripheral clock\n");
  816. return PTR_ERR(pclk);
  817. }
  818. clk_enable(pclk);
  819. retval = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  820. THIS_MODULE, sizeof(struct atmel_ac97c), &card);
  821. if (retval) {
  822. dev_dbg(&pdev->dev, "could not create sound card device\n");
  823. goto err_snd_card_new;
  824. }
  825. chip = get_chip(card);
  826. retval = request_irq(irq, atmel_ac97c_interrupt, 0, "AC97C", chip);
  827. if (retval) {
  828. dev_dbg(&pdev->dev, "unable to request irq %d\n", irq);
  829. goto err_request_irq;
  830. }
  831. chip->irq = irq;
  832. spin_lock_init(&chip->lock);
  833. strcpy(card->driver, "Atmel AC97C");
  834. strcpy(card->shortname, "Atmel AC97C");
  835. sprintf(card->longname, "Atmel AC97 controller");
  836. chip->card = card;
  837. chip->pclk = pclk;
  838. chip->pdev = pdev;
  839. chip->regs = ioremap(regs->start, resource_size(regs));
  840. if (!chip->regs) {
  841. dev_dbg(&pdev->dev, "could not remap register memory\n");
  842. goto err_ioremap;
  843. }
  844. if (gpio_is_valid(pdata->reset_pin)) {
  845. if (gpio_request(pdata->reset_pin, "reset_pin")) {
  846. dev_dbg(&pdev->dev, "reset pin not available\n");
  847. chip->reset_pin = -ENODEV;
  848. } else {
  849. gpio_direction_output(pdata->reset_pin, 1);
  850. chip->reset_pin = pdata->reset_pin;
  851. }
  852. }
  853. snd_card_set_dev(card, &pdev->dev);
  854. atmel_ac97c_reset(chip);
  855. /* Enable overrun interrupt from codec channel */
  856. ac97c_writel(chip, COMR, AC97C_CSR_OVRUN);
  857. ac97c_writel(chip, IER, ac97c_readl(chip, IMR) | AC97C_SR_COEVT);
  858. retval = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
  859. if (retval) {
  860. dev_dbg(&pdev->dev, "could not register on ac97 bus\n");
  861. goto err_ac97_bus;
  862. }
  863. retval = atmel_ac97c_mixer_new(chip);
  864. if (retval) {
  865. dev_dbg(&pdev->dev, "could not register ac97 mixer\n");
  866. goto err_ac97_bus;
  867. }
  868. if (cpu_is_at32ap7000()) {
  869. if (pdata->rx_dws.dma_dev) {
  870. struct dw_dma_slave *dws = &pdata->rx_dws;
  871. dma_cap_mask_t mask;
  872. dws->rx_reg = regs->start + AC97C_CARHR + 2;
  873. dma_cap_zero(mask);
  874. dma_cap_set(DMA_SLAVE, mask);
  875. chip->dma.rx_chan = dma_request_channel(mask, filter,
  876. dws);
  877. dev_info(&chip->pdev->dev, "using %s for DMA RX\n",
  878. dev_name(&chip->dma.rx_chan->dev->device));
  879. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  880. }
  881. if (pdata->tx_dws.dma_dev) {
  882. struct dw_dma_slave *dws = &pdata->tx_dws;
  883. dma_cap_mask_t mask;
  884. dws->tx_reg = regs->start + AC97C_CATHR + 2;
  885. dma_cap_zero(mask);
  886. dma_cap_set(DMA_SLAVE, mask);
  887. chip->dma.tx_chan = dma_request_channel(mask, filter,
  888. dws);
  889. dev_info(&chip->pdev->dev, "using %s for DMA TX\n",
  890. dev_name(&chip->dma.tx_chan->dev->device));
  891. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  892. }
  893. if (!test_bit(DMA_RX_CHAN_PRESENT, &chip->flags) &&
  894. !test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) {
  895. dev_dbg(&pdev->dev, "DMA not available\n");
  896. retval = -ENODEV;
  897. goto err_dma;
  898. }
  899. } else {
  900. /* Just pretend that we have DMA channel(for at91 i is actually
  901. * the PDC) */
  902. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  903. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  904. }
  905. retval = atmel_ac97c_pcm_new(chip);
  906. if (retval) {
  907. dev_dbg(&pdev->dev, "could not register ac97 pcm device\n");
  908. goto err_dma;
  909. }
  910. retval = snd_card_register(card);
  911. if (retval) {
  912. dev_dbg(&pdev->dev, "could not register sound card\n");
  913. goto err_dma;
  914. }
  915. platform_set_drvdata(pdev, card);
  916. dev_info(&pdev->dev, "Atmel AC97 controller at 0x%p, irq = %d\n",
  917. chip->regs, irq);
  918. return 0;
  919. err_dma:
  920. if (cpu_is_at32ap7000()) {
  921. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  922. dma_release_channel(chip->dma.rx_chan);
  923. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  924. dma_release_channel(chip->dma.tx_chan);
  925. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  926. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  927. chip->dma.rx_chan = NULL;
  928. chip->dma.tx_chan = NULL;
  929. }
  930. err_ac97_bus:
  931. snd_card_set_dev(card, NULL);
  932. if (gpio_is_valid(chip->reset_pin))
  933. gpio_free(chip->reset_pin);
  934. iounmap(chip->regs);
  935. err_ioremap:
  936. free_irq(irq, chip);
  937. err_request_irq:
  938. snd_card_free(card);
  939. err_snd_card_new:
  940. clk_disable(pclk);
  941. clk_put(pclk);
  942. return retval;
  943. }
  944. #ifdef CONFIG_PM
  945. static int atmel_ac97c_suspend(struct platform_device *pdev, pm_message_t msg)
  946. {
  947. struct snd_card *card = platform_get_drvdata(pdev);
  948. struct atmel_ac97c *chip = card->private_data;
  949. if (cpu_is_at32ap7000()) {
  950. if (test_bit(DMA_RX_READY, &chip->flags))
  951. dw_dma_cyclic_stop(chip->dma.rx_chan);
  952. if (test_bit(DMA_TX_READY, &chip->flags))
  953. dw_dma_cyclic_stop(chip->dma.tx_chan);
  954. }
  955. clk_disable(chip->pclk);
  956. return 0;
  957. }
  958. static int atmel_ac97c_resume(struct platform_device *pdev)
  959. {
  960. struct snd_card *card = platform_get_drvdata(pdev);
  961. struct atmel_ac97c *chip = card->private_data;
  962. clk_enable(chip->pclk);
  963. if (cpu_is_at32ap7000()) {
  964. if (test_bit(DMA_RX_READY, &chip->flags))
  965. dw_dma_cyclic_start(chip->dma.rx_chan);
  966. if (test_bit(DMA_TX_READY, &chip->flags))
  967. dw_dma_cyclic_start(chip->dma.tx_chan);
  968. }
  969. return 0;
  970. }
  971. #else
  972. #define atmel_ac97c_suspend NULL
  973. #define atmel_ac97c_resume NULL
  974. #endif
  975. static int __devexit atmel_ac97c_remove(struct platform_device *pdev)
  976. {
  977. struct snd_card *card = platform_get_drvdata(pdev);
  978. struct atmel_ac97c *chip = get_chip(card);
  979. if (gpio_is_valid(chip->reset_pin))
  980. gpio_free(chip->reset_pin);
  981. ac97c_writel(chip, CAMR, 0);
  982. ac97c_writel(chip, COMR, 0);
  983. ac97c_writel(chip, MR, 0);
  984. clk_disable(chip->pclk);
  985. clk_put(chip->pclk);
  986. iounmap(chip->regs);
  987. free_irq(chip->irq, chip);
  988. if (cpu_is_at32ap7000()) {
  989. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  990. dma_release_channel(chip->dma.rx_chan);
  991. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  992. dma_release_channel(chip->dma.tx_chan);
  993. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  994. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  995. chip->dma.rx_chan = NULL;
  996. chip->dma.tx_chan = NULL;
  997. }
  998. snd_card_set_dev(card, NULL);
  999. snd_card_free(card);
  1000. platform_set_drvdata(pdev, NULL);
  1001. return 0;
  1002. }
  1003. static struct platform_driver atmel_ac97c_driver = {
  1004. .remove = __devexit_p(atmel_ac97c_remove),
  1005. .driver = {
  1006. .name = "atmel_ac97c",
  1007. },
  1008. .suspend = atmel_ac97c_suspend,
  1009. .resume = atmel_ac97c_resume,
  1010. };
  1011. static int __init atmel_ac97c_init(void)
  1012. {
  1013. return platform_driver_probe(&atmel_ac97c_driver,
  1014. atmel_ac97c_probe);
  1015. }
  1016. module_init(atmel_ac97c_init);
  1017. static void __exit atmel_ac97c_exit(void)
  1018. {
  1019. platform_driver_unregister(&atmel_ac97c_driver);
  1020. }
  1021. module_exit(atmel_ac97c_exit);
  1022. MODULE_LICENSE("GPL");
  1023. MODULE_DESCRIPTION("Driver for Atmel AC97 controller");
  1024. MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");