/arch/arm/mm/mmu.c
C | 1052 lines | 718 code | 120 blank | 214 comment | 120 complexity | df173adcdacb2f2204507bba5e110a08 MD5 | raw file
- /*
- * linux/arch/arm/mm/mmu.c
- *
- * Copyright (C) 1995-2005 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
- #include <linux/module.h>
- #include <linux/kernel.h>
- #include <linux/errno.h>
- #include <linux/init.h>
- #include <linux/mman.h>
- #include <linux/nodemask.h>
- #include <linux/memblock.h>
- #include <linux/fs.h>
- #include <asm/cputype.h>
- #include <asm/sections.h>
- #include <asm/cachetype.h>
- #include <asm/setup.h>
- #include <asm/sizes.h>
- #include <asm/smp_plat.h>
- #include <asm/tlb.h>
- #include <asm/highmem.h>
- #include <asm/traps.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include "mm.h"
- /*
- * empty_zero_page is a special page that is used for
- * zero-initialized data and COW.
- */
- struct page *empty_zero_page;
- EXPORT_SYMBOL(empty_zero_page);
- /*
- * The pmd table for the upper-most set of pages.
- */
- pmd_t *top_pmd;
- #define CPOLICY_UNCACHED 0
- #define CPOLICY_BUFFERED 1
- #define CPOLICY_WRITETHROUGH 2
- #define CPOLICY_WRITEBACK 3
- #define CPOLICY_WRITEALLOC 4
- static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
- static unsigned int ecc_mask __initdata = 0;
- pgprot_t pgprot_user;
- pgprot_t pgprot_kernel;
- EXPORT_SYMBOL(pgprot_user);
- EXPORT_SYMBOL(pgprot_kernel);
- struct cachepolicy {
- const char policy[16];
- unsigned int cr_mask;
- unsigned int pmd;
- pteval_t pte;
- };
- static struct cachepolicy cache_policies[] __initdata = {
- {
- .policy = "uncached",
- .cr_mask = CR_W|CR_C,
- .pmd = PMD_SECT_UNCACHED,
- .pte = L_PTE_MT_UNCACHED,
- }, {
- .policy = "buffered",
- .cr_mask = CR_C,
- .pmd = PMD_SECT_BUFFERED,
- .pte = L_PTE_MT_BUFFERABLE,
- }, {
- .policy = "writethrough",
- .cr_mask = 0,
- .pmd = PMD_SECT_WT,
- .pte = L_PTE_MT_WRITETHROUGH,
- }, {
- .policy = "writeback",
- .cr_mask = 0,
- .pmd = PMD_SECT_WB,
- .pte = L_PTE_MT_WRITEBACK,
- }, {
- .policy = "writealloc",
- .cr_mask = 0,
- .pmd = PMD_SECT_WBWA,
- .pte = L_PTE_MT_WRITEALLOC,
- }
- };
- /*
- * These are useful for identifying cache coherency
- * problems by allowing the cache or the cache and
- * writebuffer to be turned off. (Note: the write
- * buffer should not be on and the cache off).
- */
- static int __init early_cachepolicy(char *p)
- {
- int i;
- for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
- int len = strlen(cache_policies[i].policy);
- if (memcmp(p, cache_policies[i].policy, len) == 0) {
- cachepolicy = i;
- cr_alignment &= ~cache_policies[i].cr_mask;
- cr_no_alignment &= ~cache_policies[i].cr_mask;
- break;
- }
- }
- if (i == ARRAY_SIZE(cache_policies))
- printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
- /*
- * This restriction is partly to do with the way we boot; it is
- * unpredictable to have memory mapped using two different sets of
- * memory attributes (shared, type, and cache attribs). We can not
- * change these attributes once the initial assembly has setup the
- * page tables.
- */
- if (cpu_architecture() >= CPU_ARCH_ARMv6) {
- printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
- cachepolicy = CPOLICY_WRITEBACK;
- }
- flush_cache_all();
- set_cr(cr_alignment);
- return 0;
- }
- early_param("cachepolicy", early_cachepolicy);
- static int __init early_nocache(char *__unused)
- {
- char *p = "buffered";
- printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
- early_cachepolicy(p);
- return 0;
- }
- early_param("nocache", early_nocache);
- static int __init early_nowrite(char *__unused)
- {
- char *p = "uncached";
- printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
- early_cachepolicy(p);
- return 0;
- }
- early_param("nowb", early_nowrite);
- static int __init early_ecc(char *p)
- {
- if (memcmp(p, "on", 2) == 0)
- ecc_mask = PMD_PROTECTION;
- else if (memcmp(p, "off", 3) == 0)
- ecc_mask = 0;
- return 0;
- }
- early_param("ecc", early_ecc);
- static int __init noalign_setup(char *__unused)
- {
- cr_alignment &= ~CR_A;
- cr_no_alignment &= ~CR_A;
- set_cr(cr_alignment);
- return 1;
- }
- __setup("noalign", noalign_setup);
- #ifndef CONFIG_SMP
- void adjust_cr(unsigned long mask, unsigned long set)
- {
- unsigned long flags;
- mask &= ~CR_A;
- set &= mask;
- local_irq_save(flags);
- cr_no_alignment = (cr_no_alignment & ~mask) | set;
- cr_alignment = (cr_alignment & ~mask) | set;
- set_cr((get_cr() & ~mask) | set);
- local_irq_restore(flags);
- }
- #endif
- #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
- #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
- static struct mem_type mem_types[] = {
- [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
- .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
- L_PTE_SHARED,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
- .domain = DOMAIN_IO,
- },
- [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
- .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PROT_SECT_DEVICE,
- .domain = DOMAIN_IO,
- },
- [MT_DEVICE_CACHED] = { /* ioremap_cached */
- .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
- .domain = DOMAIN_IO,
- },
- [MT_DEVICE_WC] = { /* ioremap_wc */
- .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PROT_SECT_DEVICE,
- .domain = DOMAIN_IO,
- },
- [MT_UNCACHED] = {
- .prot_pte = PROT_PTE_DEVICE,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
- .domain = DOMAIN_IO,
- },
- [MT_CACHECLEAN] = {
- .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
- .domain = DOMAIN_KERNEL,
- },
- [MT_MINICLEAN] = {
- .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
- .domain = DOMAIN_KERNEL,
- },
- [MT_LOW_VECTORS] = {
- .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
- L_PTE_RDONLY,
- .prot_l1 = PMD_TYPE_TABLE,
- .domain = DOMAIN_USER,
- },
- [MT_HIGH_VECTORS] = {
- .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
- L_PTE_USER | L_PTE_RDONLY,
- .prot_l1 = PMD_TYPE_TABLE,
- .domain = DOMAIN_USER,
- },
- [MT_MEMORY] = {
- .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
- .domain = DOMAIN_KERNEL,
- },
- [MT_ROM] = {
- .prot_sect = PMD_TYPE_SECT,
- .domain = DOMAIN_KERNEL,
- },
- [MT_MEMORY_NONCACHED] = {
- .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
- L_PTE_MT_BUFFERABLE,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
- .domain = DOMAIN_KERNEL,
- },
- [MT_MEMORY_DTCM] = {
- .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
- L_PTE_XN,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
- .domain = DOMAIN_KERNEL,
- },
- [MT_MEMORY_ITCM] = {
- .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
- .prot_l1 = PMD_TYPE_TABLE,
- .domain = DOMAIN_KERNEL,
- },
- };
- const struct mem_type *get_mem_type(unsigned int type)
- {
- return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
- }
- EXPORT_SYMBOL(get_mem_type);
- /*
- * Adjust the PMD section entries according to the CPU in use.
- */
- static void __init build_mem_type_table(void)
- {
- struct cachepolicy *cp;
- unsigned int cr = get_cr();
- unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
- int cpu_arch = cpu_architecture();
- int i;
- if (cpu_arch < CPU_ARCH_ARMv6) {
- #if defined(CONFIG_CPU_DCACHE_DISABLE)
- if (cachepolicy > CPOLICY_BUFFERED)
- cachepolicy = CPOLICY_BUFFERED;
- #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
- if (cachepolicy > CPOLICY_WRITETHROUGH)
- cachepolicy = CPOLICY_WRITETHROUGH;
- #endif
- }
- if (cpu_arch < CPU_ARCH_ARMv5) {
- if (cachepolicy >= CPOLICY_WRITEALLOC)
- cachepolicy = CPOLICY_WRITEBACK;
- ecc_mask = 0;
- }
- if (is_smp())
- cachepolicy = CPOLICY_WRITEALLOC;
- /*
- * Strip out features not present on earlier architectures.
- * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
- * without extended page tables don't have the 'Shared' bit.
- */
- if (cpu_arch < CPU_ARCH_ARMv5)
- for (i = 0; i < ARRAY_SIZE(mem_types); i++)
- mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
- if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
- for (i = 0; i < ARRAY_SIZE(mem_types); i++)
- mem_types[i].prot_sect &= ~PMD_SECT_S;
- /*
- * ARMv5 and lower, bit 4 must be set for page tables (was: cache
- * "update-able on write" bit on ARM610). However, Xscale and
- * Xscale3 require this bit to be cleared.
- */
- if (cpu_is_xscale() || cpu_is_xsc3()) {
- for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
- mem_types[i].prot_sect &= ~PMD_BIT4;
- mem_types[i].prot_l1 &= ~PMD_BIT4;
- }
- } else if (cpu_arch < CPU_ARCH_ARMv6) {
- for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
- if (mem_types[i].prot_l1)
- mem_types[i].prot_l1 |= PMD_BIT4;
- if (mem_types[i].prot_sect)
- mem_types[i].prot_sect |= PMD_BIT4;
- }
- }
- /*
- * Mark the device areas according to the CPU/architecture.
- */
- if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
- if (!cpu_is_xsc3()) {
- /*
- * Mark device regions on ARMv6+ as execute-never
- * to prevent speculative instruction fetches.
- */
- mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
- mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
- mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
- }
- if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
- /*
- * For ARMv7 with TEX remapping,
- * - shared device is SXCB=1100
- * - nonshared device is SXCB=0100
- * - write combine device mem is SXCB=0001
- * (Uncached Normal memory)
- */
- mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
- mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
- } else if (cpu_is_xsc3()) {
- /*
- * For Xscale3,
- * - shared device is TEXCB=00101
- * - nonshared device is TEXCB=01000
- * - write combine device mem is TEXCB=00100
- * (Inner/Outer Uncacheable in xsc3 parlance)
- */
- mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
- mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
- } else {
- /*
- * For ARMv6 and ARMv7 without TEX remapping,
- * - shared device is TEXCB=00001
- * - nonshared device is TEXCB=01000
- * - write combine device mem is TEXCB=00100
- * (Uncached Normal in ARMv6 parlance).
- */
- mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
- mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
- }
- } else {
- /*
- * On others, write combining is "Uncached/Buffered"
- */
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
- }
- /*
- * Now deal with the memory-type mappings
- */
- cp = &cache_policies[cachepolicy];
- vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
- /*
- * Only use write-through for non-SMP systems
- */
- if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
- vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
- /*
- * Enable CPU-specific coherency if supported.
- * (Only available on XSC3 at the moment.)
- */
- if (arch_is_coherent() && cpu_is_xsc3()) {
- mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
- mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
- mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
- mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
- }
- /*
- * ARMv6 and above have extended page tables.
- */
- if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
- /*
- * Mark cache clean areas and XIP ROM read only
- * from SVC mode and no access from userspace.
- */
- mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
- mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
- mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
- if (is_smp()) {
- /*
- * Mark memory with the "shared" attribute
- * for SMP systems
- */
- user_pgprot |= L_PTE_SHARED;
- kern_pgprot |= L_PTE_SHARED;
- vecs_pgprot |= L_PTE_SHARED;
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
- mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
- mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
- mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
- mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
- mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
- mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
- mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
- }
- }
- /*
- * Non-cacheable Normal - intended for memory areas that must
- * not cause dirty cache line writebacks when used
- */
- if (cpu_arch >= CPU_ARCH_ARMv6) {
- if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
- /* Non-cacheable Normal is XCB = 001 */
- mem_types[MT_MEMORY_NONCACHED].prot_sect |=
- PMD_SECT_BUFFERED;
- } else {
- /* For both ARMv6 and non-TEX-remapping ARMv7 */
- mem_types[MT_MEMORY_NONCACHED].prot_sect |=
- PMD_SECT_TEX(1);
- }
- } else {
- mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
- }
- for (i = 0; i < 16; i++) {
- unsigned long v = pgprot_val(protection_map[i]);
- protection_map[i] = __pgprot(v | user_pgprot);
- }
- mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
- mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
- pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
- pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
- L_PTE_DIRTY | kern_pgprot);
- mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
- mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
- mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
- mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
- mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
- mem_types[MT_ROM].prot_sect |= cp->pmd;
- switch (cp->pmd) {
- case PMD_SECT_WT:
- mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
- break;
- case PMD_SECT_WB:
- case PMD_SECT_WBWA:
- mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
- break;
- }
- printk("Memory policy: ECC %sabled, Data cache %s\n",
- ecc_mask ? "en" : "dis", cp->policy);
- for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
- struct mem_type *t = &mem_types[i];
- if (t->prot_l1)
- t->prot_l1 |= PMD_DOMAIN(t->domain);
- if (t->prot_sect)
- t->prot_sect |= PMD_DOMAIN(t->domain);
- }
- }
- #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
- pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
- unsigned long size, pgprot_t vma_prot)
- {
- if (!pfn_valid(pfn))
- return pgprot_noncached(vma_prot);
- else if (file->f_flags & O_SYNC)
- return pgprot_writecombine(vma_prot);
- return vma_prot;
- }
- EXPORT_SYMBOL(phys_mem_access_prot);
- #endif
- #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
- static void __init *early_alloc(unsigned long sz)
- {
- void *ptr = __va(memblock_alloc(sz, sz));
- memset(ptr, 0, sz);
- return ptr;
- }
- static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
- {
- if (pmd_none(*pmd)) {
- pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
- __pmd_populate(pmd, __pa(pte), prot);
- }
- BUG_ON(pmd_bad(*pmd));
- return pte_offset_kernel(pmd, addr);
- }
- static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
- unsigned long end, unsigned long pfn,
- const struct mem_type *type)
- {
- pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
- do {
- set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
- pfn++;
- } while (pte++, addr += PAGE_SIZE, addr != end);
- }
- static void __init alloc_init_section(pud_t *pud, unsigned long addr,
- unsigned long end, phys_addr_t phys,
- const struct mem_type *type)
- {
- pmd_t *pmd = pmd_offset(pud, addr);
- /*
- * Try a section mapping - end, addr and phys must all be aligned
- * to a section boundary. Note that PMDs refer to the individual
- * L1 entries, whereas PGDs refer to a group of L1 entries making
- * up one logical pointer to an L2 table.
- */
- if (((addr | end | phys) & ~SECTION_MASK) == 0) {
- pmd_t *p = pmd;
- if (addr & SECTION_SIZE)
- pmd++;
- do {
- *pmd = __pmd(phys | type->prot_sect);
- phys += SECTION_SIZE;
- } while (pmd++, addr += SECTION_SIZE, addr != end);
- flush_pmd_entry(p);
- } else {
- /*
- * No need to loop; pte's aren't interested in the
- * individual L1 entries.
- */
- alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
- }
- }
- static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
- unsigned long phys, const struct mem_type *type)
- {
- pud_t *pud = pud_offset(pgd, addr);
- unsigned long next;
- do {
- next = pud_addr_end(addr, end);
- alloc_init_section(pud, addr, next, phys, type);
- phys += next - addr;
- } while (pud++, addr = next, addr != end);
- }
- static void __init create_36bit_mapping(struct map_desc *md,
- const struct mem_type *type)
- {
- unsigned long addr, length, end;
- phys_addr_t phys;
- pgd_t *pgd;
- addr = md->virtual;
- phys = __pfn_to_phys(md->pfn);
- length = PAGE_ALIGN(md->length);
- if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
- printk(KERN_ERR "MM: CPU does not support supersection "
- "mapping for 0x%08llx at 0x%08lx\n",
- (long long)__pfn_to_phys((u64)md->pfn), addr);
- return;
- }
- /* N.B. ARMv6 supersections are only defined to work with domain 0.
- * Since domain assignments can in fact be arbitrary, the
- * 'domain == 0' check below is required to insure that ARMv6
- * supersections are only allocated for domain 0 regardless
- * of the actual domain assignments in use.
- */
- if (type->domain) {
- printk(KERN_ERR "MM: invalid domain in supersection "
- "mapping for 0x%08llx at 0x%08lx\n",
- (long long)__pfn_to_phys((u64)md->pfn), addr);
- return;
- }
- if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
- printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
- " at 0x%08lx invalid alignment\n",
- (long long)__pfn_to_phys((u64)md->pfn), addr);
- return;
- }
- /*
- * Shift bits [35:32] of address into bits [23:20] of PMD
- * (See ARMv6 spec).
- */
- phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
- pgd = pgd_offset_k(addr);
- end = addr + length;
- do {
- pud_t *pud = pud_offset(pgd, addr);
- pmd_t *pmd = pmd_offset(pud, addr);
- int i;
- for (i = 0; i < 16; i++)
- *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
- addr += SUPERSECTION_SIZE;
- phys += SUPERSECTION_SIZE;
- pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
- } while (addr != end);
- }
- /*
- * Create the page directory entries and any necessary
- * page tables for the mapping specified by `md'. We
- * are able to cope here with varying sizes and address
- * offsets, and we take full advantage of sections and
- * supersections.
- */
- static void __init create_mapping(struct map_desc *md)
- {
- unsigned long addr, length, end;
- phys_addr_t phys;
- const struct mem_type *type;
- pgd_t *pgd;
- if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
- printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
- " at 0x%08lx in user region\n",
- (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
- return;
- }
- if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
- md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
- printk(KERN_WARNING "BUG: mapping for 0x%08llx"
- " at 0x%08lx overlaps vmalloc space\n",
- (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
- }
- type = &mem_types[md->type];
- /*
- * Catch 36-bit addresses
- */
- if (md->pfn >= 0x100000) {
- create_36bit_mapping(md, type);
- return;
- }
- addr = md->virtual & PAGE_MASK;
- phys = __pfn_to_phys(md->pfn);
- length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
- if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
- printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
- "be mapped using pages, ignoring.\n",
- (long long)__pfn_to_phys(md->pfn), addr);
- return;
- }
- pgd = pgd_offset_k(addr);
- end = addr + length;
- do {
- unsigned long next = pgd_addr_end(addr, end);
- alloc_init_pud(pgd, addr, next, phys, type);
- phys += next - addr;
- addr = next;
- } while (pgd++, addr != end);
- }
- /*
- * Create the architecture specific mappings
- */
- void __init iotable_init(struct map_desc *io_desc, int nr)
- {
- int i;
- for (i = 0; i < nr; i++)
- create_mapping(io_desc + i);
- }
- static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
- /*
- * vmalloc=size forces the vmalloc area to be exactly 'size'
- * bytes. This can be used to increase (or decrease) the vmalloc
- * area - the default is 128m.
- */
- static int __init early_vmalloc(char *arg)
- {
- unsigned long vmalloc_reserve = memparse(arg, NULL);
- if (vmalloc_reserve < SZ_16M) {
- vmalloc_reserve = SZ_16M;
- printk(KERN_WARNING
- "vmalloc area too small, limiting to %luMB\n",
- vmalloc_reserve >> 20);
- }
- if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
- vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
- printk(KERN_WARNING
- "vmalloc area is too big, limiting to %luMB\n",
- vmalloc_reserve >> 20);
- }
- vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
- return 0;
- }
- early_param("vmalloc", early_vmalloc);
- static phys_addr_t lowmem_limit __initdata = 0;
- void __init sanity_check_meminfo(void)
- {
- int i, j, highmem = 0;
- for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
- struct membank *bank = &meminfo.bank[j];
- *bank = meminfo.bank[i];
- #ifdef CONFIG_HIGHMEM
- if (__va(bank->start) >= vmalloc_min ||
- __va(bank->start) < (void *)PAGE_OFFSET)
- highmem = 1;
- bank->highmem = highmem;
- /*
- * Split those memory banks which are partially overlapping
- * the vmalloc area greatly simplifying things later.
- */
- if (__va(bank->start) < vmalloc_min &&
- bank->size > vmalloc_min - __va(bank->start)) {
- if (meminfo.nr_banks >= NR_BANKS) {
- printk(KERN_CRIT "NR_BANKS too low, "
- "ignoring high memory\n");
- } else {
- memmove(bank + 1, bank,
- (meminfo.nr_banks - i) * sizeof(*bank));
- meminfo.nr_banks++;
- i++;
- bank[1].size -= vmalloc_min - __va(bank->start);
- bank[1].start = __pa(vmalloc_min - 1) + 1;
- bank[1].highmem = highmem = 1;
- j++;
- }
- bank->size = vmalloc_min - __va(bank->start);
- }
- #else
- bank->highmem = highmem;
- /*
- * Check whether this memory bank would entirely overlap
- * the vmalloc area.
- */
- if (__va(bank->start) >= vmalloc_min ||
- __va(bank->start) < (void *)PAGE_OFFSET) {
- printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
- "(vmalloc region overlap).\n",
- (unsigned long long)bank->start,
- (unsigned long long)bank->start + bank->size - 1);
- continue;
- }
- /*
- * Check whether this memory bank would partially overlap
- * the vmalloc area.
- */
- if (__va(bank->start + bank->size) > vmalloc_min ||
- __va(bank->start + bank->size) < __va(bank->start)) {
- unsigned long newsize = vmalloc_min - __va(bank->start);
- printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
- "to -%.8llx (vmalloc region overlap).\n",
- (unsigned long long)bank->start,
- (unsigned long long)bank->start + bank->size - 1,
- (unsigned long long)bank->start + newsize - 1);
- bank->size = newsize;
- }
- #endif
- if (!bank->highmem && bank->start + bank->size > lowmem_limit)
- lowmem_limit = bank->start + bank->size;
- j++;
- }
- #ifdef CONFIG_HIGHMEM
- if (highmem) {
- const char *reason = NULL;
- if (cache_is_vipt_aliasing()) {
- /*
- * Interactions between kmap and other mappings
- * make highmem support with aliasing VIPT caches
- * rather difficult.
- */
- reason = "with VIPT aliasing cache";
- }
- if (reason) {
- printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
- reason);
- while (j > 0 && meminfo.bank[j - 1].highmem)
- j--;
- }
- }
- #endif
- meminfo.nr_banks = j;
- memblock_set_current_limit(lowmem_limit);
- }
- static inline void prepare_page_table(void)
- {
- unsigned long addr;
- phys_addr_t end;
- /*
- * Clear out all the mappings below the kernel image.
- */
- for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
- pmd_clear(pmd_off_k(addr));
- #ifdef CONFIG_XIP_KERNEL
- /* The XIP kernel is mapped in the module area -- skip over it */
- addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
- #endif
- for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
- pmd_clear(pmd_off_k(addr));
- /*
- * Find the end of the first block of lowmem.
- */
- end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
- if (end >= lowmem_limit)
- end = lowmem_limit;
- /*
- * Clear out all the kernel space mappings, except for the first
- * memory bank, up to the end of the vmalloc region.
- */
- for (addr = __phys_to_virt(end);
- addr < VMALLOC_END; addr += PGDIR_SIZE)
- pmd_clear(pmd_off_k(addr));
- }
- /*
- * Reserve the special regions of memory
- */
- void __init arm_mm_memblock_reserve(void)
- {
- /*
- * Reserve the page tables. These are already in use,
- * and can only be in node 0.
- */
- memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
- #ifdef CONFIG_SA1111
- /*
- * Because of the SA1111 DMA bug, we want to preserve our
- * precious DMA-able memory...
- */
- memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
- #endif
- }
- /*
- * Set up device the mappings. Since we clear out the page tables for all
- * mappings above VMALLOC_END, we will remove any debug device mappings.
- * This means you have to be careful how you debug this function, or any
- * called function. This means you can't use any function or debugging
- * method which may touch any device, otherwise the kernel _will_ crash.
- */
- static void __init devicemaps_init(struct machine_desc *mdesc)
- {
- struct map_desc map;
- unsigned long addr;
- /*
- * Allocate the vector page early.
- */
- vectors_page = early_alloc(PAGE_SIZE);
- for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
- pmd_clear(pmd_off_k(addr));
- /*
- * Map the kernel if it is XIP.
- * It is always first in the modulearea.
- */
- #ifdef CONFIG_XIP_KERNEL
- map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
- map.virtual = MODULES_VADDR;
- map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
- map.type = MT_ROM;
- create_mapping(&map);
- #endif
- /*
- * Map the cache flushing regions.
- */
- #ifdef FLUSH_BASE
- map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
- map.virtual = FLUSH_BASE;
- map.length = SZ_1M;
- map.type = MT_CACHECLEAN;
- create_mapping(&map);
- #endif
- #ifdef FLUSH_BASE_MINICACHE
- map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
- map.virtual = FLUSH_BASE_MINICACHE;
- map.length = SZ_1M;
- map.type = MT_MINICLEAN;
- create_mapping(&map);
- #endif
- /*
- * Create a mapping for the machine vectors at the high-vectors
- * location (0xffff0000). If we aren't using high-vectors, also
- * create a mapping at the low-vectors virtual address.
- */
- map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
- map.virtual = 0xffff0000;
- map.length = PAGE_SIZE;
- map.type = MT_HIGH_VECTORS;
- create_mapping(&map);
- if (!vectors_high()) {
- map.virtual = 0;
- map.type = MT_LOW_VECTORS;
- create_mapping(&map);
- }
- /*
- * Ask the machine support to map in the statically mapped devices.
- */
- if (mdesc->map_io)
- mdesc->map_io();
- /*
- * Finally flush the caches and tlb to ensure that we're in a
- * consistent state wrt the writebuffer. This also ensures that
- * any write-allocated cache lines in the vector page are written
- * back. After this point, we can start to touch devices again.
- */
- local_flush_tlb_all();
- flush_cache_all();
- }
- static void __init kmap_init(void)
- {
- #ifdef CONFIG_HIGHMEM
- pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
- PKMAP_BASE, _PAGE_KERNEL_TABLE);
- #endif
- }
- static void __init map_lowmem(void)
- {
- struct memblock_region *reg;
- /* Map all the lowmem memory banks. */
- for_each_memblock(memory, reg) {
- phys_addr_t start = reg->base;
- phys_addr_t end = start + reg->size;
- struct map_desc map;
- if (end > lowmem_limit)
- end = lowmem_limit;
- if (start >= end)
- break;
- map.pfn = __phys_to_pfn(start);
- map.virtual = __phys_to_virt(start);
- map.length = end - start;
- map.type = MT_MEMORY;
- create_mapping(&map);
- }
- }
- /*
- * paging_init() sets up the page tables, initialises the zone memory
- * maps, and sets up the zero page, bad page and bad page tables.
- */
- void __init paging_init(struct machine_desc *mdesc)
- {
- void *zero_page;
- memblock_set_current_limit(lowmem_limit);
- build_mem_type_table();
- prepare_page_table();
- map_lowmem();
- devicemaps_init(mdesc);
- kmap_init();
- top_pmd = pmd_off_k(0xffff0000);
- /* allocate the zero page. */
- zero_page = early_alloc(PAGE_SIZE);
- bootmem_init();
- empty_zero_page = virt_to_page(zero_page);
- __flush_dcache_page(NULL, empty_zero_page);
- }