PageRenderTime 40ms CodeModel.GetById 15ms RepoModel.GetById 0ms app.codeStats 0ms

/arch/sparc/kernel/setup_64.c

https://bitbucket.org/androidarmv6/android_kernel_semc_msm7x27
C | 434 lines | 342 code | 63 blank | 29 comment | 52 complexity | b3706da67629e1dfea60f9f640208ca2 MD5 | raw file
  1. /*
  2. * linux/arch/sparc64/kernel/setup.c
  3. *
  4. * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
  5. * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/sched.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mm.h>
  11. #include <linux/stddef.h>
  12. #include <linux/unistd.h>
  13. #include <linux/ptrace.h>
  14. #include <linux/slab.h>
  15. #include <asm/smp.h>
  16. #include <linux/user.h>
  17. #include <linux/screen_info.h>
  18. #include <linux/delay.h>
  19. #include <linux/fs.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/syscalls.h>
  22. #include <linux/kdev_t.h>
  23. #include <linux/major.h>
  24. #include <linux/string.h>
  25. #include <linux/init.h>
  26. #include <linux/inet.h>
  27. #include <linux/console.h>
  28. #include <linux/root_dev.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/cpu.h>
  31. #include <linux/initrd.h>
  32. #include <asm/system.h>
  33. #include <asm/io.h>
  34. #include <asm/processor.h>
  35. #include <asm/oplib.h>
  36. #include <asm/page.h>
  37. #include <asm/pgtable.h>
  38. #include <asm/idprom.h>
  39. #include <asm/head.h>
  40. #include <asm/starfire.h>
  41. #include <asm/mmu_context.h>
  42. #include <asm/timer.h>
  43. #include <asm/sections.h>
  44. #include <asm/setup.h>
  45. #include <asm/mmu.h>
  46. #include <asm/ns87303.h>
  47. #ifdef CONFIG_IP_PNP
  48. #include <net/ipconfig.h>
  49. #endif
  50. #include "entry.h"
  51. #include "kernel.h"
  52. /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
  53. * operations in asm/ns87303.h
  54. */
  55. DEFINE_SPINLOCK(ns87303_lock);
  56. EXPORT_SYMBOL(ns87303_lock);
  57. struct screen_info screen_info = {
  58. 0, 0, /* orig-x, orig-y */
  59. 0, /* unused */
  60. 0, /* orig-video-page */
  61. 0, /* orig-video-mode */
  62. 128, /* orig-video-cols */
  63. 0, 0, 0, /* unused, ega_bx, unused */
  64. 54, /* orig-video-lines */
  65. 0, /* orig-video-isVGA */
  66. 16 /* orig-video-points */
  67. };
  68. static void
  69. prom_console_write(struct console *con, const char *s, unsigned n)
  70. {
  71. prom_write(s, n);
  72. }
  73. /* Exported for mm/init.c:paging_init. */
  74. unsigned long cmdline_memory_size = 0;
  75. static struct console prom_early_console = {
  76. .name = "earlyprom",
  77. .write = prom_console_write,
  78. .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
  79. .index = -1,
  80. };
  81. /*
  82. * Process kernel command line switches that are specific to the
  83. * SPARC or that require special low-level processing.
  84. */
  85. static void __init process_switch(char c)
  86. {
  87. switch (c) {
  88. case 'd':
  89. case 's':
  90. break;
  91. case 'h':
  92. prom_printf("boot_flags_init: Halt!\n");
  93. prom_halt();
  94. break;
  95. case 'p':
  96. /* Just ignore, this behavior is now the default. */
  97. break;
  98. case 'P':
  99. /* Force UltraSPARC-III P-Cache on. */
  100. if (tlb_type != cheetah) {
  101. printk("BOOT: Ignoring P-Cache force option.\n");
  102. break;
  103. }
  104. cheetah_pcache_forced_on = 1;
  105. add_taint(TAINT_MACHINE_CHECK);
  106. cheetah_enable_pcache();
  107. break;
  108. default:
  109. printk("Unknown boot switch (-%c)\n", c);
  110. break;
  111. }
  112. }
  113. static void __init boot_flags_init(char *commands)
  114. {
  115. while (*commands) {
  116. /* Move to the start of the next "argument". */
  117. while (*commands && *commands == ' ')
  118. commands++;
  119. /* Process any command switches, otherwise skip it. */
  120. if (*commands == '\0')
  121. break;
  122. if (*commands == '-') {
  123. commands++;
  124. while (*commands && *commands != ' ')
  125. process_switch(*commands++);
  126. continue;
  127. }
  128. if (!strncmp(commands, "mem=", 4)) {
  129. /*
  130. * "mem=XXX[kKmM]" overrides the PROM-reported
  131. * memory size.
  132. */
  133. cmdline_memory_size = simple_strtoul(commands + 4,
  134. &commands, 0);
  135. if (*commands == 'K' || *commands == 'k') {
  136. cmdline_memory_size <<= 10;
  137. commands++;
  138. } else if (*commands=='M' || *commands=='m') {
  139. cmdline_memory_size <<= 20;
  140. commands++;
  141. }
  142. }
  143. while (*commands && *commands != ' ')
  144. commands++;
  145. }
  146. }
  147. extern unsigned short root_flags;
  148. extern unsigned short root_dev;
  149. extern unsigned short ram_flags;
  150. #define RAMDISK_IMAGE_START_MASK 0x07FF
  151. #define RAMDISK_PROMPT_FLAG 0x8000
  152. #define RAMDISK_LOAD_FLAG 0x4000
  153. extern int root_mountflags;
  154. char reboot_command[COMMAND_LINE_SIZE];
  155. static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
  156. void __init per_cpu_patch(void)
  157. {
  158. struct cpuid_patch_entry *p;
  159. unsigned long ver;
  160. int is_jbus;
  161. if (tlb_type == spitfire && !this_is_starfire)
  162. return;
  163. is_jbus = 0;
  164. if (tlb_type != hypervisor) {
  165. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  166. is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
  167. (ver >> 32UL) == __SERRANO_ID);
  168. }
  169. p = &__cpuid_patch;
  170. while (p < &__cpuid_patch_end) {
  171. unsigned long addr = p->addr;
  172. unsigned int *insns;
  173. switch (tlb_type) {
  174. case spitfire:
  175. insns = &p->starfire[0];
  176. break;
  177. case cheetah:
  178. case cheetah_plus:
  179. if (is_jbus)
  180. insns = &p->cheetah_jbus[0];
  181. else
  182. insns = &p->cheetah_safari[0];
  183. break;
  184. case hypervisor:
  185. insns = &p->sun4v[0];
  186. break;
  187. default:
  188. prom_printf("Unknown cpu type, halting.\n");
  189. prom_halt();
  190. };
  191. *(unsigned int *) (addr + 0) = insns[0];
  192. wmb();
  193. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  194. *(unsigned int *) (addr + 4) = insns[1];
  195. wmb();
  196. __asm__ __volatile__("flush %0" : : "r" (addr + 4));
  197. *(unsigned int *) (addr + 8) = insns[2];
  198. wmb();
  199. __asm__ __volatile__("flush %0" : : "r" (addr + 8));
  200. *(unsigned int *) (addr + 12) = insns[3];
  201. wmb();
  202. __asm__ __volatile__("flush %0" : : "r" (addr + 12));
  203. p++;
  204. }
  205. }
  206. void __init sun4v_patch(void)
  207. {
  208. extern void sun4v_hvapi_init(void);
  209. struct sun4v_1insn_patch_entry *p1;
  210. struct sun4v_2insn_patch_entry *p2;
  211. if (tlb_type != hypervisor)
  212. return;
  213. p1 = &__sun4v_1insn_patch;
  214. while (p1 < &__sun4v_1insn_patch_end) {
  215. unsigned long addr = p1->addr;
  216. *(unsigned int *) (addr + 0) = p1->insn;
  217. wmb();
  218. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  219. p1++;
  220. }
  221. p2 = &__sun4v_2insn_patch;
  222. while (p2 < &__sun4v_2insn_patch_end) {
  223. unsigned long addr = p2->addr;
  224. *(unsigned int *) (addr + 0) = p2->insns[0];
  225. wmb();
  226. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  227. *(unsigned int *) (addr + 4) = p2->insns[1];
  228. wmb();
  229. __asm__ __volatile__("flush %0" : : "r" (addr + 4));
  230. p2++;
  231. }
  232. sun4v_hvapi_init();
  233. }
  234. #ifdef CONFIG_SMP
  235. void __init boot_cpu_id_too_large(int cpu)
  236. {
  237. prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
  238. cpu, NR_CPUS);
  239. prom_halt();
  240. }
  241. #endif
  242. void __init setup_arch(char **cmdline_p)
  243. {
  244. /* Initialize PROM console and command line. */
  245. *cmdline_p = prom_getbootargs();
  246. strcpy(boot_command_line, *cmdline_p);
  247. parse_early_param();
  248. boot_flags_init(*cmdline_p);
  249. register_console(&prom_early_console);
  250. if (tlb_type == hypervisor)
  251. printk("ARCH: SUN4V\n");
  252. else
  253. printk("ARCH: SUN4U\n");
  254. #ifdef CONFIG_DUMMY_CONSOLE
  255. conswitchp = &dummy_con;
  256. #elif defined(CONFIG_PROM_CONSOLE)
  257. conswitchp = &prom_con;
  258. #endif
  259. idprom_init();
  260. if (!root_flags)
  261. root_mountflags &= ~MS_RDONLY;
  262. ROOT_DEV = old_decode_dev(root_dev);
  263. #ifdef CONFIG_BLK_DEV_RAM
  264. rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
  265. rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
  266. rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
  267. #endif
  268. task_thread_info(&init_task)->kregs = &fake_swapper_regs;
  269. #ifdef CONFIG_IP_PNP
  270. if (!ic_set_manually) {
  271. int chosen = prom_finddevice ("/chosen");
  272. u32 cl, sv, gw;
  273. cl = prom_getintdefault (chosen, "client-ip", 0);
  274. sv = prom_getintdefault (chosen, "server-ip", 0);
  275. gw = prom_getintdefault (chosen, "gateway-ip", 0);
  276. if (cl && sv) {
  277. ic_myaddr = cl;
  278. ic_servaddr = sv;
  279. if (gw)
  280. ic_gateway = gw;
  281. #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
  282. ic_proto_enabled = 0;
  283. #endif
  284. }
  285. }
  286. #endif
  287. /* Get boot processor trap_block[] setup. */
  288. init_cur_cpu_trap(current_thread_info());
  289. paging_init();
  290. }
  291. /* BUFFER is PAGE_SIZE bytes long. */
  292. extern void smp_info(struct seq_file *);
  293. extern void smp_bogo(struct seq_file *);
  294. extern void mmu_info(struct seq_file *);
  295. unsigned int dcache_parity_tl1_occurred;
  296. unsigned int icache_parity_tl1_occurred;
  297. int ncpus_probed;
  298. static int show_cpuinfo(struct seq_file *m, void *__unused)
  299. {
  300. seq_printf(m,
  301. "cpu\t\t: %s\n"
  302. "fpu\t\t: %s\n"
  303. "pmu\t\t: %s\n"
  304. "prom\t\t: %s\n"
  305. "type\t\t: %s\n"
  306. "ncpus probed\t: %d\n"
  307. "ncpus active\t: %d\n"
  308. "D$ parity tl1\t: %u\n"
  309. "I$ parity tl1\t: %u\n"
  310. #ifndef CONFIG_SMP
  311. "Cpu0ClkTck\t: %016lx\n"
  312. #endif
  313. ,
  314. sparc_cpu_type,
  315. sparc_fpu_type,
  316. sparc_pmu_type,
  317. prom_version,
  318. ((tlb_type == hypervisor) ?
  319. "sun4v" :
  320. "sun4u"),
  321. ncpus_probed,
  322. num_online_cpus(),
  323. dcache_parity_tl1_occurred,
  324. icache_parity_tl1_occurred
  325. #ifndef CONFIG_SMP
  326. , cpu_data(0).clock_tick
  327. #endif
  328. );
  329. #ifdef CONFIG_SMP
  330. smp_bogo(m);
  331. #endif
  332. mmu_info(m);
  333. #ifdef CONFIG_SMP
  334. smp_info(m);
  335. #endif
  336. return 0;
  337. }
  338. static void *c_start(struct seq_file *m, loff_t *pos)
  339. {
  340. /* The pointer we are returning is arbitrary,
  341. * it just has to be non-NULL and not IS_ERR
  342. * in the success case.
  343. */
  344. return *pos == 0 ? &c_start : NULL;
  345. }
  346. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  347. {
  348. ++*pos;
  349. return c_start(m, pos);
  350. }
  351. static void c_stop(struct seq_file *m, void *v)
  352. {
  353. }
  354. const struct seq_operations cpuinfo_op = {
  355. .start =c_start,
  356. .next = c_next,
  357. .stop = c_stop,
  358. .show = show_cpuinfo,
  359. };
  360. extern int stop_a_enabled;
  361. void sun_do_break(void)
  362. {
  363. if (!stop_a_enabled)
  364. return;
  365. prom_printf("\n");
  366. flush_user_windows();
  367. prom_cmdline();
  368. }
  369. EXPORT_SYMBOL(sun_do_break);
  370. int stop_a_enabled = 1;
  371. EXPORT_SYMBOL(stop_a_enabled);