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/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml

https://github.com/kvaneesh/linux
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  1. # SPDX-License-Identifier: GPL-2.0
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Tegra Power Management Controller (PMC)
  7. maintainers:
  8. - Thierry Reding <thierry.reding@gmail.com>
  9. - Jonathan Hunter <jonathanh@nvidia.com>
  10. properties:
  11. compatible:
  12. enum:
  13. - nvidia,tegra20-pmc
  14. - nvidia,tegra20-pmc
  15. - nvidia,tegra30-pmc
  16. - nvidia,tegra114-pmc
  17. - nvidia,tegra124-pmc
  18. - nvidia,tegra210-pmc
  19. reg:
  20. maxItems: 1
  21. description:
  22. Offset and length of the register set for the device.
  23. clock-names:
  24. items:
  25. - const: pclk
  26. - const: clk32k_in
  27. description:
  28. Must includes entries pclk and clk32k_in.
  29. pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
  30. input to Tegra.
  31. clocks:
  32. maxItems: 2
  33. description:
  34. Must contain an entry for each entry in clock-names.
  35. See ../clocks/clocks-bindings.txt for details.
  36. '#clock-cells':
  37. const: 1
  38. description:
  39. Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
  40. PMC also has blink control which allows 32Khz clock output to
  41. Tegra blink pad.
  42. Consumer of PMC clock should specify the desired clock by having
  43. the clock ID in its "clocks" phandle cell with pmc clock provider.
  44. See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
  45. clock IDs.
  46. '#interrupt-cells':
  47. const: 2
  48. description:
  49. Specifies number of cells needed to encode an interrupt source.
  50. The value must be 2.
  51. interrupt-controller: true
  52. nvidia,invert-interrupt:
  53. $ref: /schemas/types.yaml#/definitions/flag
  54. description: Inverts the PMU interrupt signal.
  55. The PMU is an external Power Management Unit, whose interrupt output
  56. signal is fed into the PMC. This signal is optionally inverted, and
  57. then fed into the ARM GIC. The PMC is not involved in the detection
  58. or handling of this interrupt signal, merely its inversion.
  59. nvidia,core-power-req-active-high:
  60. $ref: /schemas/types.yaml#/definitions/flag
  61. description: Core power request active-high.
  62. nvidia,sys-clock-req-active-high:
  63. $ref: /schemas/types.yaml#/definitions/flag
  64. description: System clock request active-high.
  65. nvidia,combined-power-req:
  66. $ref: /schemas/types.yaml#/definitions/flag
  67. description: combined power request for CPU and Core.
  68. nvidia,cpu-pwr-good-en:
  69. $ref: /schemas/types.yaml#/definitions/flag
  70. description:
  71. CPU power good signal from external PMIC to PMC is enabled.
  72. nvidia,suspend-mode:
  73. $ref: /schemas/types.yaml#/definitions/uint32
  74. enum: [0, 1, 2]
  75. description:
  76. The suspend mode that the platform should use.
  77. Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
  78. Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
  79. Mode 2 is for LP2, CPU voltage off
  80. nvidia,cpu-pwr-good-time:
  81. $ref: /schemas/types.yaml#/definitions/uint32
  82. description: CPU power good time in uSec.
  83. nvidia,cpu-pwr-off-time:
  84. $ref: /schemas/types.yaml#/definitions/uint32
  85. description: CPU power off time in uSec.
  86. nvidia,core-pwr-good-time:
  87. $ref: /schemas/types.yaml#/definitions/uint32-array
  88. description:
  89. <Oscillator-stable-time Power-stable-time>
  90. Core power good time in uSec.
  91. nvidia,core-pwr-off-time:
  92. $ref: /schemas/types.yaml#/definitions/uint32
  93. description: Core power off time in uSec.
  94. nvidia,lp0-vec:
  95. $ref: /schemas/types.yaml#/definitions/uint32-array
  96. description:
  97. <start length> Starting address and length of LP0 vector.
  98. The LP0 vector contains the warm boot code that is executed
  99. by AVP when resuming from the LP0 state.
  100. The AVP (Audio-Video Processor) is an ARM7 processor and
  101. always being the first boot processor when chip is power on
  102. or resume from deep sleep mode. When the system is resumed
  103. from the deep sleep mode, the warm boot code will restore
  104. some PLLs, clocks and then brings up CPU0 for resuming the
  105. system.
  106. i2c-thermtrip:
  107. type: object
  108. description:
  109. On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
  110. hardware-triggered thermal reset will be enabled.
  111. properties:
  112. nvidia,i2c-controller-id:
  113. $ref: /schemas/types.yaml#/definitions/uint32
  114. description:
  115. ID of I2C controller to send poweroff command to PMU.
  116. Valid values are described in section 9.2.148
  117. "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
  118. Manual.
  119. nvidia,bus-addr:
  120. $ref: /schemas/types.yaml#/definitions/uint32
  121. description: Bus address of the PMU on the I2C bus.
  122. nvidia,reg-addr:
  123. $ref: /schemas/types.yaml#/definitions/uint32
  124. description: PMU I2C register address to issue poweroff command.
  125. nvidia,reg-data:
  126. $ref: /schemas/types.yaml#/definitions/uint32
  127. description: Poweroff command to write to PMU.
  128. nvidia,pinmux-id:
  129. $ref: /schemas/types.yaml#/definitions/uint32
  130. description:
  131. Pinmux used by the hardware when issuing Poweroff command.
  132. Defaults to 0. Valid values are described in section 12.5.2
  133. "Pinmux Support" of the Tegra4 Technical Reference Manual.
  134. required:
  135. - nvidia,i2c-controller-id
  136. - nvidia,bus-addr
  137. - nvidia,reg-addr
  138. - nvidia,reg-data
  139. additionalProperties: false
  140. powergates:
  141. type: object
  142. description: |
  143. This node contains a hierarchy of power domain nodes, which should
  144. match the powergates on the Tegra SoC. Each powergate node
  145. represents a power-domain on the Tegra SoC that can be power-gated
  146. by the Tegra PMC.
  147. Hardware blocks belonging to a power domain should contain
  148. "power-domains" property that is a phandle pointing to corresponding
  149. powergate node.
  150. The name of the powergate node should be one of the below. Note that
  151. not every powergate is applicable to all Tegra devices and the following
  152. list shows which powergates are applicable to which devices.
  153. Please refer to Tegra TRM for mode details on the powergate nodes to
  154. use for each power-gate block inside Tegra.
  155. Name Description Devices Applicable
  156. 3d 3D Graphics Tegra20/114/124/210
  157. 3d0 3D Graphics 0 Tegra30
  158. 3d1 3D Graphics 1 Tegra30
  159. aud Audio Tegra210
  160. dfd Debug Tegra210
  161. dis Display A Tegra114/124/210
  162. disb Display B Tegra114/124/210
  163. heg 2D Graphics Tegra30/114/124/210
  164. iram Internal RAM Tegra124/210
  165. mpe MPEG Encode All
  166. nvdec NVIDIA Video Decode Engine Tegra210
  167. nvjpg NVIDIA JPEG Engine Tegra210
  168. pcie PCIE Tegra20/30/124/210
  169. sata SATA Tegra30/124/210
  170. sor Display interfaces Tegra124/210
  171. ve2 Video Encode Engine 2 Tegra210
  172. venc Video Encode Engine All
  173. vdec Video Decode Engine Tegra20/30/114/124
  174. vic Video Imaging Compositor Tegra124/210
  175. xusba USB Partition A Tegra114/124/210
  176. xusbb USB Partition B Tegra114/124/210
  177. xusbc USB Partition C Tegra114/124/210
  178. patternProperties:
  179. "^[a-z0-9]+$":
  180. type: object
  181. patternProperties:
  182. clocks:
  183. minItems: 1
  184. maxItems: 8
  185. description:
  186. Must contain an entry for each clock required by the PMC
  187. for controlling a power-gate.
  188. See ../clocks/clock-bindings.txt document for more details.
  189. resets:
  190. minItems: 1
  191. maxItems: 8
  192. description:
  193. Must contain an entry for each reset required by the PMC
  194. for controlling a power-gate.
  195. See ../reset/reset.txt for more details.
  196. '#power-domain-cells':
  197. const: 0
  198. description: Must be 0.
  199. required:
  200. - clocks
  201. - resets
  202. - '#power-domain-cells'
  203. additionalProperties: false
  204. patternProperties:
  205. "^[a-f0-9]+-[a-f0-9]+$":
  206. type: object
  207. description:
  208. This is a Pad configuration node. On Tegra SOCs a pad is a set of
  209. pins which are configured as a group. The pin grouping is a fixed
  210. attribute of the hardware. The PMC can be used to set pad power state
  211. and signaling voltage. A pad can be either in active or power down mode.
  212. The support for power state and signaling voltage configuration varies
  213. depending on the pad in question. 3.3V and 1.8V signaling voltages
  214. are supported on pins where software controllable signaling voltage
  215. switching is available.
  216. The pad configuration state nodes are placed under the pmc node and they
  217. are referred to by the pinctrl client properties. For more information
  218. see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
  219. The pad name should be used as the value of the pins property in pin
  220. configuration nodes.
  221. The following pads are present on Tegra124 and Tegra132
  222. audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
  223. hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
  224. sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
  225. The following pads are present on Tegra210
  226. audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
  227. debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
  228. hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
  229. sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
  230. properties:
  231. pins:
  232. $ref: /schemas/types.yaml#/definitions/string
  233. description: Must contain name of the pad(s) to be configured.
  234. low-power-enable:
  235. $ref: /schemas/types.yaml#/definitions/flag
  236. description: Configure the pad into power down mode.
  237. low-power-disable:
  238. $ref: /schemas/types.yaml#/definitions/flag
  239. description: Configure the pad into active mode.
  240. power-source:
  241. $ref: /schemas/types.yaml#/definitions/uint32
  242. description:
  243. Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
  244. TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
  245. The values are defined in
  246. include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
  247. Power state can be configured on all Tegra124 and Tegra132
  248. pads. None of the Tegra124 or Tegra132 pads support signaling
  249. voltage switching.
  250. All of the listed Tegra210 pads except pex-cntrl support power
  251. state configuration. Signaling voltage switching is supported
  252. on below Tegra210 pads.
  253. audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
  254. sdmmc3, spi, spi-hv, and uart.
  255. required:
  256. - pins
  257. additionalProperties: false
  258. core-domain:
  259. type: object
  260. description: |
  261. The vast majority of hardware blocks of Tegra SoC belong to a
  262. Core power domain, which has a dedicated voltage rail that powers
  263. the blocks.
  264. properties:
  265. operating-points-v2:
  266. description:
  267. Should contain level, voltages and opp-supported-hw property.
  268. The supported-hw is a bitfield indicating SoC speedo or process
  269. ID mask.
  270. "#power-domain-cells":
  271. const: 0
  272. required:
  273. - operating-points-v2
  274. - "#power-domain-cells"
  275. additionalProperties: false
  276. core-supply:
  277. description:
  278. Phandle to voltage regulator connected to the SoC Core power rail.
  279. required:
  280. - compatible
  281. - reg
  282. - clock-names
  283. - clocks
  284. - '#clock-cells'
  285. additionalProperties: false
  286. dependencies:
  287. "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
  288. "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
  289. "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
  290. examples:
  291. - |
  292. #include <dt-bindings/clock/tegra210-car.h>
  293. #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
  294. #include <dt-bindings/soc/tegra-pmc.h>
  295. tegra_pmc: pmc@7000e400 {
  296. compatible = "nvidia,tegra210-pmc";
  297. reg = <0x7000e400 0x400>;
  298. core-supply = <&regulator>;
  299. clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
  300. clock-names = "pclk", "clk32k_in";
  301. #clock-cells = <1>;
  302. nvidia,invert-interrupt;
  303. nvidia,suspend-mode = <0>;
  304. nvidia,cpu-pwr-good-time = <0>;
  305. nvidia,cpu-pwr-off-time = <0>;
  306. nvidia,core-pwr-good-time = <4587 3876>;
  307. nvidia,core-pwr-off-time = <39065>;
  308. nvidia,core-power-req-active-high;
  309. nvidia,sys-clock-req-active-high;
  310. pd_core: core-domain {
  311. operating-points-v2 = <&core_opp_table>;
  312. #power-domain-cells = <0>;
  313. };
  314. powergates {
  315. pd_audio: aud {
  316. clocks = <&tegra_car TEGRA210_CLK_APE>,
  317. <&tegra_car TEGRA210_CLK_APB2APE>;
  318. resets = <&tegra_car 198>;
  319. power-domains = <&pd_core>;
  320. #power-domain-cells = <0>;
  321. };
  322. pd_xusbss: xusba {
  323. clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
  324. resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
  325. power-domains = <&pd_core>;
  326. #power-domain-cells = <0>;
  327. };
  328. };
  329. };