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/drivers/scsi/smartpqi/smartpqi_sis.c

https://github.com/tklauser/linux-nios2
C | 404 lines | 272 code | 75 blank | 57 comment | 33 complexity | 097b118f49369c02ae8c033bf04318bc MD5 | raw file
  1. /*
  2. * driver for Microsemi PQI-based storage controllers
  3. * Copyright (c) 2016 Microsemi Corporation
  4. * Copyright (c) 2016 PMC-Sierra, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13. * NON INFRINGEMENT. See the GNU General Public License for more details.
  14. *
  15. * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
  16. *
  17. */
  18. #include <linux/module.h>
  19. #include <linux/kernel.h>
  20. #include <linux/delay.h>
  21. #include <linux/pci.h>
  22. #include <scsi/scsi_device.h>
  23. #include <asm/unaligned.h>
  24. #include "smartpqi.h"
  25. #include "smartpqi_sis.h"
  26. /* legacy SIS interface commands */
  27. #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19
  28. #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b
  29. #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000
  30. /* for submission of legacy SIS commands */
  31. #define SIS_REENABLE_SIS_MODE 0x1
  32. #define SIS_ENABLE_MSIX 0x40
  33. #define SIS_SOFT_RESET 0x100
  34. #define SIS_CMD_READY 0x200
  35. #define SIS_CMD_COMPLETE 0x1000
  36. #define SIS_CLEAR_CTRL_TO_HOST_DOORBELL 0x1000
  37. #define SIS_CMD_STATUS_SUCCESS 0x1
  38. #define SIS_CMD_COMPLETE_TIMEOUT_SECS 30
  39. #define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS 10
  40. /* used with SIS_CMD_GET_ADAPTER_PROPERTIES command */
  41. #define SIS_EXTENDED_PROPERTIES_SUPPORTED 0x800000
  42. #define SIS_SMARTARRAY_FEATURES_SUPPORTED 0x2
  43. #define SIS_PQI_MODE_SUPPORTED 0x4
  44. #define SIS_REQUIRED_EXTENDED_PROPERTIES \
  45. (SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED)
  46. /* used with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
  47. #define SIS_BASE_STRUCT_REVISION 9
  48. #define SIS_BASE_STRUCT_ALIGNMENT 16
  49. #define SIS_CTRL_KERNEL_UP 0x80
  50. #define SIS_CTRL_KERNEL_PANIC 0x100
  51. #define SIS_CTRL_READY_TIMEOUT_SECS 30
  52. #define SIS_CTRL_READY_POLL_INTERVAL_MSECS 10
  53. #pragma pack(1)
  54. /* for use with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
  55. struct sis_base_struct {
  56. __le32 revision; /* revision of this structure */
  57. __le32 flags; /* reserved */
  58. __le32 error_buffer_paddr_low; /* lower 32 bits of physical memory */
  59. /* buffer for PQI error response */
  60. /* data */
  61. __le32 error_buffer_paddr_high; /* upper 32 bits of physical */
  62. /* memory buffer for PQI */
  63. /* error response data */
  64. __le32 error_buffer_element_length; /* length of each PQI error */
  65. /* response buffer element */
  66. /* in bytes */
  67. __le32 error_buffer_num_elements; /* total number of PQI error */
  68. /* response buffers available */
  69. };
  70. #pragma pack()
  71. int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info)
  72. {
  73. unsigned long timeout;
  74. u32 status;
  75. timeout = (SIS_CTRL_READY_TIMEOUT_SECS * HZ) + jiffies;
  76. while (1) {
  77. status = readl(&ctrl_info->registers->sis_firmware_status);
  78. if (status != ~0) {
  79. if (status & SIS_CTRL_KERNEL_PANIC) {
  80. dev_err(&ctrl_info->pci_dev->dev,
  81. "controller is offline: status code 0x%x\n",
  82. readl(
  83. &ctrl_info->registers->sis_mailbox[7]));
  84. return -ENODEV;
  85. }
  86. if (status & SIS_CTRL_KERNEL_UP)
  87. break;
  88. }
  89. if (time_after(jiffies, timeout))
  90. return -ETIMEDOUT;
  91. msleep(SIS_CTRL_READY_POLL_INTERVAL_MSECS);
  92. }
  93. return 0;
  94. }
  95. bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info)
  96. {
  97. bool running;
  98. u32 status;
  99. status = readl(&ctrl_info->registers->sis_firmware_status);
  100. if (status & SIS_CTRL_KERNEL_PANIC)
  101. running = false;
  102. else
  103. running = true;
  104. if (!running)
  105. dev_err(&ctrl_info->pci_dev->dev,
  106. "controller is offline: status code 0x%x\n",
  107. readl(&ctrl_info->registers->sis_mailbox[7]));
  108. return running;
  109. }
  110. /* used for passing command parameters/results when issuing SIS commands */
  111. struct sis_sync_cmd_params {
  112. u32 mailbox[6]; /* mailboxes 0-5 */
  113. };
  114. static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info,
  115. u32 cmd, struct sis_sync_cmd_params *params)
  116. {
  117. struct pqi_ctrl_registers __iomem *registers;
  118. unsigned int i;
  119. unsigned long timeout;
  120. u32 doorbell;
  121. u32 cmd_status;
  122. registers = ctrl_info->registers;
  123. /* Write the command to mailbox 0. */
  124. writel(cmd, &registers->sis_mailbox[0]);
  125. /*
  126. * Write the command parameters to mailboxes 1-4 (mailbox 5 is not used
  127. * when sending a command to the controller).
  128. */
  129. for (i = 1; i <= 4; i++)
  130. writel(params->mailbox[i], &registers->sis_mailbox[i]);
  131. /* Clear the command doorbell. */
  132. writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL,
  133. &registers->sis_ctrl_to_host_doorbell_clear);
  134. /* Disable doorbell interrupts by masking all interrupts. */
  135. writel(~0, &registers->sis_interrupt_mask);
  136. /*
  137. * Force the completion of the interrupt mask register write before
  138. * submitting the command.
  139. */
  140. readl(&registers->sis_interrupt_mask);
  141. /* Submit the command to the controller. */
  142. writel(SIS_CMD_READY, &registers->sis_host_to_ctrl_doorbell);
  143. /*
  144. * Poll for command completion. Note that the call to msleep() is at
  145. * the top of the loop in order to give the controller time to start
  146. * processing the command before we start polling.
  147. */
  148. timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * HZ) + jiffies;
  149. while (1) {
  150. msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS);
  151. doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
  152. if (doorbell & SIS_CMD_COMPLETE)
  153. break;
  154. if (time_after(jiffies, timeout))
  155. return -ETIMEDOUT;
  156. }
  157. /* Read the command status from mailbox 0. */
  158. cmd_status = readl(&registers->sis_mailbox[0]);
  159. if (cmd_status != SIS_CMD_STATUS_SUCCESS) {
  160. dev_err(&ctrl_info->pci_dev->dev,
  161. "SIS command failed for command 0x%x: status = 0x%x\n",
  162. cmd, cmd_status);
  163. return -EINVAL;
  164. }
  165. /*
  166. * The command completed successfully, so save the command status and
  167. * read the values returned in mailboxes 1-5.
  168. */
  169. params->mailbox[0] = cmd_status;
  170. for (i = 1; i < ARRAY_SIZE(params->mailbox); i++)
  171. params->mailbox[i] = readl(&registers->sis_mailbox[i]);
  172. return 0;
  173. }
  174. /*
  175. * This function verifies that we are talking to a controller that speaks PQI.
  176. */
  177. int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info)
  178. {
  179. int rc;
  180. u32 properties;
  181. u32 extended_properties;
  182. struct sis_sync_cmd_params params;
  183. memset(&params, 0, sizeof(params));
  184. rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_ADAPTER_PROPERTIES,
  185. &params);
  186. if (rc)
  187. return rc;
  188. properties = params.mailbox[1];
  189. if (!(properties & SIS_EXTENDED_PROPERTIES_SUPPORTED))
  190. return -ENODEV;
  191. extended_properties = params.mailbox[4];
  192. if ((extended_properties & SIS_REQUIRED_EXTENDED_PROPERTIES) !=
  193. SIS_REQUIRED_EXTENDED_PROPERTIES)
  194. return -ENODEV;
  195. return 0;
  196. }
  197. int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info)
  198. {
  199. int rc;
  200. struct sis_sync_cmd_params params;
  201. memset(&params, 0, sizeof(params));
  202. rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_PQI_CAPABILITIES,
  203. &params);
  204. if (rc)
  205. return rc;
  206. ctrl_info->max_sg_entries = params.mailbox[1];
  207. ctrl_info->max_transfer_size = params.mailbox[2];
  208. ctrl_info->max_outstanding_requests = params.mailbox[3];
  209. ctrl_info->config_table_offset = params.mailbox[4];
  210. ctrl_info->config_table_length = params.mailbox[5];
  211. return 0;
  212. }
  213. int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
  214. {
  215. int rc;
  216. void *base_struct_unaligned;
  217. struct sis_base_struct *base_struct;
  218. struct sis_sync_cmd_params params;
  219. unsigned long error_buffer_paddr;
  220. dma_addr_t bus_address;
  221. base_struct_unaligned = kzalloc(sizeof(*base_struct)
  222. + SIS_BASE_STRUCT_ALIGNMENT - 1, GFP_KERNEL);
  223. if (!base_struct_unaligned)
  224. return -ENOMEM;
  225. base_struct = PTR_ALIGN(base_struct_unaligned,
  226. SIS_BASE_STRUCT_ALIGNMENT);
  227. error_buffer_paddr = (unsigned long)ctrl_info->error_buffer_dma_handle;
  228. put_unaligned_le32(SIS_BASE_STRUCT_REVISION, &base_struct->revision);
  229. put_unaligned_le32(lower_32_bits(error_buffer_paddr),
  230. &base_struct->error_buffer_paddr_low);
  231. put_unaligned_le32(upper_32_bits(error_buffer_paddr),
  232. &base_struct->error_buffer_paddr_high);
  233. put_unaligned_le32(PQI_ERROR_BUFFER_ELEMENT_LENGTH,
  234. &base_struct->error_buffer_element_length);
  235. put_unaligned_le32(ctrl_info->max_io_slots,
  236. &base_struct->error_buffer_num_elements);
  237. bus_address = pci_map_single(ctrl_info->pci_dev, base_struct,
  238. sizeof(*base_struct), PCI_DMA_TODEVICE);
  239. if (pci_dma_mapping_error(ctrl_info->pci_dev, bus_address)) {
  240. rc = -ENOMEM;
  241. goto out;
  242. }
  243. memset(&params, 0, sizeof(params));
  244. params.mailbox[1] = lower_32_bits((u64)bus_address);
  245. params.mailbox[2] = upper_32_bits((u64)bus_address);
  246. params.mailbox[3] = sizeof(*base_struct);
  247. rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS,
  248. &params);
  249. pci_unmap_single(ctrl_info->pci_dev, bus_address, sizeof(*base_struct),
  250. PCI_DMA_TODEVICE);
  251. out:
  252. kfree(base_struct_unaligned);
  253. return rc;
  254. }
  255. /* Enable MSI-X interrupts on the controller. */
  256. void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
  257. {
  258. u32 doorbell_register;
  259. doorbell_register =
  260. readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
  261. doorbell_register |= SIS_ENABLE_MSIX;
  262. writel(doorbell_register,
  263. &ctrl_info->registers->sis_host_to_ctrl_doorbell);
  264. }
  265. /* Disable MSI-X interrupts on the controller. */
  266. void sis_disable_msix(struct pqi_ctrl_info *ctrl_info)
  267. {
  268. u32 doorbell_register;
  269. doorbell_register =
  270. readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
  271. doorbell_register &= ~SIS_ENABLE_MSIX;
  272. writel(doorbell_register,
  273. &ctrl_info->registers->sis_host_to_ctrl_doorbell);
  274. }
  275. void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
  276. {
  277. writel(SIS_SOFT_RESET,
  278. &ctrl_info->registers->sis_host_to_ctrl_doorbell);
  279. }
  280. #define SIS_MODE_READY_TIMEOUT_SECS 30
  281. int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info)
  282. {
  283. int rc;
  284. unsigned long timeout;
  285. struct pqi_ctrl_registers __iomem *registers;
  286. u32 doorbell;
  287. registers = ctrl_info->registers;
  288. writel(SIS_REENABLE_SIS_MODE,
  289. &registers->sis_host_to_ctrl_doorbell);
  290. rc = 0;
  291. timeout = (SIS_MODE_READY_TIMEOUT_SECS * HZ) + jiffies;
  292. while (1) {
  293. doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
  294. if ((doorbell & SIS_REENABLE_SIS_MODE) == 0)
  295. break;
  296. if (time_after(jiffies, timeout)) {
  297. rc = -ETIMEDOUT;
  298. break;
  299. }
  300. }
  301. if (rc)
  302. dev_err(&ctrl_info->pci_dev->dev,
  303. "re-enabling SIS mode failed\n");
  304. return rc;
  305. }
  306. void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value)
  307. {
  308. writel(value, &ctrl_info->registers->sis_driver_scratch);
  309. }
  310. u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info)
  311. {
  312. return readl(&ctrl_info->registers->sis_driver_scratch);
  313. }
  314. static void __attribute__((unused)) verify_structures(void)
  315. {
  316. BUILD_BUG_ON(offsetof(struct sis_base_struct,
  317. revision) != 0x0);
  318. BUILD_BUG_ON(offsetof(struct sis_base_struct,
  319. flags) != 0x4);
  320. BUILD_BUG_ON(offsetof(struct sis_base_struct,
  321. error_buffer_paddr_low) != 0x8);
  322. BUILD_BUG_ON(offsetof(struct sis_base_struct,
  323. error_buffer_paddr_high) != 0xc);
  324. BUILD_BUG_ON(offsetof(struct sis_base_struct,
  325. error_buffer_element_length) != 0x10);
  326. BUILD_BUG_ON(offsetof(struct sis_base_struct,
  327. error_buffer_num_elements) != 0x14);
  328. BUILD_BUG_ON(sizeof(struct sis_base_struct) != 0x18);
  329. }