/bertos/cpu/cortex-m3/io/lm3s_i2c.h

https://github.com/robots/APRS · C Header · 255 lines · 135 code · 62 blank · 58 comment · 0 complexity · f1b39d0c55134bcf8305e818e4cd9dfc MD5 · raw file 

    

  1. /**
    2. 

  2.  * \file
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  3.  * <!--
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  4.  * This file is part of BeRTOS.
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  23.  * this file and link it with other files to produce an executable, this
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  24.  * file does not by itself cause the resulting executable to be covered by
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  25.  * the GNU General Public License.  This exception does not however
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  26.  * invalidate any other reasons why the executable file might be covered by
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  27.  * the GNU General Public License.
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  28.  *
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  29.  * Copyright 2010 Develer S.r.l. (http:///<www.develer.com/)
    30. 

  30.  *
    31. 

  31.  * -->
    32. 

  32.  *
    33. 

  33.  * \brief LM3S I2C definition.
    34. 

  34.  */
    35. 

  35. 

  36. #ifndef LM3S_I2C_H
    37. 

  37. #define LM3S_I2C_H
    38. 

  38. 

  39. 

  40. /* The following are defines for the I2C register offsets. */
    41. 

  41. #define I2C_O_MSA               0x00000000  ///< I2C Master Slave Address
    42. 

  42. #define I2C_O_SOAR              0x00000000  ///< I2C Slave Own Address
    43. 

  43. #define I2C_O_SCSR              0x00000004  ///< I2C Slave Control/Status
    44. 

  44. #define I2C_O_MCS               0x00000004  ///< I2C Master Control/Status
    45. 

  45. #define I2C_O_SDR               0x00000008  ///< I2C Slave Data
    46. 

  46. #define I2C_O_MDR               0x00000008  ///< I2C Master Data
    47. 

  47. #define I2C_O_MTPR              0x0000000C  ///< I2C Master Timer Period
    48. 

  48. #define I2C_O_SIMR              0x0000000C  ///< I2C Slave Interrupt Mask
    49. 

  49. #define I2C_O_SRIS              0x00000010  ///< I2C Slave Raw Interrupt Status
    50. 

  50. #define I2C_O_MIMR              0x00000010  ///< I2C Master Interrupt Mask
    51. 

  51. #define I2C_O_MRIS              0x00000014  ///< I2C Master Raw Interrupt Status
    52. 

  52. #define I2C_O_SMIS              0x00000014  ///< I2C Slave Masked Interrupt
    53. 

  53.                                             ///< Status
    54. 

  54. #define I2C_O_SICR              0x00000018  ///< I2C Slave Interrupt Clear
    55. 

  55. #define I2C_O_MMIS              0x00000018  ///< I2C Master Masked Interrupt
    56. 

  56.                                             ///< Status
    57. 

  57. #define I2C_O_MICR              0x0000001C  ///< I2C Master Interrupt Clear
    58. 

  58. #define I2C_O_MCR               0x00000020  ///< I2C Master Configuration
    59. 

  59. 

  60. 

  61. /* The following are defines for the bit fields in the I2C_O_MSA register. */
    62. 

  62. #define I2C_MSA_SA_M            0x000000FE  ///< I2C Slave Address
    63. 

  63. #define I2C_MSA_RS              0x00000001  ///< Receive not send
    64. 

  64. #define I2C_MSA_SA_S            1
    65. 

  65. #define I2C_MSA_ADDS            0           ///< Set address write bit
    66. 

  66. #define I2C_MSA_ADDR            1           ///< Set address read bit
    67. 

  67. 

  68. 

  69. /* The following are defines for the bit fields in the I2C_O_SOAR register. */
    70. 

  70. #define I2C_SOAR_OAR_M          0x0000007F  ///< I2C Slave Own Address
    71. 

  71. #define I2C_SOAR_OAR_S          0
    72. 

  72. 

  73. 

  74. /* The following are defines for the bit fields in the I2C_O_SCSR register. */
    75. 

  75. #define I2C_SCSR_FBR            0x00000004  ///< First Byte Received
    76. 

  76. #define I2C_SCSR_TREQ           0x00000002  ///< Transmit Request
    77. 

  77. #define I2C_SCSR_DA             0x00000001  ///< Device Active
    78. 

  78. #define I2C_SCSR_RREQ           0x00000001  ///< Receive Request
    79. 

  79. 

  80. /* The following are defines for the bit fields in the I2C_O_MCS register. */
    81. 

  81. #define I2C_MCS_BUSBSY          0x00000040  ///< Bus Busy
    82. 

  82. #define I2C_MCS_IDLE            0x00000020  ///< I2C Idle
    83. 

  83. #define I2C_MCS_ARBLST          0x00000010  ///< Arbitration Lost
    84. 

  84. #define I2C_MCS_ACK             0x00000008  ///< Data Acknowledge Enable
    85. 

  85. #define I2C_MCS_DATACK          0x00000008  ///< Acknowledge Data
    86. 

  86. #define I2C_MCS_ADRACK          0x00000004  ///< Acknowledge Address
    87. 

  87. #define I2C_MCS_STOP            0x00000004  ///< Generate STOP
    88. 

  88. #define I2C_MCS_START           0x00000002  ///< Generate START
    89. 

  89. #define I2C_MCS_ERROR           0x00000002  ///< Error
    90. 

  90. #define I2C_MCS_RUN             0x00000001  ///< I2C Master Enable
    91. 

  91. #define I2C_MCS_BUSY            0x00000001  ///< I2C Busy
    92. 

  92. 

  93. 

  94. /* The following are defines for the bit fields in the I2C_O_SDR register. */
    95. 

  95. #define I2C_SDR_DATA_M          0x000000FF  ///< Data for Transfer
    96. 

  96. #define I2C_SDR_DATA_S          0
    97. 

  97. 

  98. /* The following are defines for the bit fields in the I2C_O_MDR register. */
    99. 

  99. #define I2C_MDR_DATA_M          0x000000FF  ///< Data Transferred
    100. 

  100. #define I2C_MDR_DATA_S          0
    101. 

  101. 

  102. 

  103. /* The following are defines for the bit fields in the I2C_O_MTPR register. */
    104. 

  104. #define I2C_MTPR_TPR_M          0x000000FF  ///< SCL Clock Period
    105. 

  105. #define I2C_MTPR_TPR_S          0
    106. 

  106. 

  107. 

  108. /* The following are defines for the bit fields in the I2C_O_SIMR register. */
    109. 

  109. #define I2C_SIMR_STOPIM         0x00000004  ///< Stop Condition Interrupt Mask
    110. 

  110. #define I2C_SIMR_STARTIM        0x00000002  ///< Start Condition Interrupt Mask
    111. 

  111. #define I2C_SIMR_DATAIM         0x00000001  ///< Data Interrupt Mask
    112. 

  112. 

  113. 

  114. /* The following are defines for the bit fields in the I2C_O_SRIS register. */
    115. 

  115. #define I2C_SRIS_STOPRIS        0x00000004  ///< Stop Condition Raw Interrupt
    116. 

  116.                                             ///< Status
    117. 

  117. #define I2C_SRIS_STARTRIS       0x00000002  ///< Start Condition Raw Interrupt
    118. 

  118.                                             ///< Status
    119. 

  119. #define I2C_SRIS_DATARIS        0x00000001  ///< Data Raw Interrupt Status
    120. 

  120. 

  121. 

  122. /* The following are defines for the bit fields in the I2C_O_MIMR register. */
    123. 

  123. #define I2C_MIMR_IM             0x00000001  ///< Interrupt Mask
    124. 

  124. 

  125. 

  126. /* The following are defines for the bit fields in the I2C_O_MRIS register. */
    127. 

  127. #define I2C_MRIS_RIS            0x00000001  ///< Raw Interrupt Status
    128. 

  128. 

  129. /* The following are defines for the bit fields in the I2C_O_SMIS register. */
    130. 

  130. #define I2C_SMIS_STOPMIS        0x00000004  ///< Stop Condition Masked Interrupt
    131. 

  131.                                             ///< Status
    132. 

  132. #define I2C_SMIS_STARTMIS       0x00000002  ///< Start Condition Masked Interrupt
    133. 

  133.                                             ///< Status
    134. 

  134. #define I2C_SMIS_DATAMIS        0x00000001  ///< Data Masked Interrupt Status
    135. 

  135. 

  136. /* The following are defines for the bit fields in the I2C_O_SICR register. */
    137. 

  137. #define I2C_SICR_STOPIC         0x00000004  ///< Stop Condition Interrupt Clear
    138. 

  138. #define I2C_SICR_STARTIC        0x00000002  ///< Start Condition Interrupt Clear
    139. 

  139. #define I2C_SICR_DATAIC         0x00000001  ///< Data Interrupt Clear
    140. 

  140. 

  141. /* The following are defines for the bit fields in the I2C_O_MMIS register. */
    142. 

  142. #define I2C_MMIS_MIS            0x00000001  ///< Masked Interrupt Status
    143. 

  143. 

  144. 

  145. /* The following are defines for the bit fields in the I2C_O_MICR register. */
    146. 

  146. #define I2C_MICR_IC             0x00000001  ///< Interrupt Clear
    147. 

  147. 

  148. 

  149. /* The following are defines for the bit fields in the I2C_O_MCR register. */
    150. 

  150. #define I2C_MCR_SFE             0x00000020  ///< I2C Slave Function Enable
    151. 

  151. #define I2C_MCR_MFE             0x00000010  ///< I2C Master Function Enable
    152. 

  152. #define I2C_MCR_LPBK            0x00000001  ///< I2C Loopback
    153. 

  153. 

  154. 

  155. 

  156. #define I2C_MASTER_CMD_SINGLE_SEND                     0x00000007
    157. 

  157. #define I2C_MASTER_CMD_SINGLE_RECEIVE                  0x00000007
    158. 

  158. 

  159. #define I2C_MASTER_CMD_BURST_SEND_START                0x00000003
    160. 

  160. #define I2C_MASTER_CMD_BURST_SEND_CONT                 0x00000001
    161. 

  161. #define I2C_MASTER_CMD_BURST_SEND_FINISH               0x00000005
    162. 

  162. #define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP           0x00000004
    163. 

  163. 

  164. #define I2C_MASTER_CMD_BURST_RECEIVE_START             0x0000000b
    165. 

  165. #define I2C_MASTER_CMD_BURST_RECEIVE_CONT              0x00000009
    166. 

  166. #define I2C_MASTER_CMD_BURST_RECEIVE_FINISH            0x00000005
    167. 

  167. #define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP        0x00000004
    168. 

  168. 

  169. 

  170. /* The following definitions are deprecated. */
    171. 

  171. 

  172. #ifndef DEPRECATED
    173. 

  173. 

  174. 	#define I2C_O_SLAVE             0x00000800  ///< Offset from master to slave
    175. 

  175. 

  176. 	#define I2C_SIMR_IM             0x00000001  ///< Interrupt Mask
    177. 

  177. 

  178. 	#define I2C_SRIS_RIS            0x00000001  ///< Raw Interrupt Status
    179. 

  179. 

  180. 	#define I2C_SMIS_MIS            0x00000001  ///< Masked Interrupt Status
    181. 

  181. 

  182. 	#define I2C_SICR_IC             0x00000001  ///< Clear Interrupt
    183. 

  183. 

  184. 	#define I2C_MASTER_O_SA         0x00000000  ///< Slave address register
    185. 

  185. 	#define I2C_MASTER_O_CS         0x00000004  ///< Control and Status register
    186. 

  186. 	#define I2C_MASTER_O_DR         0x00000008  ///< Data register
    187. 

  187. 	#define I2C_MASTER_O_TPR        0x0000000C  ///< Timer period register
    188. 

  188. 	#define I2C_MASTER_O_IMR        0x00000010  ///< Interrupt mask register
    189. 

  189. 	#define I2C_MASTER_O_RIS        0x00000014  ///< Raw interrupt status register
    190. 

  190. 	#define I2C_MASTER_O_MIS        0x00000018  ///< Masked interrupt status reg
    191. 

  191. 	#define I2C_MASTER_O_MICR       0x0000001C  ///< Interrupt clear register
    192. 

  192. 	#define I2C_MASTER_O_CR         0x00000020  ///< Configuration register
    193. 

  193. 

  194. 	#define I2C_SLAVE_O_SICR        0x00000018  ///< Interrupt clear register
    195. 

  195. 	#define I2C_SLAVE_O_MIS         0x00000014  ///< Masked interrupt status reg
    196. 

  196. 	#define I2C_SLAVE_O_RIS         0x00000010  ///< Raw interrupt status register
    197. 

  197. 	#define I2C_SLAVE_O_IM          0x0000000C  ///< Interrupt mask register
    198. 

  198. 	#define I2C_SLAVE_O_DR          0x00000008  ///< Data register
    199. 

  199. 	#define I2C_SLAVE_O_CSR         0x00000004  ///< Control/Status register
    200. 

  200. 	#define I2C_SLAVE_O_OAR         0x00000000  ///< Own address register
    201. 

  201. 

  202. 	#define I2C_MASTER_SA_SA_MASK   0x000000FE  ///< Slave address
    203. 

  203. 	#define I2C_MASTER_SA_RS        0x00000001  ///< Receive/send
    204. 

  204. 	#define I2C_MASTER_SA_SA_SHIFT  1
    205. 

  205. 

  206. 	#define I2C_MASTER_CS_BUS_BUSY  0x00000040  ///< Bus busy
    207. 

  207. 	#define I2C_MASTER_CS_IDLE      0x00000020  ///< Idle
    208. 

  208. 	#define I2C_MASTER_CS_ERR_MASK  0x0000001C
    209. 

  209. 	#define I2C_MASTER_CS_BUSY      0x00000001  ///< Controller is TX/RX data
    210. 

  210. 	#define I2C_MASTER_CS_ERROR     0x00000002  ///< Error occurred
    211. 

  211. 	#define I2C_MASTER_CS_ADDR_ACK  0x00000004  ///< Address byte not acknowledged
    212. 

  212. 	#define I2C_MASTER_CS_DATA_ACK  0x00000008  ///< Data byte not acknowledged
    213. 

  213. 	#define I2C_MASTER_CS_ARB_LOST  0x00000010  ///< Lost arbitration
    214. 

  214. 	#define I2C_MASTER_CS_ACK       0x00000008  ///< Acknowlegde
    215. 

  215. 	#define I2C_MASTER_CS_STOP      0x00000004  ///< Stop
    216. 

  216. 	#define I2C_MASTER_CS_START     0x00000002  ///< Start
    217. 

  217. 	#define I2C_MASTER_CS_RUN       0x00000001  ///< Run
    218. 

  218. 

  219. 

  220. 	#define I2C_SCL_FAST            400000      ///< SCL fast frequency
    221. 

  221. 	#define I2C_SCL_STANDARD        100000      ///< SCL standard frequency
    222. 

  222. 	#define I2C_MASTER_TPR_SCL_LP   0x00000006  ///< SCL low period
    223. 

  223. 	#define I2C_MASTER_TPR_SCL_HP   0x00000004  ///< SCL high period
    224. 

  224. 	#define I2C_MASTER_TPR_SCL      (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
    225. 

  225. 

  226. 	#define I2C_MASTER_IMR_IM       0x00000001  ///< Master interrupt mask
    227. 

  227. 

  228. 	#define I2C_MASTER_RIS_RIS      0x00000001  ///< Master raw interrupt status
    229. 

  229. 

  230. 	#define I2C_MASTER_MIS_MIS      0x00000001  ///< Master masked interrupt status
    231. 

  231. 

  232. 	#define I2C_MASTER_MICR_IC      0x00000001  ///< Master interrupt clear
    233. 

  233. 

  234. 	#define I2C_MASTER_CR_SFE       0x00000020  ///< Slave function enable
    235. 

  235. 	#define I2C_MASTER_CR_MFE       0x00000010  ///< Master function enable
    236. 

  236. 	#define I2C_MASTER_CR_LPBK      0x00000001  ///< Loopback enable
    237. 

  237. 

  238. 	#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  ///< Slave address
    239. 

  239. 

  240. 	#define I2C_SLAVE_CSR_FBR       0x00000004  ///< First byte received from master
    241. 

  241. 	#define I2C_SLAVE_CSR_TREQ      0x00000002  ///< Transmit request received
    242. 

  242. 	#define I2C_SLAVE_CSR_DA        0x00000001  ///< Enable the device
    243. 

  243. 	#define I2C_SLAVE_CSR_RREQ      0x00000001  ///< Receive data from I2C master
    244. 

  244. 

  245. 	#define I2C_SLAVE_IMR_IM        0x00000001  ///< Slave interrupt mask
    246. 

  246. 

  247. 	#define I2C_SLAVE_RIS_RIS       0x00000001  ///< Slave raw interrupt status
    248. 

  248. 

  249. 	#define I2C_SLAVE_MIS_MIS       0x00000001  ///< Slave masked interrupt status
    250. 

  250. 

  251. 	#define I2C_SLAVE_SICR_IC       0x00000001  ///< Slave interrupt clear
    252. 

  252. 

  253. #endif
    254. 

  254. 

  255. #endif /* LM3S_I2C_H */
    256.