/u-boot/board/bf537-stamp/post-memory.c

https://github.com/cAPSLOCK7/EVBSP-SRC · C · 321 lines · 278 code · 35 blank · 8 comment · 65 complexity · 46083b0ad2e41dba5fa9c6a024217088 MD5 · raw file 

    

  1. #include <common.h>
    2. 

  2. #include <asm/io.h>
    3. 

  3. 

  4. #ifdef CONFIG_POST
    5. 

  5. 

  6. #include <post.h>
    7. 

  7. #include <watchdog.h>
    8. 

  8. 

  9. #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
    10. 

  10. #define CLKIN 25000000
    11. 

  11. #define PATTERN1 0x5A5A5A5A
    12. 

  12. #define PATTERN2 0xAAAAAAAA
    13. 

  13. 

  14. #define CCLK_NUM	4
    15. 

  15. #define SCLK_NUM	3
    16. 

  16. 

  17. void post_out_buff(char *buff);
    18. 

  18. int post_key_pressed(void);
    19. 

  19. void post_init_pll(int mult, int div);
    20. 

  20. int post_init_sdram(int sclk);
    21. 

  21. void post_init_uart(int sclk);
    22. 

  22. 

  23. const int pll[CCLK_NUM][SCLK_NUM][2] = {
    24. 

  24. 	{ {20, 4}, {20, 5}, {20, 10} },	/* CCLK = 500M */
    25. 

  25. 	{ {16, 4}, {16, 5}, {16, 8} },	/* CCLK = 400M */
    26. 

  26. 	{ {8, 2}, {8, 4}, {8, 5} },	/* CCLK = 200M */
    27. 

  27. 	{ {4, 1}, {4, 2}, {4, 4} }	/* CCLK = 100M */
    28. 

  28. };
    29. 

  29. const char *const log[CCLK_NUM][SCLK_NUM] = {
    30. 

  30. 	{"CCLK-500MHz SCLK-125MHz:    Writing...\0",
    31. 

  31. 	 "CCLK-500MHz SCLK-100MHz:    Writing...\0",
    32. 

  32. 	 "CCLK-500MHz SCLK- 50MHz:    Writing...\0",},
    33. 

  33. 	{"CCLK-400MHz SCLK-100MHz:    Writing...\0",
    34. 

  34. 	 "CCLK-400MHz SCLK- 80MHz:    Writing...\0",
    35. 

  35. 	 "CCLK-400MHz SCLK- 50MHz:    Writing...\0",},
    36. 

  36. 	{"CCLK-200MHz SCLK-100MHz:    Writing...\0",
    37. 

  37. 	 "CCLK-200MHz SCLK- 50MHz:    Writing...\0",
    38. 

  38. 	 "CCLK-200MHz SCLK- 40MHz:    Writing...\0",},
    39. 

  39. 	{"CCLK-100MHz SCLK-100MHz:    Writing...\0",
    40. 

  40. 	 "CCLK-100MHz SCLK- 50MHz:    Writing...\0",
    41. 

  41. 	 "CCLK-100MHz SCLK- 25MHz:    Writing...\0",},
    42. 

  42. };
    43. 

  43. 

  44. int memory_post_test(int flags)
    45. 

  45. {
    46. 

  46. 	int addr;
    47. 

  47. 	int m, n;
    48. 

  48. 	int sclk, sclk_temp;
    49. 

  49. 	int ret = 1;
    50. 

  50. 

  51. 	sclk_temp = CLKIN / 1000000;
    52. 

  52. 	sclk_temp = sclk_temp * CONFIG_VCO_MULT;
    53. 

  53. 	for (sclk = 0; sclk_temp > 0; sclk++)
    54. 

  54. 		sclk_temp -= CONFIG_SCLK_DIV;
    55. 

  55. 	sclk = sclk * 1000000;
    56. 

  56. 	post_init_uart(sclk);
    57. 

  57. 	if (post_key_pressed() == 0)
    58. 

  58. 		return 0;
    59. 

  59. 

  60. 	for (m = 0; m < CCLK_NUM; m++) {
    61. 

  61. 		for (n = 0; n < SCLK_NUM; n++) {
    62. 

  62. 			/* Calculate the sclk */
    63. 

  63. 			sclk_temp = CLKIN / 1000000;
    64. 

  64. 			sclk_temp = sclk_temp * pll[m][n][0];
    65. 

  65. 			for (sclk = 0; sclk_temp > 0; sclk++)
    66. 

  66. 				sclk_temp -= pll[m][n][1];
    67. 

  67. 			sclk = sclk * 1000000;
    68. 

  68. 

  69. 			post_init_pll(pll[m][n][0], pll[m][n][1]);
    70. 

  70. 			post_init_sdram(sclk);
    71. 

  71. 			post_init_uart(sclk);
    72. 

  72. 			post_out_buff("\n\r\0");
    73. 

  73. 			post_out_buff(log[m][n]);
    74. 

  74. 			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
    75. 

  75. 				*(unsigned long *)addr = PATTERN1;
    76. 

  76. 			post_out_buff("Reading...\0");
    77. 

  77. 			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
    78. 

  78. 				if ((*(unsigned long *)addr) != PATTERN1) {
    79. 

  79. 					post_out_buff("Error\n\r\0");
    80. 

  80. 					ret = 0;
    81. 

  81. 				}
    82. 

  82. 			}
    83. 

  83. 			post_out_buff("OK\n\r\0");
    84. 

  84. 		}
    85. 

  85. 	}
    86. 

  86. 	if (ret)
    87. 

  87. 		post_out_buff("memory POST passed\n\r\0");
    88. 

  88. 	else
    89. 

  89. 		post_out_buff("memory POST failed\n\r\0");
    90. 

  90. 

  91. 	post_out_buff("\n\r\n\r\0");
    92. 

  92. 	return 1;
    93. 

  93. }
    94. 

  94. 

  95. void post_init_uart(int sclk)
    96. 

  96. {
    97. 

  97. 	int divisor;
    98. 

  98. 

  99. 	for (divisor = 0; sclk > 0; divisor++)
    100. 

  100. 		sclk -= 57600 * 16;
    101. 

  101. 

  102. 	*pPORTF_FER = 0x000F;
    103. 

  103. 	*pPORTH_FER = 0xFFFF;
    104. 

  104. 

  105. 	*pUART_GCTL = 0x00;
    106. 

  106. 	*pUART_LCR = 0x83;
    107. 

  107. 	SSYNC();
    108. 

  108. 	*pUART_DLL = (divisor & 0xFF);
    109. 

  109. 	SSYNC();
    110. 

  110. 	*pUART_DLH = ((divisor >> 8) & 0xFF);
    111. 

  111. 	SSYNC();
    112. 

  112. 	*pUART_LCR = 0x03;
    113. 

  113. 	SSYNC();
    114. 

  114. 	*pUART_GCTL = 0x01;
    115. 

  115. 	SSYNC();
    116. 

  116. }
    117. 

  117. 

  118. void post_out_buff(char *buff)
    119. 

  119. {
    120. 

  120. 

  121. 	int i = 0;
    122. 

  122. 	for (i = 0; i < 0x80000; i++)
    123. 

  123. 		;
    124. 

  124. 	i = 0;
    125. 

  125. 	while ((buff[i] != '\0') && (i != 100)) {
    126. 

  126. 		while (!(*pUART_LSR & 0x20)) ;
    127. 

  127. 		*pUART_THR = buff[i];
    128. 

  128. 		SSYNC();
    129. 

  129. 		i++;
    130. 

  130. 	}
    131. 

  131. 	for (i = 0; i < 0x80000; i++)
    132. 

  132. 		;
    133. 

  133. }
    134. 

  134. 

  135. /* Using sw10-PF5 as the hotkey */
    136. 

  136. #define KEY_LOOP 0x80000
    137. 

  137. #define KEY_DELAY 0x80
    138. 

  138. int post_key_pressed(void)
    139. 

  139. {
    140. 

  140. 	int i, n;
    141. 

  141. 	unsigned short value;
    142. 

  142. 

  143. 	*pPORTF_FER &= ~PF5;
    144. 

  144. 	*pPORTFIO_DIR &= ~PF5;
    145. 

  145. 	*pPORTFIO_INEN |= PF5;
    146. 

  146. 	SSYNC();
    147. 

  147. 

  148. 	post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
    149. 

  149. 	for (i = 0; i < KEY_LOOP; i++) {
    150. 

  150. 		value = *pPORTFIO & PF5;
    151. 

  151. 		if (*pUART0_RBR == 0x0D) {
    152. 

  152. 			value = 0;
    153. 

  153. 			goto key_pressed;
    154. 

  154. 		}
    155. 

  155. 		if (value != 0)
    156. 

  156. 			goto key_pressed;
    157. 

  157. 		for (n = 0; n < KEY_DELAY; n++)
    158. 

  158. 			asm("nop");
    159. 

  159. 	}
    160. 

  160. 	post_out_buff("\b2\0");
    161. 

  161. 

  162. 	for (i = 0; i < KEY_LOOP; i++) {
    163. 

  163. 		value = *pPORTFIO & PF5;
    164. 

  164. 		if (*pUART0_RBR == 0x0D) {
    165. 

  165. 			value = 0;
    166. 

  166. 			goto key_pressed;
    167. 

  167. 		}
    168. 

  168. 		if (value != 0)
    169. 

  169. 			goto key_pressed;
    170. 

  170. 		for (n = 0; n < KEY_DELAY; n++)
    171. 

  171. 			asm("nop");
    172. 

  172. 	}
    173. 

  173. 	post_out_buff("\b1\0");
    174. 

  174. 

  175. 	for (i = 0; i < KEY_LOOP; i++) {
    176. 

  176. 		value = *pPORTFIO & PF5;
    177. 

  177. 		if (*pUART0_RBR == 0x0D) {
    178. 

  178. 			value = 0;
    179. 

  179. 			goto key_pressed;
    180. 

  180. 		}
    181. 

  181. 		if (value != 0)
    182. 

  182. 			goto key_pressed;
    183. 

  183. 		for (n = 0; n < KEY_DELAY; n++)
    184. 

  184. 			asm("nop");
    185. 

  185. 	}
    186. 

  186.       key_pressed:
    187. 

  187. 	post_out_buff("\b0");
    188. 

  188. 	post_out_buff("\n\r\0");
    189. 

  189. 	if (value == 0)
    190. 

  190. 		return 0;
    191. 

  191. 	post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
    192. 

  192. 	return 1;
    193. 

  193. }
    194. 

  194. 

  195. void post_init_pll(int mult, int div)
    196. 

  196. {
    197. 

  197. 

  198. 	*pSIC_IWR = 0x01;
    199. 

  199. 	*pPLL_CTL = (mult << 9);
    200. 

  200. 	*pPLL_DIV = div;
    201. 

  201. 	asm("CLI R2;");
    202. 

  202. 	asm("IDLE;");
    203. 

  203. 	asm("STI R2;");
    204. 

  204. 	while (!(*pPLL_STAT & 0x20)) ;
    205. 

  205. }
    206. 

  206. 

  207. int post_init_sdram(int sclk)
    208. 

  208. {
    209. 

  209. 	int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
    210. 

  210. 	    SDRAM_tWR;
    211. 

  211. 	int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
    212. 

  212. 	    mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
    213. 

  213. 

  214. 	if ((sclk > 119402985)) {
    215. 

  215. 		SDRAM_tRP = TRP_2;
    216. 

  216. 		SDRAM_tRP_num = 2;
    217. 

  217. 		SDRAM_tRAS = TRAS_7;
    218. 

  218. 		SDRAM_tRAS_num = 7;
    219. 

  219. 		SDRAM_tRCD = TRCD_2;
    220. 

  220. 		SDRAM_tWR = TWR_2;
    221. 

  221. 	} else if ((sclk > 104477612) && (sclk <= 119402985)) {
    222. 

  222. 		SDRAM_tRP = TRP_2;
    223. 

  223. 		SDRAM_tRP_num = 2;
    224. 

  224. 		SDRAM_tRAS = TRAS_6;
    225. 

  225. 		SDRAM_tRAS_num = 6;
    226. 

  226. 		SDRAM_tRCD = TRCD_2;
    227. 

  227. 		SDRAM_tWR = TWR_2;
    228. 

  228. 	} else if ((sclk > 89552239) && (sclk <= 104477612)) {
    229. 

  229. 		SDRAM_tRP = TRP_2;
    230. 

  230. 		SDRAM_tRP_num = 2;
    231. 

  231. 		SDRAM_tRAS = TRAS_5;
    232. 

  232. 		SDRAM_tRAS_num = 5;
    233. 

  233. 		SDRAM_tRCD = TRCD_2;
    234. 

  234. 		SDRAM_tWR = TWR_2;
    235. 

  235. 	} else if ((sclk > 74626866) && (sclk <= 89552239)) {
    236. 

  236. 		SDRAM_tRP = TRP_2;
    237. 

  237. 		SDRAM_tRP_num = 2;
    238. 

  238. 		SDRAM_tRAS = TRAS_4;
    239. 

  239. 		SDRAM_tRAS_num = 4;
    240. 

  240. 		SDRAM_tRCD = TRCD_2;
    241. 

  241. 		SDRAM_tWR = TWR_2;
    242. 

  242. 	} else if ((sclk > 66666667) && (sclk <= 74626866)) {
    243. 

  243. 		SDRAM_tRP = TRP_2;
    244. 

  244. 		SDRAM_tRP_num = 2;
    245. 

  245. 		SDRAM_tRAS = TRAS_3;
    246. 

  246. 		SDRAM_tRAS_num = 3;
    247. 

  247. 		SDRAM_tRCD = TRCD_2;
    248. 

  248. 		SDRAM_tWR = TWR_2;
    249. 

  249. 	} else if ((sclk > 59701493) && (sclk <= 66666667)) {
    250. 

  250. 		SDRAM_tRP = TRP_1;
    251. 

  251. 		SDRAM_tRP_num = 1;
    252. 

  252. 		SDRAM_tRAS = TRAS_4;
    253. 

  253. 		SDRAM_tRAS_num = 4;
    254. 

  254. 		SDRAM_tRCD = TRCD_1;
    255. 

  255. 		SDRAM_tWR = TWR_2;
    256. 

  256. 	} else if ((sclk > 44776119) && (sclk <= 59701493)) {
    257. 

  257. 		SDRAM_tRP = TRP_1;
    258. 

  258. 		SDRAM_tRP_num = 1;
    259. 

  259. 		SDRAM_tRAS = TRAS_3;
    260. 

  260. 		SDRAM_tRAS_num = 3;
    261. 

  261. 		SDRAM_tRCD = TRCD_1;
    262. 

  262. 		SDRAM_tWR = TWR_2;
    263. 

  263. 	} else if ((sclk > 29850746) && (sclk <= 44776119)) {
    264. 

  264. 		SDRAM_tRP = TRP_1;
    265. 

  265. 		SDRAM_tRP_num = 1;
    266. 

  266. 		SDRAM_tRAS = TRAS_2;
    267. 

  267. 		SDRAM_tRAS_num = 2;
    268. 

  268. 		SDRAM_tRCD = TRCD_1;
    269. 

  269. 		SDRAM_tWR = TWR_2;
    270. 

  270. 	} else if (sclk <= 29850746) {
    271. 

  271. 		SDRAM_tRP = TRP_1;
    272. 

  272. 		SDRAM_tRP_num = 1;
    273. 

  273. 		SDRAM_tRAS = TRAS_1;
    274. 

  274. 		SDRAM_tRAS_num = 1;
    275. 

  275. 		SDRAM_tRCD = TRCD_1;
    276. 

  276. 		SDRAM_tWR = TWR_2;
    277. 

  277. 	} else {
    278. 

  278. 		SDRAM_tRP = TRP_1;
    279. 

  279. 		SDRAM_tRP_num = 1;
    280. 

  280. 		SDRAM_tRAS = TRAS_1;
    281. 

  281. 		SDRAM_tRAS_num = 1;
    282. 

  282. 		SDRAM_tRCD = TRCD_1;
    283. 

  283. 		SDRAM_tWR = TWR_2;
    284. 

  284. 	}
    285. 

  285. 	/*SDRAM INFORMATION: */
    286. 

  286. 	SDRAM_Tref = 64;	/* Refresh period in milliseconds */
    287. 

  287. 	SDRAM_NRA = 4096;	/* Number of row addresses in SDRAM */
    288. 

  288. 	SDRAM_CL = CL_3;	/* 2 */
    289. 

  289. 

  290. 	SDRAM_SIZE = EBSZ_64;
    291. 

  291. 	SDRAM_WIDTH = EBCAW_10;
    292. 

  292. 

  293. 	mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
    294. 

  294. 

  295. 	/* Equation from section 17 (p17-46) of BF533 HRM */
    296. 

  296. 	mem_SDRRC =
    297. 

  297. 	    (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
    298. 

  298. 	    (SDRAM_tRAS_num + SDRAM_tRP_num);
    299. 

  299. 

  300. 	/* Enable SCLK Out */
    301. 

  301. 	mem_SDGCTL =
    302. 

  302. 	    (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
    303. 

  303. 	     | PSS);
    304. 

  304. 

  305. 	SSYNC();
    306. 

  306. 

  307. 	*pEBIU_SDGCTL |= 0x1000000;
    308. 

  308. 	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
    309. 

  309. 	*pEBIU_SDRRC = mem_SDRRC;
    310. 

  310. 

  311. 	/* SDRAM Memory Bank Control Register */
    312. 

  312. 	*pEBIU_SDBCTL = mem_SDBCTL;
    313. 

  313. 

  314. 	/* SDRAM Memory Global Control Register */
    315. 

  315. 	*pEBIU_SDGCTL = mem_SDGCTL;
    316. 

  316. 	SSYNC();
    317. 

  317. 	return mem_SDRRC;
    318. 

  318. }
    319. 

  319. 

  320. #endif				/* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
    321. 

  321. #endif				/* CONFIG_POST */
    322.