/arch/arm/nxt/AT91SAM7.h

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  1. // ----------------------------------------------------------------------------
    2. 

  2. //          ATMEL Microcontroller Software Support  -  ROUSSET  -
    3. 

  3. // ----------------------------------------------------------------------------
    4. 

  4. //  The software is delivered "AS IS" without warranty or condition of any
    5. 

  5. //  kind, either express, implied or statutory. This includes without
    6. 

  6. //  limitation any warranty or condition with respect to merchantability or
    7. 

  7. //  fitness for any particular purpose, or against the infringements of
    8. 

  8. //  intellectual property rights of others.
    9. 

  9. // ----------------------------------------------------------------------------
    10. 

  10. // File Name           : AT91SAM7S64.h
    11. 

  11. // Object              : AT91SAM7S64 definitions
    12. 

  12. // Generated           : AT91 SW Application Group  09/01/2004 (10:02:06)
    13. 

  13. // 
    14. 

  14. // CVS Reference       : /AT91SAM7S64.pl/1.15/Mon Aug 30 08:48:08 2004//
    15. 

  15. // CVS Reference       : /SYS_SAM7Sxxx.pl/1.5/Mon Aug 30 13:17:50 2004//
    16. 

  16. // CVS Reference       : /MC_SAM02.pl/1.3/Mon Mar 08 09:22:24 2004//
    17. 

  17. // CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//
    18. 

  18. // CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
    19. 

  19. // CVS Reference       : /PMC_SAM.pl/1.10/Mon May 10 12:08:48 2004//
    20. 

  20. // CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
    21. 

  21. // CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
    22. 

  22. // CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:26 2002//
    23. 

  23. // CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
    24. 

  24. // CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:40 2002//
    25. 

  25. // CVS Reference       : /TC_1753B.pl/1.4/Mon Mar 01 14:10:12 2004//
    26. 

  26. // CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:08 2003//
    27. 

  27. // CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
    28. 

  28. // CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
    29. 

  29. // CVS Reference       : /PWM_SAM.pl/1.5/Wed Apr 14 12:02:52 2004//
    30. 

  30. // ----------------------------------------------------------------------------
    31. 

  31. 

  32. #ifndef AT91SAM7S64_H
    33. 

  33. #  define AT91SAM7S64_H
    34. 

  34. 

  35. #  define CLOCK_FREQUENCY 48000000
    36. 

  36. 

  37. 

  38. 

  39. // AIC peripheral ids
    40. 

  40. #  define AT91C_PERIPHERAL_ID_FIQ		0
    41. 

  41. #  define AT91C_PERIPHERAL_ID_SYSIRQ	1
    42. 

  42. #  define AT91C_PERIPHERAL_ID_PIOA		2
    43. 

  43. #  define AT91C_PERIPHERAL_ID_ADC		4
    44. 

  44. #  define AT91C_PERIPHERAL_ID_SPI		5
    45. 

  45. #  define AT91C_PERIPHERAL_ID_US0		6
    46. 

  46. #  define AT91C_PERIPHERAL_ID_US1		7
    47. 

  47. #  define AT91C_PERIPHERAL_ID_SSC		8
    48. 

  48. #  define AT91C_PERIPHERAL_ID_TWI		9
    49. 

  49. #  define AT91C_PERIPHERAL_ID_PWMC		10
    50. 

  50. #  define AT91C_PERIPHERAL_ID_UDP		11
    51. 

  51. #  define AT91C_PERIPHERAL_ID_TC0		12
    52. 

  52. #  define AT91C_PERIPHERAL_ID_TC1		13
    53. 

  53. #  define AT91C_PERIPHERAL_ID_TC2		14
    54. 

  54. #  define AT91C_PERIPHERAL_ID_IRQ0		30
    55. 

  55. #  define AT91C_PERIPHERAL_ID_IRQ1		31
    56. 

  56. 

  57. 

  58. typedef volatile unsigned int AT91_REG;	// Hardware register definition
    59. 

  59. 

  60. // *****************************************************************************
    61. 

  61. //              SOFTWARE API DEFINITION  FOR System Peripherals
    62. 

  62. // *****************************************************************************
    63. 

  63. typedef struct _AT91S_SYSC {
    64. 

  64.   AT91_REG SYSC_AIC_SMR[32];	// Source Mode Register
    65. 

  65.   AT91_REG SYSC_AIC_SVR[32];	// Source Vector Register
    66. 

  66.   AT91_REG SYSC_AIC_IVR;	// IRQ Vector Register
    67. 

  67.   AT91_REG SYSC_AIC_FVR;	// FIQ Vector Register
    68. 

  68.   AT91_REG SYSC_AIC_ISR;	// Interrupt Status Register
    69. 

  69.   AT91_REG SYSC_AIC_IPR;	// Interrupt Pending Register
    70. 

  70.   AT91_REG SYSC_AIC_IMR;	// Interrupt Mask Register
    71. 

  71.   AT91_REG SYSC_AIC_CISR;	// Core Interrupt Status Register
    72. 

  72.   AT91_REG Reserved0[2];	// 
    73. 

  73.   AT91_REG SYSC_AIC_IECR;	// Interrupt Enable Command Register
    74. 

  74.   AT91_REG SYSC_AIC_IDCR;	// Interrupt Disable Command Register
    75. 

  75.   AT91_REG SYSC_AIC_ICCR;	// Interrupt Clear Command Register
    76. 

  76.   AT91_REG SYSC_AIC_ISCR;	// Interrupt Set Command Register
    77. 

  77.   AT91_REG SYSC_AIC_EOICR;	// End of Interrupt Command Register
    78. 

  78.   AT91_REG SYSC_AIC_SPU;	// Spurious Vector Register
    79. 

  79.   AT91_REG SYSC_AIC_DCR;	// Debug Control Register (Protect)
    80. 

  80.   AT91_REG Reserved1[1];	// 
    81. 

  81.   AT91_REG SYSC_AIC_FFER;	// Fast Forcing Enable Register
    82. 

  82.   AT91_REG SYSC_AIC_FFDR;	// Fast Forcing Disable Register
    83. 

  83.   AT91_REG SYSC_AIC_FFSR;	// Fast Forcing Status Register
    84. 

  84.   AT91_REG Reserved2[45];	// 
    85. 

  85.   AT91_REG SYSC_DBGU_CR;	// Control Register
    86. 

  86.   AT91_REG SYSC_DBGU_MR;	// Mode Register
    87. 

  87.   AT91_REG SYSC_DBGU_IER;	// Interrupt Enable Register
    88. 

  88.   AT91_REG SYSC_DBGU_IDR;	// Interrupt Disable Register
    89. 

  89.   AT91_REG SYSC_DBGU_IMR;	// Interrupt Mask Register
    90. 

  90.   AT91_REG SYSC_DBGU_CSR;	// Channel Status Register
    91. 

  91.   AT91_REG SYSC_DBGU_RHR;	// Receiver Holding Register
    92. 

  92.   AT91_REG SYSC_DBGU_THR;	// Transmitter Holding Register
    93. 

  93.   AT91_REG SYSC_DBGU_BRGR;	// Baud Rate Generator Register
    94. 

  94.   AT91_REG Reserved3[7];	// 
    95. 

  95.   AT91_REG SYSC_DBGU_C1R;	// Chip ID1 Register
    96. 

  96.   AT91_REG SYSC_DBGU_C2R;	// Chip ID2 Register
    97. 

  97.   AT91_REG SYSC_DBGU_FNTR;	// Force NTRST Register
    98. 

  98.   AT91_REG Reserved4[45];	// 
    99. 

  99.   AT91_REG SYSC_DBGU_RPR;	// Receive Pointer Register
    100. 

  100.   AT91_REG SYSC_DBGU_RCR;	// Receive Counter Register
    101. 

  101.   AT91_REG SYSC_DBGU_TPR;	// Transmit Pointer Register
    102. 

  102.   AT91_REG SYSC_DBGU_TCR;	// Transmit Counter Register
    103. 

  103.   AT91_REG SYSC_DBGU_RNPR;	// Receive Next Pointer Register
    104. 

  104.   AT91_REG SYSC_DBGU_RNCR;	// Receive Next Counter Register
    105. 

  105.   AT91_REG SYSC_DBGU_TNPR;	// Transmit Next Pointer Register
    106. 

  106.   AT91_REG SYSC_DBGU_TNCR;	// Transmit Next Counter Register
    107. 

  107.   AT91_REG SYSC_DBGU_PTCR;	// PDC Transfer Control Register
    108. 

  108.   AT91_REG SYSC_DBGU_PTSR;	// PDC Transfer Status Register
    109. 

  109.   AT91_REG Reserved5[54];	// 
    110. 

  110.   AT91_REG SYSC_PIOA_PER;	// PIO Enable Register
    111. 

  111.   AT91_REG SYSC_PIOA_PDR;	// PIO Disable Register
    112. 

  112.   AT91_REG SYSC_PIOA_PSR;	// PIO Status Register
    113. 

  113.   AT91_REG Reserved6[1];	// 
    114. 

  114.   AT91_REG SYSC_PIOA_OER;	// Output Enable Register
    115. 

  115.   AT91_REG SYSC_PIOA_ODR;	// Output Disable Registerr
    116. 

  116.   AT91_REG SYSC_PIOA_OSR;	// Output Status Register
    117. 

  117.   AT91_REG Reserved7[1];	// 
    118. 

  118.   AT91_REG SYSC_PIOA_IFER;	// Input Filter Enable Register
    119. 

  119.   AT91_REG SYSC_PIOA_IFDR;	// Input Filter Disable Register
    120. 

  120.   AT91_REG SYSC_PIOA_IFSR;	// Input Filter Status Register
    121. 

  121.   AT91_REG Reserved8[1];	// 
    122. 

  122.   AT91_REG SYSC_PIOA_SODR;	// Set Output Data Register
    123. 

  123.   AT91_REG SYSC_PIOA_CODR;	// Clear Output Data Register
    124. 

  124.   AT91_REG SYSC_PIOA_ODSR;	// Output Data Status Register
    125. 

  125.   AT91_REG SYSC_PIOA_PDSR;	// Pin Data Status Register
    126. 

  126.   AT91_REG SYSC_PIOA_IER;	// Interrupt Enable Register
    127. 

  127.   AT91_REG SYSC_PIOA_IDR;	// Interrupt Disable Register
    128. 

  128.   AT91_REG SYSC_PIOA_IMR;	// Interrupt Mask Register
    129. 

  129.   AT91_REG SYSC_PIOA_ISR;	// Interrupt Status Register
    130. 

  130.   AT91_REG SYSC_PIOA_MDER;	// Multi-driver Enable Register
    131. 

  131.   AT91_REG SYSC_PIOA_MDDR;	// Multi-driver Disable Register
    132. 

  132.   AT91_REG SYSC_PIOA_MDSR;	// Multi-driver Status Register
    133. 

  133.   AT91_REG Reserved9[1];	// 
    134. 

  134.   AT91_REG SYSC_PIOA_PPUDR;	// Pull-up Disable Register
    135. 

  135.   AT91_REG SYSC_PIOA_PPUER;	// Pull-up Enable Register
    136. 

  136.   AT91_REG SYSC_PIOA_PPUSR;	// Pad Pull-up Status Register
    137. 

  137.   AT91_REG Reserved10[1];	// 
    138. 

  138.   AT91_REG SYSC_PIOA_ASR;	// Select A Register
    139. 

  139.   AT91_REG SYSC_PIOA_BSR;	// Select B Register
    140. 

  140.   AT91_REG SYSC_PIOA_ABSR;	// AB Select Status Register
    141. 

  141.   AT91_REG Reserved11[9];	// 
    142. 

  142.   AT91_REG SYSC_PIOA_OWER;	// Output Write Enable Register
    143. 

  143.   AT91_REG SYSC_PIOA_OWDR;	// Output Write Disable Register
    144. 

  144.   AT91_REG SYSC_PIOA_OWSR;	// Output Write Status Register
    145. 

  145.   AT91_REG Reserved12[469];	// 
    146. 

  146.   AT91_REG SYSC_PMC_SCER;	// System Clock Enable Register
    147. 

  147.   AT91_REG SYSC_PMC_SCDR;	// System Clock Disable Register
    148. 

  148.   AT91_REG SYSC_PMC_SCSR;	// System Clock Status Register
    149. 

  149.   AT91_REG Reserved13[1];	// 
    150. 

  150.   AT91_REG SYSC_PMC_PCER;	// Peripheral Clock Enable Register
    151. 

  151.   AT91_REG SYSC_PMC_PCDR;	// Peripheral Clock Disable Register
    152. 

  152.   AT91_REG SYSC_PMC_PCSR;	// Peripheral Clock Status Register
    153. 

  153.   AT91_REG Reserved14[1];	// 
    154. 

  154.   AT91_REG SYSC_PMC_MOR;	// Main Oscillator Register
    155. 

  155.   AT91_REG SYSC_PMC_MCFR;	// Main Clock  Frequency Register
    156. 

  156.   AT91_REG Reserved15[1];	// 
    157. 

  157.   AT91_REG SYSC_PMC_PLLR;	// PLL Register
    158. 

  158.   AT91_REG SYSC_PMC_MCKR;	// Master Clock Register
    159. 

  159.   AT91_REG Reserved16[3];	// 
    160. 

  160.   AT91_REG SYSC_PMC_PCKR[8];	// Programmable Clock Register
    161. 

  161.   AT91_REG SYSC_PMC_IER;	// Interrupt Enable Register
    162. 

  162.   AT91_REG SYSC_PMC_IDR;	// Interrupt Disable Register
    163. 

  163.   AT91_REG SYSC_PMC_SR;		// Status Register
    164. 

  164.   AT91_REG SYSC_PMC_IMR;	// Interrupt Mask Register
    165. 

  165.   AT91_REG Reserved17[36];	// 
    166. 

  166.   AT91_REG SYSC_RSTC_RCR;	// Reset Control Register
    167. 

  167.   AT91_REG SYSC_RSTC_RSR;	// Reset Status Register
    168. 

  168.   AT91_REG SYSC_RSTC_RMR;	// Reset Mode Register
    169. 

  169.   AT91_REG Reserved18[5];	// 
    170. 

  170.   AT91_REG SYSC_RTTC_RTMR;	// Real-time Mode Register
    171. 

  171.   AT91_REG SYSC_RTTC_RTAR;	// Real-time Alarm Register
    172. 

  172.   AT91_REG SYSC_RTTC_RTVR;	// Real-time Value Register
    173. 

  173.   AT91_REG SYSC_RTTC_RTSR;	// Real-time Status Register
    174. 

  174.   AT91_REG SYSC_PITC_PIMR;	// Period Interval Mode Register
    175. 

  175.   AT91_REG SYSC_PITC_PISR;	// Period Interval Status Register
    176. 

  176.   AT91_REG SYSC_PITC_PIVR;	// Period Interval Value Register
    177. 

  177.   AT91_REG SYSC_PITC_PIIR;	// Period Interval Image Register
    178. 

  178.   AT91_REG SYSC_WDTC_WDCR;	// Watchdog Control Register
    179. 

  179.   AT91_REG SYSC_WDTC_WDMR;	// Watchdog Mode Register
    180. 

  180.   AT91_REG SYSC_WDTC_WDSR;	// Watchdog Status Register
    181. 

  181.   AT91_REG Reserved19[5];	// 
    182. 

  182.   AT91_REG SYSC_SYSC_VREG;	// Voltage Regulator Mode Register
    183. 

  183. } AT91S_SYSC, *AT91PS_SYSC;
    184. 

  184. 

  185. // -------- VREG : (SYSC Offset: 0xd60) Voltage Regulator Mode Register -------- 
    186. 

  186. #  define AT91C_SYSC_PSTDBY     ((unsigned int) 0x1 <<  0)	// (SYSC) Voltage Regulator Power Mode
    187. 

  187. 

  188. // *****************************************************************************
    189. 

  189. //              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
    190. 

  190. // *****************************************************************************
    191. 

  191. typedef struct _AT91S_AIC {
    192. 

  192.   AT91_REG AIC_SMR[32];		// Source Mode Register
    193. 

  193.   AT91_REG AIC_SVR[32];		// Source Vector Register
    194. 

  194.   AT91_REG AIC_IVR;		// IRQ Vector Register
    195. 

  195.   AT91_REG AIC_FVR;		// FIQ Vector Register
    196. 

  196.   AT91_REG AIC_ISR;		// Interrupt Status Register
    197. 

  197.   AT91_REG AIC_IPR;		// Interrupt Pending Register
    198. 

  198.   AT91_REG AIC_IMR;		// Interrupt Mask Register
    199. 

  199.   AT91_REG AIC_CISR;		// Core Interrupt Status Register
    200. 

  200.   AT91_REG Reserved0[2];	// 
    201. 

  201.   AT91_REG AIC_IECR;		// Interrupt Enable Command Register
    202. 

  202.   AT91_REG AIC_IDCR;		// Interrupt Disable Command Register
    203. 

  203.   AT91_REG AIC_ICCR;		// Interrupt Clear Command Register
    204. 

  204.   AT91_REG AIC_ISCR;		// Interrupt Set Command Register
    205. 

  205.   AT91_REG AIC_EOICR;		// End of Interrupt Command Register
    206. 

  206.   AT91_REG AIC_SPU;		// Spurious Vector Register
    207. 

  207.   AT91_REG AIC_DCR;		// Debug Control Register (Protect)
    208. 

  208.   AT91_REG Reserved1[1];	// 
    209. 

  209.   AT91_REG AIC_FFER;		// Fast Forcing Enable Register
    210. 

  210.   AT91_REG AIC_FFDR;		// Fast Forcing Disable Register
    211. 

  211.   AT91_REG AIC_FFSR;		// Fast Forcing Status Register
    212. 

  212. } AT91S_AIC, *AT91PS_AIC;
    213. 

  213. 

  214. // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
    215. 

  215. #  define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0)	// (AIC) Priority Level
    216. 

  216. #  define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0)	// (AIC) Lowest priority level
    217. 

  217. #  define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7)	// (AIC) Highest priority level
    218. 

  218. #  define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5)	// (AIC) Interrupt Source Type
    219. 

  219. #  define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5)	// (AIC) Internal Sources Code Label Level Sensitive
    220. 

  220. #  define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5)	// (AIC) Internal Sources Code Label Edge triggered
    221. 

  221. #  define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5)	// (AIC) External Sources Code Label High-level Sensitive
    222. 

  222. #  define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5)	// (AIC) External Sources Code Label Positive Edge triggered
    223. 

  223. // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
    224. 

  224. #  define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0)	// (AIC) NFIQ Status
    225. 

  225. #  define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1)	// (AIC) NIRQ Status
    226. 

  226. // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
    227. 

  227. #  define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0)	// (AIC) Protection Mode
    228. 

  228. #  define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1)	// (AIC) General Mask
    229. 

  229. 

  230. // *****************************************************************************
    231. 

  231. //              SOFTWARE API DEFINITION  FOR Debug Unit
    232. 

  232. // *****************************************************************************
    233. 

  233. typedef struct _AT91S_DBGU {
    234. 

  234.   AT91_REG DBGU_CR;		// Control Register
    235. 

  235.   AT91_REG DBGU_MR;		// Mode Register
    236. 

  236.   AT91_REG DBGU_IER;		// Interrupt Enable Register
    237. 

  237.   AT91_REG DBGU_IDR;		// Interrupt Disable Register
    238. 

  238.   AT91_REG DBGU_IMR;		// Interrupt Mask Register
    239. 

  239.   AT91_REG DBGU_CSR;		// Channel Status Register
    240. 

  240.   AT91_REG DBGU_RHR;		// Receiver Holding Register
    241. 

  241.   AT91_REG DBGU_THR;		// Transmitter Holding Register
    242. 

  242.   AT91_REG DBGU_BRGR;		// Baud Rate Generator Register
    243. 

  243.   AT91_REG Reserved0[7];	// 
    244. 

  244.   AT91_REG DBGU_C1R;		// Chip ID1 Register
    245. 

  245.   AT91_REG DBGU_C2R;		// Chip ID2 Register
    246. 

  246.   AT91_REG DBGU_FNTR;		// Force NTRST Register
    247. 

  247.   AT91_REG Reserved1[45];	// 
    248. 

  248.   AT91_REG DBGU_RPR;		// Receive Pointer Register
    249. 

  249.   AT91_REG DBGU_RCR;		// Receive Counter Register
    250. 

  250.   AT91_REG DBGU_TPR;		// Transmit Pointer Register
    251. 

  251.   AT91_REG DBGU_TCR;		// Transmit Counter Register
    252. 

  252.   AT91_REG DBGU_RNPR;		// Receive Next Pointer Register
    253. 

  253.   AT91_REG DBGU_RNCR;		// Receive Next Counter Register
    254. 

  254.   AT91_REG DBGU_TNPR;		// Transmit Next Pointer Register
    255. 

  255.   AT91_REG DBGU_TNCR;		// Transmit Next Counter Register
    256. 

  256.   AT91_REG DBGU_PTCR;		// PDC Transfer Control Register
    257. 

  257.   AT91_REG DBGU_PTSR;		// PDC Transfer Status Register
    258. 

  258. } AT91S_DBGU, *AT91PS_DBGU;
    259. 

  259. 

  260. // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
    261. 

  261. #  define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2)	// (DBGU) Reset Receiver
    262. 

  262. #  define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3)	// (DBGU) Reset Transmitter
    263. 

  263. #  define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4)	// (DBGU) Receiver Enable
    264. 

  264. #  define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5)	// (DBGU) Receiver Disable
    265. 

  265. #  define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6)	// (DBGU) Transmitter Enable
    266. 

  266. #  define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7)	// (DBGU) Transmitter Disable
    267. 

  267. // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
    268. 

  268. #  define AT91C_US_PAR          ((unsigned int) 0x7 <<  9)	// (DBGU) Parity type
    269. 

  269. #  define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9)	// (DBGU) Even Parity
    270. 

  270. #  define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9)	// (DBGU) Odd Parity
    271. 

  271. #  define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9)	// (DBGU) Parity forced to 0 (Space)
    272. 

  272. #  define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9)	// (DBGU) Parity forced to 1 (Mark)
    273. 

  273. #  define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9)	// (DBGU) No Parity
    274. 

  274. #  define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9)	// (DBGU) Multi-drop mode
    275. 

  275. #  define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14)	// (DBGU) Channel Mode
    276. 

  276. #  define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14)	// (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
    277. 

  277. #  define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14)	// (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
    278. 

  278. #  define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14)	// (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
    279. 

  279. #  define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14)	// (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
    280. 

  280. // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
    281. 

  281. #  define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0)	// (DBGU) RXRDY Interrupt
    282. 

  282. #  define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1)	// (DBGU) TXRDY Interrupt
    283. 

  283. #  define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3)	// (DBGU) End of Receive Transfer Interrupt
    284. 

  284. #  define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4)	// (DBGU) End of Transmit Interrupt
    285. 

  285. #  define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5)	// (DBGU) Overrun Interrupt
    286. 

  286. #  define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6)	// (DBGU) Framing Error Interrupt
    287. 

  287. #  define AT91C_US_PARE         ((unsigned int) 0x1 <<  7)	// (DBGU) Parity Error Interrupt
    288. 

  288. #  define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9)	// (DBGU) TXEMPTY Interrupt
    289. 

  289. #  define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11)	// (DBGU) TXBUFE Interrupt
    290. 

  290. #  define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12)	// (DBGU) RXBUFF Interrupt
    291. 

  291. #  define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30)	// (DBGU) COMM_TX Interrupt
    292. 

  292. #  define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31)	// (DBGU) COMM_RX Interrupt
    293. 

  293. // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
    294. 

  294. // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
    295. 

  295. // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
    296. 

  296. // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
    297. 

  297. #  define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0)	// (DBGU) Force NTRST in JTAG
    298. 

  298. 

  299. // *****************************************************************************
    300. 

  300. //              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
    301. 

  301. // *****************************************************************************
    302. 

  302. typedef struct _AT91S_PDC {
    303. 

  303.   AT91_REG PDC_RPR;		// Receive Pointer Register
    304. 

  304.   AT91_REG PDC_RCR;		// Receive Counter Register
    305. 

  305.   AT91_REG PDC_TPR;		// Transmit Pointer Register
    306. 

  306.   AT91_REG PDC_TCR;		// Transmit Counter Register
    307. 

  307.   AT91_REG PDC_RNPR;		// Receive Next Pointer Register
    308. 

  308.   AT91_REG PDC_RNCR;		// Receive Next Counter Register
    309. 

  309.   AT91_REG PDC_TNPR;		// Transmit Next Pointer Register
    310. 

  310.   AT91_REG PDC_TNCR;		// Transmit Next Counter Register
    311. 

  311.   AT91_REG PDC_PTCR;		// PDC Transfer Control Register
    312. 

  312.   AT91_REG PDC_PTSR;		// PDC Transfer Status Register
    313. 

  313. } AT91S_PDC, *AT91PS_PDC;
    314. 

  314. 

  315. // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
    316. 

  316. #  define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0)	// (PDC) Receiver Transfer Enable
    317. 

  317. #  define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1)	// (PDC) Receiver Transfer Disable
    318. 

  318. #  define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8)	// (PDC) Transmitter Transfer Enable
    319. 

  319. #  define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9)	// (PDC) Transmitter Transfer Disable
    320. 

  320. // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
    321. 

  321. 

  322. // *****************************************************************************
    323. 

  323. //              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
    324. 

  324. // *****************************************************************************
    325. 

  325. typedef struct _AT91S_PIO {
    326. 

  326.   AT91_REG PIO_PER;		// PIO Enable Register
    327. 

  327.   AT91_REG PIO_PDR;		// PIO Disable Register
    328. 

  328.   AT91_REG PIO_PSR;		// PIO Status Register
    329. 

  329.   AT91_REG Reserved0[1];	// 
    330. 

  330.   AT91_REG PIO_OER;		// Output Enable Register
    331. 

  331.   AT91_REG PIO_ODR;		// Output Disable Registerr
    332. 

  332.   AT91_REG PIO_OSR;		// Output Status Register
    333. 

  333.   AT91_REG Reserved1[1];	// 
    334. 

  334.   AT91_REG PIO_IFER;		// Input Filter Enable Register
    335. 

  335.   AT91_REG PIO_IFDR;		// Input Filter Disable Register
    336. 

  336.   AT91_REG PIO_IFSR;		// Input Filter Status Register
    337. 

  337.   AT91_REG Reserved2[1];	// 
    338. 

  338.   AT91_REG PIO_SODR;		// Set Output Data Register
    339. 

  339.   AT91_REG PIO_CODR;		// Clear Output Data Register
    340. 

  340.   AT91_REG PIO_ODSR;		// Output Data Status Register
    341. 

  341.   AT91_REG PIO_PDSR;		// Pin Data Status Register
    342. 

  342.   AT91_REG PIO_IER;		// Interrupt Enable Register
    343. 

  343.   AT91_REG PIO_IDR;		// Interrupt Disable Register
    344. 

  344.   AT91_REG PIO_IMR;		// Interrupt Mask Register
    345. 

  345.   AT91_REG PIO_ISR;		// Interrupt Status Register
    346. 

  346.   AT91_REG PIO_MDER;		// Multi-driver Enable Register
    347. 

  347.   AT91_REG PIO_MDDR;		// Multi-driver Disable Register
    348. 

  348.   AT91_REG PIO_MDSR;		// Multi-driver Status Register
    349. 

  349.   AT91_REG Reserved3[1];	// 
    350. 

  350.   AT91_REG PIO_PPUDR;		// Pull-up Disable Register
    351. 

  351.   AT91_REG PIO_PPUER;		// Pull-up Enable Register
    352. 

  352.   AT91_REG PIO_PPUSR;		// Pad Pull-up Status Register
    353. 

  353.   AT91_REG Reserved4[1];	// 
    354. 

  354.   AT91_REG PIO_ASR;		// Select A Register
    355. 

  355.   AT91_REG PIO_BSR;		// Select B Register
    356. 

  356.   AT91_REG PIO_ABSR;		// AB Select Status Register
    357. 

  357.   AT91_REG Reserved5[9];	// 
    358. 

  358.   AT91_REG PIO_OWER;		// Output Write Enable Register
    359. 

  359.   AT91_REG PIO_OWDR;		// Output Write Disable Register
    360. 

  360.   AT91_REG PIO_OWSR;		// Output Write Status Register
    361. 

  361. } AT91S_PIO, *AT91PS_PIO;
    362. 

  362. 

  363. 

  364. // *****************************************************************************
    365. 

  365. //              SOFTWARE API DEFINITION  FOR Clock Generator Controler
    366. 

  366. // *****************************************************************************
    367. 

  367. typedef struct _AT91S_CKGR {
    368. 

  368.   AT91_REG CKGR_MOR;		// Main Oscillator Register
    369. 

  369.   AT91_REG CKGR_MCFR;		// Main Clock  Frequency Register
    370. 

  370.   AT91_REG Reserved0[1];	// 
    371. 

  371.   AT91_REG CKGR_PLLR;		// PLL Register
    372. 

  372. } AT91S_CKGR, *AT91PS_CKGR;
    373. 

  373. 

  374. // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
    375. 

  375. #  define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0)	// (CKGR) Main Oscillator Enable
    376. 

  376. #  define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1)	// (CKGR) Main Oscillator Bypass
    377. 

  377. #  define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8)	// (CKGR) Main Oscillator Start-up Time
    378. 

  378. // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
    379. 

  379. #  define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0)	// (CKGR) Main Clock Frequency
    380. 

  380. #  define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16)	// (CKGR) Main Clock Ready
    381. 

  381. // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
    382. 

  382. #  define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0)	// (CKGR) Divider Selected
    383. 

  383. #  define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0)	// (CKGR) Divider output is 0
    384. 

  384. #  define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1)	// (CKGR) Divider is bypassed
    385. 

  385. #  define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8)	// (CKGR) PLL Counter
    386. 

  386. #  define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14)	// (CKGR) PLL Output Frequency Range
    387. 

  387. #  define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14)	// (CKGR) Please refer to the PLL datasheet
    388. 

  388. #  define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14)	// (CKGR) Please refer to the PLL datasheet
    389. 

  389. #  define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14)	// (CKGR) Please refer to the PLL datasheet
    390. 

  390. #  define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14)	// (CKGR) Please refer to the PLL datasheet
    391. 

  391. #  define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16)	// (CKGR) PLL Multiplier
    392. 

  392. #  define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28)	// (CKGR) Divider for USB Clocks
    393. 

  393. #  define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28)	// (CKGR) Divider output is PLL clock output
    394. 

  394. #  define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28)	// (CKGR) Divider output is PLL clock output divided by 2
    395. 

  395. #  define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28)	// (CKGR) Divider output is PLL clock output divided by 4
    396. 

  396. 

  397. // *****************************************************************************
    398. 

  398. //              SOFTWARE API DEFINITION  FOR Power Management Controler
    399. 

  399. // *****************************************************************************
    400. 

  400. typedef struct _AT91S_PMC {
    401. 

  401.   AT91_REG PMC_SCER;		// System Clock Enable Register
    402. 

  402.   AT91_REG PMC_SCDR;		// System Clock Disable Register
    403. 

  403.   AT91_REG PMC_SCSR;		// System Clock Status Register
    404. 

  404.   AT91_REG Reserved0[1];	// 
    405. 

  405.   AT91_REG PMC_PCER;		// Peripheral Clock Enable Register
    406. 

  406.   AT91_REG PMC_PCDR;		// Peripheral Clock Disable Register
    407. 

  407.   AT91_REG PMC_PCSR;		// Peripheral Clock Status Register
    408. 

  408.   AT91_REG Reserved1[1];	// 
    409. 

  409.   AT91_REG PMC_MOR;		// Main Oscillator Register
    410. 

  410.   AT91_REG PMC_MCFR;		// Main Clock  Frequency Register
    411. 

  411.   AT91_REG Reserved2[1];	// 
    412. 

  412.   AT91_REG PMC_PLLR;		// PLL Register
    413. 

  413.   AT91_REG PMC_MCKR;		// Master Clock Register
    414. 

  414.   AT91_REG Reserved3[3];	// 
    415. 

  415.   AT91_REG PMC_PCKR[8];		// Programmable Clock Register
    416. 

  416.   AT91_REG PMC_IER;		// Interrupt Enable Register
    417. 

  417.   AT91_REG PMC_IDR;		// Interrupt Disable Register
    418. 

  418.   AT91_REG PMC_SR;		// Status Register
    419. 

  419.   AT91_REG PMC_IMR;		// Interrupt Mask Register
    420. 

  420. } AT91S_PMC, *AT91PS_PMC;
    421. 

  421. 

  422. // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
    423. 

  423. #  define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0)	// (PMC) Processor Clock
    424. 

  424. #  define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7)	// (PMC) USB Device Port Clock
    425. 

  425. #  define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8)	// (PMC) Programmable Clock Output
    426. 

  426. #  define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9)	// (PMC) Programmable Clock Output
    427. 

  427. #  define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10)	// (PMC) Programmable Clock Output
    428. 

  428. #  define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11)	// (PMC) Programmable Clock Output
    429. 

  429. // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
    430. 

  430. // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
    431. 

  431. // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
    432. 

  432. // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
    433. 

  433. // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
    434. 

  434. // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
    435. 

  435. #  define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0)	// (PMC) Programmable Clock Selection
    436. 

  436. #  define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0)	// (PMC) Slow Clock is selected
    437. 

  437. #  define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1)	// (PMC) Main Clock is selected
    438. 

  438. #  define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3)	// (PMC) Clock from PLL is selected
    439. 

  439. #  define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2)	// (PMC) Programmable Clock Prescaler
    440. 

  440. #  define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2)	// (PMC) Selected clock
    441. 

  441. #  define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2)	// (PMC) Selected clock divided by 2
    442. 

  442. #  define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2)	// (PMC) Selected clock divided by 4
    443. 

  443. #  define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2)	// (PMC) Selected clock divided by 8
    444. 

  444. #  define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2)	// (PMC) Selected clock divided by 16
    445. 

  445. #  define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2)	// (PMC) Selected clock divided by 32
    446. 

  446. #  define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2)	// (PMC) Selected clock divided by 64
    447. 

  447. // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
    448. 

  448. // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
    449. 

  449. #  define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0)	// (PMC) MOSC Status/Enable/Disable/Mask
    450. 

  450. #  define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2)	// (PMC) PLL Status/Enable/Disable/Mask
    451. 

  451. #  define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3)	// (PMC) MCK_RDY Status/Enable/Disable/Mask
    452. 

  452. #  define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8)	// (PMC) PCK0_RDY Status/Enable/Disable/Mask
    453. 

  453. #  define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9)	// (PMC) PCK1_RDY Status/Enable/Disable/Mask
    454. 

  454. #  define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10)	// (PMC) PCK2_RDY Status/Enable/Disable/Mask
    455. 

  455. #  define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11)	// (PMC) PCK3_RDY Status/Enable/Disable/Mask
    456. 

  456. // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
    457. 

  457. // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
    458. 

  458. // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
    459. 

  459. 

  460. // *****************************************************************************
    461. 

  461. //              SOFTWARE API DEFINITION  FOR Reset Controller Interface
    462. 

  462. // *****************************************************************************
    463. 

  463. typedef struct _AT91S_RSTC {
    464. 

  464.   AT91_REG RSTC_RCR;		// Reset Control Register
    465. 

  465.   AT91_REG RSTC_RSR;		// Reset Status Register
    466. 

  466.   AT91_REG RSTC_RMR;		// Reset Mode Register
    467. 

  467. } AT91S_RSTC, *AT91PS_RSTC;
    468. 

  468. 

  469. // -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
    470. 

  470. #  define AT91C_SYSC_PROCRST    ((unsigned int) 0x1 <<  0)	// (RSTC) Processor Reset
    471. 

  471. #  define AT91C_SYSC_ICERST     ((unsigned int) 0x1 <<  1)	// (RSTC) ICE Interface Reset
    472. 

  472. #  define AT91C_SYSC_PERRST     ((unsigned int) 0x1 <<  2)	// (RSTC) Peripheral Reset
    473. 

  473. #  define AT91C_SYSC_EXTRST     ((unsigned int) 0x1 <<  3)	// (RSTC) External Reset
    474. 

  474. #  define AT91C_SYSC_KEY        ((unsigned int) 0xFF << 24)	// (RSTC) Password
    475. 

  475. // -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
    476. 

  476. #  define AT91C_SYSC_URSTS      ((unsigned int) 0x1 <<  0)	// (RSTC) User Reset Status
    477. 

  477. #  define AT91C_SYSC_BODSTS     ((unsigned int) 0x1 <<  1)	// (RSTC) Brown-out Detection Status
    478. 

  478. #  define AT91C_SYSC_RSTTYP     ((unsigned int) 0x7 <<  8)	// (RSTC) Reset Type
    479. 

  479. #  define 	AT91C_SYSC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8)	// (RSTC) Power-up Reset. VDDCORE rising.
    480. 

  480. #  define 	AT91C_SYSC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8)	// (RSTC) Watchdog Reset. Watchdog overflow occured.
    481. 

  481. #  define 	AT91C_SYSC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8)	// (RSTC) Software Reset. Processor reset required by the software.
    482. 

  482. #  define 	AT91C_SYSC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8)	// (RSTC) User Reset. NRST pin detected low.
    483. 

  483. #  define 	AT91C_SYSC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8)	// (RSTC) Brown-out Reset.
    484. 

  484. #  define AT91C_SYSC_NRSTL      ((unsigned int) 0x1 << 16)	// (RSTC) NRST pin level
    485. 

  485. #  define AT91C_SYSC_SRCMP      ((unsigned int) 0x1 << 17)	// (RSTC) Software Reset Command in Progress.
    486. 

  486. // -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
    487. 

  487. #  define AT91C_SYSC_URSTEN     ((unsigned int) 0x1 <<  0)	// (RSTC) User Reset Enable
    488. 

  488. #  define AT91C_SYSC_URSTIEN    ((unsigned int) 0x1 <<  4)	// (RSTC) User Reset Interrupt Enable
    489. 

  489. #  define AT91C_SYSC_ERSTL      ((unsigned int) 0xF <<  8)	// (RSTC) User Reset Enable
    490. 

  490. #  define AT91C_SYSC_BODIEN     ((unsigned int) 0x1 << 16)	// (RSTC) Brown-out Detection Interrupt Enable
    491. 

  491. 

  492. // *****************************************************************************
    493. 

  493. //              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
    494. 

  494. // *****************************************************************************
    495. 

  495. typedef struct _AT91S_RTTC {
    496. 

  496.   AT91_REG RTTC_RTMR;		// Real-time Mode Register
    497. 

  497.   AT91_REG RTTC_RTAR;		// Real-time Alarm Register
    498. 

  498.   AT91_REG RTTC_RTVR;		// Real-time Value Register
    499. 

  499.   AT91_REG RTTC_RTSR;		// Real-time Status Register
    500. 

  500. } AT91S_RTTC, *AT91PS_RTTC;
    501. 

  501. 

  502. // -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
    503. 

  503. #  define AT91C_SYSC_RTPRES     ((unsigned int) 0xFFFF <<  0)	// (RTTC) Real-time Timer Prescaler Value
    504. 

  504. #  define AT91C_SYSC_ALMIEN     ((unsigned int) 0x1 << 16)	// (RTTC) Alarm Interrupt Enable
    505. 

  505. #  define AT91C_SYSC_RTTINCIEN  ((unsigned int) 0x1 << 17)	// (RTTC) Real Time Timer Increment Interrupt Enable
    506. 

  506. #  define AT91C_SYSC_RTTRST     ((unsigned int) 0x1 << 18)	// (RTTC) Real Time Timer Restart
    507. 

  507. // -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
    508. 

  508. #  define AT91C_SYSC_ALMV       ((unsigned int) 0x0 <<  0)	// (RTTC) Alarm Value
    509. 

  509. // -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
    510. 

  510. #  define AT91C_SYSC_CRTV       ((unsigned int) 0x0 <<  0)	// (RTTC) Current Real-time Value
    511. 

  511. // -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
    512. 

  512. #  define AT91C_SYSC_ALMS       ((unsigned int) 0x1 <<  0)	// (RTTC) Real-time Alarm Status
    513. 

  513. #  define AT91C_SYSC_RTTINC     ((unsigned int) 0x1 <<  1)	// (RTTC) Real-time Timer Increment
    514. 

  514. 

  515. // *****************************************************************************
    516. 

  516. //              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
    517. 

  517. // *****************************************************************************
    518. 

  518. typedef struct _AT91S_PITC {
    519. 

  519.   AT91_REG PITC_PIMR;		// Period Interval Mode Register
    520. 

  520.   AT91_REG PITC_PISR;		// Period Interval Status Register
    521. 

  521.   AT91_REG PITC_PIVR;		// Period Interval Value Register
    522. 

  522.   AT91_REG PITC_PIIR;		// Period Interval Image Register
    523. 

  523. } AT91S_PITC, *AT91PS_PITC;
    524. 

  524. 

  525. // -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
    526. 

  526. #  define AT91C_SYSC_PIV        ((unsigned int) 0xFFFFF <<  0)	// (PITC) Periodic Interval Value
    527. 

  527. #  define AT91C_SYSC_PITEN      ((unsigned int) 0x1 << 24)	// (PITC) Periodic Interval Timer Enabled
    528. 

  528. #  define AT91C_SYSC_PITIEN     ((unsigned int) 0x1 << 25)	// (PITC) Periodic Interval Timer Interrupt Enable
    529. 

  529. // -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
    530. 

  530. #  define AT91C_SYSC_PITS       ((unsigned int) 0x1 <<  0)	// (PITC) Periodic Interval Timer Status
    531. 

  531. // -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
    532. 

  532. #  define AT91C_SYSC_CPIV       ((unsigned int) 0xFFFFF <<  0)	// (PITC) Current Periodic Interval Value
    533. 

  533. #  define AT91C_SYSC_PICNT      ((unsigned int) 0xFFF << 20)	// (PITC) Periodic Interval Counter
    534. 

  534. // -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
    535. 

  535. 

  536. // *****************************************************************************
    537. 

  537. //              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
    538. 

  538. // *****************************************************************************
    539. 

  539. typedef struct _AT91S_WDTC {
    540. 

  540.   AT91_REG WDTC_WDCR;		// Watchdog Control Register
    541. 

  541.   AT91_REG WDTC_WDMR;		// Watchdog Mode Register
    542. 

  542.   AT91_REG WDTC_WDSR;		// Watchdog Status Register
    543. 

  543. } AT91S_WDTC, *AT91PS_WDTC;
    544. 

  544. 

  545. // -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
    546. 

  546. #  define AT91C_SYSC_WDRSTT     ((unsigned int) 0x1 <<  0)	// (WDTC) Watchdog Restart
    547. 

  547. // -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
    548. 

  548. #  define AT91C_SYSC_WDV        ((unsigned int) 0xFFF <<  0)	// (WDTC) Watchdog Timer Restart
    549. 

  549. #  define AT91C_SYSC_WDFIEN     ((unsigned int) 0x1 << 12)	// (WDTC) Watchdog Fault Interrupt Enable
    550. 

  550. #  define AT91C_SYSC_WDRSTEN    ((unsigned int) 0x1 << 13)	// (WDTC) Watchdog Reset Enable
    551. 

  551. #  define AT91C_SYSC_WDRPROC    ((unsigned int) 0x1 << 14)	// (WDTC) Watchdog Timer Restart
    552. 

  552. #  define AT91C_SYSC_WDDIS      ((unsigned int) 0x1 << 15)	// (WDTC) Watchdog Disable
    553. 

  553. #  define AT91C_SYSC_WDD        ((unsigned int) 0xFFF << 16)	// (WDTC) Watchdog Delta Value
    554. 

  554. #  define AT91C_SYSC_WDDBGHLT   ((unsigned int) 0x1 << 28)	// (WDTC) Watchdog Debug Halt
    555. 

  555. #  define AT91C_SYSC_WDIDLEHLT  ((unsigned int) 0x1 << 29)	// (WDTC) Watchdog Idle Halt
    556. 

  556. // -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
    557. 

  557. #  define AT91C_SYSC_WDUNF      ((unsigned int) 0x1 <<  0)	// (WDTC) Watchdog Underflow
    558. 

  558. #  define AT91C_SYSC_WDERR      ((unsigned int) 0x1 <<  1)	// (WDTC) Watchdog Error
    559. 

  559. 

  560. // *****************************************************************************
    561. 

  561. //              SOFTWARE API DEFINITION  FOR Memory Controller Interface
    562. 

  562. // *****************************************************************************
    563. 

  563. typedef struct _AT91S_MC {
    564. 

  564.   AT91_REG MC_RCR;		// MC Remap Control Register
    565. 

  565.   AT91_REG MC_ASR;		// MC Abort Status Register
    566. 

  566.   AT91_REG MC_AASR;		// MC Abort Address Status Register
    567. 

  567.   AT91_REG Reserved0[21];	// 
    568. 

  568.   AT91_REG MC_FMR;		// MC Flash Mode Register
    569. 

  569.   AT91_REG MC_FCR;		// MC Flash Command Register
    570. 

  570.   AT91_REG MC_FSR;		// MC Flash Status Register
    571. 

  571. } AT91S_MC, *AT91PS_MC;
    572. 

  572. 

  573. // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
    574. 

  574. #  define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0)	// (MC) Remap Command Bit
    575. 

  575. // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
    576. 

  576. #  define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0)	// (MC) Undefined Addess Abort Status
    577. 

  577. #  define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1)	// (MC) Misaligned Addess Abort Status
    578. 

  578. #  define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8)	// (MC) Abort Size Status
    579. 

  579. #  define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8)	// (MC) Byte
    580. 

  580. #  define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8)	// (MC) Half-word
    581. 

  581. #  define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8)	// (MC) Word
    582. 

  582. #  define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10)	// (MC) Abort Type Status
    583. 

  583. #  define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10)	// (MC) Data Read
    584. 

  584. #  define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10)	// (MC) Data Write
    585. 

  585. #  define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10)	// (MC) Code Fetch
    586. 

  586. #  define AT91C_MC_MST0         ((unsigned int) 0x1 << 16)	// (MC) Master 0 Abort Source
    587. 

  587. #  define AT91C_MC_MST1         ((unsigned int) 0x1 << 17)	// (MC) Master 1 Abort Source
    588. 

  588. #  define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24)	// (MC) Saved Master 0 Abort Source
    589. 

  589. #  define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25)	// (MC) Saved Master 1 Abort Source
    590. 

  590. // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
    591. 

  591. #  define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0)	// (MC) Flash Ready
    592. 

  592. #  define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2)	// (MC) Lock Error
    593. 

  593. #  define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3)	// (MC) Programming Error
    594. 

  594. #  define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7)	// (MC) No Erase Before Programming
    595. 

  595. #  define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8)	// (MC) Flash Wait State
    596. 

  596. #  define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8)	// (MC) 1 cycle for Read, 2 for Write operations
    597. 

  597. #  define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8)	// (MC) 2 cycles for Read, 3 for Write operations
    598. 

  598. #  define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8)	// (MC) 3 cycles for Read, 4 for Write operations
    599. 

  599. #  define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8)	// (MC) 4 cycles for Read, 4 for Write operations
    600. 

  600. #  define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16)	// (MC) Flash Microsecond Cycle Number
    601. 

  601. // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
    602. 

  602. #  define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0)	// (MC) Flash Command
    603. 

  603. #  define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1)	// (MC) Starts the programming of th epage specified by PAGEN.
    604. 

  604. #  define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2)	// (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
    605. 

  605. #  define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3)	// (MC) The lock sequence automatically happens after the programming sequence is completed.
    606. 

  606. #  define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4)	// (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
    607. 

  607. #  define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8)	// (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
    608. 

  608. #  define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB)	// (MC) Set General Purpose NVM bits.
    609. 

  609. #  define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD)	// (MC) Clear General Purpose NVM bits.
    610. 

  610. #  define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF)	// (MC) Set Security Bit.
    611. 

  611. #  define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8)	// (MC) Page Number
    612. 

  612. #  define AT91C_MC_KEY          ((unsigned int) 0xFF << 24)	// (MC) Writing Protect Key
    613. 

  613. // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
    614. 

  614. #  define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4)	// (MC) Security Bit Status
    615. 

  615. #  define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8)	// (MC) Sector 0 Lock Status
    616. 

  616. #  define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9)	// (MC) Sector 1 Lock Status
    617. 

  617. #  define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10)	// (MC) Sector 2 Lock Status
    618. 

  618. #  define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11)	// (MC) Sector 3 Lock Status
    619. 

  619. #  define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12)	// (MC) Sector 4 Lock Status
    620. 

  620. #  define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13)	// (MC) Sector 5 Lock Status
    621. 

  621. #  define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14)	// (MC) Sector 6 Lock Status
    622. 

  622. #  define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15)	// (MC) Sector 7 Lock Status
    623. 

  623. #  define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16)	// (MC) Sector 0 Lock Status
    624. 

  624. #  define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17)	// (MC) Sector 1 Lock Status
    625. 

  625. #  define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18)	// (MC) Sector 2 Lock Status
    626. 

  626. #  define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19)	// (MC) Sector 3 Lock Status
    627. 

  627. #  define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20)	// (MC) Sector 4 Lock Status
    628. 

  628. #  define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21)	// (MC) Sector 5 Lock Status
    629. 

  629. #  define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22)	// (MC) Sector 6 Lock Status
    630. 

  630. #  define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23)	// (MC) Sector 7 Lock Status
    631. 

  631. #  define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24)	// (MC) Sector 8 Lock Status
    632. 

  632. #  define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25)	// (MC) Sector 9 Lock Status
    633. 

  633. #  define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26)	// (MC) Sector 10 Lock Status
    634. 

  634. #  define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27)	// (MC) Sector 11 Lock Status
    635. 

  635. #  define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28)	// (MC) Sector 12 Lock Status
    636. 

  636. #  define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29)	// (MC) Sector 13 Lock Status
    637. 

  637. #  define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30)	// (MC) Sector 14 Lock Status
    638. 

  638. #  define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31)	// (MC) Sector 15 Lock Status
    639. 

  639. 

  640. // *****************************************************************************
    641. 

  641. //              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
    642. 

  642. // *****************************************************************************
    643. 

  643. typedef struct _AT91S_SPI {
    644. 

  644.   AT91_REG SPI_CR;		// Control Register
    645. 

  645.   AT91_REG SPI_MR;		// Mode Register
    646. 

  646.   AT91_REG SPI_RDR;		// Receive Data Register
    647. 

  647.   AT91_REG SPI_TDR;		// Transmit Data Register
    648. 

  648.   AT91_REG SPI_SR;		// Status Register
    649. 

  649.   AT91_REG SPI_IER;		// Interrupt Enable Register
    650. 

  650.   AT91_REG SPI_IDR;		// Interrupt Disable Register
    651. 

  651.   AT91_REG SPI_IMR;		// Interrupt Mask Register
    652. 

  652.   AT91_REG Reserved0[4];	// 
    653. 

  653.   AT91_REG SPI_CSR[4];		// Chip Select Register
    654. 

  654.   AT91_REG Reserved1[48];	// 
    655. 

  655.   AT91_REG SPI_RPR;		// Receive Pointer Register
    656. 

  656.   AT91_REG SPI_RCR;		// Receive Counter Register
    657. 

  657.   AT91_REG SPI_TPR;		// Transmit Pointer Register
    658. 

  658.   AT91_REG SPI_TCR;		// Transmit Counter Register
    659. 

  659.   AT91_REG SPI_RNPR;		// Receive Next Pointer Register
    660. 

  660.   AT91_REG SPI_RNCR;		// Receive Next Counter Register
    661. 

  661.   AT91_REG SPI_TNPR;		// Transmit Next Pointer Register
    662. 

  662.   AT91_REG SPI_TNCR;		// Transmit Next Counter Register
    663. 

  663.   AT91_REG SPI_PTCR;		// PDC Transfer Control Register
    664. 

  664.   AT91_REG SPI_PTSR;		// PDC Transfer Status Register
    665. 

  665. } AT91S_SPI, *AT91PS_SPI;
    666. 

  666. 

  667. // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
    668. 

  668. #  define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0)	// (SPI) SPI Enable
    669. 

  669. #  define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1)	// (SPI) SPI Disable
    670. 

  670. #  define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7)	// (SPI) SPI Software reset
    671. 

  671. #  define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24)	// (SPI) SPI Last Transfer
    672. 

  672. // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
    673. 

  673. #  define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0)	// (SPI) Master/Slave Mode
    674. 

  674. #  define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1)	// (SPI) Peripheral Select
    675. 

  675. #  define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1)	// (SPI) Fixed Peripheral Select
    676. 

  676. #  define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1)	// (SPI) Variable Peripheral Select
    677. 

  677. #  define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2)	// (SPI) Chip Select Decode
    678. 

  678. #  define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3)	// (SPI) Clock Selection
    679. 

  679. #  define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4)	// (SPI) Mode Fault Detection
    680. 

  680. #  define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7)	// (SPI) Clock Selection
    681. 

  681. #  define AT91C_SPI_PCS         ((unsigned int) 0xF << 16)	// (SPI) Peripheral Chip Select
    682. 

  682. #  define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24)	// (SPI) Delay Between Chip Selects
    683. 

  683. // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
    684. 

  684. #  define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0)	// (SPI) Receive Data
    685. 

  685. #  define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16)	// (SPI) Peripheral Chip Select Status
    686. 

  686. // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
    687. 

  687. #  define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0)	// (SPI) Transmit Data
    688. 

  688. #  define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16)	// (SPI) Peripheral Chip Select Status
    689. 

  689. // -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
    690. 

  690. #  define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0)	// (SPI) Receive Data Register Full
    691. 

  691. #  define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1)	// (SPI) Transmit Data Register Empty
    692. 

  692. #  define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2)	// (SPI) Mode Fault Error
    693. 

  693. #  define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3)	// (SPI) Overrun Error Status
    694. 

  694. #  define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4)	// (SPI) End of Receiver Transfer
    695. 

  695. #  define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5)	// (SPI) End of Receiver Transfer
    696. 

  696. #  define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6)	// (SPI) RXBUFF Interrupt
    697. 

  697. #  define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7)	// (SPI) TXBUFE Interrupt
    698. 

  698. #  define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8)	// (SPI) NSSR Interrupt
    699. 

  699. #  define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9)	// (SPI) TXEMPTY Interrupt
    700. 

  700. #  define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16)	// (SPI) Enable Status
    701. 

  701. // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
    702. 

  702. // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
    703. 

  703. // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
    704. 

  704. // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
    705. 

  705. #  define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0)	// (SPI) Clock Polarity
    706. 

  706. #  define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1)	// (SPI) Clock Phase
    707. 

  707. #  define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  2)	// (SPI) Chip Select Active After Transfer
    708. 

  708. #  define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4)	// (SPI) Bits Per Transfer
    709. 

  709. #  define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4)	// (SPI) 8 Bits Per transfer
    710. 

  710. #  define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4)	// (SPI) 9 Bits Per transfer
    711. 

  711. #  define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4)	// (SPI) 10 Bits Per transfer
    712. 

  712. #  define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4)	// (SPI) 11 Bits Per transfer
    713. 

  713. #  define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4)	// (SPI) 12 Bits Per transfer
    714. 

  714. #  define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4)	// (SPI) 13 Bits Per transfer
    715. 

  715. #  define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4)	// (SPI) 14 Bits Per transfer
    716. 

  716. #  define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4)	// (SPI) 15 Bits Per transfer
    717. 

  717. #  define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4)	// (SPI) 16 Bits Per transfer
    718. 

  718. #  define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8)	// (SPI) Serial Clock Baud Rate
    719. 

  719. #  define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16)	// (SPI) Serial Clock Baud Rate
    720. 

  720. #  define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24)	// (SPI) Delay Between Consecutive Transfers
    721. 

  721. 

  722. // *****************************************************************************
    723. 

  723. //              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
    724. 

  724. // *****************************************************************************
    725. 

  725. typedef struct _AT91S_ADC {
    726. 

  726.   AT91_REG ADC_CR;		// ADC Control Register
    727. 

  727.   AT91_REG ADC_MR;		// ADC Mode Register
    728. 

  728.   AT91_REG Reserved0[2];	// 
    729. 

  729.   AT91_REG ADC_CHER;		// ADC Channel Enable Register
    730. 

  730.   AT91_REG ADC_CHDR;		// ADC Channel Disable Register
    731. 

  731.   AT91_REG ADC_CHSR;		// ADC Channel Status Register
    732. 

  732.   AT91_REG ADC_SR;		// ADC Status Register
    733. 

  733.   AT91_REG ADC_LCDR;		// ADC Last Converted Data Register
    734. 

  734.   AT91_REG ADC_IER;		// ADC Interrupt Enable Register
    735. 

  735.   AT91_REG ADC_IDR;		// ADC Interrupt Disable Register
    736. 

  736.   AT91_REG ADC_IMR;		// ADC Interrupt Mask Register
    737. 

  737.   AT91_REG ADC_CDR0;		// ADC Channel Data Register 0
    738. 

  738.   AT91_REG ADC_CDR1;		// ADC Channel Data Register 1
    739. 

  739.   AT91_REG ADC_CDR2;		// ADC Channel Data Register 2
    740. 

  740.   AT91_REG ADC_CDR3;		// ADC Channel Data Register 3
    741. 

  741.   AT91_REG ADC_CDR4;		// ADC Channel Data Register 4
    742. 

  742.   AT91_REG ADC_CDR5;		// ADC Channel Data Register 5
    743. 

  743.   AT91_REG ADC_CDR6;		// ADC Channel Data Register 6
    744. 

  744.   AT91_REG ADC_CDR7;		// ADC Channel Data Register 7
    745. 

  745.   AT91_REG Reserved1[44];	// 
    746. 

  746.   AT91_REG ADC_RPR;		// Receive Pointer Register
    747. 

  747.   AT91_REG ADC_RCR;		// Receive Counter Register
    748. 

  748.   AT91_REG ADC_TPR;		// Transmit Pointer Register
    749. 

  749.   AT91_REG ADC_TCR;		// Transmit Counter Register
    750. 

  750.   AT91_REG ADC_RNPR;		// Receive Next Pointer Register
    751. 

  751.   AT91_REG ADC_RNCR;		// Receive Next Counter Register
    752. 

  752.   AT91_REG ADC_TNPR;		// Transmit Next Pointer Register
    753. 

  753.   AT91_REG ADC_TNCR;		// Transmit Next Counter Register
    754. 

  754.   AT91_REG ADC_PTCR;		// PDC Transfer Control Register
    755. 

  755.   AT91_REG ADC_PTSR;		// PDC Transfer Status Register
    756. 

  756. } AT91S_ADC, *AT91PS_ADC;
    757. 

  757. 

  758. // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
    759. 

  759. #  define A…
    760.