/js/src/nanojit/RegAlloc.h

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 40
 41#ifndef __nanojit_RegAlloc__
 42#define __nanojit_RegAlloc__
 43
 44
 45namespace nanojit
 46{
 47    class RegAlloc
 48    {
 49    public:
 50        RegAlloc()
 51        {
 52            clear();
 53        }
 54
 55        void clear()
 56        {
 57            VMPI_memset(this, 0, sizeof(*this));
 58        }
 59
 60        bool isFree(Register r) const
 61        {
 62            return (free & rmask(r)) != 0;
 63        }
 64
 65        void addFree(Register r)
 66        {
 67            NanoAssert(!isFree(r));
 68            free |= rmask(r);
 69        }
 70
 71        void removeFree(Register r)
 72        {
 73            NanoAssert(isFree(r));
 74            free &= ~rmask(r);
 75        }
 76
 77        void addActive(Register r, LIns* v)
 78        {
 79            //  Count++;
 80            NanoAssert(v);
 81            NanoAssert(active[REGNUM(r)] == NULL);
 82            active[REGNUM(r)] = v;
 83            useActive(r);
 84        }
 85
 86        void useActive(Register r)
 87        {
 88            NanoAssert(active[REGNUM(r)] != NULL);
 89            usepri[REGNUM(r)] = priority++;
 90        }
 91
 92        void removeActive(Register r)
 93        {
 94            //registerReleaseCount++;
 95            NanoAssert(active[REGNUM(r)] != NULL);
 96
 97            // remove the given register from the active list
 98            active[REGNUM(r)] = NULL;
 99        }
100
101        void retire(Register r)
102        {
103            NanoAssert(active[REGNUM(r)] != NULL);
104            active[REGNUM(r)] = NULL;
105            free |= rmask(r);
106        }
107
108        int32_t getPriority(Register r) {
109            NanoAssert(active[REGNUM(r)]);
110            return usepri[REGNUM(r)];
111        }
112
113        LIns* getActive(Register r) const {
114            return active[REGNUM(r)];
115        }
116
117        // Return a mask containing the active registers.  For each register
118        // in this set, getActive(register) will be a nonzero LIns pointer.
119        RegisterMask activeMask() const {
120            return ~free & managed;
121        }
122
123        debug_only( bool        isConsistent(Register r, LIns* v) const; )
124
125        // Some basics:
126        //
127        // - 'active' indicates which registers are active at a particular
128        //   point, and for each active register, which instruction
129        //   defines the value it holds.  At the start of register
130        //   allocation no registers are active.
131        //
132        // - 'free' indicates which registers are free at a particular point
133        //   and thus available for use.  At the start of register
134        //   allocation most registers are free;  those that are not
135        //   aren't available for general use, e.g. the stack pointer and
136        //   frame pointer registers.
137        //
138        // - 'managed' is exactly this list of initially free registers,
139        //   ie. the registers managed by the register allocator.
140        //
141        // - Each LIns has a "reservation" which includes a register value,
142        //   'reg'.  Combined with 'active', this provides a two-way
143        //   mapping between registers and LIR instructions.
144        //
145        // - Invariant 1: each register must be in exactly one of the
146        //   following states at all times:  unmanaged, free, or active.
147        //   In terms of the relevant fields:
148        //
149        //   * A register in 'managed' must be in 'active' or 'free' but
150        //     not both.
151        //
152        //   * A register not in 'managed' must be in neither 'active' nor
153        //     'free'.
154        //
155        // - Invariant 2: the two-way mapping between active registers and
156        //   their defining instructions must always hold in both
157        //   directions and be unambiguous.  More specifically:
158        //
159        //   * An LIns can appear at most once in 'active'.
160        //
161        //   * An LIns named by 'active[R]' must have an in-use
162        //     reservation that names R.
163        //
164        //   * And vice versa:  an LIns with an in-use reservation that
165        //     names R must be named by 'active[R]'.
166        //
167        //   * If an LIns's reservation names 'deprecated_UnknownReg' then LIns
168        //     should not be in 'active'.
169        //
170        LIns*           active[LastRegNum + 1]; // active[REGNUM(r)] = LIns that defines r
171        int32_t         usepri[LastRegNum + 1]; // used priority. lower = more likely to spill.
172        RegisterMask    free;       // Registers currently free.
173        RegisterMask    managed;    // Registers under management (invariant).
174        int32_t         priority;
175
176        DECLARE_PLATFORM_REGALLOC()
177    };
178
179    // Return the lowest numbered Register in mask.
180    inline Register lsReg(RegisterMask mask) {
181        // This is faster than it looks; we rely on the C++ optimizer
182        // to strip the dead branch and inline just one alternative.
183        Register r = { (sizeof(RegisterMask) == 4) ? lsbSet32(mask) : lsbSet64(mask) };
184        return r;
185    }
186
187    // Return the highest numbered Register in mask.
188    inline Register msReg(RegisterMask mask) {
189        // This is faster than it looks; we rely on the C++ optimizer
190        // to strip the dead branch and inline just one alternative.
191        Register r = { (sizeof(RegisterMask) == 4) ? msbSet32(mask) : msbSet64(mask) };
192        return r;
193    }
194
195    // Clear bit r in mask, then return lsReg(mask).
196    inline Register nextLsReg(RegisterMask& mask, Register r) {
197        return lsReg(mask &= ~rmask(r));
198    }
199
200    // Clear bit r in mask, then return msReg(mask).
201    inline Register nextMsReg(RegisterMask& mask, Register r) {
202        return msReg(mask &= ~rmask(r));
203    }
204}
205#endif // __nanojit_RegAlloc__