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/arch/powerpc/boot/dts/pcm030.dts

https://github.com/SatrioDwiPrabowo/android_kernel_sony_apq8064
Device Tree | 137 lines | 99 code | 22 blank | 16 comment | 0 complexity | 9fa4cd9a5c6bee59fd7e2946e65deac1 MD5 | raw file
Possible License(s): GPL-2.0
  1. /*
  2. * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
  3. *
  4. * Copyright 2006 Pengutronix
  5. * Sascha Hauer <s.hauer@pengutronix.de>
  6. * Copyright 2007 Pengutronix
  7. * Juergen Beisert <j.beisert@pengutronix.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. /include/ "mpc5200b.dtsi"
  15. / {
  16. model = "phytec,pcm030";
  17. compatible = "phytec,pcm030";
  18. soc5200@f0000000 {
  19. timer@600 { // General Purpose Timer
  20. fsl,has-wdt;
  21. };
  22. gpt2: timer@620 { // General Purpose Timer in GPIO mode
  23. compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
  24. gpio-controller;
  25. #gpio-cells = <2>;
  26. };
  27. gpt3: timer@630 { // General Purpose Timer in GPIO mode
  28. compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
  29. gpio-controller;
  30. #gpio-cells = <2>;
  31. };
  32. gpt4: timer@640 { // General Purpose Timer in GPIO mode
  33. compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
  34. gpio-controller;
  35. #gpio-cells = <2>;
  36. };
  37. gpt5: timer@650 { // General Purpose Timer in GPIO mode
  38. compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
  39. gpio-controller;
  40. #gpio-cells = <2>;
  41. };
  42. gpt6: timer@660 { // General Purpose Timer in GPIO mode
  43. compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
  44. gpio-controller;
  45. #gpio-cells = <2>;
  46. };
  47. gpt7: timer@670 { // General Purpose Timer in GPIO mode
  48. compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
  49. gpio-controller;
  50. #gpio-cells = <2>;
  51. };
  52. psc@2000 { /* PSC1 in ac97 mode */
  53. compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
  54. cell-index = <0>;
  55. };
  56. /* PSC2 port is used by CAN1/2 */
  57. psc@2200 {
  58. status = "disabled";
  59. };
  60. psc@2400 { /* PSC3 in UART mode */
  61. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  62. };
  63. /* PSC4 is ??? */
  64. psc@2600 {
  65. status = "disabled";
  66. };
  67. /* PSC5 is ??? */
  68. psc@2800 {
  69. status = "disabled";
  70. };
  71. psc@2c00 { /* PSC6 in UART mode */
  72. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  73. };
  74. ethernet@3000 {
  75. phy-handle = <&phy0>;
  76. };
  77. mdio@3000 {
  78. phy0: ethernet-phy@0 {
  79. reg = <0>;
  80. };
  81. };
  82. i2c@3d40 {
  83. rtc@51 {
  84. compatible = "nxp,pcf8563";
  85. reg = <0x51>;
  86. };
  87. eeprom@52 {
  88. compatible = "catalyst,24c32";
  89. reg = <0x52>;
  90. pagesize = <32>;
  91. };
  92. };
  93. sram@8000 {
  94. compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
  95. reg = <0x8000 0x4000>;
  96. };
  97. };
  98. pci@f0000d00 {
  99. interrupt-map-mask = <0xf800 0 0 7>;
  100. interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
  101. 0xc000 0 0 2 &mpc5200_pic 1 1 3
  102. 0xc000 0 0 3 &mpc5200_pic 1 2 3
  103. 0xc000 0 0 4 &mpc5200_pic 1 3 3
  104. 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
  105. 0xc800 0 0 2 &mpc5200_pic 1 2 3
  106. 0xc800 0 0 3 &mpc5200_pic 1 3 3
  107. 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
  108. ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
  109. 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
  110. 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
  111. };
  112. localbus {
  113. status = "disabled";
  114. };
  115. };