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/debug.cpp

https://github.com/tonioni/WinUAE
C++ | 7823 lines | 7210 code | 509 blank | 104 comment | 2449 complexity | cf330f5eec37f77f7e4a85245c01a51d MD5 | raw file
  1. /*
  2. * UAE - The Un*x Amiga Emulator
  3. *
  4. * Debugger
  5. *
  6. * (c) 1995 Bernd Schmidt
  7. * (c) 2006 Toni Wilen
  8. *
  9. */
  10. #include "sysconfig.h"
  11. #include "sysdeps.h"
  12. #include <ctype.h>
  13. #include <signal.h>
  14. #include "options.h"
  15. #include "uae.h"
  16. #include "memory.h"
  17. #include "custom.h"
  18. #include "newcpu.h"
  19. #include "cpu_prefetch.h"
  20. #include "debug.h"
  21. #include "disasm.h"
  22. #include "debugmem.h"
  23. #include "cia.h"
  24. #include "xwin.h"
  25. #include "identify.h"
  26. #include "audio.h"
  27. #include "sounddep/sound.h"
  28. #include "disk.h"
  29. #include "savestate.h"
  30. #include "autoconf.h"
  31. #include "akiko.h"
  32. #include "inputdevice.h"
  33. #include "crc32.h"
  34. #include "cpummu.h"
  35. #include "rommgr.h"
  36. #include "inputrecord.h"
  37. #include "calc.h"
  38. #include "cpummu.h"
  39. #include "cpummu030.h"
  40. #include "ar.h"
  41. #include "pci.h"
  42. #include "ppc/ppcd.h"
  43. #include "uae/io.h"
  44. #include "uae/ppc.h"
  45. #include "drawing.h"
  46. #include "devices.h"
  47. #include "blitter.h"
  48. #include "ini.h"
  49. #include "readcpu.h"
  50. #include "cputbl.h"
  51. #include "keybuf.h"
  52. static int trace_mode;
  53. static uae_u32 trace_param[3];
  54. int debugger_active;
  55. static int debug_rewind;
  56. static int memwatch_triggered;
  57. static int inside_debugger;
  58. int debugger_used;
  59. int memwatch_access_validator;
  60. int memwatch_enabled;
  61. int debugging;
  62. int exception_debugging;
  63. int no_trace_exceptions;
  64. int debug_copper = 0;
  65. int debug_dma = 0, debug_heatmap = 0;
  66. int debug_sprite_mask = 0xff;
  67. int debug_illegal = 0;
  68. uae_u64 debug_illegal_mask;
  69. static int debug_mmu_mode;
  70. static bool break_if_enforcer;
  71. static uaecptr debug_pc;
  72. static int trace_cycles;
  73. static int last_hpos1, last_hpos2;
  74. static int last_vpos1, last_vpos2;
  75. static int last_frame = -1;
  76. static uae_u32 last_cycles1, last_cycles2;
  77. static uaecptr processptr;
  78. static uae_char *processname;
  79. static uaecptr debug_copper_pc;
  80. extern int audio_channel_mask;
  81. extern int inputdevice_logging;
  82. static void debug_cycles(void)
  83. {
  84. trace_cycles = 1;
  85. last_cycles2 = get_cycles();
  86. last_vpos2 = vpos;
  87. last_hpos2 = current_hpos();
  88. }
  89. void deactivate_debugger (void)
  90. {
  91. inside_debugger = 0;
  92. debugger_active = 0;
  93. debugging = 0;
  94. exception_debugging = 0;
  95. processptr = 0;
  96. xfree (processname);
  97. processname = NULL;
  98. debugmem_enable();
  99. debug_pc = 0xffffffff;
  100. keybuf_ignore_next_release();
  101. }
  102. void activate_debugger (void)
  103. {
  104. disasm_init();
  105. if (isfullscreen() > 0)
  106. return;
  107. debugger_load_libraries();
  108. debugger_used = 1;
  109. inside_debugger = 1;
  110. debug_pc = 0xffffffff;
  111. trace_mode = 0;
  112. if (debugger_active) {
  113. // already in debugger but some break point triggered
  114. // during disassembly etc..
  115. return;
  116. }
  117. debug_cycles();
  118. debugger_active = 1;
  119. set_special (SPCFLAG_BRK);
  120. debugging = 1;
  121. mmu_triggered = 0;
  122. debugmem_disable();
  123. }
  124. void activate_debugger_new(void)
  125. {
  126. activate_debugger();
  127. debug_pc = M68K_GETPC;
  128. }
  129. void activate_debugger_new_pc(uaecptr pc, int len)
  130. {
  131. activate_debugger();
  132. trace_mode = TRACE_RANGE_PC;
  133. trace_param[0] = pc;
  134. trace_param[1] = pc + len;
  135. }
  136. bool debug_enforcer(void)
  137. {
  138. if (!break_if_enforcer)
  139. return false;
  140. activate_debugger();
  141. return true;
  142. }
  143. int firsthist = 0;
  144. int lasthist = 0;
  145. struct cpuhistory {
  146. struct regstruct regs;
  147. int fp, vpos, hpos;
  148. };
  149. static struct cpuhistory history[MAX_HIST];
  150. static const TCHAR help[] = {
  151. _T(" HELP for UAE Debugger\n")
  152. _T(" -----------------------\n\n")
  153. _T(" g [<address>] Start execution at the current address or <address>.\n")
  154. _T(" c Dump state of the CIA, disk drives and custom registers.\n")
  155. _T(" r Dump state of the CPU.\n")
  156. _T(" r <reg> <value> Modify CPU registers (Dx,Ax,USP,ISP,VBR,...).\n")
  157. _T(" rc[d] Show CPU instruction or data cache contents.\n")
  158. _T(" m <address> [<lines>] Memory dump starting at <address>.\n")
  159. _T(" a <address> Assembler.\n")
  160. _T(" d <address> [<lines>] Disassembly starting at <address>.\n")
  161. _T(" t [instructions] Step one or more instructions.\n")
  162. _T(" z Step through one instruction - useful for JSR, DBRA etc.\n")
  163. _T(" f Step forward until PC in RAM (\"boot block finder\").\n")
  164. _T(" f <address> Add/remove breakpoint.\n")
  165. _T(" fa <address> [<start>] [<end>]\n")
  166. _T(" Find effective address <address>.\n")
  167. _T(" fi Step forward until PC points to RTS, RTD or RTE.\n")
  168. _T(" fi <opcode> [<w2>] [<w3>] Step forward until PC points to <opcode>.\n")
  169. _T(" fp \"<name>\"/<addr> Step forward until process <name> or <addr> is active.\n")
  170. _T(" fl List breakpoints.\n")
  171. _T(" fd Remove all breakpoints.\n")
  172. _T(" fs <lines to wait> | <vpos> <hpos> Wait n scanlines/position.\n")
  173. _T(" fc <CCKs to wait> Wait n color clocks.\n")
  174. _T(" fo <num> <reg> <oper> <val> [<mask> <val2>] Conditional register breakpoint.\n")
  175. _T(" reg=Dx,Ax,PC,USP,ISP,VBR,SR. oper:!=,==,<,>,>=,<=,-,!- (-=val to val2 range).\n")
  176. _T(" f <addr1> <addr2> Step forward until <addr1> <= PC <= <addr2>.\n")
  177. _T(" e[x] Dump contents of all custom registers, ea = AGA colors.\n")
  178. _T(" i [<addr>] Dump contents of interrupt and trap vectors.\n")
  179. _T(" il [<mask>] Exception breakpoint.\n")
  180. _T(" o <0-2|addr> [<lines>]View memory as Copper instructions.\n")
  181. _T(" od Enable/disable Copper vpos/hpos tracing.\n")
  182. _T(" ot Copper single step trace.\n")
  183. _T(" ob <addr> Copper breakpoint.\n")
  184. _T(" H[H] <cnt> Show PC history (HH=full CPU info) <cnt> instructions.\n")
  185. _T(" C <value> Search for values like energy or lifes in games.\n")
  186. _T(" Cl List currently found trainer addresses.\n")
  187. _T(" D[idxzs <[max diff]>] Deep trainer. i=new value must be larger, d=smaller,\n")
  188. _T(" x = must be same, z = must be different, s = restart.\n")
  189. _T(" W <addr> <values[.x] separated by space> Write into Amiga memory.\n")
  190. _T(" W <addr> 'string' Write into Amiga memory.\n")
  191. _T(" Wf <addr> <endaddr> <bytes or string like above>, fill memory.\n")
  192. _T(" Wc <addr> <endaddr> <destaddr>, copy memory.\n")
  193. _T(" w <num> <address> <length> <R/W/I> <F/C/L/N> [<value>[.x]] (read/write/opcode) (freeze/mustchange/logonly/nobreak).\n")
  194. _T(" Add/remove memory watchpoints.\n")
  195. _T(" wd [<0-1>] Enable illegal access logger. 1 = enable break.\n")
  196. _T(" L <file> <addr> [<n>] Load a block of Amiga memory.\n")
  197. _T(" S <file> <addr> <n> Save a block of Amiga memory.\n")
  198. _T(" s \"<string>\"/<values> [<addr>] [<length>]\n")
  199. _T(" Search for string/bytes.\n")
  200. _T(" T or Tt Show exec tasks and their PCs.\n")
  201. _T(" Td,Tl,Tr,Tp,Ts,TS,Ti,TO,TM,Tf Show devs, libs, resources, ports, semaphores,\n")
  202. _T(" residents, interrupts, doslist, memorylist, fsres.\n")
  203. _T(" b Step to previous state capture position.\n")
  204. _T(" M<a/b/s> <val> Enable or disable audio channels, bitplanes or sprites.\n")
  205. _T(" sp <addr> [<addr2][<size>] Dump sprite information.\n")
  206. _T(" di <mode> [<track>] Break on disk access. R=DMA read,W=write,RW=both,P=PIO.\n")
  207. _T(" Also enables level 1 disk logging.\n")
  208. _T(" did <log level> Enable disk logging.\n")
  209. _T(" dj [<level bitmask>] Enable joystick/mouse input debugging.\n")
  210. _T(" smc [<0-1>] Enable self-modifying code detector. 1 = enable break.\n")
  211. _T(" dm Dump current address space map.\n")
  212. _T(" v <vpos> [<hpos>] Show DMA data (accurate only in cycle-exact mode).\n")
  213. _T(" v [-1 to -4] = enable visual DMA debugger.\n")
  214. _T(" vh [<ratio> <lines>] \"Heat map\"\n")
  215. _T(" I <custom event> Send custom event string\n")
  216. _T(" ?<value> Hex ($ and 0x)/Bin (%)/Dec (!) converter and calculator.\n")
  217. #ifdef _WIN32
  218. _T(" x Close debugger.\n")
  219. _T(" xx Switch between console and GUI debugger.\n")
  220. _T(" mg <address> Memory dump starting at <address> in GUI.\n")
  221. _T(" dg <address> Disassembly starting at <address> in GUI.\n")
  222. #endif
  223. _T(" q Quit the emulator. You don't want to use this command.\n\n")
  224. };
  225. void debug_help (void)
  226. {
  227. console_out (help);
  228. }
  229. struct mw_acc {
  230. uae_u32 mask;
  231. const TCHAR *name;
  232. };
  233. static const struct mw_acc memwatch_access_masks[] =
  234. {
  235. { MW_MASK_ALL, _T("ALL") },
  236. { MW_MASK_NONE, _T("NONE") },
  237. { MW_MASK_ALL & ~(MW_MASK_CPU_I | MW_MASK_CPU_D_R | MW_MASK_CPU_D_W), _T("DMA") },
  238. { MW_MASK_BLITTER_A | MW_MASK_BLITTER_B | MW_MASK_BLITTER_C | MW_MASK_BLITTER_D_N | MW_MASK_BLITTER_D_L | MW_MASK_BLITTER_D_F, _T("BLT") },
  239. { MW_MASK_BLITTER_D_N | MW_MASK_BLITTER_D_L | MW_MASK_BLITTER_D_F, _T("BLTD") },
  240. { MW_MASK_AUDIO_0 | MW_MASK_AUDIO_1 | MW_MASK_AUDIO_2 | MW_MASK_AUDIO_3, _T("AUD") },
  241. { MW_MASK_BPL_0 | MW_MASK_BPL_1 | MW_MASK_BPL_2 | MW_MASK_BPL_3 |
  242. MW_MASK_BPL_4 | MW_MASK_BPL_5 | MW_MASK_BPL_6 | MW_MASK_BPL_7, _T("BPL") },
  243. { MW_MASK_SPR_0 | MW_MASK_SPR_1 | MW_MASK_SPR_2 | MW_MASK_SPR_3 |
  244. MW_MASK_SPR_4 | MW_MASK_SPR_5 | MW_MASK_SPR_6 | MW_MASK_SPR_7, _T("SPR") },
  245. { MW_MASK_CPU_I | MW_MASK_CPU_D_R | MW_MASK_CPU_D_W, _T("CPU") },
  246. { MW_MASK_CPU_D_R | MW_MASK_CPU_D_W, _T("CPUD") },
  247. { MW_MASK_CPU_I, _T("CPUI") },
  248. { MW_MASK_CPU_D_R, _T("CPUDR") },
  249. { MW_MASK_CPU_D_W, _T("CPUDW") },
  250. { MW_MASK_COPPER, _T("COP") },
  251. { MW_MASK_BLITTER_A, _T("BLTA") },
  252. { MW_MASK_BLITTER_B, _T("BLTB") },
  253. { MW_MASK_BLITTER_C, _T("BLTC") },
  254. { MW_MASK_BLITTER_D_N, _T("BLTDN") },
  255. { MW_MASK_BLITTER_D_L, _T("BLTDL") },
  256. { MW_MASK_BLITTER_D_F, _T("BLTDF") },
  257. { MW_MASK_DISK, _T("DSK") },
  258. { MW_MASK_AUDIO_0, _T("AUD0") },
  259. { MW_MASK_AUDIO_1, _T("AUD1") },
  260. { MW_MASK_AUDIO_2, _T("AUD2") },
  261. { MW_MASK_AUDIO_3, _T("AUD3") },
  262. { MW_MASK_BPL_0, _T("BPL0") },
  263. { MW_MASK_BPL_1, _T("BPL1") },
  264. { MW_MASK_BPL_2, _T("BPL2") },
  265. { MW_MASK_BPL_3, _T("BPL3") },
  266. { MW_MASK_BPL_4, _T("BPL4") },
  267. { MW_MASK_BPL_5, _T("BPL5") },
  268. { MW_MASK_BPL_6, _T("BPL6") },
  269. { MW_MASK_BPL_7, _T("BPL7") },
  270. { MW_MASK_SPR_0, _T("SPR0") },
  271. { MW_MASK_SPR_1, _T("SPR1") },
  272. { MW_MASK_SPR_2, _T("SPR2") },
  273. { MW_MASK_SPR_3, _T("SPR3") },
  274. { MW_MASK_SPR_4, _T("SPR4") },
  275. { MW_MASK_SPR_5, _T("SPR5") },
  276. { MW_MASK_SPR_6, _T("SPR6") },
  277. { MW_MASK_SPR_7, _T("SPR7") },
  278. { 0, NULL },
  279. };
  280. static void mw_help(void)
  281. {
  282. for (int i = 0; memwatch_access_masks[i].mask; i++) {
  283. console_out_f(_T("%s "), memwatch_access_masks[i].name);
  284. }
  285. console_out_f(_T("\n"));
  286. }
  287. static int debug_linecounter;
  288. #define MAX_LINECOUNTER 1000
  289. static int debug_out (const TCHAR *format, ...)
  290. {
  291. va_list parms;
  292. TCHAR buffer[4000];
  293. va_start (parms, format);
  294. _vsntprintf (buffer, 4000 - 1, format, parms);
  295. va_end (parms);
  296. console_out (buffer);
  297. if (debug_linecounter < MAX_LINECOUNTER)
  298. debug_linecounter++;
  299. if (debug_linecounter >= MAX_LINECOUNTER)
  300. return 0;
  301. return 1;
  302. }
  303. uae_u32 get_byte_debug (uaecptr addr)
  304. {
  305. uae_u32 v = 0xff;
  306. if (debug_mmu_mode) {
  307. flagtype olds = regs.s;
  308. regs.s = (debug_mmu_mode & 4) != 0;
  309. TRY(p) {
  310. if (currprefs.mmu_model == 68030) {
  311. v = mmu030_get_generic (addr, debug_mmu_mode, sz_byte, MMU030_SSW_SIZE_B);
  312. } else {
  313. if (debug_mmu_mode & 1) {
  314. bool odd = (addr & 1) != 0;
  315. addr &= ~1;
  316. v = mmu_get_iword(addr, sz_byte);
  317. if (!odd)
  318. v >>= 8;
  319. } else {
  320. v = mmu_get_user_byte (addr, regs.s != 0, false, sz_byte, false);
  321. }
  322. }
  323. } CATCH(p) {
  324. } ENDTRY
  325. regs.s = olds;
  326. } else {
  327. v = get_byte (addr);
  328. }
  329. return v;
  330. }
  331. uae_u32 get_word_debug (uaecptr addr)
  332. {
  333. uae_u32 v = 0xffff;
  334. if (debug_mmu_mode) {
  335. flagtype olds = regs.s;
  336. regs.s = (debug_mmu_mode & 4) != 0;
  337. TRY(p) {
  338. if (currprefs.mmu_model == 68030) {
  339. v = mmu030_get_generic (addr, debug_mmu_mode, sz_word, MMU030_SSW_SIZE_W);
  340. } else {
  341. if (debug_mmu_mode & 1) {
  342. v = mmu_get_iword(addr, sz_word);
  343. } else {
  344. v = mmu_get_user_word (addr, regs.s != 0, false, sz_word, false);
  345. }
  346. }
  347. } CATCH(p) {
  348. } ENDTRY
  349. regs.s = olds;
  350. } else {
  351. v = get_word (addr);
  352. }
  353. return v;
  354. }
  355. uae_u32 get_long_debug (uaecptr addr)
  356. {
  357. uae_u32 v = 0xffffffff;
  358. if (debug_mmu_mode) {
  359. flagtype olds = regs.s;
  360. regs.s = (debug_mmu_mode & 4) != 0;
  361. TRY(p) {
  362. if (currprefs.mmu_model == 68030) {
  363. v = mmu030_get_generic (addr, debug_mmu_mode, sz_long, MMU030_SSW_SIZE_L);
  364. } else {
  365. if (debug_mmu_mode & 1) {
  366. v = mmu_get_ilong(addr, sz_long);
  367. } else {
  368. v = mmu_get_user_long (addr, regs.s != 0, false, sz_long, false);
  369. }
  370. }
  371. } CATCH(p) {
  372. } ENDTRY
  373. regs.s = olds;
  374. } else {
  375. v = get_long (addr);
  376. }
  377. return v;
  378. }
  379. uae_u32 get_iword_debug (uaecptr addr)
  380. {
  381. if (debug_mmu_mode) {
  382. return get_word_debug (addr);
  383. } else {
  384. if (valid_address (addr, 2))
  385. return get_word (addr);
  386. return 0xffff;
  387. }
  388. }
  389. uae_u32 get_ilong_debug (uaecptr addr)
  390. {
  391. if (debug_mmu_mode) {
  392. return get_long_debug (addr);
  393. } else {
  394. if (valid_address (addr, 4))
  395. return get_long (addr);
  396. return 0xffffffff;
  397. }
  398. }
  399. uae_u8 *get_real_address_debug(uaecptr addr)
  400. {
  401. if (debug_mmu_mode) {
  402. flagtype olds = regs.s;
  403. TRY(p) {
  404. if (currprefs.mmu_model >= 68040)
  405. addr = mmu_translate(addr, 0, regs.s != 0, (debug_mmu_mode & 1), false, 0);
  406. else
  407. addr = mmu030_translate(addr, regs.s != 0, (debug_mmu_mode & 1), false);
  408. } CATCH(p) {
  409. } ENDTRY
  410. }
  411. return get_real_address(addr);
  412. }
  413. int debug_safe_addr (uaecptr addr, int size)
  414. {
  415. if (debug_mmu_mode) {
  416. flagtype olds = regs.s;
  417. regs.s = (debug_mmu_mode & 4) != 0;
  418. TRY(p) {
  419. if (currprefs.mmu_model >= 68040)
  420. addr = mmu_translate (addr, 0, regs.s != 0, (debug_mmu_mode & 1), false, size);
  421. else
  422. addr = mmu030_translate (addr, regs.s != 0, (debug_mmu_mode & 1), false);
  423. } CATCH(p) {
  424. STOPTRY;
  425. return 0;
  426. } ENDTRY
  427. regs.s = olds;
  428. }
  429. addrbank *ab = &get_mem_bank (addr);
  430. if (!ab)
  431. return 0;
  432. if (ab->flags & ABFLAG_SAFE)
  433. return 1;
  434. if (!ab->check (addr, size))
  435. return 0;
  436. if (ab->flags & (ABFLAG_RAM | ABFLAG_ROM | ABFLAG_ROMIN | ABFLAG_SAFE))
  437. return 1;
  438. return 0;
  439. }
  440. static bool iscancel (int counter)
  441. {
  442. static int cnt;
  443. cnt++;
  444. if (cnt < counter)
  445. return false;
  446. cnt = 0;
  447. if (!console_isch ())
  448. return false;
  449. console_getch ();
  450. return true;
  451. }
  452. static bool isoperator(TCHAR **cp)
  453. {
  454. TCHAR c = **cp;
  455. return c == '+' || c == '-' || c == '/' || c == '*' || c == '(' || c == ')';
  456. }
  457. static void ignore_ws (TCHAR **c)
  458. {
  459. while (**c && _istspace(**c))
  460. (*c)++;
  461. }
  462. static TCHAR peekchar (TCHAR **c)
  463. {
  464. return **c;
  465. }
  466. static TCHAR readchar (TCHAR **c)
  467. {
  468. TCHAR cc = **c;
  469. (*c)++;
  470. return cc;
  471. }
  472. static TCHAR next_char(TCHAR **c)
  473. {
  474. ignore_ws (c);
  475. return *(*c)++;
  476. }
  477. static TCHAR next_char2(TCHAR **c)
  478. {
  479. return *(*c)++;
  480. }
  481. static TCHAR peek_next_char (TCHAR **c)
  482. {
  483. TCHAR *pc = *c;
  484. return pc[1];
  485. }
  486. static int more_params(TCHAR **c)
  487. {
  488. ignore_ws(c);
  489. return (**c) != 0;
  490. }
  491. static int more_params2(TCHAR **c)
  492. {
  493. return (**c) != 0;
  494. }
  495. static uae_u32 readint (TCHAR **c);
  496. static uae_u32 readbin (TCHAR **c);
  497. static uae_u32 readhex (TCHAR **c);
  498. static const TCHAR *debugoper[] = {
  499. _T("=="),
  500. _T("!="),
  501. _T("<="),
  502. _T(">="),
  503. _T("<"),
  504. _T(">"),
  505. _T("-"),
  506. _T("!-"),
  507. NULL
  508. };
  509. static int getoperidx(TCHAR **c)
  510. {
  511. int i;
  512. TCHAR *p = *c;
  513. TCHAR tmp[10];
  514. int extra = 0;
  515. i = 0;
  516. while (p[i]) {
  517. tmp[i] = _totupper(p[i]);
  518. if (i >= sizeof(tmp) / sizeof(TCHAR) - 1)
  519. break;
  520. i++;
  521. }
  522. tmp[i] = 0;
  523. if (!_tcsncmp(tmp, _T("!="), 2)) {
  524. (*c) += 2;
  525. return BREAKPOINT_CMP_NEQUAL;
  526. } else if (!_tcsncmp(tmp, _T("=="), 2)) {
  527. (*c) += 2;
  528. return BREAKPOINT_CMP_EQUAL;
  529. } else if (!_tcsncmp(tmp, _T(">="), 2)) {
  530. (*c) += 2;
  531. return BREAKPOINT_CMP_LARGER_EQUAL;
  532. } else if (!_tcsncmp(tmp, _T("<="), 2)) {
  533. (*c) += 2;
  534. return BREAKPOINT_CMP_SMALLER_EQUAL;
  535. } else if (!_tcsncmp(tmp, _T(">"), 1)) {
  536. (*c) += 1;
  537. return BREAKPOINT_CMP_LARGER;
  538. } else if (!_tcsncmp(tmp, _T("<"), 1)) {
  539. (*c) += 1;
  540. return BREAKPOINT_CMP_SMALLER;
  541. } else if (!_tcsncmp(tmp, _T("-"), 1)) {
  542. (*c) += 1;
  543. return BREAKPOINT_CMP_RANGE;
  544. } else if (!_tcsncmp(tmp, _T("!-"), 2)) {
  545. (*c) += 2;
  546. return BREAKPOINT_CMP_NRANGE;
  547. }
  548. return -1;
  549. }
  550. static const TCHAR *debugregs[] = {
  551. _T("D0"),
  552. _T("D1"),
  553. _T("D2"),
  554. _T("D3"),
  555. _T("D4"),
  556. _T("D5"),
  557. _T("D6"),
  558. _T("D7"),
  559. _T("A0"),
  560. _T("A1"),
  561. _T("A2"),
  562. _T("A3"),
  563. _T("A4"),
  564. _T("A5"),
  565. _T("A6"),
  566. _T("A7"),
  567. _T("PC"),
  568. _T("USP"),
  569. _T("MSP"),
  570. _T("ISP"),
  571. _T("VBR"),
  572. _T("SR"),
  573. _T("CCR"),
  574. _T("CACR"),
  575. _T("CAAR"),
  576. _T("SFC"),
  577. _T("DFC"),
  578. _T("TC"),
  579. _T("ITT0"),
  580. _T("ITT1"),
  581. _T("DTT0"),
  582. _T("DTT1"),
  583. _T("BUSC"),
  584. _T("PCR"),
  585. NULL
  586. };
  587. static int getregidx(TCHAR **c)
  588. {
  589. int i;
  590. TCHAR *p = *c;
  591. TCHAR tmp[10];
  592. int extra = 0;
  593. i = 0;
  594. while (p[i]) {
  595. tmp[i] = _totupper(p[i]);
  596. if (i >= sizeof(tmp) / sizeof(TCHAR) - 1)
  597. break;
  598. i++;
  599. }
  600. tmp[i] = 0;
  601. for (int i = 0; debugregs[i]; i++) {
  602. if (!_tcsncmp(tmp, debugregs[i], _tcslen(debugregs[i]))) {
  603. (*c) += _tcslen(debugregs[i]);
  604. return i;
  605. }
  606. }
  607. return -1;
  608. }
  609. static uae_u32 returnregx(int regid)
  610. {
  611. if (regid < BREAKPOINT_REG_PC)
  612. return regs.regs[regid];
  613. switch(regid)
  614. {
  615. case BREAKPOINT_REG_PC:
  616. return M68K_GETPC;
  617. case BREAKPOINT_REG_USP:
  618. return regs.usp;
  619. case BREAKPOINT_REG_MSP:
  620. return regs.msp;
  621. case BREAKPOINT_REG_ISP:
  622. return regs.isp;
  623. case BREAKPOINT_REG_VBR:
  624. return regs.vbr;
  625. case BREAKPOINT_REG_SR:
  626. MakeSR();
  627. return regs.sr;
  628. case BREAKPOINT_REG_CCR:
  629. MakeSR();
  630. return regs.sr & 31;
  631. case BREAKPOINT_REG_CACR:
  632. return regs.cacr;
  633. case BREAKPOINT_REG_CAAR:
  634. return regs.caar;
  635. case BREAKPOINT_REG_SFC:
  636. return regs.sfc;
  637. case BREAKPOINT_REG_DFC:
  638. return regs.dfc;
  639. case BREAKPOINT_REG_TC:
  640. if (currprefs.cpu_model == 68030)
  641. return tc_030;
  642. return regs.tcr;
  643. case BREAKPOINT_REG_ITT0:
  644. if (currprefs.cpu_model == 68030)
  645. return tt0_030;
  646. return regs.itt0;
  647. case BREAKPOINT_REG_ITT1:
  648. if (currprefs.cpu_model == 68030)
  649. return tt1_030;
  650. return regs.itt1;
  651. case BREAKPOINT_REG_DTT0:
  652. return regs.dtt0;
  653. case BREAKPOINT_REG_DTT1:
  654. return regs.dtt1;
  655. case BREAKPOINT_REG_BUSC:
  656. return regs.buscr;
  657. case BREAKPOINT_REG_PCR:
  658. return regs.fpcr;
  659. }
  660. return 0;
  661. }
  662. static int readregx (TCHAR **c, uae_u32 *valp)
  663. {
  664. int i;
  665. uae_u32 addr;
  666. TCHAR *p = *c;
  667. TCHAR tmp[10], *tp;
  668. int extra = 0;
  669. addr = 0;
  670. i = 0;
  671. while (p[i]) {
  672. tmp[i] = _totupper (p[i]);
  673. if (i >= sizeof (tmp) / sizeof (TCHAR) - 1)
  674. break;
  675. i++;
  676. }
  677. tmp[i] = 0;
  678. tp = tmp;
  679. if (_totupper (tmp[0]) == 'R') {
  680. tp = tmp + 1;
  681. extra = 1;
  682. }
  683. if (!_tcsncmp (tp, _T("USP"), 3)) {
  684. addr = regs.usp;
  685. (*c) += 3;
  686. } else if (!_tcsncmp (tp, _T("VBR"), 3)) {
  687. addr = regs.vbr;
  688. (*c) += 3;
  689. } else if (!_tcsncmp (tp, _T("MSP"), 3)) {
  690. addr = regs.msp;
  691. (*c) += 3;
  692. } else if (!_tcsncmp (tp, _T("ISP"), 3)) {
  693. addr = regs.isp;
  694. (*c) += 3;
  695. } else if (!_tcsncmp (tp, _T("PC"), 2)) {
  696. addr = regs.pc;
  697. (*c) += 2;
  698. } else if (tp[0] == 'A' || tp[0] == 'D') {
  699. int reg = 0;
  700. if (tp[0] == 'A')
  701. reg += 8;
  702. reg += tp[1] - '0';
  703. if (reg < 0 || reg > 15)
  704. return 0;
  705. addr = regs.regs[reg];
  706. (*c) += 2;
  707. } else {
  708. return 0;
  709. }
  710. *valp = addr;
  711. (*c) += extra;
  712. return 1;
  713. }
  714. static bool readbinx (TCHAR **c, uae_u32 *valp)
  715. {
  716. uae_u32 val = 0;
  717. bool first = true;
  718. ignore_ws (c);
  719. for (;;) {
  720. TCHAR nc = **c;
  721. if (nc != '1' && nc != '0') {
  722. if (first)
  723. return false;
  724. break;
  725. }
  726. first = false;
  727. (*c)++;
  728. val <<= 1;
  729. if (nc == '1')
  730. val |= 1;
  731. }
  732. *valp = val;
  733. return true;
  734. }
  735. static bool readhexx (TCHAR **c, uae_u32 *valp)
  736. {
  737. uae_u32 val = 0;
  738. TCHAR nc;
  739. ignore_ws (c);
  740. if (!isxdigit (peekchar (c)))
  741. return false;
  742. while (isxdigit (nc = **c)) {
  743. (*c)++;
  744. val *= 16;
  745. nc = _totupper (nc);
  746. if (isdigit (nc)) {
  747. val += nc - '0';
  748. } else {
  749. val += nc - 'A' + 10;
  750. }
  751. }
  752. *valp = val;
  753. return true;
  754. }
  755. static bool readintx (TCHAR **c, uae_u32 *valp)
  756. {
  757. uae_u32 val = 0;
  758. TCHAR nc;
  759. int negative = 0;
  760. ignore_ws (c);
  761. if (**c == '-')
  762. negative = 1, (*c)++;
  763. if (!isdigit (peekchar (c)))
  764. return false;
  765. while (isdigit (nc = **c)) {
  766. (*c)++;
  767. val *= 10;
  768. val += nc - '0';
  769. }
  770. *valp = val * (negative ? -1 : 1);
  771. return true;
  772. }
  773. static int checkvaltype2 (TCHAR **c, uae_u32 *val, TCHAR def)
  774. {
  775. TCHAR nc;
  776. ignore_ws (c);
  777. nc = _totupper (**c);
  778. if (nc == '!') {
  779. (*c)++;
  780. return readintx (c, val) ? 1 : 0;
  781. }
  782. if (nc == '$') {
  783. (*c)++;
  784. return readhexx (c, val) ? 1 : 0;
  785. }
  786. if (nc == '0' && _totupper ((*c)[1]) == 'X') {
  787. (*c)+= 2;
  788. return readhexx (c, val) ? 1 : 0;
  789. }
  790. if (nc == '%') {
  791. (*c)++;
  792. return readbinx (c, val) ? 1: 0;
  793. }
  794. if (nc >= 'A' && nc <= 'Z' && nc != 'A' && nc != 'D') {
  795. if (readregx (c, val))
  796. return 1;
  797. }
  798. TCHAR name[256];
  799. name[0] = 0;
  800. for (int i = 0; i < sizeof name / sizeof(TCHAR) - 1; i++) {
  801. nc = (*c)[i];
  802. if (nc == 0 || nc == ' ')
  803. break;
  804. name[i] = nc;
  805. name[i + 1] = 0;
  806. }
  807. if (name[0]) {
  808. TCHAR *np = name;
  809. if (*np == '#')
  810. np++;
  811. if (debugmem_get_symbol_value(np, val)) {
  812. (*c) += _tcslen(name);
  813. return 1;
  814. }
  815. }
  816. if (def == '!') {
  817. return readintx (c, val) ? -1 : 0;
  818. } else if (def == '$') {
  819. return readhexx (c, val) ? -1 : 0;
  820. } else if (def == '%') {
  821. return readbinx (c, val) ? -1 : 0;
  822. }
  823. return 0;
  824. }
  825. static int readsize (int val, TCHAR **c)
  826. {
  827. TCHAR cc = _totupper (readchar(c));
  828. if (cc == 'B')
  829. return 1;
  830. if (cc == 'W')
  831. return 2;
  832. if (cc == '3')
  833. return 3;
  834. if (cc == 'L')
  835. return 4;
  836. return 0;
  837. }
  838. static int checkvaltype (TCHAR **cp, uae_u32 *val, int *size, TCHAR def)
  839. {
  840. TCHAR form[256], *p;
  841. bool gotop = false;
  842. double out;
  843. form[0] = 0;
  844. if (size)
  845. *size = 0;
  846. p = form;
  847. for (;;) {
  848. uae_u32 v;
  849. if (!checkvaltype2 (cp, &v, def))
  850. return 0;
  851. *val = v;
  852. // stupid but works!
  853. _stprintf(p, _T("%u"), v);
  854. p += _tcslen (p);
  855. if (peekchar (cp) == '.') {
  856. readchar (cp);
  857. if (size)
  858. *size = readsize (v, cp);
  859. }
  860. if (!isoperator (cp))
  861. break;
  862. gotop = true;
  863. *p++= readchar (cp);
  864. *p = 0;
  865. }
  866. if (!gotop) {
  867. if (size && *size == 0) {
  868. uae_s32 v = (uae_s32)(*val);
  869. if (v > 65535 || v < -32767) {
  870. *size = 4;
  871. } else if (v > 255 || v < -127) {
  872. *size = 2;
  873. } else {
  874. *size = 1;
  875. }
  876. }
  877. return 1;
  878. }
  879. if (calc (form, &out)) {
  880. *val = (uae_u32)out;
  881. if (size && *size == 0) {
  882. uae_s32 v = (uae_s32)(*val);
  883. if (v > 255 || v < -127) {
  884. *size = 2;
  885. } else if (v > 65535 || v < -32767) {
  886. *size = 4;
  887. } else {
  888. *size = 1;
  889. }
  890. }
  891. return 1;
  892. }
  893. return 0;
  894. }
  895. static uae_u32 readnum (TCHAR **c, int *size, TCHAR def)
  896. {
  897. uae_u32 val;
  898. if (checkvaltype (c, &val, size, def))
  899. return val;
  900. return 0;
  901. }
  902. static uae_u32 readint (TCHAR **c)
  903. {
  904. int size;
  905. return readnum (c, &size, '!');
  906. }
  907. static uae_u32 readhex (TCHAR **c)
  908. {
  909. int size;
  910. return readnum (c, &size, '$');
  911. }
  912. static uae_u32 readbin (TCHAR **c)
  913. {
  914. int size;
  915. return readnum (c, &size, '%');
  916. }
  917. static uae_u32 readint (TCHAR **c, int *size)
  918. {
  919. return readnum (c, size, '!');
  920. }
  921. static uae_u32 readhex (TCHAR **c, int *size)
  922. {
  923. return readnum (c, size, '$');
  924. }
  925. static int next_string (TCHAR **c, TCHAR *out, int max, int forceupper)
  926. {
  927. TCHAR *p = out;
  928. int startmarker = 0;
  929. if (**c == '\"') {
  930. startmarker = 1;
  931. (*c)++;
  932. }
  933. *p = 0;
  934. while (**c != 0) {
  935. if (**c == '\"' && startmarker)
  936. break;
  937. if (**c == 32 && !startmarker) {
  938. ignore_ws (c);
  939. break;
  940. }
  941. *p = next_char (c);
  942. if (forceupper)
  943. *p = _totupper(*p);
  944. *++p = 0;
  945. max--;
  946. if (max <= 1)
  947. break;
  948. }
  949. return _tcslen (out);
  950. }
  951. static void converter (TCHAR **c)
  952. {
  953. uae_u32 v = readint (c);
  954. TCHAR s[100];
  955. int i;
  956. for (i = 0; i < 32; i++)
  957. s[i] = (v & (1 << (31 - i))) ? '1' : '0';
  958. s[i] = 0;
  959. console_out_f (_T("0x%08X = %%%s = %u = %d\n"), v, s, v, (uae_s32)v);
  960. }
  961. int notinrom (void)
  962. {
  963. uaecptr pc = munge24 (m68k_getpc ());
  964. if (pc < 0x00e00000 || pc > 0x00ffffff)
  965. return 1;
  966. return 0;
  967. }
  968. static uae_u32 lastaddr (void)
  969. {
  970. int lastbank = currprefs.address_space_24 ? 255 : 65535;
  971. for (int i = lastbank; i >= 0; i--) {
  972. addrbank *ab = get_mem_bank_real(i << 16);
  973. if (ab->baseaddr && (ab->flags & ABFLAG_RAM)) {
  974. return (i + 1) << 16;
  975. }
  976. }
  977. return 0;
  978. }
  979. static uaecptr nextaddr (uaecptr addr, uaecptr last, uaecptr *endp, bool verbose)
  980. {
  981. addrbank *ab;
  982. int lastbank = currprefs.address_space_24 ? 255 : 65535;
  983. if (addr != 0xffffffff) {
  984. addrbank *ab2 = get_mem_bank_real(addr);
  985. addr++;
  986. ab = get_mem_bank_real(addr);
  987. if (ab->baseaddr && (ab->flags & ABFLAG_RAM) && ab == ab2)
  988. return addr;
  989. } else {
  990. addr = 0;
  991. }
  992. while (addr < (lastbank << 16)) {
  993. ab = get_mem_bank_real(addr);
  994. if (ab->baseaddr && (ab->flags & ABFLAG_RAM))
  995. break;
  996. addr += 65536;
  997. }
  998. if (addr >= (lastbank << 16)) {
  999. if (endp)
  1000. *endp = 0xffffffff;
  1001. return 0xffffffff;
  1002. }
  1003. uaecptr start = addr;
  1004. while (addr <= (lastbank << 16)) {
  1005. addrbank *ab2 = get_mem_bank_real(addr);
  1006. if ((last && last != 0xffffffff && addr >= last) || !ab2->baseaddr || !(ab2->flags & ABFLAG_RAM) || ab != ab2) {
  1007. if (endp)
  1008. *endp = addr;
  1009. break;
  1010. }
  1011. addr += 65536;
  1012. }
  1013. if (verbose) {
  1014. console_out_f(_T("Scanning.. %08x - %08x (%s)\n"), start, addr, get_mem_bank(start).name);
  1015. }
  1016. return start;
  1017. }
  1018. uaecptr dumpmem2 (uaecptr addr, TCHAR *out, int osize)
  1019. {
  1020. int i, cols = 8;
  1021. int nonsafe = 0;
  1022. if (osize <= (9 + cols * 5 + 1 + 2 * cols))
  1023. return addr;
  1024. _stprintf (out, _T("%08X "), addr);
  1025. for (i = 0; i < cols; i++) {
  1026. uae_u8 b1, b2;
  1027. b1 = b2 = 0;
  1028. if (debug_safe_addr (addr, 1)) {
  1029. b1 = get_byte_debug (addr + 0);
  1030. b2 = get_byte_debug (addr + 1);
  1031. _stprintf (out + 9 + i * 5, _T("%02X%02X "), b1, b2);
  1032. out[9 + cols * 5 + 1 + i * 2 + 0] = b1 >= 32 && b1 < 127 ? b1 : '.';
  1033. out[9 + cols * 5 + 1 + i * 2 + 1] = b2 >= 32 && b2 < 127 ? b2 : '.';
  1034. } else {
  1035. nonsafe++;
  1036. _tcscpy (out + 9 + i * 5, _T("**** "));
  1037. out[9 + cols * 5 + 1 + i * 2 + 0] = '*';
  1038. out[9 + cols * 5 + 1 + i * 2 + 1] = '*';
  1039. }
  1040. addr += 2;
  1041. }
  1042. out[9 + cols * 5] = ' ';
  1043. out[9 + cols * 5 + 1 + 2 * cols] = 0;
  1044. if (nonsafe == cols) {
  1045. addrbank *ab = &get_mem_bank (addr);
  1046. if (ab->name)
  1047. memcpy (out + (9 + 4 + 1) * sizeof (TCHAR), ab->name, _tcslen (ab->name) * sizeof (TCHAR));
  1048. }
  1049. return addr;
  1050. }
  1051. static void dumpmem (uaecptr addr, uaecptr *nxmem, int lines)
  1052. {
  1053. TCHAR line[MAX_LINEWIDTH + 1];
  1054. for (;lines--;) {
  1055. addr = dumpmem2 (addr, line, sizeof(line));
  1056. debug_out (_T("%s"), line);
  1057. if (!debug_out (_T("\n")))
  1058. break;
  1059. }
  1060. *nxmem = addr;
  1061. }
  1062. static void dump_custom_regs(bool aga, bool ext)
  1063. {
  1064. int len;
  1065. uae_u8 *p1, *p2, *p3, *p4;
  1066. TCHAR extra1[256], extra2[256];
  1067. extra1[0] = 0;
  1068. extra2[0] = 0;
  1069. if (aga) {
  1070. dump_aga_custom();
  1071. return;
  1072. }
  1073. p1 = p2 = save_custom (&len, 0, 1);
  1074. p1 += 4; // skip chipset type
  1075. for (int i = 0; i < 4; i++) {
  1076. p4 = p1 + 0xa0 + i * 16;
  1077. p3 = save_audio (i, &len, 0);
  1078. p4[0] = p3[12];
  1079. p4[1] = p3[13];
  1080. p4[2] = p3[14];
  1081. p4[3] = p3[15];
  1082. p4[4] = p3[4];
  1083. p4[5] = p3[5];
  1084. p4[6] = p3[8];
  1085. p4[7] = p3[9];
  1086. p4[8] = 0;
  1087. p4[9] = p3[1];
  1088. p4[10] = p3[10];
  1089. p4[11] = p3[11];
  1090. free (p3);
  1091. }
  1092. int total = 0;
  1093. int i = 0;
  1094. while (custd[i].name) {
  1095. if (!(custd[i].special & CD_NONE))
  1096. total++;
  1097. i++;
  1098. }
  1099. int cnt1 = 0;
  1100. int cnt2 = 0;
  1101. i = 0;
  1102. while (i < total / 2 + 1) {
  1103. for (;;) {
  1104. cnt2++;
  1105. if (!(custd[cnt2].special & CD_NONE))
  1106. break;
  1107. }
  1108. i++;
  1109. }
  1110. for (int i = 0; i < total / 2 + 1; i++) {
  1111. uae_u16 v1, v2;
  1112. int addr1, addr2;
  1113. addr1 = custd[cnt1].adr & 0x1ff;
  1114. addr2 = custd[cnt2].adr & 0x1ff;
  1115. v1 = (p1[addr1 + 0] << 8) | p1[addr1 + 1];
  1116. v2 = (p1[addr2 + 0] << 8) | p1[addr2 + 1];
  1117. if (ext) {
  1118. struct custom_store *cs;
  1119. cs = &custom_storage[addr1 >> 1];
  1120. _stprintf(extra1, _T("\t%04X %08X %s"), cs->value, cs->pc & ~1, (cs->pc & 1) ? _T("COP") : _T("CPU"));
  1121. cs = &custom_storage[addr2 >> 1];
  1122. _stprintf(extra2, _T("\t%04X %08X %s"), cs->value, cs->pc & ~1, (cs->pc & 1) ? _T("COP") : _T("CPU"));
  1123. }
  1124. console_out_f (_T("%03X %s\t%04X%s\t%03X %s\t%04X%s\n"),
  1125. addr1, custd[cnt1].name, v1, extra1,
  1126. addr2, custd[cnt2].name, v2, extra2);
  1127. for (;;) {
  1128. cnt1++;
  1129. if (!(custd[cnt1].special & CD_NONE))
  1130. break;
  1131. }
  1132. for (;;) {
  1133. cnt2++;
  1134. if (!(custd[cnt2].special & CD_NONE))
  1135. break;
  1136. }
  1137. }
  1138. xfree(p2);
  1139. }
  1140. static void dump_vectors (uaecptr addr)
  1141. {
  1142. int i = 0, j = 0;
  1143. if (addr == 0xffffffff)
  1144. addr = regs.vbr;
  1145. while (int_labels[i].name || trap_labels[j].name) {
  1146. if (int_labels[i].name) {
  1147. console_out_f (_T("$%08X %02d: %12s $%08X "), int_labels[i].adr + addr, int_labels[i].adr / 4,
  1148. int_labels[i].name, get_long_debug (int_labels[i].adr + addr));
  1149. i++;
  1150. }
  1151. if (trap_labels[j].name) {
  1152. console_out_f (_T("$%08X %02d: %12s $%08X"), trap_labels[j].adr + addr, trap_labels[j].adr / 4,
  1153. trap_labels[j].name, get_long_debug (trap_labels[j].adr + addr));
  1154. j++;
  1155. }
  1156. console_out (_T("\n"));
  1157. }
  1158. }
  1159. static void disassemble_wait (FILE *file, unsigned long insn)
  1160. {
  1161. int vp, hp, ve, he, bfd, v_mask, h_mask;
  1162. int doout = 0;
  1163. vp = (insn & 0xff000000) >> 24;
  1164. hp = (insn & 0x00fe0000) >> 16;
  1165. ve = (insn & 0x00007f00) >> 8;
  1166. he = (insn & 0x000000fe);
  1167. bfd = (insn & 0x00008000) >> 15;
  1168. /* bit15 can never be masked out*/
  1169. v_mask = vp & (ve | 0x80);
  1170. h_mask = hp & he;
  1171. if (v_mask > 0) {
  1172. doout = 1;
  1173. console_out (_T("vpos "));
  1174. if (ve != 0x7f) {
  1175. console_out_f (_T("& 0x%02x "), ve);
  1176. }
  1177. console_out_f (_T(">= 0x%02x"), v_mask);
  1178. }
  1179. if (he > 0) {
  1180. if (v_mask > 0) {
  1181. console_out (_T(" and"));
  1182. }
  1183. console_out (_T(" hpos "));
  1184. if (he != 0xfe) {
  1185. console_out_f (_T("& 0x%02x "), he);
  1186. }
  1187. console_out_f (_T(">= 0x%02x"), h_mask);
  1188. } else {
  1189. if (doout)
  1190. console_out (_T(", "));
  1191. console_out (_T(", ignore horizontal"));
  1192. }
  1193. console_out_f (_T("\n \t; VP %02x, VE %02x; HP %02x, HE %02x; BFD %d\n"),
  1194. vp, ve, hp, he, bfd);
  1195. }
  1196. #define NR_COPPER_RECORDS 100000
  1197. /* Record copper activity for the debugger. */
  1198. struct cop_rec
  1199. {
  1200. uae_u16 w1, w2;
  1201. int hpos, vpos;
  1202. int bhpos, bvpos;
  1203. uaecptr addr, nextaddr;
  1204. };
  1205. static struct cop_rec *cop_record[2];
  1206. static int nr_cop_records[2], curr_cop_set, selected_cop_set;
  1207. #define NR_DMA_REC_HPOS 256
  1208. #define NR_DMA_REC_VPOS 1000
  1209. static struct dma_rec *dma_record[2];
  1210. static int dma_record_toggle, dma_record_frame[2];
  1211. void record_dma_reset (void)
  1212. {
  1213. int v, h;
  1214. struct dma_rec *dr, *dr2;
  1215. if (!dma_record[0])
  1216. return;
  1217. dma_record_toggle ^= 1;
  1218. dr = dma_record[dma_record_toggle];
  1219. for (v = 0; v < NR_DMA_REC_VPOS; v++) {
  1220. for (h = 0; h < NR_DMA_REC_HPOS; h++) {
  1221. dr2 = &dr[v * NR_DMA_REC_HPOS + h];
  1222. memset (dr2, 0, sizeof (struct dma_rec));
  1223. dr2->reg = 0xffff;
  1224. dr2->cf_reg = 0xffff;
  1225. dr2->addr = 0xffffffff;
  1226. }
  1227. }
  1228. }
  1229. void record_copper_reset (void)
  1230. {
  1231. /* Start a new set of copper records. */
  1232. curr_cop_set ^= 1;
  1233. nr_cop_records[curr_cop_set] = 0;
  1234. }
  1235. STATIC_INLINE uae_u32 ledcolor (uae_u32 c, uae_u32 *rc, uae_u32 *gc, uae_u32 *bc, uae_u32 *a)
  1236. {
  1237. uae_u32 v = rc[(c >> 16) & 0xff] | gc[(c >> 8) & 0xff] | bc[(c >> 0) & 0xff];
  1238. if (a)
  1239. v |= a[255 - ((c >> 24) & 0xff)];
  1240. return v;
  1241. }
  1242. STATIC_INLINE void putpixel (uae_u8 *buf, int bpp, int x, xcolnr c8)
  1243. {
  1244. if (x <= 0)
  1245. return;
  1246. switch (bpp) {
  1247. case 1:
  1248. buf[x] = (uae_u8)c8;
  1249. break;
  1250. case 2:
  1251. {
  1252. uae_u16 *p = (uae_u16*)buf + x;
  1253. *p = (uae_u16)c8;
  1254. break;
  1255. }
  1256. case 3:
  1257. /* no 24 bit yet */
  1258. break;
  1259. case 4:
  1260. {
  1261. uae_u32 *p = (uae_u32*)buf + x;
  1262. *p = c8;
  1263. break;
  1264. }
  1265. }
  1266. }
  1267. #define lc(x) ledcolor (x, xredcolors, xgreencolors, xbluecolors, NULL)
  1268. #define DMARECORD_SUBITEMS 8
  1269. struct dmadebug
  1270. {
  1271. uae_u32 l[DMARECORD_SUBITEMS];
  1272. uae_u8 r, g, b;
  1273. bool enabled;
  1274. int max;
  1275. const TCHAR *name;
  1276. };
  1277. static uae_u32 intlevc[] = { 0x000000, 0x444444, 0x008800, 0xffff00, 0x000088, 0x880000, 0xff0000, 0xffffff };
  1278. static struct dmadebug debug_colors[DMARECORD_MAX];
  1279. static bool debug_colors_set;
  1280. static void set_dbg_color(int index, int extra, uae_u8 r, uae_u8 g, uae_u8 b, int max, const TCHAR *name)
  1281. {
  1282. if (extra == 0) {
  1283. debug_colors[index].r = r;
  1284. debug_colors[index].g = g;
  1285. debug_colors[index].b = b;
  1286. debug_colors[index].enabled = true;
  1287. }
  1288. if (name != NULL)
  1289. debug_colors[index].name = name;
  1290. if (max > 0)
  1291. debug_colors[index].max = max;
  1292. debug_colors[index].l[extra] = lc((r << 16) | (g << 8) | (b << 0));
  1293. }
  1294. static void set_debug_colors(void)
  1295. {
  1296. if (debug_colors_set)
  1297. return;
  1298. debug_colors_set = true;
  1299. set_dbg_color(0, 0, 0x22, 0x22, 0x22, 1, _T("-"));
  1300. set_dbg_color(DMARECORD_REFRESH, 0, 0x44, 0x44, 0x44, 4, _T("Refresh"));
  1301. set_dbg_color(DMARECORD_CPU, 0, 0xa2, 0x53, 0x42, 2, _T("CPU")); // code
  1302. set_dbg_color(DMARECORD_COPPER, 0, 0xee, 0xee, 0x00, 3, _T("Copper"));
  1303. set_dbg_color(DMARECORD_AUDIO, 0, 0xff, 0x00, 0x00, 4, _T("Audio"));
  1304. set_dbg_color(DMARECORD_BLITTER, 0, 0x00, 0x88, 0x88, 2, _T("Blitter"));
  1305. set_dbg_color(DMARECORD_BITPLANE, 0, 0x00, 0x00, 0xff, 8, _T("Bitplane"));
  1306. set_dbg_color(DMARECORD_SPRITE, 0, 0xff, 0x00, 0xff, 8, _T("Sprite"));
  1307. set_dbg_color(DMARECORD_DISK, 0, 0xff, 0xff, 0xff, 3, _T("Disk"));
  1308. for (int i = 0; i < DMARECORD_MAX; i++) {
  1309. for (int j = 1; j < DMARECORD_SUBITEMS; j++) {
  1310. debug_colors[i].l[j] = debug_colors[i].l[0];
  1311. }
  1312. }
  1313. set_dbg_color(DMARECORD_CPU, 1, 0xad, 0x98, 0xd6, 0, NULL); // data
  1314. set_dbg_color(DMARECORD_COPPER, 1, 0xaa, 0xaa, 0x22, 0, NULL); // wait
  1315. set_dbg_color(DMARECORD_COPPER, 2, 0x66, 0x66, 0x44, 0, NULL); // special
  1316. set_dbg_color(DMARECORD_BLITTER, 1, 0x00, 0x88, 0xff, 0, NULL); // fill
  1317. set_dbg_color(DMARECORD_BLITTER, 2, 0x00, 0xff, 0x00, 0, NULL); // line
  1318. }
  1319. static void debug_draw_cycles (uae_u8 *buf, int bpp, int line, int width, int height, uae_u32 *xredcolors, uae_u32 *xgreencolors, uae_u32 *xbluescolors)
  1320. {
  1321. int y, x, xx, dx, xplus, yplus;
  1322. struct dma_rec *dr;
  1323. int t;
  1324. if (debug_dma >= 4)
  1325. yplus = 2;
  1326. else
  1327. yplus = 1;
  1328. if (debug_dma >= 5)
  1329. xplus = 3;
  1330. else if (debug_dma >= 3)
  1331. xplus = 2;
  1332. else
  1333. xplus = 1;
  1334. t = dma_record_toggle ^ 1;
  1335. y = line / yplus;
  1336. if (yplus < 2)
  1337. y -= 8;
  1338. if (y < 0)
  1339. return;
  1340. if (y > maxvpos)
  1341. return;
  1342. if (y >= height)
  1343. return;
  1344. dx = width - xplus * ((maxhpos + 1) & ~1) - 16;
  1345. uae_s8 intlev = 0;
  1346. for (x = 0; x < maxhpos; x++) {
  1347. uae_u32 c = debug_colors[0].l[0];
  1348. xx = x * xplus + dx;
  1349. dr = &dma_record[t][y * NR_DMA_REC_HPOS + x];
  1350. if (dr->reg != 0xffff && debug_colors[dr->type].enabled) {
  1351. c = debug_colors[dr->type].l[dr->extra];
  1352. }
  1353. if (dr->intlev > intlev)
  1354. intlev = dr->intlev;
  1355. putpixel (buf, bpp, xx + 4, c);
  1356. if (xplus)
  1357. putpixel (buf, bpp, xx + 4 + 1, c);
  1358. if (debug_dma >= 6)
  1359. putpixel (buf, bpp, xx + 4 + 2, c);
  1360. }
  1361. putpixel (buf, bpp, dx + 0, 0);
  1362. putpixel (buf, bpp, dx + 1, lc(intlevc[intlev]));
  1363. putpixel (buf, bpp, dx + 2, lc(intlevc[intlev]));
  1364. putpixel (buf, bpp, dx + 3, 0);
  1365. }
  1366. #define HEATMAP_WIDTH 256
  1367. #define HEATMAP_HEIGHT 256
  1368. #define HEATMAP_COUNT 32
  1369. #define HEATMAP_DIV 8
  1370. static const int max_heatmap = 16 * 1048576; // 16M
  1371. static uae_u32 *heatmap_debug_colors;
  1372. static struct memory_heatmap *heatmap;
  1373. struct memory_heatmap
  1374. {
  1375. uae_u32 mask;
  1376. uae_u32 cpucnt;
  1377. uae_u16 cnt;
  1378. uae_u16 type, extra;
  1379. };
  1380. static void debug_draw_heatmap(uae_u8 *buf, int bpp, int line, int width, int height, uae_u32 *xredcolors, uae_u32 *xgreencolors, uae_u32 *xbluescolors)
  1381. {
  1382. struct memory_heatmap *mht = heatmap;
  1383. int dx = 16;
  1384. int y = line;
  1385. if (y < 0 || y >= HEATMAP_HEIGHT)
  1386. return;
  1387. mht += y * HEATMAP_WIDTH;
  1388. for (int x = 0; x < HEATMAP_WIDTH; x++) {
  1389. uae_u32 c = heatmap_debug_colors[mht->cnt * DMARECORD_MAX + mht->type];
  1390. //c = heatmap_debug_colors[(HEATMAP_COUNT - 1) * DMARECORD_MAX + DMARECORD_CPU_I];
  1391. int xx = x + dx;
  1392. putpixel(buf, bpp, xx, c);
  1393. if (mht->cnt > 0)
  1394. mht->cnt--;
  1395. mht++;
  1396. }
  1397. }
  1398. void debug_draw(uae_u8 *buf, int bpp, int line, int width, int height, uae_u32 *xredcolors, uae_u32 *xgreencolors, uae_u32 *xbluescolors)
  1399. {
  1400. if (!heatmap_debug_colors) {
  1401. heatmap_debug_colors = xcalloc(uae_u32, DMARECORD_MAX * HEATMAP_COUNT);
  1402. set_debug_colors();
  1403. for (int i = 0; i < HEATMAP_COUNT; i++) {
  1404. uae_u32 *cp = heatmap_debug_colors + i * DMARECORD_MAX;
  1405. for (int j = 0; j < DMARECORD_MAX; j++) {
  1406. uae_u8 r = debug_colors[j].r;
  1407. uae_u8 g = debug_colors[j].g;
  1408. uae_u8 b = debug_colors[j].b;
  1409. r = r * i / HEATMAP_COUNT;
  1410. g = g * i / HEATMAP_COUNT;
  1411. b = b * i / HEATMAP_COUNT;
  1412. cp[j] = lc((r << 16) | (g << 8) | (b << 0));
  1413. }
  1414. }
  1415. }
  1416. if (heatmap) {
  1417. debug_draw_heatmap(buf, bpp, line, width, height, xredcolors, xgreencolors, xbluecolors);
  1418. } else if (dma_record[0]) {
  1419. debug_draw_cycles(buf, bpp, line, width, height, xredcolors, xgreencolors, xbluecolors);
  1420. }
  1421. }
  1422. struct heatmapstore
  1423. {
  1424. TCHAR *s;
  1425. double v;
  1426. };
  1427. static void heatmap_stats(TCHAR **c)
  1428. {
  1429. int range = 95;
  1430. int maxlines = 30;
  1431. double max;
  1432. int maxcnt;
  1433. uae_u32 mask = MW_MASK_CPU_I;
  1434. const TCHAR *maskname = NULL;
  1435. if (more_params(c)) {
  1436. if (**c == 'c' && peek_next_char(c) == 0) {
  1437. for (int i = 0; i < max_heatmap / HEATMAP_DIV; i++) {
  1438. struct memory_heatmap *hm = &heatmap[i];
  1439. memset(hm, 0, sizeof(struct memory_heatmap));
  1440. }
  1441. console_out(_T("heatmap data cleared\n"));
  1442. return;
  1443. }
  1444. if (!isdigit(peek_next_char(c))) {
  1445. TCHAR str[100];
  1446. if (next_string(c, str, sizeof str / sizeof (TCHAR), true)) {
  1447. for (int j = 0; memwatch_access_masks[j].mask; j++) {
  1448. if (!_tcsicmp(str, memwatch_access_masks[j].name)) {
  1449. mask = memwatch_access_masks[j].mask;
  1450. maskname = memwatch_access_masks[j].name;
  1451. console_out_f(_T("Mask %08x Name %s\n"), mask, maskname);
  1452. break;
  1453. }
  1454. }
  1455. }
  1456. if (more_params(c)) {
  1457. maxlines = readint(c);
  1458. }
  1459. } else {
  1460. range = readint(c);
  1461. if (more_params(c)) {
  1462. maxlines = readint(c);
  1463. }
  1464. }
  1465. }
  1466. if (maxlines <= 0)
  1467. maxlines = 10000;
  1468. if (mask != MW_MASK_CPU_I) {
  1469. int found = -1;
  1470. int firstaddress = 0;
  1471. for (int lines = 0; lines < maxlines; lines++) {
  1472. for (; firstaddress < max_heatmap / HEATMAP_DIV; firstaddress++) {
  1473. struct memory_heatmap *hm = &heatmap[firstaddress];
  1474. if (hm->mask & mask)
  1475. break;
  1476. }
  1477. if (firstaddress == max_heatmap / HEATMAP_DIV)
  1478. return;
  1479. int lastaddress;
  1480. for (lastaddress = firstaddress; lastaddress < max_heatmap / HEATMAP_DIV; lastaddress++) {
  1481. struct memory_heatmap *hm = &heatmap[lastaddress];
  1482. if (!(hm->mask & mask))
  1483. break;
  1484. }
  1485. lastaddress--;
  1486. console_out_f(_T("%03d: %08x - %08x %08x (%d) %s\n"),
  1487. lines,
  1488. firstaddress * HEATMAP_DIV, lastaddress * HEATMAP_DIV + HEATMAP_DIV - 1,
  1489. lastaddress * HEATMAP_DIV - firstaddress * HEATMAP_DIV + HEATMAP_DIV - 1,
  1490. lastaddress * HEATMAP_DIV - firstaddress * HEATMAP_DIV + HEATMAP_DIV - 1,
  1491. maskname);
  1492. firstaddress = lastaddress + 1;
  1493. }
  1494. } else {
  1495. #define MAX_HEATMAP_LINES 1000
  1496. struct heatmapstore linestore[MAX_HEATMAP_LINES] = { 0 };
  1497. int storecnt = 0;
  1498. uae_u32 maxlimit = 0xffffffff;
  1499. max = 0;
  1500. maxcnt = 0;
  1501. for (int i = 0; i < max_heatmap / HEATMAP_DIV; i++) {
  1502. struct memory_heatmap *hm = &heatmap[i];
  1503. if (hm->cpucnt > 0) {
  1504. max += hm->cpucnt;
  1505. maxcnt++;
  1506. }
  1507. }
  1508. if (!maxcnt) {
  1509. console_out(_T("No CPU accesses found\n"));
  1510. return;
  1511. }
  1512. for (int lines = 0; lines < maxlines; lines++) {
  1513. int found = -1;
  1514. int foundcnt = 0;
  1515. for (int i = 0; i < max_heatmap / HEATMAP_DIV; i++) {
  1516. struct memory_heatmap *hm = &heatmap[i];
  1517. if (hm->cpucnt > 0 && hm->cpucnt > foundcnt && hm->cpucnt < maxlimit) {
  1518. foundcnt = hm->cpucnt;
  1519. found = i;
  1520. }
  1521. }
  1522. if (found < 0)
  1523. break;
  1524. int totalcnt = 0;
  1525. int cntrange = foundcnt * range / 100;
  1526. if (cntrange <= 0)
  1527. cntrange = 1;
  1528. int lastaddress;
  1529. for (lastaddress = found; lastaddress < max_heatmap / HEATMAP_DIV; lastaddress++) {
  1530. struct memory_heatmap *hm = &heatmap[lastaddress];
  1531. if (hm->cpucnt == 0 || hm->cpucnt < cntrange || hm->cpucnt >= maxlimit)
  1532. break;
  1533. totalcnt += hm->cpucnt;
  1534. }
  1535. lastaddress--;
  1536. int firstaddress;
  1537. for (firstaddress = found - 1; firstaddress >= 0; firstaddress--) {
  1538. struct memory_heatmap *hm = &heatmap[firstaddress];
  1539. if (hm->cpucnt == 0 || hm->cpucnt < cntrange || hm->cpucnt >= maxlimit)
  1540. break;
  1541. totalcnt += hm->cpucnt;
  1542. }
  1543. firstaddress--;
  1544. firstaddress *= HEATMAP_DIV;
  1545. lastaddress *= HEATMAP_DIV;
  1546. TCHAR tmp[100];
  1547. double pct = totalcnt / max * 100.0;
  1548. _stprintf(tmp, _T("%03d: %08x - %08x %08x (%d) %.5f%%\n"), lines + 1,
  1549. firstaddress, lastaddress + HEATMAP_DIV - 1,
  1550. lastaddress - firstaddress + HEATMAP_DIV - 1,
  1551. lastaddress - firstaddress + HEATMAP_DIV - 1,
  1552. pct);
  1553. linestore[storecnt].s = my_strdup(tmp);
  1554. linestore[storecnt].v = pct;
  1555. storecnt++;
  1556. if (storecnt >= MAX_HEATMAP_LINES)
  1557. break;
  1558. maxlimit = foundcnt;
  1559. }
  1560. for (int lines1 = 0; lines1 < storecnt; lines1++) {
  1561. for (int lines2 = lines1 + 1; lines2 < storecnt; lines2++) {
  1562. if (linestore[lines1].v < linestore[lines2].v) {
  1563. struct heatmapstore hms;
  1564. memcpy(&hms, &linestore[lines1], sizeof(struct heatmapstore));
  1565. memcpy(&linestore[lines1], &linestore[lines2], sizeof(struct heatmapstore));
  1566. memcpy(&linestore[lines2], &hms, sizeof(struct heatmapstore));
  1567. }
  1568. }
  1569. }
  1570. for (int lines1 = 0; lines1 < storecnt; lines1++) {
  1571. console_out(linestore[lines1].s);
  1572. xfree(linestore[lines1].s);
  1573. }
  1574. }
  1575. }
  1576. static void free_heatmap(void)
  1577. {
  1578. xfree(heatmap);
  1579. heatmap = NULL;
  1580. debug_heatmap = 0;
  1581. }
  1582. static void init_heatmap(void)
  1583. {
  1584. if (!heatmap)
  1585. heatmap = xcalloc(struct memory_heatmap, max_heatmap / HEATMAP_DIV);
  1586. }
  1587. static void memwatch_heatmap (uaecptr addr, int rwi, int size, uae_u32 accessmask)
  1588. {
  1589. if (addr >= max_heatmap || !heatmap)
  1590. return;
  1591. struct memory_heatmap *hm = &heatmap[addr / HEATMAP_DIV];
  1592. if (accessmask & MW_MASK_CPU_I) {
  1593. hm->cpucnt++;
  1594. }
  1595. hm->cnt = HEATMAP_COUNT - 1;
  1596. int type = 0;
  1597. int extra = 0;
  1598. for (int i = 0; i < 32; i++) {
  1599. if (accessmask & (1 << i)) {
  1600. switch (1 << i)
  1601. {
  1602. case MW_MASK_BPL_0:
  1603. case MW_MASK_BPL_1:
  1604. case MW_MASK_BPL_2:
  1605. case MW_MASK_BPL_3:
  1606. case MW_MASK_BPL_4:
  1607. case MW_MASK_BPL_5:
  1608. case MW_MASK_BPL_6:
  1609. case MW_MASK_BPL_7:
  1610. type = DMARECORD_BITPLANE;
  1611. break;
  1612. case MW_MASK_AUDIO_0:
  1613. case MW_MASK_AUDIO_1:
  1614. case MW_MASK_AUDIO_2:
  1615. case MW_MASK_AUDIO_3:
  1616. type = DMARECORD_AUDIO;
  1617. break;
  1618. case MW_MASK_BLITTER_A:
  1619. case MW_MASK_BLITTER_B:
  1620. case MW_MASK_BLITTER_C:
  1621. case MW_MASK_BLITTER_D_N:
  1622. case MW_MASK_BLITTER_D_F:
  1623. case MW_MASK_BLITTER_D_L:
  1624. type = DMARECORD_BLITTER;
  1625. break;
  1626. case MW_MASK_COPPER:
  1627. type = DMARECORD_COPPER;
  1628. break;
  1629. case MW_MASK_DISK:
  1630. type = DMARECORD_DISK;
  1631. break;
  1632. case MW_MASK_CPU_I:
  1633. type = DMARECORD_CPU;
  1634. break;
  1635. case MW_MASK_CPU_D_R:
  1636. case MW_MASK_CPU_D_W:
  1637. type = DMARECORD_CPU;
  1638. extra = 1;
  1639. break;
  1640. }
  1641. }
  1642. }
  1643. hm->type = type;
  1644. hm->extra = extra;
  1645. hm->mask |= accessmask;
  1646. }
  1647. void record_dma_event (uae_u32 evt, int hpos, int vpos)
  1648. {
  1649. struct dma_rec *dr;
  1650. if (!dma_record[0])
  1651. return;
  1652. if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
  1653. return;
  1654. dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
  1655. dr->evt |= evt;
  1656. }
  1657. void record_dma_replace(int hpos, int vpos, int type, int extra)
  1658. {
  1659. struct dma_rec *dr;
  1660. if (!dma_record[0])
  1661. return;
  1662. if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
  1663. return;
  1664. dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
  1665. if (dr->reg == 0xffff) {
  1666. write_log(_T("DMA record replace without old data!\n"));
  1667. return;
  1668. }
  1669. if (dr->type != type) {
  1670. write_log(_T("DMA record replace type change %d -> %d!\n"), dr->type, type);
  1671. return;
  1672. }
  1673. dr->extra = extra;
  1674. }
  1675. static void dma_conflict(int vpos, int hpos, struct dma_rec *dr, int reg, bool write)
  1676. {
  1677. write_log(_T("DMA conflict %c: v=%d h=%d OREG=%04X NREG=%04X\n"), write ? 'W' : 'R', vpos, hpos, dr->reg, reg);
  1678. }
  1679. void record_dma_write(uae_u16 reg, uae_u32 dat, uae_u32 addr, int hpos, int vpos, int type, int extra)
  1680. {
  1681. struct dma_rec *dr;
  1682. if (!dma_record[0]) {
  1683. dma_record[0] = xmalloc(struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
  1684. dma_record[1] = xmalloc(struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
  1685. dma_record_toggle = 0;
  1686. record_dma_reset();
  1687. dma_record_frame[0] = -1;
  1688. dma_record_frame[1] = -1;
  1689. }
  1690. if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
  1691. return;
  1692. dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
  1693. dma_record_frame[dma_record_toggle] = timeframes;
  1694. if (dr->reg != 0xffff) {
  1695. dr->cf_reg = reg;
  1696. dr->cf_dat = dat;
  1697. dr->cf_addr = addr;
  1698. dma_conflict(vpos, hpos, dr, reg, false);
  1699. return;
  1700. }
  1701. dr->reg = reg;
  1702. dr->dat = dat;
  1703. dr->addr = addr;
  1704. dr->type = type;
  1705. dr->extra = extra;
  1706. dr->intlev = regs.intmask;
  1707. dr->size = 2;
  1708. last_dma_rec = dr;
  1709. }
  1710. struct dma_rec *last_dma_rec;
  1711. void record_dma_read_value(uae_u32 v)
  1712. {
  1713. if (last_dma_rec) {
  1714. if (last_dma_rec->cf_reg != 0xffff) {
  1715. last_dma_rec->cf_dat = v;
  1716. } else {
  1717. last_dma_rec->dat = v;
  1718. }
  1719. last_dma_rec->size = 2;
  1720. }
  1721. }
  1722. void record_dma_read_value_wide(uae_u64 v, bool quad)
  1723. {
  1724. if (last_dma_rec) {
  1725. if (last_dma_rec->cf_reg != 0xffff) {
  1726. last_dma_rec->cf_dat = v;
  1727. } else {
  1728. last_dma_rec->dat = v;
  1729. }
  1730. last_dma_rec->size = quad ? 8 : 4;
  1731. }
  1732. }
  1733. void record_dma_read(uae_u16 reg, uae_u32 addr, int hpos, int vpos, int type, int extra)
  1734. {
  1735. struct dma_rec *dr;
  1736. if (!dma_record[0]) {
  1737. dma_record[0] = xmalloc (struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
  1738. dma_record[1] = xmalloc (struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
  1739. dma_record_toggle = 0;
  1740. record_dma_reset ();
  1741. dma_record_frame[0] = -1;
  1742. dma_record_frame[1] = -1;
  1743. }
  1744. if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
  1745. return;
  1746. dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
  1747. dma_record_frame[dma_record_toggle] = timeframes;
  1748. if (dr->reg != 0xffff) {
  1749. if (dr->reg != reg) {
  1750. dma_conflict(vpos, hpos, dr, reg, false);
  1751. dr->cf_reg = reg;
  1752. dr->cf_addr = addr;
  1753. }
  1754. return;
  1755. }
  1756. dr->reg = reg;
  1757. dr->dat = 0;
  1758. dr->addr = addr;
  1759. dr->type = type;
  1760. dr->extra = extra;
  1761. dr->intlev = regs.intmask;
  1762. last_dma_rec = dr;
  1763. }
  1764. static bool get_record_dma_info(struct dma_rec *dr, int hpos, int vpos, uae_u32 cycles, TCHAR *l1, TCHAR *l2, TCHAR *l3, TCHAR *l4, TCHAR *l5)
  1765. {
  1766. int longsize = dr->size;
  1767. bool got = false;
  1768. int r = dr->reg;
  1769. int regsize = 3;
  1770. const TCHAR *sr;
  1771. int br = dr->extra & 7;
  1772. int chcnt = -1;
  1773. TCHAR srtext[10];
  1774. bool extra64 = false;
  1775. uae_u32 extraval;
  1776. bool noval = false;
  1777. if (l1)
  1778. l1[0] = 0;
  1779. if (l2)
  1780. l2[0] = 0;
  1781. if (l3)
  1782. l3[0] = 0;
  1783. if (l4)
  1784. l4[0] = 0;
  1785. if (l5)
  1786. l5[0] = 0;
  1787. if (dr->type != 0 || dr->reg != 0xffff || dr->evt)
  1788. got = true;
  1789. sr = _T(" ");
  1790. if (dr->type == DMARECORD_COPPER) {
  1791. if (dr->extra == 3)
  1792. sr = _T("COPW");
  1793. else
  1794. sr = _T("COP ");
  1795. } else if (dr->type == DMARECORD_BLITTER) {
  1796. if (dr->extra & 0x20) {
  1797. if (br == 0)
  1798. sr = _T("BLL-A");
  1799. if (br == 1)
  1800. sr = _T("BLL-B");
  1801. if (br == 2)
  1802. sr = _T("BLL-C");
  1803. if (br == 3)
  1804. sr = _T("BLL-D");
  1805. } else if (dr->extra & 0x10) {
  1806. if (br == 0)
  1807. sr = _T("BLF-A");
  1808. if (br == 1)
  1809. sr = _T("BLF-B");
  1810. if (br == 2)
  1811. sr = _T("BLF-C");
  1812. if (br == 3)
  1813. sr = _T("BLF-D");
  1814. } else {
  1815. if (br == 0)
  1816. sr = _T("BLT-A");
  1817. if (br == 1)
  1818. sr = _T("BLT-B");
  1819. if (br == 2)
  1820. sr = _T("BLT-C");
  1821. if (br == 3)
  1822. sr = _T("BLT-D");
  1823. }
  1824. regsize = 2;
  1825. } else if (dr->type == DMARECORD_REFRESH) {
  1826. sr = _T("RFS");
  1827. chcnt = br;
  1828. noval = true;
  1829. } else if (dr->type == DMARECORD_AUDIO) {
  1830. sr = _T("AUD");
  1831. chcnt = br;
  1832. } else if (dr->type == DMARECORD_DISK) {
  1833. sr = _T("DSK");
  1834. chcnt = br;
  1835. } else if (dr->type == DMARECORD_SPRITE) {
  1836. sr = _T("SPR");
  1837. chcnt = br;
  1838. } else if (dr->type == DMARECORD_BITPLANE) {
  1839. sr = _T("BPL");
  1840. chcnt = br + 1;
  1841. }
  1842. if (dr->cf_reg != 0xffff) {
  1843. _stprintf(srtext, _T("!%03x "), dr->cf_reg);
  1844. chcnt = -1;
  1845. } else {
  1846. _tcscpy(srtext, sr);
  1847. }
  1848. _stprintf (l1, _T("[%02X %3d]"), hpos, hpos);
  1849. if (l4) {
  1850. _tcscpy (l4, _T(" "));
  1851. }
  1852. if (r != 0xffff) {
  1853. if (r & 0x1000) {
  1854. if ((r & 0x0100) == 0x0000)
  1855. _tcscpy (l2, _T("CPU-R "));
  1856. else if ((r & 0x0100) == 0x0100)
  1857. _tcscpy (l2, _T("CPU-W "));
  1858. if ((r & 0xff) == 4) {
  1859. l2[5] = 'L';
  1860. longsize = 4;
  1861. }
  1862. if ((r & 0xff) == 2)
  1863. l2[5] = 'W';
  1864. if ((r & 0xff) == 1)
  1865. l2[5] = 'B';
  1866. } else {
  1867. if (chcnt >= 0) {
  1868. if (regsize == 3)
  1869. _stprintf(l2, _T("%3s%d %03X"), srtext, chcnt, r);
  1870. else
  1871. _stprintf(l2, _T("%4s%d %02X"), srtext, chcnt, r);
  1872. } else {
  1873. if (regsize == 3)
  1874. _stprintf(l2, _T("%4s %03X"), srtext, r);
  1875. else
  1876. _stprintf(l2, _T("%5s %02X"), srtext, r);
  1877. }
  1878. }
  1879. if (l3 && !noval) {
  1880. uae_u64 v = dr->dat;
  1881. if (longsize == 4) {
  1882. _stprintf(l3, _T("%08X"), (uae_u32)v);
  1883. } else if (longsize == 8) {
  1884. _stprintf(l3, _T("%08X"), (uae_u32)(v >> 32));
  1885. extra64 = true;
  1886. extraval = (uae_u32)v;
  1887. } else {
  1888. _stprintf(l3, _T(" %04X"), (uae_u32)(v & 0xffff));
  1889. }
  1890. }
  1891. if (l4 && dr->addr != 0xffffffff)
  1892. _stprintf (l4, _T("%08X"), dr->addr & 0x00ffffff);
  1893. } else {
  1894. _tcscpy (l2, _T(" "));
  1895. if (l3) {
  1896. _tcscpy (l3, _T(" "));
  1897. }
  1898. }
  1899. if (l3) {
  1900. int cl2 = 0;
  1901. if (dr->evt & DMA_EVENT_BLITFINALD)
  1902. l3[cl2++] = 'D';
  1903. if (dr->evt & DMA_EVENT_BLITSTARTFINISH)
  1904. l3[cl2++] = 'B';
  1905. if (dr->evt & DMA_EVENT_CPUBLITTERSTEAL)
  1906. l3[cl2++] = 's';
  1907. if (dr->evt & DMA_EVENT_CPUBLITTERSTOLEN)
  1908. l3[cl2++] = 'S';
  1909. if (dr->evt & DMA_EVENT_BLITIRQ)
  1910. l3[cl2++] = 'b';
  1911. if (dr->evt & DMA_EVENT_BPLFETCHUPDATE)
  1912. l3[cl2++] = 'p';
  1913. if (dr->evt & (DMA_EVENT_COPPERWAKE | DMA_EVENT_COPPERSKIP))
  1914. l3[cl2++] = 'W';
  1915. if (dr->evt & DMA_EVENT_NOONEGETS) {
  1916. l3[cl2++] = '#';
  1917. } else if (dr->evt & DMA_EVENT_COPPERWANTED) {
  1918. l3[cl2++] = 'c';
  1919. }
  1920. if (dr->evt & DMA_EVENT_CPUIRQ)
  1921. l3[cl2++] = 'I';
  1922. if (dr->evt & DMA_EVENT_INTREQ)
  1923. l3[cl2++] = 'i';
  1924. if (dr->evt & DMA_EVENT_SPECIAL)
  1925. l3[cl2++] = 'X';
  1926. if (dr->evt & DMA_EVENT_DDFSTRT)
  1927. l3[cl2++] = '0';
  1928. if (dr->evt & DMA_EVENT_DDFSTOP)
  1929. l3[cl2++] = '1';
  1930. if (dr->evt & DMA_EVENT_DDFSTOP2)
  1931. l3[cl2++] = '2';
  1932. if (dr->evt & DMA_EVENT_HDIWS) {
  1933. l3[cl2++] = '(';
  1934. }
  1935. if (dr->evt & DMA_EVENT_HDIWE) {
  1936. l3[cl2++] = ')';
  1937. }
  1938. if (dr->evt & DMA_EVENT_HBS) {
  1939. l3[cl2++] = '[';
  1940. }
  1941. if (dr->evt & DMA_EVENT_HBE) {
  1942. l3[cl2++] = ']';
  1943. }
  1944. if (dr->evt & DMA_EVENT_HSS) {
  1945. l3[cl2++] = '{';
  1946. }
  1947. if (dr->evt & DMA_EVENT_HSE) {
  1948. l3[cl2++] = '}';
  1949. }
  1950. if (dr->evt & (DMA_EVENT_VB | DMA_EVENT_VS | DMA_EVENT_LOL | DMA_EVENT_LOF | DMA_EVENT_VDIW)) {
  1951. l3[cl2++] = '*';
  1952. }
  1953. if (dr->evt & DMA_EVENT_VS) {
  1954. l3[cl2++] = 'S';
  1955. }
  1956. if (dr->evt & DMA_EVENT_VB) {
  1957. l3[cl2++] = 'B';
  1958. }
  1959. if (dr->evt & DMA_EVENT_LOL) {
  1960. l3[cl2++] = 'L';
  1961. }
  1962. if (dr->evt & DMA_EVENT_LOF) {
  1963. l3[cl2++] = 'F';
  1964. }
  1965. if (dr->evt & DMA_EVENT_VDIW) {
  1966. l3[cl2++] = '=';
  1967. }
  1968. if (dr->evt & (DMA_EVENT_VB | DMA_EVENT_VS | DMA_EVENT_LOL | DMA_EVENT_LOF | DMA_EVENT_VDIW)) {
  1969. l3[cl2++] = 0;
  1970. }
  1971. }
  1972. if (l5) {
  1973. _stprintf (l5, _T("%08X"), cycles + (vpos * maxhpos + hpos) * CYCLE_UNIT);
  1974. }
  1975. if (extra64) {
  1976. _tcscpy(l5, l4);
  1977. _stprintf(l4, _T("%08X"), extraval);
  1978. }
  1979. return got;
  1980. }
  1981. static void decode_dma_record (int hpos, int vpos, int toggle, bool logfile)
  1982. {
  1983. struct dma_rec *dr, *dr_start;
  1984. int h, i, maxh;
  1985. uae_u32 cycles;
  1986. if (!dma_record[0] || hpos < 0 || vpos < 0)
  1987. return;
  1988. dr_start = dr = &dma_record[dma_record_toggle ^ toggle][vpos * NR_DMA_REC_HPOS];
  1989. if (logfile)
  1990. write_dlog (_T("Line: %02X %3d HPOS %02X %3d:\n"), vpos, vpos, hpos, hpos);
  1991. else
  1992. console_out_f (_T("Line: %02X %3d HPOS %02X %3d:\n"), vpos, vpos, hpos, hpos);
  1993. h = hpos;
  1994. dr += hpos;
  1995. maxh = hpos + (logfile ? maxhpos_short : 80);
  1996. if (maxh > maxhpos_short)
  1997. maxh = maxhpos_short;
  1998. cycles = vsync_cycles;
  1999. if (toggle)
  2000. cycles -= maxvpos * maxhpos_short * CYCLE_UNIT;
  2001. while (h < maxh) {
  2002. int cols = (logfile ? 16 : 8);
  2003. TCHAR l1[200];
  2004. TCHAR l2[200];
  2005. TCHAR l3[200];
  2006. TCHAR l4[200];
  2007. TCHAR l5[200];
  2008. l1[0] = 0;
  2009. l2[0] = 0;
  2010. l3[0] = 0;
  2011. l4[0] = 0;
  2012. l5[0] = 0;
  2013. for (i = 0; i < cols && h < maxh; i++, h++, dr++) {
  2014. TCHAR l1l[16], l2l[16], l3l[16], l4l[16], l5l[16];
  2015. get_record_dma_info(dr, h, vpos, cycles, l1l, l2l, l3l, l4l, l5l);
  2016. if (dr_start[3 + 2].evt & DMA_EVENT_LOL) {
  2017. if (maxh == maxhpos_short) {
  2018. maxh++;
  2019. }
  2020. }
  2021. TCHAR *p = l1 + _tcslen(l1);
  2022. _stprintf(p, _T("%9s "), l1l);
  2023. p = l2 + _tcslen(l2);
  2024. _stprintf(p, _T("%9s "), l2l);
  2025. p = l3 + _tcslen(l3);
  2026. _stprintf(p, _T("%9s "), l3l);
  2027. p = l4 + _tcslen(l4);
  2028. _stprintf(p, _T("%9s "), l4l);
  2029. p = l5 + _tcslen(l5);
  2030. _stprintf(p, _T("%9s "), l5l);
  2031. }
  2032. if (logfile) {
  2033. write_dlog (_T("%s\n"), l1);
  2034. write_dlog (_T("%s\n"), l2);
  2035. write_dlog (_T("%s\n"), l3);
  2036. write_dlog (_T("%s\n"), l4);
  2037. write_dlog (_T("%s\n"), l5);
  2038. write_dlog (_T("\n"));
  2039. } else {
  2040. console_out_f (_T("%s\n"), l1);
  2041. console_out_f (_T("%s\n"), l2);
  2042. console_out_f (_T("%s\n"), l3);
  2043. console_out_f (_T("%s\n"), l4);
  2044. console_out_f (_T("%s\n"), l5);
  2045. console_out_f (_T("\n"));
  2046. }
  2047. }
  2048. if (logfile)
  2049. flush_log();
  2050. }
  2051. void log_dma_record (void)
  2052. {
  2053. if (!input_record && !input_play)
  2054. return;
  2055. if (!debug_dma)
  2056. debug_dma = 1;
  2057. decode_dma_record (0, 0, 0, true);
  2058. }
  2059. static void init_record_copper(void)
  2060. {
  2061. if (!cop_record[0]) {
  2062. cop_record[0] = xmalloc(struct cop_rec, NR_COPPER_RECORDS);
  2063. cop_record[1] = xmalloc(struct cop_rec, NR_COPPER_RECORDS);
  2064. }
  2065. }
  2066. void record_copper_blitwait (uaecptr addr, int hpos, int vpos)
  2067. {
  2068. int t = nr_cop_records[curr_cop_set];
  2069. init_record_copper();
  2070. cop_record[curr_cop_set][t].bhpos = hpos;
  2071. cop_record[curr_cop_set][t].bvpos = vpos;
  2072. }
  2073. void record_copper (uaecptr addr, uaecptr nextaddr, uae_u16 word1, uae_u16 word2, int hpos, int vpos)
  2074. {
  2075. int t = nr_cop_records[curr_cop_set];
  2076. init_record_copper();
  2077. if (t < NR_COPPER_RECORDS) {
  2078. cop_record[curr_cop_set][t].addr = addr;
  2079. cop_record[curr_cop_set][t].nextaddr = nextaddr;
  2080. cop_record[curr_cop_set][t].w1 = word1;
  2081. cop_record[curr_cop_set][t].w2 = word2;
  2082. cop_record[curr_cop_set][t].hpos = hpos;
  2083. cop_record[curr_cop_set][t].vpos = vpos;
  2084. cop_record[curr_cop_set][t].bvpos = -1;
  2085. nr_cop_records[curr_cop_set] = t + 1;
  2086. }
  2087. if (debug_copper & 2) { /* trace */
  2088. debug_copper &= ~2;
  2089. activate_debugger_new();
  2090. }
  2091. if ((debug_copper & 4) && addr >= debug_copper_pc && addr <= debug_copper_pc + 3) {
  2092. debug_copper &= ~4;
  2093. activate_debugger_new();
  2094. }
  2095. }
  2096. static struct cop_rec *find_copper_records(uaecptr addr)
  2097. {
  2098. int s = selected_cop_set;
  2099. int t = nr_cop_records[s];
  2100. int i;
  2101. for (i = 0; i < t; i++) {
  2102. if (cop_record[s][i].addr == addr)
  2103. return &cop_record[s][i];
  2104. }
  2105. return 0;
  2106. }
  2107. /* simple decode copper by Mark Cox */
  2108. static uaecptr decode_copper_insn(FILE *file, uae_u16 mword1, uae_u16 mword2, uaecptr addr)
  2109. {
  2110. struct cop_rec *cr = NULL;
  2111. uae_u32 insn_type, insn;
  2112. TCHAR here = ' ';
  2113. TCHAR record[] = _T(" ");
  2114. if ((cr = find_copper_records(addr))) {
  2115. _stprintf(record, _T(" [%03x %03x]"), cr->vpos, cr->hpos);
  2116. insn = (cr->w1 << 16) | cr->w2;
  2117. } else {
  2118. insn = (mword1 << 16) | mword2;
  2119. }
  2120. insn_type = insn & 0x00010001;
  2121. if (get_copper_address(-1) >= addr && get_copper_address(-1) <= addr + 3)
  2122. here = '*';
  2123. console_out_f (_T("%c%08x: %04x %04x%s\t;%c "), here, addr, insn >> 16, insn & 0xFFFF, record, insn != ((mword1 << 16) | mword2) ? '!' : ' ');
  2124. switch (insn_type) {
  2125. case 0x00010000: /* WAIT insn */
  2126. console_out(_T("Wait for "));
  2127. disassemble_wait(file, insn);
  2128. if (insn == 0xfffffffe)
  2129. console_out(_T(" \t; End of Copperlist\n"));
  2130. break;
  2131. case 0x00010001: /* SKIP insn */
  2132. console_out(_T("Skip if "));
  2133. disassemble_wait(file, insn);
  2134. break;
  2135. case 0x00000000:
  2136. case 0x00000001: /* MOVE insn */
  2137. {
  2138. int addr = (insn >> 16) & 0x1fe;
  2139. int i = 0;
  2140. while (custd[i].name) {
  2141. if (custd[i].adr == addr + 0xdff000)
  2142. break;
  2143. i++;
  2144. }
  2145. if (custd[i].name)
  2146. console_out_f(_T("%s := 0x%04x\n"), custd[i].name, insn & 0xffff);
  2147. else
  2148. console_out_f(_T("%04x := 0x%04x\n"), addr, insn & 0xffff);
  2149. }
  2150. break;
  2151. default:
  2152. abort ();
  2153. }
  2154. if (cr && cr->bvpos >= 0) {
  2155. console_out_f(_T(" BLT [%03x %03x]\n"), cr->bvpos, cr->bhpos);
  2156. }
  2157. if (cr && cr->nextaddr != 0xffffffff && cr->nextaddr != addr + 4) {
  2158. console_out_f(_T(" %08x: Copper jump\n"), cr->nextaddr);
  2159. return cr->nextaddr;
  2160. }
  2161. return addr + 4;
  2162. }
  2163. static uaecptr decode_copperlist(FILE *file, uaecptr address, int nolines)
  2164. {
  2165. uaecptr next;
  2166. while (nolines-- > 0) {
  2167. next = decode_copper_insn(file, chipmem_wget_indirect(address), chipmem_wget_indirect(address + 2), address);
  2168. address = next;
  2169. }
  2170. return address;
  2171. /* You may wonder why I don't stop this at the end of the copperlist?
  2172. * Well, often nice things are hidden at the end and it is debatable the actual
  2173. * values that mean the end of the copperlist */
  2174. }
  2175. static int copper_debugger (TCHAR **c)
  2176. {
  2177. static uaecptr nxcopper;
  2178. uae_u32 maddr;
  2179. int lines;
  2180. if (**c == 'd') {
  2181. next_char (c);
  2182. if (debug_copper)
  2183. debug_copper = 0;
  2184. else
  2185. debug_copper = 1;
  2186. console_out_f (_T("Copper debugger %s.\n"), debug_copper ? _T("enabled") : _T("disabled"));
  2187. } else if (**c == 't') {
  2188. debug_copper = 1|2;
  2189. return 1;
  2190. } else if (**c == 'b') {
  2191. (*c)++;
  2192. debug_copper = 1|4;
  2193. if (more_params (c)) {
  2194. debug_copper_pc = readhex (c);
  2195. console_out_f (_T("Copper breakpoint @0x%08x\n"), debug_copper_pc);
  2196. } else {
  2197. debug_copper &= ~4;
  2198. }
  2199. } else {
  2200. if (more_params(c)) {
  2201. maddr = readhex(c);
  2202. if (maddr == 1 || maddr == 2 || maddr == 3)
  2203. maddr = get_copper_address(maddr);
  2204. else if (maddr == 0)
  2205. maddr = get_copper_address(-1);
  2206. } else {
  2207. maddr = nxcopper;
  2208. }
  2209. selected_cop_set = curr_cop_set;
  2210. if (!find_copper_records(maddr)) {
  2211. selected_cop_set = curr_cop_set ^ 1;
  2212. }
  2213. if (more_params (c))
  2214. lines = readhex (c);
  2215. else
  2216. lines = 20;
  2217. nxcopper = decode_copperlist (stdout, maddr, lines);
  2218. }
  2219. return 0;
  2220. }
  2221. #define MAX_CHEAT_VIEW 100
  2222. struct trainerstruct {
  2223. uaecptr addr;
  2224. int size;
  2225. };
  2226. static struct trainerstruct *trainerdata;
  2227. static int totaltrainers;
  2228. static void clearcheater(void)
  2229. {
  2230. if (!trainerdata)
  2231. trainerdata = xmalloc(struct trainerstruct, MAX_CHEAT_VIEW);
  2232. memset(trainerdata, 0, sizeof (struct trainerstruct) * MAX_CHEAT_VIEW);
  2233. totaltrainers = 0;
  2234. }
  2235. static int addcheater(uaecptr addr, int size)
  2236. {
  2237. if (totaltrainers >= MAX_CHEAT_VIEW)
  2238. return 0;
  2239. trainerdata[totaltrainers].addr = addr;
  2240. trainerdata[totaltrainers].size = size;
  2241. totaltrainers++;
  2242. return 1;
  2243. }
  2244. static void listcheater(int mode, int size)
  2245. {
  2246. int i, skip;
  2247. if (!trainerdata)
  2248. return;
  2249. if (mode)
  2250. skip = 6;
  2251. else
  2252. skip = 8;
  2253. for(i = 0; i < totaltrainers; i++) {
  2254. struct trainerstruct *ts = &trainerdata[i];
  2255. uae_u16 b;
  2256. if (size) {
  2257. b = get_byte_debug (ts->addr);
  2258. } else {
  2259. b = get_word_debug (ts->addr);
  2260. }
  2261. if (mode)
  2262. console_out_f (_T("%08X=%04X "), ts->addr, b);
  2263. else
  2264. console_out_f (_T("%08X "), ts->addr);
  2265. if ((i % skip) == skip)
  2266. console_out (_T("\n"));
  2267. }
  2268. }
  2269. static void deepcheatsearch (TCHAR **c)
  2270. {
  2271. static int first = 1;
  2272. static uae_u8 *memtmp;
  2273. static int memsize, memsize2;
  2274. uae_u8 *p1, *p2;
  2275. uaecptr addr, end;
  2276. int i, wasmodified, nonmodified;
  2277. static int size;
  2278. static int inconly, deconly, maxdiff;
  2279. int addrcnt, cnt;
  2280. TCHAR v;
  2281. v = _totupper (**c);
  2282. if(!memtmp || v == 'S') {
  2283. maxdiff = 0x10000;
  2284. inconly = 0;
  2285. deconly = 0;
  2286. size = 1;
  2287. }
  2288. if (**c)
  2289. (*c)++;
  2290. ignore_ws (c);
  2291. if ((**c) == '1' || (**c) == '2') {
  2292. size = **c - '0';
  2293. (*c)++;
  2294. }
  2295. if (more_params (c))
  2296. maxdiff = readint (c);
  2297. if (!memtmp || v == 'S') {
  2298. first = 1;
  2299. xfree (memtmp);
  2300. memsize = 0;
  2301. addr = 0xffffffff;
  2302. while ((addr = nextaddr (addr, 0, &end, false)) != 0xffffffff) {
  2303. memsize += end - addr;
  2304. addr = end - 1;
  2305. }
  2306. memsize2 = (memsize + 7) / 8;
  2307. memtmp = xmalloc (uae_u8, memsize + memsize2);
  2308. if (!memtmp)
  2309. return;
  2310. memset (memtmp + memsize, 0xff, memsize2);
  2311. p1 = memtmp;
  2312. addr = 0xffffffff;
  2313. while ((addr = nextaddr (addr, 0, &end, true)) != 0xffffffff) {
  2314. for (i = addr; i < end; i++)
  2315. *p1++ = get_byte_debug (i);
  2316. addr = end - 1;
  2317. }
  2318. console_out (_T("Deep trainer first pass complete.\n"));
  2319. return;
  2320. }
  2321. inconly = deconly = 0;
  2322. wasmodified = v == 'X' ? 0 : 1;
  2323. nonmodified = v == 'Z' ? 1 : 0;
  2324. if (v == 'I')
  2325. inconly = 1;
  2326. if (v == 'D')
  2327. deconly = 1;
  2328. p1 = memtmp;
  2329. p2 = memtmp + memsize;
  2330. addrcnt = 0;
  2331. cnt = 0;
  2332. addr = 0xffffffff;
  2333. while ((addr = nextaddr (addr, 0, NULL, true)) != 0xffffffff) {
  2334. uae_s32 b, b2;
  2335. int doremove = 0;
  2336. int addroff = addrcnt >> 3;
  2337. int addrmask ;
  2338. if (size == 1) {
  2339. b = (uae_s8)get_byte_debug (addr);
  2340. b2 = (uae_s8)p1[addrcnt];
  2341. addrmask = 1 << (addrcnt & 7);
  2342. } else {
  2343. b = (uae_s16)get_word_debug (addr);
  2344. b2 = (uae_s16)((p1[addrcnt] << 8) | p1[addrcnt + 1]);
  2345. addrmask = 3 << (addrcnt & 7);
  2346. }
  2347. if (p2[addroff] & addrmask) {
  2348. if (wasmodified && !nonmodified) {
  2349. int diff = b - b2;
  2350. if (b == b2)
  2351. doremove = 1;
  2352. if (abs(diff) > maxdiff)
  2353. doremove = 1;
  2354. if (inconly && diff < 0)
  2355. doremove = 1;
  2356. if (deconly && diff > 0)
  2357. doremove = 1;
  2358. } else if (nonmodified && b == b2) {
  2359. doremove = 1;
  2360. } else if (!wasmodified && b != b2) {
  2361. doremove = 1;
  2362. }
  2363. if (doremove)
  2364. p2[addroff] &= ~addrmask;
  2365. else
  2366. cnt++;
  2367. }
  2368. if (size == 1) {
  2369. p1[addrcnt] = b;
  2370. addrcnt++;
  2371. } else {
  2372. p1[addrcnt] = b >> 8;
  2373. p1[addrcnt + 1] = b >> 0;
  2374. addr = nextaddr (addr, 0, NULL, true);
  2375. if (addr == 0xffffffff)
  2376. break;
  2377. addrcnt += 2;
  2378. }
  2379. if (iscancel (65536)) {
  2380. console_out_f (_T("Aborted at %08X\n"), addr);
  2381. break;
  2382. }
  2383. }
  2384. console_out_f (_T("%d addresses found\n"), cnt);
  2385. if (cnt <= MAX_CHEAT_VIEW) {
  2386. clearcheater ();
  2387. cnt = 0;
  2388. addrcnt = 0;
  2389. addr = 0xffffffff;
  2390. while ((addr = nextaddr(addr, 0, NULL, true)) != 0xffffffff) {
  2391. int addroff = addrcnt >> 3;
  2392. int addrmask = (size == 1 ? 1 : 3) << (addrcnt & 7);
  2393. if (p2[addroff] & addrmask)
  2394. addcheater (addr, size);
  2395. addrcnt += size;
  2396. cnt++;
  2397. }
  2398. if (cnt > 0)
  2399. console_out (_T("\n"));
  2400. listcheater (1, size);
  2401. } else {
  2402. console_out (_T("Now continue with 'g' and use 'D' again after you have lost another life\n"));
  2403. }
  2404. }
  2405. /* cheat-search by Toni Wilen (originally by Holger Jakob) */
  2406. static void cheatsearch (TCHAR **c)
  2407. {
  2408. static uae_u8 *vlist;
  2409. static int listsize;
  2410. static int first = 1;
  2411. static int size = 1;
  2412. uae_u32 val, memcnt, prevmemcnt;
  2413. int i, count, vcnt, memsize;
  2414. uaecptr addr, end;
  2415. memsize = 0;
  2416. addr = 0xffffffff;
  2417. while ((addr = nextaddr (addr, 0, &end, false)) != 0xffffffff) {
  2418. memsize += end - addr;
  2419. addr = end - 1;
  2420. }
  2421. if (_totupper (**c) == 'L') {
  2422. listcheater (1, size);
  2423. return;
  2424. }
  2425. ignore_ws (c);
  2426. if (!more_params (c)) {
  2427. first = 1;
  2428. console_out (_T("Search reset\n"));
  2429. xfree (vlist);
  2430. listsize = memsize;
  2431. vlist = xcalloc (uae_u8, listsize >> 3);
  2432. return;
  2433. }
  2434. if (first)
  2435. val = readint (c, &size);
  2436. else
  2437. val = readint (c);
  2438. if (vlist == NULL) {
  2439. listsize = memsize;
  2440. vlist = xcalloc (uae_u8, listsize >> 3);
  2441. }
  2442. count = 0;
  2443. vcnt = 0;
  2444. clearcheater ();
  2445. addr = 0xffffffff;
  2446. prevmemcnt = memcnt = 0;
  2447. while ((addr = nextaddr (addr, 0, &end, true)) != 0xffffffff) {
  2448. if (addr + size < end) {
  2449. for (i = 0; i < size; i++) {
  2450. int shift = (size - i - 1) * 8;
  2451. if (get_byte_debug (addr + i) != ((val >> shift) & 0xff))
  2452. break;
  2453. }
  2454. if (i == size) {
  2455. int voffset = memcnt >> 3;
  2456. int vmask = 1 << (memcnt & 7);
  2457. if (!first) {
  2458. while (prevmemcnt < memcnt) {
  2459. vlist[prevmemcnt >> 3] &= ~(1 << (prevmemcnt & 7));
  2460. prevmemcnt++;
  2461. }
  2462. if (vlist[voffset] & vmask) {
  2463. count++;
  2464. addcheater(addr, size);
  2465. } else {
  2466. vlist[voffset] &= ~vmask;
  2467. }
  2468. prevmemcnt = memcnt + 1;
  2469. } else {
  2470. vlist[voffset] |= vmask;
  2471. count++;
  2472. }
  2473. }
  2474. }
  2475. memcnt++;
  2476. if (iscancel (65536)) {
  2477. console_out_f (_T("Aborted at %08X\n"), addr);
  2478. break;
  2479. }
  2480. }
  2481. if (!first) {
  2482. while (prevmemcnt < memcnt) {
  2483. vlist[prevmemcnt >> 3] &= ~(1 << (prevmemcnt & 7));
  2484. prevmemcnt++;
  2485. }
  2486. listcheater (0, size);
  2487. }
  2488. console_out_f (_T("Found %d possible addresses with 0x%X (%u) (%d bytes)\n"), count, val, val, size);
  2489. if (count > 0)
  2490. console_out (_T("Now continue with 'g' and use 'C' with a different value\n"));
  2491. first = 0;
  2492. }
  2493. struct breakpoint_node bpnodes[BREAKPOINT_TOTAL];
  2494. static addrbank **debug_mem_banks;
  2495. static addrbank *debug_mem_area;
  2496. struct memwatch_node mwnodes[MEMWATCH_TOTAL];
  2497. static int mwnodes_start, mwnodes_end;
  2498. static struct memwatch_node mwhit;
  2499. #define MUNGWALL_SLOTS 16
  2500. struct mungwall_data
  2501. {
  2502. int slots;
  2503. uae_u32 start[MUNGWALL_SLOTS], end[MUNGWALL_SLOTS];
  2504. };
  2505. static struct mungwall_data **mungwall;
  2506. static uae_u8 *illgdebug, *illghdebug;
  2507. static int illgdebug_break;
  2508. static void illg_free (void)
  2509. {
  2510. xfree (illgdebug);
  2511. illgdebug = NULL;
  2512. xfree (illghdebug);
  2513. illghdebug = NULL;
  2514. }
  2515. static void illg_init (void)
  2516. {
  2517. int i;
  2518. uae_u8 c = 3;
  2519. uaecptr addr, end;
  2520. illgdebug = xcalloc (uae_u8, 0x01000000);
  2521. illghdebug = xcalloc (uae_u8, 65536);
  2522. if (!illgdebug || !illghdebug) {
  2523. illg_free();
  2524. return;
  2525. }
  2526. addr = 0xffffffff;
  2527. while ((addr = nextaddr (addr, 0, &end, false)) != 0xffffffff) {
  2528. if (end < 0x01000000) {
  2529. memset (illgdebug + addr, c, end - addr);
  2530. } else {
  2531. uae_u32 s = addr >> 16;
  2532. uae_u32 e = end >> 16;
  2533. memset (illghdebug + s, c, e - s);
  2534. }
  2535. addr = end - 1;
  2536. }
  2537. for (int i = 0; i < MAX_RTG_BOARDS; i++) {
  2538. if (currprefs.rtgboards[i].rtgmem_size)
  2539. memset (illghdebug + (gfxmem_banks[i]->start >> 16), 3, currprefs.rtgboards[i].rtgmem_size >> 16);
  2540. }
  2541. i = 0;
  2542. while (custd[i].name) {
  2543. int rw = (custd[i].special & CD_WO) ? 2 : 1;
  2544. illgdebug[custd[i].adr] = rw;
  2545. illgdebug[custd[i].adr + 1] = rw;
  2546. i++;
  2547. }
  2548. for (i = 0; i < 16; i++) { /* CIAs */
  2549. if (i == 11)
  2550. continue;
  2551. illgdebug[0xbfe001 + i * 0x100] = c;
  2552. illgdebug[0xbfd000 + i * 0x100] = c;
  2553. }
  2554. memset (illgdebug + 0xf80000, 1, 512 * 1024); /* KS ROM */
  2555. memset (illgdebug + 0xdc0000, c, 0x3f); /* clock */
  2556. #ifdef CDTV
  2557. if (currprefs.cs_cdtvram) {
  2558. memset (illgdebug + 0xdc8000, c, 4096); /* CDTV batt RAM */
  2559. memset (illgdebug + 0xf00000, 1, 256 * 1024); /* CDTV ext ROM */
  2560. }
  2561. #endif
  2562. #ifdef CD32
  2563. if (currprefs.cs_cd32cd) {
  2564. memset (illgdebug + AKIKO_BASE, c, AKIKO_BASE_END - AKIKO_BASE);
  2565. memset (illgdebug + 0xe00000, 1, 512 * 1024); /* CD32 ext ROM */
  2566. }
  2567. #endif
  2568. if (currprefs.cs_ksmirror_e0)
  2569. memset (illgdebug + 0xe00000, 1, 512 * 1024);
  2570. if (currprefs.cs_ksmirror_a8)
  2571. memset (illgdebug + 0xa80000, 1, 2 * 512 * 1024);
  2572. #ifdef FILESYS
  2573. if (uae_boot_rom_type) /* filesys "rom" */
  2574. memset (illgdebug + rtarea_base, 1, 0x10000);
  2575. #endif
  2576. if (currprefs.cs_ide > 0)
  2577. memset (illgdebug + 0xdd0000, 3, 65536);
  2578. }
  2579. /* add special custom register check here */
  2580. static void illg_debug_check (uaecptr addr, int rwi, int size, uae_u32 val)
  2581. {
  2582. return;
  2583. }
  2584. static void illg_debug_do (uaecptr addr, int rwi, int size, uae_u32 val)
  2585. {
  2586. uae_u8 mask;
  2587. uae_u32 pc = m68k_getpc ();
  2588. int i;
  2589. for (i = size - 1; i >= 0; i--) {
  2590. uae_u8 v = val >> (i * 8);
  2591. uae_u32 ad = addr + i;
  2592. if (ad >= 0x01000000)
  2593. mask = illghdebug[ad >> 16];
  2594. else
  2595. mask = illgdebug[ad];
  2596. if ((mask & 3) == 3)
  2597. return;
  2598. if (mask & 0x80) {
  2599. illg_debug_check (ad, rwi, size, val);
  2600. } else if ((mask & 3) == 0) {
  2601. if (rwi & 2)
  2602. console_out_f (_T("W: %08X=%02X PC=%08X\n"), ad, v, pc);
  2603. else if (rwi & 1)
  2604. console_out_f (_T("R: %08X PC=%08X\n"), ad, pc);
  2605. if (illgdebug_break)
  2606. activate_debugger_new();
  2607. } else if (!(mask & 1) && (rwi & 1)) {
  2608. console_out_f (_T("RO: %08X=%02X PC=%08X\n"), ad, v, pc);
  2609. if (illgdebug_break)
  2610. activate_debugger_new();
  2611. } else if (!(mask & 2) && (rwi & 2)) {
  2612. console_out_f (_T("WO: %08X PC=%08X\n"), ad, pc);
  2613. if (illgdebug_break)
  2614. activate_debugger_new();
  2615. }
  2616. }
  2617. }
  2618. static int debug_mem_off (uaecptr *addrp)
  2619. {
  2620. uaecptr addr = *addrp;
  2621. addrbank *ba;
  2622. int offset = munge24 (addr) >> 16;
  2623. if (!debug_mem_banks)
  2624. return offset;
  2625. ba = debug_mem_banks[offset];
  2626. if (!ba)
  2627. return offset;
  2628. if (ba->mask || ba->startmask) {
  2629. uae_u32 start = ba->startmask ? ba->startmask : ba->start;
  2630. addr -= start;
  2631. addr &= ba->mask;
  2632. addr += start;
  2633. }
  2634. *addrp = addr;
  2635. return offset;
  2636. }
  2637. struct smc_item {
  2638. uae_u32 addr;
  2639. uae_u8 cnt;
  2640. };
  2641. static int smc_size, smc_mode;
  2642. static struct smc_item *smc_table;
  2643. static void smc_free (void)
  2644. {
  2645. if (smc_table)
  2646. console_out (_T("SMCD disabled\n"));
  2647. xfree(smc_table);
  2648. smc_mode = 0;
  2649. smc_table = NULL;
  2650. }
  2651. static void initialize_memwatch (int mode);
  2652. static void smc_detect_init (TCHAR **c)
  2653. {
  2654. int v, i;
  2655. ignore_ws (c);
  2656. v = readint (c);
  2657. smc_free ();
  2658. smc_size = 1 << 24;
  2659. if (currprefs.z3fastmem[0].size)
  2660. smc_size = currprefs.z3autoconfig_start + currprefs.z3fastmem[0].size;
  2661. smc_size += 4;
  2662. smc_table = xmalloc (struct smc_item, smc_size);
  2663. if (!smc_table)
  2664. return;
  2665. for (i = 0; i < smc_size; i++) {
  2666. smc_table[i].addr = 0xffffffff;
  2667. smc_table[i].cnt = 0;
  2668. }
  2669. if (!memwatch_enabled)
  2670. initialize_memwatch (0);
  2671. if (v)
  2672. smc_mode = 1;
  2673. console_out_f (_T("SMCD enabled. Break=%d\n"), smc_mode);
  2674. }
  2675. #define SMC_MAXHITS 8
  2676. static void smc_detector (uaecptr addr, int rwi, int size, uae_u32 *valp)
  2677. {
  2678. int i, hitcnt;
  2679. uaecptr hitaddr, hitpc;
  2680. if (!smc_table)
  2681. return;
  2682. if (addr >= smc_size)
  2683. return;
  2684. if (rwi == 2) {
  2685. for (i = 0; i < size; i++) {
  2686. if (smc_table[addr + i].cnt < SMC_MAXHITS) {
  2687. smc_table[addr + i].addr = m68k_getpc ();
  2688. }
  2689. }
  2690. return;
  2691. }
  2692. hitpc = smc_table[addr].addr;
  2693. if (hitpc == 0xffffffff)
  2694. return;
  2695. hitaddr = addr;
  2696. hitcnt = 0;
  2697. while (addr < smc_size && smc_table[addr].addr != 0xffffffff) {
  2698. smc_table[addr++].addr = 0xffffffff;
  2699. hitcnt++;
  2700. }
  2701. if ((hitpc & 0xFFF80000) == 0xF80000)
  2702. return;
  2703. if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible) {
  2704. /* ignore single-word unconditional jump instructions
  2705. * (instruction prefetch from PC+2 can cause false positives) */
  2706. if (regs.irc == 0x4e75 || regs.irc == 4e74 || regs.irc == 0x4e72 || regs.irc == 0x4e77)
  2707. return; /* RTS, RTD, RTE, RTR */
  2708. if ((regs.irc & 0xff00) == 0x6000 && (regs.irc & 0x00ff) != 0 && (regs.irc & 0x00ff) != 0xff)
  2709. return; /* BRA.B */
  2710. }
  2711. if (hitcnt < 100) {
  2712. smc_table[hitaddr].cnt++;
  2713. console_out_f (_T("SMC at %08X - %08X (%d) from %08X\n"),
  2714. hitaddr, hitaddr + hitcnt, hitcnt, hitpc);
  2715. if (smc_mode)
  2716. activate_debugger_new();
  2717. if (smc_table[hitaddr].cnt >= SMC_MAXHITS)
  2718. console_out_f (_T("* hit count >= %d, future hits ignored\n"), SMC_MAXHITS);
  2719. }
  2720. }
  2721. uae_u8 *save_debug_memwatch (int *len, uae_u8 *dstptr)
  2722. {
  2723. uae_u8 *dstbak, *dst;
  2724. int total;
  2725. total = 0;
  2726. for (int i = 0; i < MEMWATCH_TOTAL; i++) {
  2727. if (mwnodes[i].size > 0)
  2728. total++;
  2729. }
  2730. if (!total)
  2731. return NULL;
  2732. if (dstptr)
  2733. dstbak = dst = dstptr;
  2734. else
  2735. dstbak = dst = xmalloc (uae_u8, 1000);
  2736. save_u32 (1);
  2737. save_u8 (total);
  2738. for (int i = 0; i < MEMWATCH_TOTAL; i++) {
  2739. struct memwatch_node *m = &mwnodes[i];
  2740. if (m->size <= 0)
  2741. continue;
  2742. save_store_pos ();
  2743. save_u8 (i);
  2744. save_u8 (m->modval_written);
  2745. save_u8 (m->mustchange);
  2746. save_u8 (m->frozen);
  2747. save_u8 (m->val_enabled);
  2748. save_u8 (m->rwi);
  2749. save_u32 (m->addr);
  2750. save_u32 (m->size);
  2751. save_u32 (m->modval);
  2752. save_u32 (m->val_mask);
  2753. save_u32 (m->val_size);
  2754. save_u32 (m->val);
  2755. save_u32 (m->pc);
  2756. save_u32 (m->access_mask);
  2757. save_u32 (m->reg);
  2758. save_u8(m->nobreak);
  2759. save_u8(m->reportonly);
  2760. save_store_size ();
  2761. }
  2762. *len = dst - dstbak;
  2763. return dstbak;
  2764. }
  2765. uae_u8 *restore_debug_memwatch (uae_u8 *src)
  2766. {
  2767. if (restore_u32 () != 1)
  2768. return src;
  2769. int total = restore_u8 ();
  2770. for (int i = 0; i < total; i++) {
  2771. restore_store_pos ();
  2772. int idx = restore_u8 ();
  2773. struct memwatch_node *m = &mwnodes[idx];
  2774. m->modval_written = restore_u8 ();
  2775. m->mustchange = restore_u8 ();
  2776. m->frozen = restore_u8 ();
  2777. m->val_enabled = restore_u8 ();
  2778. m->rwi = restore_u8 ();
  2779. m->addr = restore_u32 ();
  2780. m->size = restore_u32 ();
  2781. m->modval = restore_u32 ();
  2782. m->val_mask = restore_u32 ();
  2783. m->val_size = restore_u32 ();
  2784. m->val = restore_u32 ();
  2785. m->pc = restore_u32 ();
  2786. m->access_mask = restore_u32();
  2787. m->reg = restore_u32();
  2788. m->nobreak = restore_u8();
  2789. m->reportonly = restore_u8();
  2790. restore_store_size ();
  2791. }
  2792. return src;
  2793. }
  2794. void restore_debug_memwatch_finish (void)
  2795. {
  2796. for (int i = 0; i < MEMWATCH_TOTAL; i++) {
  2797. struct memwatch_node *m = &mwnodes[i];
  2798. if (m->size) {
  2799. if (!memwatch_enabled)
  2800. initialize_memwatch (0);
  2801. return;
  2802. }
  2803. }
  2804. }
  2805. void debug_check_reg(uae_u32 addr, int write, uae_u16 v)
  2806. {
  2807. if (!memwatch_access_validator)
  2808. return;
  2809. int reg = addr & 0x1ff;
  2810. const struct customData *cd = &custd[reg >> 1];
  2811. if (((addr & 0xfe00) != 0xf000 && (addr & 0xffff0000) != 0) || ((addr & 0xffff0000) != 0 && (addr & 0xffff0000) != 0x00df0000) || (addr & 0x0600)) {
  2812. write_log(_T("Mirror custom register %08x (%s) %s access. PC=%08x\n"), addr, cd->name, write ? _T("write") : _T("read"), M68K_GETPC);
  2813. }
  2814. int spc = cd->special;
  2815. if ((spc & CD_AGA) && !(currprefs.chipset_mask & CSMASK_AGA))
  2816. spc |= CD_NONE;
  2817. if ((spc & CD_ECS_DENISE) && !(currprefs.chipset_mask & CSMASK_ECS_DENISE))
  2818. spc |= CD_NONE;
  2819. if ((spc & CD_ECS_AGNUS) && !(currprefs.chipset_mask & CSMASK_ECS_AGNUS))
  2820. spc |= CD_NONE;
  2821. if (spc & CD_NONE) {
  2822. write_log(_T("Non-existing custom register %04x (%s) %s access. PC=%08x\n"), reg, cd->name, write ? _T("write") : _T("read"), M68K_GETPC);
  2823. return;
  2824. }
  2825. if (spc & CD_COLOR) {
  2826. if (currprefs.chipset_mask & CSMASK_AGA)
  2827. return;
  2828. }
  2829. if (write & !(spc & CD_WO)) {
  2830. write_log(_T("Write access to read-only custom register %04x (%s). PC=%08x\n"), reg, cd->name, M68K_GETPC);
  2831. return;
  2832. } else if (!write && (spc & CD_WO)) {
  2833. write_log(_T("Read access from write-only custom register %04x (%s). PC=%08x\n"), reg, cd->name, M68K_GETPC);
  2834. return;
  2835. }
  2836. if (write && cd->mask[2]) {
  2837. int idx = (currprefs.chipset_mask & CSMASK_AGA) ? 2 : (currprefs.chipset_mask & CSMASK_ECS_AGNUS) ? 1 : 0;
  2838. uae_u16 mask = cd->mask[idx];
  2839. if (v & ~mask) {
  2840. write_log(_T("Unuset bits set %04x when writing custom register %04x (%s) PC=%08x\n"), v & ~mask, reg, cd->name, M68K_GETPC);
  2841. }
  2842. }
  2843. if (spc & CD_DMA_PTR) {
  2844. uae_u32 addr = (custom_storage[((reg & ~2) >> 1)].value << 16) | custom_storage[((reg | 2) >> 1)].value;
  2845. if (currprefs.z3chipmem.size) {
  2846. if (addr >= currprefs.z3chipmem.start_address && addr < currprefs.z3chipmem.start_address + currprefs.z3chipmem.size)
  2847. return;
  2848. }
  2849. if(addr >= currprefs.chipmem.size)
  2850. write_log(_T("DMA pointer %04x (%s) set to invalid value %08x %s=%08x\n"), reg, cd->name, addr,
  2851. custom_storage[reg >> 1].pc & 1 ? _T("COP") : _T("PC"), custom_storage[reg >> 1].pc);
  2852. }
  2853. }
  2854. void debug_invalid_reg(int reg, int size, uae_u16 v)
  2855. {
  2856. if (!memwatch_access_validator)
  2857. return;
  2858. reg &= 0x1ff;
  2859. if (size == 1) {
  2860. if (reg == 2) // DMACONR low byte
  2861. return;
  2862. if (reg == 6) // VPOS
  2863. return;
  2864. }
  2865. const struct customData *cd = &custd[reg >> 1];
  2866. if (size == -2 && (reg & 1)) {
  2867. write_log(_T("Unaligned word write to register %04x (%s) val %04x PC=%08x\n"), reg, cd->name, v, M68K_GETPC);
  2868. } else if (size == -1) {
  2869. write_log(_T("Byte write to register %04x (%s) val %02x PC=%08x\n"), reg, cd->name, v & 0xff, M68K_GETPC);
  2870. } else if (size == 2 && (reg & 1)) {
  2871. write_log(_T("Unaligned word read from register %04x (%s) PC=%08x\n"), reg, cd->name, M68K_GETPC);
  2872. } else if (size == 1) {
  2873. write_log(_T("Byte read from register %04x (%s) PC=%08x\n"), reg, cd->name, M68K_GETPC);
  2874. }
  2875. }
  2876. static void is_valid_dma(int reg, int ptrreg, uaecptr addr)
  2877. {
  2878. if (!memwatch_access_validator)
  2879. return;
  2880. if (reg == 0x1fe) // refresh
  2881. return;
  2882. if (currprefs.z3chipmem.size) {
  2883. if (addr >= currprefs.z3chipmem.start_address && addr < currprefs.z3chipmem.start_address + currprefs.z3chipmem.size)
  2884. return;
  2885. }
  2886. if (!(addr & ~(currprefs.chipmem.size - 1)))
  2887. return;
  2888. const struct customData *cdreg = &custd[reg >> 1];
  2889. const struct customData *cdptr = &custd[ptrreg >> 1];
  2890. write_log(_T("DMA DAT %04x (%s), PT %04x (%s) accessed invalid memory %08x. Init: %08x, PC/COP=%08x\n"),
  2891. reg, cdreg->name, ptrreg, cdptr->name, addr,
  2892. (custom_storage[ptrreg >> 1].value << 16) | (custom_storage[(ptrreg >> 1) + 1].value),
  2893. custom_storage[ptrreg >> 1].pc);
  2894. }
  2895. static void mungwall_memwatch(uaecptr addr, int rwi, int size, uae_u32 valp)
  2896. {
  2897. struct mungwall_data *mwd = mungwall[addr >> 16];
  2898. if (!mwd)
  2899. return;
  2900. for (int i = 0; i < mwd->slots; i++) {
  2901. if (!mwd->end[i])
  2902. continue;
  2903. if (addr + size > mwd->start[i] && addr < mwd->end[i]) {
  2904. }
  2905. }
  2906. }
  2907. static void memwatch_hit_msg(int mw)
  2908. {
  2909. console_out_f(_T("Memwatch %d: break at %08X.%c %c%c%c %08X PC=%08X "), mw, mwhit.addr,
  2910. mwhit.size == 1 ? 'B' : (mwhit.size == 2 ? 'W' : 'L'),
  2911. (mwhit.rwi & 1) ? 'R' : ' ', (mwhit.rwi & 2) ? 'W' : ' ', (mwhit.rwi & 4) ? 'I' : ' ',
  2912. mwhit.val, mwhit.pc);
  2913. for (int i = 0; memwatch_access_masks[i].mask; i++) {
  2914. if (mwhit.access_mask == memwatch_access_masks[i].mask)
  2915. console_out_f(_T("%s (%03x)\n"), memwatch_access_masks[i].name, mwhit.reg);
  2916. }
  2917. if (mwhit.access_mask & (MW_MASK_BLITTER_A | MW_MASK_BLITTER_B | MW_MASK_BLITTER_C | MW_MASK_BLITTER_D_N | MW_MASK_BLITTER_D_L | MW_MASK_BLITTER_D_F)) {
  2918. blitter_debugdump();
  2919. }
  2920. }
  2921. static int memwatch_func (uaecptr addr, int rwi, int size, uae_u32 *valp, uae_u32 accessmask, uae_u32 reg)
  2922. {
  2923. uae_u32 val = *valp;
  2924. if (inside_debugger)
  2925. return 1;
  2926. if (mungwall)
  2927. mungwall_memwatch(addr, rwi, size, val);
  2928. if (illgdebug)
  2929. illg_debug_do (addr, rwi, size, val);
  2930. if (heatmap)
  2931. memwatch_heatmap (addr, rwi, size, accessmask);
  2932. addr = munge24 (addr);
  2933. if (smc_table && (rwi >= 2))
  2934. smc_detector (addr, rwi, size, valp);
  2935. for (int i = mwnodes_start; i <= mwnodes_end; i++) {
  2936. struct memwatch_node *m = &mwnodes[i];
  2937. uaecptr addr2 = m->addr;
  2938. uaecptr addr3 = addr2 + m->size;
  2939. int rwi2 = m->rwi;
  2940. uae_u32 oldval = 0;
  2941. int isoldval = 0;
  2942. int brk = 0;
  2943. if (m->size == 0)
  2944. continue;
  2945. if (!(rwi & rwi2))
  2946. continue;
  2947. if (!(m->access_mask & accessmask))
  2948. continue;
  2949. if (addr >= addr2 && addr < addr3)
  2950. brk = 1;
  2951. if (!brk && size == 2 && (addr + 1 >= addr2 && addr + 1 < addr3))
  2952. brk = 1;
  2953. if (!brk && size == 4 && ((addr + 2 >= addr2 && addr + 2 < addr3) || (addr + 3 >= addr2 && addr + 3 < addr3)))
  2954. brk = 1;
  2955. if (!brk)
  2956. continue;
  2957. if (m->bus_error) {
  2958. if (((m->bus_error & 1) && (rwi & 1)) || ((m->bus_error & 4) && (rwi & 4)) || ((m->bus_error & 2) && (rwi & 2))) {
  2959. hardware_exception2(addr, val, (rwi & 2) != 0, (rwi & 4) != 0, size == 4 ? sz_long : (size == 2 ? sz_word : sz_byte));
  2960. }
  2961. continue;
  2962. }
  2963. if (mem_banks[addr >> 16]->check (addr, size)) {
  2964. uae_u8 *p = mem_banks[addr >> 16]->xlateaddr (addr);
  2965. if (size == 1)
  2966. oldval = p[0];
  2967. else if (size == 2)
  2968. oldval = (p[0] << 8) | p[1];
  2969. else
  2970. oldval = (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3] << 0);
  2971. isoldval = 1;
  2972. }
  2973. if (m->pc != 0xffffffff) {
  2974. if (m->pc != regs.instruction_pc)
  2975. continue;
  2976. }
  2977. if (!m->frozen && m->val_enabled) {
  2978. int trigger = 0;
  2979. uae_u32 mask = m->size == 4 ? 0xffffffff : (1 << (m->size * 8)) - 1;
  2980. uae_u32 mval = m->val;
  2981. int scnt = size;
  2982. for (;;) {
  2983. if (((mval & mask) & m->val_mask) == ((val & mask) & m->val_mask))
  2984. trigger = 1;
  2985. if (mask & 0x80000000)
  2986. break;
  2987. if (m->size == 1) {
  2988. mask <<= 8;
  2989. mval <<= 8;
  2990. scnt--;
  2991. } else if (m->size == 2) {
  2992. mask <<= 16;
  2993. scnt -= 2;
  2994. mval <<= 16;
  2995. } else {
  2996. scnt -= 4;
  2997. }
  2998. if (scnt <= 0)
  2999. break;
  3000. }
  3001. if (!trigger)
  3002. continue;
  3003. }
  3004. if (m->mustchange && rwi == 2 && isoldval) {
  3005. if (oldval == *valp)
  3006. continue;
  3007. }
  3008. if (m->modval_written) {
  3009. if (!rwi) {
  3010. brk = 0;
  3011. } else if (m->modval_written == 1) {
  3012. m->modval_written = 2;
  3013. m->modval = val;
  3014. brk = 0;
  3015. } else if (m->modval == val) {
  3016. brk = 0;
  3017. }
  3018. }
  3019. if (m->frozen) {
  3020. if (m->val_enabled) {
  3021. int shift = (addr + size - 1) - (m->addr + m->val_size - 1);
  3022. uae_u32 sval;
  3023. uae_u32 mask;
  3024. if (m->val_size == 4)
  3025. mask = 0xffffffff;
  3026. else if (m->val_size == 2)
  3027. mask = 0x0000ffff;
  3028. else
  3029. mask = 0x000000ff;
  3030. sval = m->val;
  3031. if (shift < 0) {
  3032. shift = -8 * shift;
  3033. sval >>= shift;
  3034. mask >>= shift;
  3035. } else {
  3036. shift = 8 * shift;
  3037. sval <<= shift;
  3038. mask <<= shift;
  3039. }
  3040. *valp = (sval & mask) | ((*valp) & ~mask);
  3041. //write_log (_T("%08x %08x %08x %08x %d\n"), addr, m->addr, *valp, mask, shift);
  3042. return 1;
  3043. }
  3044. return 0;
  3045. }
  3046. // if (!notinrom ())
  3047. // return 1;
  3048. mwhit.addr = addr;
  3049. mwhit.rwi = rwi;
  3050. mwhit.size = size;
  3051. mwhit.val = 0;
  3052. mwhit.access_mask = accessmask;
  3053. mwhit.reg = reg;
  3054. if (mwhit.rwi & 2)
  3055. mwhit.val = val;
  3056. mwhit.pc = M68K_GETPC;
  3057. memwatch_triggered = i + 1;
  3058. if (m->reportonly) {
  3059. memwatch_hit_msg(memwatch_triggered - 1);
  3060. }
  3061. if (!m->nobreak && !m->reportonly) {
  3062. debugging = 1;
  3063. debug_pc = M68K_GETPC;
  3064. debug_cycles();
  3065. set_special(SPCFLAG_BRK);
  3066. }
  3067. return 1;
  3068. }
  3069. return 1;
  3070. }
  3071. static int mmu_hit (uaecptr addr, int size, int rwi, uae_u32 *v);
  3072. static uae_u32 REGPARAM2 mmu_lget (uaecptr addr)
  3073. {
  3074. int off = debug_mem_off (&addr);
  3075. uae_u32 v = 0;
  3076. if (!mmu_hit (addr, 4, 0, &v))
  3077. v = debug_mem_banks[off]->lget (addr);
  3078. return v;
  3079. }
  3080. static uae_u32 REGPARAM2 mmu_wget (uaecptr addr)
  3081. {
  3082. int off = debug_mem_off (&addr);
  3083. uae_u32 v = 0;
  3084. if (!mmu_hit (addr, 2, 0, &v))
  3085. v = debug_mem_banks[off]->wget (addr);
  3086. return v;
  3087. }
  3088. static uae_u32 REGPARAM2 mmu_bget (uaecptr addr)
  3089. {
  3090. int off = debug_mem_off (&addr);
  3091. uae_u32 v = 0;
  3092. if (!mmu_hit(addr, 1, 0, &v))
  3093. v = debug_mem_banks[off]->bget (addr);
  3094. return v;
  3095. }
  3096. static void REGPARAM2 mmu_lput (uaecptr addr, uae_u32 v)
  3097. {
  3098. int off = debug_mem_off (&addr);
  3099. if (!mmu_hit (addr, 4, 1, &v))
  3100. debug_mem_banks[off]->lput (addr, v);
  3101. }
  3102. static void REGPARAM2 mmu_wput (uaecptr addr, uae_u32 v)
  3103. {
  3104. int off = debug_mem_off (&addr);
  3105. if (!mmu_hit (addr, 2, 1, &v))
  3106. debug_mem_banks[off]->wput (addr, v);
  3107. }
  3108. static void REGPARAM2 mmu_bput (uaecptr addr, uae_u32 v)
  3109. {
  3110. int off = debug_mem_off (&addr);
  3111. if (!mmu_hit (addr, 1, 1, &v))
  3112. debug_mem_banks[off]->bput (addr, v);
  3113. }
  3114. static uae_u32 REGPARAM2 mmu_lgeti (uaecptr addr)
  3115. {
  3116. int off = debug_mem_off (&addr);
  3117. uae_u32 v = 0;
  3118. if (!mmu_hit (addr, 4, 4, &v))
  3119. v = debug_mem_banks[off]->lgeti (addr);
  3120. return v;
  3121. }
  3122. static uae_u32 REGPARAM2 mmu_wgeti (uaecptr addr)
  3123. {
  3124. int off = debug_mem_off (&addr);
  3125. uae_u32 v = 0;
  3126. if (!mmu_hit (addr, 2, 4, &v))
  3127. v = debug_mem_banks[off]->wgeti (addr);
  3128. return v;
  3129. }
  3130. static uae_u32 REGPARAM2 debug_lget(uaecptr addr)
  3131. {
  3132. uae_u32 off = debug_mem_off(&addr);
  3133. uae_u32 v;
  3134. v = debug_mem_banks[off]->lget(addr);
  3135. memwatch_func(addr, 1, 4, &v, MW_MASK_CPU_D_R, 0);
  3136. return v;
  3137. }
  3138. static uae_u32 REGPARAM2 debug_wget (uaecptr addr)
  3139. {
  3140. int off = debug_mem_off (&addr);
  3141. uae_u32 v;
  3142. v = debug_mem_banks[off]->wget (addr);
  3143. memwatch_func (addr, 1, 2, &v, MW_MASK_CPU_D_R, 0);
  3144. return v;
  3145. }
  3146. static uae_u32 REGPARAM2 debug_bget (uaecptr addr)
  3147. {
  3148. int off = debug_mem_off (&addr);
  3149. uae_u32 v;
  3150. v = debug_mem_banks[off]->bget (addr);
  3151. memwatch_func (addr, 1, 1, &v, MW_MASK_CPU_D_R, 0);
  3152. return v;
  3153. }
  3154. static uae_u32 REGPARAM2 debug_lgeti (uaecptr addr)
  3155. {
  3156. int off = debug_mem_off (&addr);
  3157. uae_u32 v;
  3158. v = debug_mem_banks[off]->lgeti (addr);
  3159. memwatch_func (addr, 4, 4, &v, MW_MASK_CPU_I, 0);
  3160. return v;
  3161. }
  3162. static uae_u32 REGPARAM2 debug_wgeti (uaecptr addr)
  3163. {
  3164. int off = debug_mem_off (&addr);
  3165. uae_u32 v;
  3166. v = debug_mem_banks[off]->wgeti (addr);
  3167. memwatch_func (addr, 4, 2, &v, MW_MASK_CPU_I, 0);
  3168. return v;
  3169. }
  3170. static void REGPARAM2 debug_lput (uaecptr addr, uae_u32 v)
  3171. {
  3172. int off = debug_mem_off (&addr);
  3173. if (memwatch_func (addr, 2, 4, &v, MW_MASK_CPU_D_W, 0))
  3174. debug_mem_banks[off]->lput (addr, v);
  3175. }
  3176. static void REGPARAM2 debug_wput (uaecptr addr, uae_u32 v)
  3177. {
  3178. int off = debug_mem_off (&addr);
  3179. if (memwatch_func (addr, 2, 2, &v, MW_MASK_CPU_D_W, 0))
  3180. debug_mem_banks[off]->wput (addr, v);
  3181. }
  3182. static void REGPARAM2 debug_bput (uaecptr addr, uae_u32 v)
  3183. {
  3184. int off = debug_mem_off (&addr);
  3185. if (memwatch_func (addr, 2, 1, &v, MW_MASK_CPU_D_W, 0))
  3186. debug_mem_banks[off]->bput (addr, v);
  3187. }
  3188. static int REGPARAM2 debug_check (uaecptr addr, uae_u32 size)
  3189. {
  3190. return debug_mem_banks[munge24 (addr) >> 16]->check (addr, size);
  3191. }
  3192. static uae_u8 *REGPARAM2 debug_xlate (uaecptr addr)
  3193. {
  3194. return debug_mem_banks[munge24 (addr) >> 16]->xlateaddr (addr);
  3195. }
  3196. struct peekdma peekdma_data;
  3197. static void peekdma_save(int type, uaecptr addr, uae_u32 mask, int reg, int ptrreg)
  3198. {
  3199. peekdma_data.type = type;
  3200. peekdma_data.addr = addr;
  3201. peekdma_data.mask = mask;
  3202. peekdma_data.reg = reg;
  3203. peekdma_data.ptrreg = ptrreg;
  3204. }
  3205. void debug_getpeekdma_value(uae_u32 v)
  3206. {
  3207. uae_u32 vv = v;
  3208. if (!memwatch_enabled) {
  3209. return;
  3210. }
  3211. is_valid_dma(peekdma_data.reg, peekdma_data.ptrreg, peekdma_data.addr);
  3212. if (debug_mem_banks[peekdma_data.addr >> 16] == NULL) {
  3213. return;
  3214. }
  3215. if (!currprefs.z3chipmem.size) {
  3216. peekdma_data.addr &= chipmem_bank.mask;
  3217. }
  3218. memwatch_func(peekdma_data.addr, 1, 2, &vv, peekdma_data.mask, peekdma_data.reg);
  3219. }
  3220. void debug_getpeekdma_value_long(uae_u32 v, int offset)
  3221. {
  3222. uae_u32 vv = v;
  3223. uae_u32 mask = 0xffffffff;
  3224. if (!memwatch_enabled) {
  3225. return;
  3226. }
  3227. is_valid_dma(peekdma_data.reg, peekdma_data.ptrreg, peekdma_data.addr + offset);
  3228. if (debug_mem_banks[(peekdma_data.addr + offset) >> 16] == NULL) {
  3229. return;
  3230. }
  3231. if (!currprefs.z3chipmem.size) {
  3232. mask = chipmem_bank.mask;
  3233. }
  3234. memwatch_func((peekdma_data.addr + offset) & mask, 1, 4, &vv, peekdma_data.mask, peekdma_data.reg);
  3235. }
  3236. uae_u32 debug_putpeekdma_chipset(uaecptr addr, uae_u32 v, uae_u32 mask, int reg)
  3237. {
  3238. peekdma_save(0, addr, mask, reg, 0);
  3239. if (!memwatch_enabled)
  3240. return v;
  3241. peekdma_data.addr &= 0x1fe;
  3242. peekdma_data.addr += 0xdff000;
  3243. memwatch_func(peekdma_data.addr, 2, 2, &v, peekdma_data.mask, peekdma_data.reg);
  3244. return v;
  3245. }
  3246. uae_u32 debug_putpeekdma_chipram(uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg)
  3247. {
  3248. peekdma_save(1, addr, mask, reg, ptrreg);
  3249. if (!memwatch_enabled)
  3250. return v;
  3251. is_valid_dma(peekdma_data.reg, peekdma_data.ptrreg, peekdma_data.addr);
  3252. if (debug_mem_banks[peekdma_data.addr >> 16] == NULL)
  3253. return v;
  3254. if (!currprefs.z3chipmem.size)
  3255. peekdma_data.addr &= chipmem_bank.mask;
  3256. memwatch_func(peekdma_data.addr & chipmem_bank.mask, 2, 2, &v, peekdma_data.mask, peekdma_data.reg);
  3257. return v;
  3258. }
  3259. void debug_getpeekdma_chipram(uaecptr addr, uae_u32 mask, int reg, int ptrreg)
  3260. {
  3261. peekdma_save(2, addr, mask, reg, ptrreg);
  3262. }
  3263. static void debug_putlpeek (uaecptr addr, uae_u32 v)
  3264. {
  3265. if (!memwatch_enabled)
  3266. return;
  3267. memwatch_func (addr, 2, 4, &v, MW_MASK_CPU_D_W, 0);
  3268. }
  3269. void debug_wputpeek (uaecptr addr, uae_u32 v)
  3270. {
  3271. if (!memwatch_enabled)
  3272. return;
  3273. memwatch_func (addr, 2, 2, &v, MW_MASK_CPU_D_W, 0);
  3274. }
  3275. void debug_bputpeek (uaecptr addr, uae_u32 v)
  3276. {
  3277. if (!memwatch_enabled)
  3278. return;
  3279. memwatch_func (addr, 2, 1, &v, MW_MASK_CPU_D_W, 0);
  3280. }
  3281. void debug_bgetpeek (uaecptr addr, uae_u32 v)
  3282. {
  3283. uae_u32 vv = v;
  3284. if (!memwatch_enabled)
  3285. return;
  3286. memwatch_func (addr, 1, 1, &vv, MW_MASK_CPU_D_R, 0);
  3287. }
  3288. void debug_wgetpeek (uaecptr addr, uae_u32 v)
  3289. {
  3290. uae_u32 vv = v;
  3291. if (!memwatch_enabled)
  3292. return;
  3293. memwatch_func (addr, 1, 2, &vv, MW_MASK_CPU_D_R, 0);
  3294. }
  3295. void debug_lgetpeek (uaecptr addr, uae_u32 v)
  3296. {
  3297. uae_u32 vv = v;
  3298. if (!memwatch_enabled)
  3299. return;
  3300. memwatch_func (addr, 1, 4, &vv, MW_MASK_CPU_D_R, 0);
  3301. }
  3302. struct membank_store
  3303. {
  3304. addrbank *addr;
  3305. addrbank newbank;
  3306. int banknr;
  3307. };
  3308. static struct membank_store *membank_stores;
  3309. static int membank_total;
  3310. #define MEMWATCH_STORE_SLOTS 32
  3311. static void memwatch_reset (void)
  3312. {
  3313. for (int i = 0; i < membank_total; i++) {
  3314. addrbank *ab = debug_mem_banks[i];
  3315. if (!ab)
  3316. continue;
  3317. map_banks_quick (ab, i, 1, 1);
  3318. }
  3319. for (int i = 0; membank_stores[i].addr; i++) {
  3320. struct membank_store *ms = &membank_stores[i];
  3321. /* name was allocated in memwatch_remap */
  3322. xfree ((char*)ms->newbank.name);
  3323. memset (ms, 0, sizeof (struct membank_store));
  3324. ms->addr = NULL;
  3325. }
  3326. memset (debug_mem_banks, 0, membank_total * sizeof (addrbank*));
  3327. }
  3328. static void memwatch_remap (uaecptr addr)
  3329. {
  3330. int mode = 0;
  3331. int i;
  3332. int banknr;
  3333. struct membank_store *ms;
  3334. addrbank *bank;
  3335. addrbank *newbank = NULL;
  3336. addr &= ~65535;
  3337. banknr = addr >> 16;
  3338. if (debug_mem_banks[banknr])
  3339. return;
  3340. bank = mem_banks[banknr];
  3341. for (i = 0 ; i < MEMWATCH_STORE_SLOTS; i++) {
  3342. ms = &membank_stores[i];
  3343. if (ms->addr == NULL)
  3344. break;
  3345. if (ms->addr == bank) {
  3346. newbank = &ms->newbank;
  3347. break;
  3348. }
  3349. }
  3350. if (i >= MEMWATCH_STORE_SLOTS)
  3351. return;
  3352. if (!newbank) {
  3353. TCHAR tmp[200];
  3354. _stprintf (tmp, _T("%s [D]"), bank->name);
  3355. ms->addr = bank;
  3356. ms->banknr = banknr;
  3357. newbank = &ms->newbank;
  3358. memcpy (newbank, bank, sizeof(addrbank));
  3359. newbank->bget = mode ? mmu_bget : debug_bget;
  3360. newbank->wget = mode ? mmu_wget : debug_wget;
  3361. newbank->lget = mode ? mmu_lget : debug_lget;
  3362. newbank->bput = mode ? mmu_bput : debug_bput;
  3363. newbank->wput = mode ? mmu_wput : debug_wput;
  3364. newbank->lput = mode ? mmu_lput : debug_lput;
  3365. newbank->check = debug_check;
  3366. newbank->xlateaddr = debug_xlate;
  3367. newbank->wgeti = mode ? mmu_wgeti : debug_wgeti;
  3368. newbank->lgeti = mode ? mmu_lgeti : debug_lgeti;
  3369. /* name will be freed by memwatch_reset */
  3370. newbank->name = my_strdup (tmp);
  3371. if (!newbank->mask)
  3372. newbank->mask = -1;
  3373. newbank->baseaddr_direct_r = 0;
  3374. newbank->baseaddr_direct_w = 0;
  3375. }
  3376. debug_mem_banks[banknr] = bank;
  3377. map_banks_quick (newbank, banknr, 1, 1);
  3378. // map aliases
  3379. for (i = 0; i < membank_total; i++) {
  3380. uaecptr addr2 = i << 16;
  3381. addrbank *ab = &get_mem_bank(addr2);
  3382. if (ab != ms->addr)
  3383. continue;
  3384. if ((addr2 & ab->mask) == (addr & bank->mask)) {
  3385. debug_mem_banks[i] = ms->addr;
  3386. map_banks_quick (newbank, i, 1, 1);
  3387. }
  3388. }
  3389. }
  3390. static void memwatch_setup (void)
  3391. {
  3392. memwatch_reset ();
  3393. mwnodes_start = MEMWATCH_TOTAL - 1;
  3394. mwnodes_end = 0;
  3395. for (int i = 0; i < MEMWATCH_TOTAL; i++) {
  3396. struct memwatch_node *m = &mwnodes[i];
  3397. uae_u32 size = 0;
  3398. if (!m->size)
  3399. continue;
  3400. if (mwnodes_start > i)
  3401. mwnodes_start = i;
  3402. if (mwnodes_end < i)
  3403. mwnodes_end = i;
  3404. while (size < m->size) {
  3405. memwatch_remap (m->addr + size);
  3406. size += 65536;
  3407. }
  3408. }
  3409. }
  3410. static int deinitialize_memwatch (void)
  3411. {
  3412. int oldmode;
  3413. if (!memwatch_enabled && !mmu_enabled)
  3414. return -1;
  3415. memwatch_reset ();
  3416. oldmode = mmu_enabled ? 1 : 0;
  3417. xfree (debug_mem_banks);
  3418. debug_mem_banks = NULL;
  3419. xfree (debug_mem_area);
  3420. debug_mem_area = NULL;
  3421. xfree (membank_stores);
  3422. membank_stores = NULL;
  3423. memwatch_enabled = 0;
  3424. mmu_enabled = 0;
  3425. xfree (illgdebug);
  3426. illgdebug = 0;
  3427. return oldmode;
  3428. }
  3429. static void initialize_memwatch (int mode)
  3430. {
  3431. membank_total = currprefs.address_space_24 ? 256 : 65536;
  3432. deinitialize_memwatch ();
  3433. debug_mem_banks = xcalloc (addrbank*, 65536);
  3434. if (!debug_mem_banks)
  3435. return;
  3436. if (membank_total < 65536) {
  3437. for (int i = 256; i < 65536; i++) {
  3438. debug_mem_banks[i] = &dummy_bank;
  3439. }
  3440. }
  3441. debug_mem_area = xcalloc (addrbank, membank_total);
  3442. membank_stores = xcalloc (struct membank_store, MEMWATCH_STORE_SLOTS);
  3443. for (int i = 0; i < MEMWATCH_TOTAL; i++) {
  3444. struct memwatch_node *m = &mwnodes[i];
  3445. m->pc = 0xffffffff;
  3446. }
  3447. #if 0
  3448. int i, j, as;
  3449. addrbank *a1, *a2, *oa;
  3450. oa = NULL;
  3451. for (i = 0; i < as; i++) {
  3452. a1 = debug_mem_banks[i] = debug_mem_area + i;
  3453. a2 = mem_banks[i];
  3454. if (a2 != oa) {
  3455. for (j = 0; membank_stores[j].addr; j++) {
  3456. if (membank_stores[j].addr == a2)
  3457. break;
  3458. }
  3459. if (membank_stores[j].addr == NULL) {
  3460. membank_stores[j].addr = a2;
  3461. memcpy (&membank_stores[j].store, a2, sizeof (addrbank));
  3462. }
  3463. }
  3464. memcpy (a1, a2, sizeof (addrbank));
  3465. }
  3466. for (i = 0; i < as; i++) {
  3467. a2 = mem_banks[i];
  3468. a2->bget = mode ? mmu_bget : debug_bget;
  3469. a2->wget = mode ? mmu_wget : debug_wget;
  3470. a2->lget = mode ? mmu_lget : debug_lget;
  3471. a2->bput = mode ? mmu_bput : debug_bput;
  3472. a2->wput = mode ? mmu_wput : debug_wput;
  3473. a2->lput = mode ? mmu_lput : debug_lput;
  3474. a2->check = debug_check;
  3475. a2->xlateaddr = debug_xlate;
  3476. a2->wgeti = mode ? mmu_wgeti : debug_wgeti;
  3477. a2->lgeti = mode ? mmu_lgeti : debug_lgeti;
  3478. }
  3479. #endif
  3480. if (mode)
  3481. mmu_enabled = 1;
  3482. else
  3483. memwatch_enabled = 1;
  3484. }
  3485. int debug_bankchange (int mode)
  3486. {
  3487. if (mode == -1) {
  3488. int v = deinitialize_memwatch ();
  3489. if (v < 0)
  3490. return -2;
  3491. return v;
  3492. }
  3493. if (mode >= 0) {
  3494. initialize_memwatch (mode);
  3495. memwatch_setup ();
  3496. }
  3497. return -1;
  3498. }
  3499. addrbank *get_mem_bank_real(uaecptr addr)
  3500. {
  3501. addrbank *ab = &get_mem_bank(addr);
  3502. if (!memwatch_enabled)
  3503. return ab;
  3504. addrbank *ab2 = debug_mem_banks[addr >> 16];
  3505. if (ab2)
  3506. return ab2;
  3507. return ab;
  3508. }
  3509. static const TCHAR *getsizechar (int size)
  3510. {
  3511. if (size == 4)
  3512. return _T(".l");
  3513. if (size == 3)
  3514. return _T(".3");
  3515. if (size == 2)
  3516. return _T(".w");
  3517. if (size == 1)
  3518. return _T(".b");
  3519. return _T("");
  3520. }
  3521. void memwatch_dump2 (TCHAR *buf, int bufsize, int num)
  3522. {
  3523. int i;
  3524. struct memwatch_node *mwn;
  3525. if (buf)
  3526. memset (buf, 0, bufsize * sizeof (TCHAR));
  3527. for (i = 0; i < MEMWATCH_TOTAL; i++) {
  3528. if ((num >= 0 && num == i) || (num < 0)) {
  3529. uae_u32 usedmask = 0;
  3530. mwn = &mwnodes[i];
  3531. if (mwn->size == 0)
  3532. continue;
  3533. buf = buf_out (buf, &bufsize, _T("%2d: %08X - %08X (%d) %c%c%c"),
  3534. i, mwn->addr, mwn->addr + (mwn->size - 1), mwn->size,
  3535. (mwn->rwi & 1) ? 'R' : ' ', (mwn->rwi & 2) ? 'W' : ' ', (mwn->rwi & 4) ? 'I' : ' ');
  3536. if (mwn->frozen)
  3537. buf = buf_out (buf, &bufsize, _T(" F"));
  3538. if (mwn->val_enabled)
  3539. buf = buf_out (buf, &bufsize, _T(" =%X%s"), mwn->val, getsizechar (mwn->val_size));
  3540. if (mwn->modval_written)
  3541. buf = buf_out (buf, &bufsize, _T(" =M"));
  3542. if (mwn->mustchange)
  3543. buf = buf_out(buf, &bufsize, _T(" C"));
  3544. if (mwn->pc != 0xffffffff)
  3545. buf = buf_out(buf, &bufsize, _T(" PC=%08x"), mwn->pc);
  3546. if (mwn->reportonly)
  3547. buf = buf_out(buf, &bufsize, _T(" L"));
  3548. if (mwn->nobreak)
  3549. buf = buf_out(buf, &bufsize, _T(" N"));
  3550. if (mwn->bus_error) {
  3551. buf = buf_out(buf, &bufsize, _T(" BER%s%s%s"),
  3552. (mwn->bus_error & 1) ? _T("R") : _T(""),
  3553. (mwn->bus_error & 2) ? _T("W") : _T(""),
  3554. (mwn->bus_error & 4) ? _T("P") : _T(""));
  3555. }
  3556. for (int j = 0; memwatch_access_masks[j].mask; j++) {
  3557. uae_u32 mask = memwatch_access_masks[j].mask;
  3558. if ((mwn->access_mask & mask) == mask && (usedmask & mask) == 0) {
  3559. buf = buf_out(buf, &bufsize, _T(" "));
  3560. buf = buf_out(buf, &bufsize, memwatch_access_masks[j].name);
  3561. usedmask |= mask;
  3562. }
  3563. }
  3564. buf = buf_out (buf, &bufsize, _T("\n"));
  3565. }
  3566. }
  3567. }
  3568. static void memwatch_dump (int num)
  3569. {
  3570. TCHAR *buf;
  3571. int multiplier = num < 0 ? MEMWATCH_TOTAL : 1;
  3572. buf = xmalloc (TCHAR, 50 * multiplier);
  3573. if (!buf)
  3574. return;
  3575. memwatch_dump2 (buf, 50 * multiplier, num);
  3576. f_out (stdout, _T("%s"), buf);
  3577. xfree (buf);
  3578. }
  3579. static void memwatch (TCHAR **c)
  3580. {
  3581. int num;
  3582. struct memwatch_node *mwn;
  3583. TCHAR nc, *cp;
  3584. if (!memwatch_enabled) {
  3585. initialize_memwatch (0);
  3586. console_out (_T("Memwatch breakpoints enabled\n"));
  3587. memwatch_access_validator = 0;
  3588. }
  3589. cp = *c;
  3590. ignore_ws (c);
  3591. if (!more_params (c)) {
  3592. memwatch_dump (-1);
  3593. return;
  3594. }
  3595. nc = next_char (c);
  3596. if (nc == '-') {
  3597. deinitialize_memwatch ();
  3598. console_out (_T("Memwatch breakpoints disabled\n"));
  3599. return;
  3600. }
  3601. if (nc == 'l') {
  3602. memwatch_access_validator = !memwatch_access_validator;
  3603. console_out_f(_T("Memwatch DMA validator %s\n"), memwatch_access_validator ? _T("enabled") : _T("disabled"));
  3604. return;
  3605. }
  3606. if (nc == 'd') {
  3607. if (illgdebug) {
  3608. ignore_ws (c);
  3609. if (more_params (c)) {
  3610. uae_u32 addr = readhex (c);
  3611. uae_u32 len = 1;
  3612. if (more_params (c))
  3613. len = readhex (c);
  3614. console_out_f (_T("Cleared logging addresses %08X - %08X\n"), addr, addr + len);
  3615. while (len > 0) {
  3616. addr &= 0xffffff;
  3617. illgdebug[addr] = 7;
  3618. addr++;
  3619. len--;
  3620. }
  3621. } else {
  3622. illg_free();
  3623. console_out (_T("Illegal memory access logging disabled\n"));
  3624. }
  3625. } else {
  3626. illg_init ();
  3627. ignore_ws (c);
  3628. illgdebug_break = 0;
  3629. if (more_params (c))
  3630. illgdebug_break = 1;
  3631. console_out_f (_T("Illegal memory access logging enabled. Break=%d\n"), illgdebug_break);
  3632. }
  3633. return;
  3634. }
  3635. *c = cp;
  3636. num = readint (c);
  3637. if (num < 0 || num >= MEMWATCH_TOTAL)
  3638. return;
  3639. mwn = &mwnodes[num];
  3640. mwn->size = 0;
  3641. ignore_ws (c);
  3642. if (!more_params (c)) {
  3643. console_out_f (_T("Memwatch %d removed\n"), num);
  3644. memwatch_setup ();
  3645. return;
  3646. }
  3647. mwn->addr = readhex (c);
  3648. mwn->size = 1;
  3649. mwn->rwi = 7;
  3650. mwn->val_enabled = 0;
  3651. mwn->val_mask = 0xffffffff;
  3652. mwn->val = 0;
  3653. mwn->access_mask = 0;
  3654. mwn->reg = 0xffffffff;
  3655. mwn->frozen = 0;
  3656. mwn->modval_written = 0;
  3657. mwn->mustchange = 0;
  3658. mwn->bus_error = 0;
  3659. mwn->reportonly = false;
  3660. ignore_ws (c);
  3661. if (more_params (c)) {
  3662. mwn->size = readhex (c);
  3663. ignore_ws (c);
  3664. if (more_params (c)) {
  3665. TCHAR *cs = *c;
  3666. while (*cs) {
  3667. for (int i = 0; memwatch_access_masks[i].mask; i++) {
  3668. const TCHAR *n = memwatch_access_masks[i].name;
  3669. int len = _tcslen(n);
  3670. if (!_tcsnicmp(cs, n, len)) {
  3671. if (cs[len] == 0 || cs[len] == 10 || cs[len] == 13 || cs[len] == ' ') {
  3672. mwn->access_mask |= memwatch_access_masks[i].mask;
  3673. while (len > 0) {
  3674. len--;
  3675. cs[len] = ' ';
  3676. }
  3677. }
  3678. }
  3679. }
  3680. cs++;
  3681. }
  3682. ignore_ws (c);
  3683. if (more_params(c)) {
  3684. for (;;) {
  3685. TCHAR ncc = _totupper(peek_next_char(c));
  3686. TCHAR nc = _totupper(next_char(c));
  3687. if (mwn->rwi == 7 && (nc == 'W' || nc == 'R' || nc == 'I'))
  3688. mwn->rwi = 0;
  3689. if (nc == 'F')
  3690. mwn->frozen = 1;
  3691. if (nc == 'W')
  3692. mwn->rwi |= 2;
  3693. if (nc == 'I')
  3694. mwn->rwi |= 4;
  3695. if (nc == 'R')
  3696. mwn->rwi |= 1;
  3697. if (nc == 'B') {
  3698. mwn->bus_error = 0;
  3699. for (;;) {
  3700. ncc = next_char2(c);
  3701. if (ncc == ' ' || ncc == 0)
  3702. break;
  3703. if (ncc == 'R') {
  3704. mwn->bus_error |= 1;
  3705. mwn->rwi |= 1;
  3706. } else if (ncc == 'W') {
  3707. mwn->bus_error |= 2;
  3708. mwn->rwi |= 2;
  3709. } else if (ncc == 'P') {
  3710. mwn->bus_error |= 4;
  3711. mwn->rwi |= 4;
  3712. } else {
  3713. break;
  3714. }
  3715. }
  3716. if (!mwn->rwi)
  3717. mwn->rwi = 7;
  3718. if (!mwn->bus_error)
  3719. mwn->bus_error = 7;
  3720. }
  3721. if (nc == 'L')
  3722. mwn->reportonly = true;
  3723. if (nc == 'N')
  3724. mwn->nobreak = true;
  3725. if (ncc == ' ' || ncc == 0)
  3726. break;
  3727. if (nc == 'P' && ncc == 'C') {
  3728. next_char(c);
  3729. mwn->pc = readhex(c, NULL);
  3730. }
  3731. if (!more_params(c))
  3732. break;
  3733. }
  3734. ignore_ws (c);
  3735. }
  3736. if (more_params (c)) {
  3737. if (_totupper (**c) == 'M') {
  3738. mwn->modval_written = 1;
  3739. } else if (_totupper (**c) == 'C') {
  3740. mwn->mustchange = 1;
  3741. } else {
  3742. mwn->val = readhex (c, &mwn->val_size);
  3743. mwn->val_enabled = 1;
  3744. }
  3745. }
  3746. }
  3747. }
  3748. if (!mwn->access_mask)
  3749. mwn->access_mask = MW_MASK_CPU_D_R | MW_MASK_CPU_D_W | MW_MASK_CPU_I;
  3750. if (mwn->frozen && mwn->rwi == 0)
  3751. mwn->rwi = 3;
  3752. memwatch_setup ();
  3753. memwatch_dump (num);
  3754. }
  3755. static void copymem(TCHAR **c)
  3756. {
  3757. uae_u32 addr = 0, eaddr = 0, dst = 0;
  3758. ignore_ws(c);
  3759. if (!more_params (c))
  3760. return;
  3761. addr = readhex (c);
  3762. ignore_ws (c);
  3763. if (!more_params (c))
  3764. return;
  3765. eaddr = readhex (c);
  3766. ignore_ws (c);
  3767. if (!more_params (c))
  3768. return;
  3769. dst = readhex (c);
  3770. if (addr >= eaddr)
  3771. return;
  3772. uae_u32 addrb = addr;
  3773. uae_u32 dstb = dst;
  3774. uae_u32 len = eaddr - addr;
  3775. if (dst <= addr) {
  3776. while (addr < eaddr) {
  3777. put_byte(dst, get_byte(addr));
  3778. addr++;
  3779. dst++;
  3780. }
  3781. } else {
  3782. dst += eaddr - addr;
  3783. while (addr < eaddr) {
  3784. dst--;
  3785. eaddr--;
  3786. put_byte(dst, get_byte(eaddr));
  3787. }
  3788. }
  3789. console_out_f(_T("Copied from %08x - %08x to %08x - %08x\n"), addrb, addrb + len - 1, dstb, dstb + len - 1);
  3790. }
  3791. static void writeintomem (TCHAR **c)
  3792. {
  3793. uae_u32 addr = 0;
  3794. uae_u32 eaddr = 0xffffffff;
  3795. uae_u32 val = 0;
  3796. TCHAR cc;
  3797. int len = 1;
  3798. bool fillmode = false;
  3799. if (**c == 'f') {
  3800. fillmode = true;
  3801. (*c)++;
  3802. } else if (**c == 'c') {
  3803. (*c)++;
  3804. copymem(c);
  3805. return;
  3806. }
  3807. ignore_ws(c);
  3808. addr = readhex (c);
  3809. ignore_ws (c);
  3810. if (fillmode) {
  3811. if (!more_params (c))
  3812. return;
  3813. eaddr = readhex(c);
  3814. ignore_ws (c);
  3815. }
  3816. if (!more_params (c))
  3817. return;
  3818. TCHAR *cb = *c;
  3819. cc = peekchar (c);
  3820. uae_u32 addrc = addr;
  3821. for(;;) {
  3822. uae_u32 addrb = addr;
  3823. *c = cb;
  3824. if (cc == '\'' || cc == '\"') {
  3825. next_char2(c);
  3826. while (more_params2(c)) {
  3827. TCHAR str[2];
  3828. char *astr;
  3829. cc = next_char2(c);
  3830. if (cc == '\'' || cc == '\"')
  3831. break;
  3832. str[0] = cc;
  3833. str[1] = 0;
  3834. astr = ua (str);
  3835. put_byte (addr, astr[0]);
  3836. xfree (astr);
  3837. addr++;
  3838. if (addr >= eaddr)
  3839. break;
  3840. }
  3841. } else {
  3842. for (;;) {
  3843. ignore_ws (c);
  3844. if (!more_params (c))
  3845. break;
  3846. val = readhex (c, &len);
  3847. if (len == 4) {
  3848. put_long (addr, val);
  3849. cc = 'L';
  3850. } else if (len == 2) {
  3851. put_word (addr, val);
  3852. cc = 'W';
  3853. } else if (len == 1) {
  3854. put_byte (addr, val);
  3855. cc = 'B';
  3856. } else {
  3857. break;
  3858. }
  3859. if (!fillmode)
  3860. console_out_f (_T("Wrote %X (%u) at %08X.%c\n"), val, val, addr, cc);
  3861. addr += len;
  3862. if (addr >= eaddr)
  3863. break;
  3864. }
  3865. }
  3866. if (eaddr == 0xffffffff || addr <= addrb || addr >= eaddr)
  3867. break;
  3868. }
  3869. if (eaddr != 0xffffffff)
  3870. console_out_f(_T("Wrote data to %08x - %08x\n"), addrc, addr);
  3871. }
  3872. static uae_u8 *dump_xlate (uae_u32 addr)
  3873. {
  3874. if (!mem_banks[addr >> 16]->check (addr, 1))
  3875. return NULL;
  3876. return mem_banks[addr >> 16]->xlateaddr (addr);
  3877. }
  3878. #if 0
  3879. #define UAE_MEMORY_REGIONS_MAX 64
  3880. #define UAE_MEMORY_REGION_NAME_LENGTH 64
  3881. #define UAE_MEMORY_REGION_RAM (1 << 0)
  3882. #define UAE_MEMORY_REGION_ALIAS (1 << 1)
  3883. #define UAE_MEMORY_REGION_MIRROR (1 << 2)
  3884. typedef struct UaeMemoryRegion {
  3885. uaecptr start;
  3886. int size;
  3887. TCHAR name[UAE_MEMORY_REGION_NAME_LENGTH];
  3888. TCHAR rom_name[UAE_MEMORY_REGION_NAME_LENGTH];
  3889. uaecptr alias;
  3890. int flags;
  3891. } UaeMemoryRegion;
  3892. typedef struct UaeMemoryMap {
  3893. UaeMemoryRegion regions[UAE_MEMORY_REGIONS_MAX];
  3894. int num_regions;
  3895. } UaeMemoryMap;
  3896. #endif
  3897. static const TCHAR *bankmodes[] = { _T("F32"), _T("C16"), _T("C32"), _T("CIA"), _T("F16"), _T("F16X") };
  3898. static void memory_map_dump_3(UaeMemoryMap *map, int log)
  3899. {
  3900. bool imold;
  3901. int i, j, max;
  3902. addrbank *a1 = mem_banks[0];
  3903. TCHAR txt[256];
  3904. map->num_regions = 0;
  3905. imold = currprefs.illegal_mem;
  3906. currprefs.illegal_mem = false;
  3907. max = currprefs.address_space_24 ? 256 : 65536;
  3908. j = 0;
  3909. for (i = 0; i < max + 1; i++) {
  3910. addrbank *a2 = NULL;
  3911. if (i < max)
  3912. a2 = mem_banks[i];
  3913. if (a1 != a2) {
  3914. int k, mirrored, mirrored2, size, size_out;
  3915. TCHAR size_ext;
  3916. uae_u8 *caddr;
  3917. TCHAR tmp[MAX_DPATH];
  3918. const TCHAR *name = a1->name;
  3919. struct addrbank_sub *sb = a1->sub_banks;
  3920. int bankoffset = 0;
  3921. int region_size;
  3922. k = j;
  3923. caddr = dump_xlate (k << 16);
  3924. mirrored = caddr ? 1 : 0;
  3925. k++;
  3926. while (k < i && caddr) {
  3927. if (dump_xlate (k << 16) == caddr) {
  3928. mirrored++;
  3929. }
  3930. k++;
  3931. }
  3932. mirrored2 = mirrored;
  3933. if (mirrored2 == 0)
  3934. mirrored2 = 1;
  3935. while (bankoffset < 65536) {
  3936. int bankoffset2 = bankoffset;
  3937. if (sb) {
  3938. uaecptr daddr;
  3939. if (!sb->bank)
  3940. break;
  3941. daddr = (j << 16) | bankoffset;
  3942. a1 = get_sub_bank(&daddr);
  3943. name = a1->name;
  3944. for (;;) {
  3945. bankoffset2 += MEMORY_MIN_SUBBANK;
  3946. if (bankoffset2 >= 65536)
  3947. break;
  3948. daddr = (j << 16) | bankoffset2;
  3949. addrbank *dab = get_sub_bank(&daddr);
  3950. if (dab != a1)
  3951. break;
  3952. }
  3953. sb++;
  3954. size = (bankoffset2 - bankoffset) / 1024;
  3955. region_size = size * 1024;
  3956. } else {
  3957. size = (i - j) << (16 - 10);
  3958. region_size = ((i - j) << 16) / mirrored2;
  3959. }
  3960. if (name == NULL)
  3961. name = _T("<none>");
  3962. size_out = size;
  3963. size_ext = 'K';
  3964. if (j >= 256 && (size_out / mirrored2 >= 1024) && !((size_out / mirrored2) & 1023)) {
  3965. size_out /= 1024;
  3966. size_ext = 'M';
  3967. }
  3968. _stprintf (txt, _T("%08X %7d%c/%d = %7d%c %s%s %s %s"), (j << 16) | bankoffset, size_out, size_ext,
  3969. mirrored, mirrored ? size_out / mirrored : size_out, size_ext,
  3970. (a1->flags & ABFLAG_CACHE_ENABLE_INS) ? _T("I") : _T("-"),
  3971. (a1->flags & ABFLAG_CACHE_ENABLE_DATA) ? _T("D") : _T("-"),
  3972. bankmodes[ce_banktype[j]],
  3973. name);
  3974. tmp[0] = 0;
  3975. if ((a1->flags & ABFLAG_ROM) && mirrored) {
  3976. TCHAR *p = txt + _tcslen (txt);
  3977. uae_u32 crc = 0xffffffff;
  3978. if (a1->check(((j << 16) | bankoffset), (size * 1024) / mirrored))
  3979. crc = get_crc32 (a1->xlateaddr((j << 16) | bankoffset), (size * 1024) / mirrored);
  3980. struct romdata *rd = getromdatabycrc (crc);
  3981. _stprintf (p, _T(" (%08X)"), crc);
  3982. if (rd) {
  3983. tmp[0] = '=';
  3984. getromname (rd, tmp + 1);
  3985. _tcscat (tmp, _T("\n"));
  3986. }
  3987. }
  3988. if (a1 != &dummy_bank) {
  3989. for (int m = 0; m < mirrored2; m++) {
  3990. if (map->num_regions >= UAE_MEMORY_REGIONS_MAX)
  3991. break;
  3992. UaeMemoryRegion *r = &map->regions[map->num_regions];
  3993. r->start = (j << 16) + bankoffset + region_size * m;
  3994. r->size = region_size;
  3995. r->flags = 0;
  3996. r->memory = NULL;
  3997. if (!(a1->flags & ABFLAG_PPCIOSPACE)) {
  3998. r->memory = dump_xlate((j << 16) | bankoffset);
  3999. if (r->memory)
  4000. r->flags |= UAE_MEMORY_REGION_RAM;
  4001. }
  4002. /* just to make it easier to spot in debugger */
  4003. r->alias = 0xffffffff;
  4004. if (m >= 0) {
  4005. r->alias = j << 16;
  4006. r->flags |= UAE_MEMORY_REGION_ALIAS | UAE_MEMORY_REGION_MIRROR;
  4007. }
  4008. _stprintf(r->name, _T("%s"), name);
  4009. _stprintf(r->rom_name, _T("%s"), tmp);
  4010. map->num_regions += 1;
  4011. }
  4012. }
  4013. _tcscat (txt, _T("\n"));
  4014. if (log > 0)
  4015. write_log (_T("%s"), txt);
  4016. else if (log == 0)
  4017. console_out (txt);
  4018. if (tmp[0]) {
  4019. if (log > 0)
  4020. write_log (_T("%s"), tmp);
  4021. else if (log == 0)
  4022. console_out (tmp);
  4023. }
  4024. if (!sb)
  4025. break;
  4026. bankoffset = bankoffset2;
  4027. }
  4028. j = i;
  4029. a1 = a2;
  4030. }
  4031. }
  4032. pci_dump(log);
  4033. currprefs.illegal_mem = imold;
  4034. }
  4035. void uae_memory_map(UaeMemoryMap *map)
  4036. {
  4037. memory_map_dump_3(map, -1);
  4038. }
  4039. static void memory_map_dump_2 (int log)
  4040. {
  4041. UaeMemoryMap map;
  4042. memory_map_dump_3(&map, log);
  4043. #if 0
  4044. for (int i = 0; i < map.num_regions; i++) {
  4045. TCHAR txt[256];
  4046. UaeMemoryRegion *r = &map.regions[i];
  4047. int size = r->size / 1024;
  4048. TCHAR size_ext = 'K';
  4049. int mirrored = 1;
  4050. int size_out = 0;
  4051. _stprintf (txt, _T("%08X %7u%c/%d = %7u%c %s\n"), r->start, size, size_ext,
  4052. r->flags & UAE_MEMORY_REGION_RAM, size, size_ext, r->name);
  4053. if (log)
  4054. write_log (_T("%s"), txt);
  4055. else
  4056. console_out (txt);
  4057. if (r->rom_name[0]) {
  4058. if (log)
  4059. write_log (_T("%s"), r->rom_name);
  4060. else
  4061. console_out (r->rom_name);
  4062. }
  4063. }
  4064. #endif
  4065. }
  4066. void memory_map_dump (void)
  4067. {
  4068. memory_map_dump_2(1);
  4069. }
  4070. STATIC_INLINE uaecptr BPTR2APTR (uaecptr addr)
  4071. {
  4072. return addr << 2;
  4073. }
  4074. static TCHAR *BSTR2CSTR (uae_u8 *bstr)
  4075. {
  4076. TCHAR *s;
  4077. char *cstr = xmalloc (char, bstr[0] + 1);
  4078. if (cstr) {
  4079. memcpy (cstr, bstr + 1, bstr[0]);
  4080. cstr[bstr[0]] = 0;
  4081. }
  4082. s = au (cstr);
  4083. xfree (cstr);
  4084. return s;
  4085. }
  4086. static void print_task_info (uaecptr node, bool nonactive)
  4087. {
  4088. TCHAR *s;
  4089. int process = get_byte_debug (node + 8) == 13 ? 1 : 0;
  4090. console_out_f (_T("%08X: "), node);
  4091. s = au ((char*)get_real_address_debug(get_long_debug (node + 10)));
  4092. console_out_f (process ? _T("PROCESS '%s'\n") : _T("TASK '%s'\n"), s);
  4093. xfree (s);
  4094. if (process) {
  4095. uaecptr cli = BPTR2APTR (get_long_debug (node + 172));
  4096. int tasknum = get_long_debug (node + 140);
  4097. if (cli && tasknum) {
  4098. uae_u8 *command_bstr = get_real_address_debug(BPTR2APTR (get_long_debug (cli + 16)));
  4099. TCHAR *command = BSTR2CSTR (command_bstr);
  4100. console_out_f (_T(" [%d, '%s']\n"), tasknum, command);
  4101. xfree (command);
  4102. } else {
  4103. console_out (_T("\n"));
  4104. }
  4105. }
  4106. if (nonactive) {
  4107. uae_u32 sigwait = get_long_debug(node + 22);
  4108. if (sigwait)
  4109. console_out_f(_T(" Waiting signals: %08x\n"), sigwait);
  4110. int offset = kickstart_version >= 37 ? 74 : 70;
  4111. uae_u32 sp = get_long_debug(node + 54) + offset;
  4112. uae_u32 pc = get_long_debug(sp);
  4113. console_out_f(_T(" SP: %08x PC: %08x\n"), sp, pc);
  4114. }
  4115. }
  4116. static void show_exec_tasks (void)
  4117. {
  4118. uaecptr execbase = get_long_debug (4);
  4119. uaecptr taskready = execbase + 406;
  4120. uaecptr taskwait = execbase + 420;
  4121. uaecptr node;
  4122. console_out_f (_T("Execbase at 0x%08X\n"), execbase);
  4123. console_out (_T("Current:\n"));
  4124. node = get_long_debug (execbase + 276);
  4125. print_task_info (node, false);
  4126. console_out_f (_T("Ready:\n"));
  4127. node = get_long_debug (taskready);
  4128. while (node && get_long_debug(node)) {
  4129. print_task_info (node, true);
  4130. node = get_long_debug (node);
  4131. }
  4132. console_out (_T("Waiting:\n"));
  4133. node = get_long_debug (taskwait);
  4134. while (node && get_long_debug(node)) {
  4135. print_task_info (node, true);
  4136. node = get_long_debug (node);
  4137. }
  4138. }
  4139. static uaecptr get_base (const uae_char *name, int offset)
  4140. {
  4141. uaecptr v = get_long_debug (4);
  4142. addrbank *b = &get_mem_bank(v);
  4143. if (!b || !b->check (v, 400) || !(b->flags & ABFLAG_RAM))
  4144. return 0;
  4145. v += offset;
  4146. while ((v = get_long_debug (v))) {
  4147. uae_u32 v2;
  4148. uae_u8 *p;
  4149. b = &get_mem_bank (v);
  4150. if (!b || !b->check (v, 32) || (!(b->flags & ABFLAG_RAM) && !(b->flags & ABFLAG_ROMIN)))
  4151. goto fail;
  4152. v2 = get_long_debug (v + 10); // name
  4153. b = &get_mem_bank (v2);
  4154. if (!b || !b->check (v2, 20))
  4155. goto fail;
  4156. if ((b->flags & ABFLAG_ROM) || (b->flags & ABFLAG_RAM) || (b->flags & ABFLAG_ROMIN)) {
  4157. p = get_real_address_debug(v2);
  4158. if (!memcmp (p, name, strlen (name) + 1))
  4159. return v;
  4160. }
  4161. }
  4162. return 0;
  4163. fail:
  4164. return 0xffffffff;
  4165. }
  4166. static TCHAR *getfrombstr(uaecptr pp)
  4167. {
  4168. uae_u8 len = get_byte(pp << 2);
  4169. TCHAR *s = xcalloc (TCHAR, len + 1);
  4170. char data[256];
  4171. for (int i = 0; i < len; i++) {
  4172. data[i] = get_byte((pp << 2) + 1 + i);
  4173. data[i + 1] = 0;
  4174. }
  4175. return au_copy (s, len + 1, data);
  4176. }
  4177. // read one byte from expansion autoconfig ROM
  4178. static void copyromdata(uae_u8 bustype, uaecptr rom, int offset, uae_u8 *out, int size)
  4179. {
  4180. switch (bustype & 0xc0)
  4181. {
  4182. case 0x00: // nibble
  4183. while (size-- > 0) {
  4184. *out++ = (get_byte_debug(rom + offset * 4 + 0) & 0xf0) | ((get_byte_debug(rom + offset * 4 + 2) & 0xf0) >> 4);
  4185. offset++;
  4186. }
  4187. break;
  4188. case 0x40: // byte
  4189. while (size-- > 0) {
  4190. *out++ = get_byte_debug(rom + offset * 2);
  4191. offset++;
  4192. }
  4193. break;
  4194. case 0x80: // word
  4195. default:
  4196. while (size-- > 0) {
  4197. *out++ = get_byte_debug(rom + offset);
  4198. offset++;
  4199. }
  4200. break;
  4201. }
  4202. }
  4203. static void show_exec_lists (TCHAR *t)
  4204. {
  4205. uaecptr execbase = get_long_debug (4);
  4206. uaecptr list = 0, node;
  4207. TCHAR c = t[0];
  4208. if (c == 'o' || c == 'O') { // doslist
  4209. uaecptr dosbase = get_base ("dos.library", 378);
  4210. if (dosbase) {
  4211. uaecptr rootnode = get_long_debug (dosbase + 34);
  4212. uaecptr dosinfo = get_long_debug (rootnode + 24) << 2;
  4213. console_out_f (_T("ROOTNODE: %08x DOSINFO: %08x\n"), rootnode, dosinfo);
  4214. uaecptr doslist = get_long_debug (dosinfo + 4) << 2;
  4215. while (doslist) {
  4216. int type = get_long_debug (doslist + 4);
  4217. uaecptr msgport = get_long_debug (doslist + 8);
  4218. uaecptr lock = get_long_debug(doslist + 12);
  4219. TCHAR *name = getfrombstr(get_long_debug(doslist + 40));
  4220. console_out_f(_T("%08x: Type=%d Port=%08x Lock=%08x '%s'\n"), doslist, type, msgport, lock, name);
  4221. if (type == 0) {
  4222. uaecptr fssm = get_long_debug(doslist + 28) << 2;
  4223. console_out_f (_T(" - H=%08x Stack=%5d Pri=%2d Start=%08x Seg=%08x GV=%08x\n"),
  4224. get_long_debug (doslist + 16) << 2, get_long_debug (doslist + 20),
  4225. get_long_debug (doslist + 24), fssm,
  4226. get_long_debug (doslist + 32) << 2, get_long_debug (doslist + 36));
  4227. if (fssm >= 0x100 && (fssm & 3) == 0) {
  4228. TCHAR *unitname = getfrombstr(get_long_debug(fssm + 4));
  4229. console_out_f (_T(" %s:%d %08x\n"), unitname, get_long_debug(fssm), get_long_debug(fssm + 8));
  4230. uaecptr de = get_long_debug(fssm + 8) << 2;
  4231. if (de) {
  4232. console_out_f (_T(" TableSize %u\n"), get_long_debug(de + 0));
  4233. console_out_f (_T(" SizeBlock %u\n"), get_long_debug(de + 4));
  4234. console_out_f (_T(" SecOrg %u\n"), get_long_debug(de + 8));
  4235. console_out_f (_T(" Surfaces %u\n"), get_long_debug(de + 12));
  4236. console_out_f (_T(" SectorPerBlock %u\n"), get_long_debug(de + 16));
  4237. console_out_f (_T(" BlocksPerTrack %u\n"), get_long_debug(de + 20));
  4238. console_out_f (_T(" Reserved %u\n"), get_long_debug(de + 24));
  4239. console_out_f (_T(" PreAlloc %u\n"), get_long_debug(de + 28));
  4240. console_out_f (_T(" Interleave %u\n"), get_long_debug(de + 32));
  4241. console_out_f (_T(" LowCyl %u\n"), get_long_debug(de + 36));
  4242. console_out_f (_T(" HighCyl %u (Total %u)\n"), get_long_debug(de + 40), get_long_debug(de + 40) - get_long_debug(de + 36) + 1);
  4243. console_out_f (_T(" NumBuffers %u\n"), get_long_debug(de + 44));
  4244. console_out_f (_T(" BufMemType 0x%08x\n"), get_long_debug(de + 48));
  4245. console_out_f (_T(" MaxTransfer 0x%08x\n"), get_long_debug(de + 52));
  4246. console_out_f (_T(" Mask 0x%08x\n"), get_long_debug(de + 56));
  4247. console_out_f (_T(" BootPri %d\n"), get_long_debug(de + 60));
  4248. console_out_f (_T(" DosType 0x%08x\n"), get_long_debug(de + 64));
  4249. }
  4250. xfree(unitname);
  4251. }
  4252. } else if (type == 2) {
  4253. console_out_f(_T(" - VolumeDate=%08x %08x %08x LockList=%08x DiskType=%08x\n"),
  4254. get_long_debug(doslist + 16), get_long_debug(doslist + 20), get_long_debug(doslist + 24),
  4255. get_long_debug(doslist + 28),
  4256. get_long_debug(doslist + 32));
  4257. }
  4258. xfree (name);
  4259. doslist = get_long_debug (doslist) << 2;
  4260. }
  4261. } else {
  4262. console_out_f (_T("can't find dos.library\n"));
  4263. }
  4264. return;
  4265. } else if (c == 'i' || c == 'I') { // interrupts
  4266. static const int it[] = { 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0 };
  4267. static const int it2[] = { 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7 };
  4268. list = execbase + 84;
  4269. for (int i = 0; i < 16; i++) {
  4270. console_out_f (_T("%2d %d: %08X\n"), i + 1, it2[i], list);
  4271. if (it[i]) {
  4272. console_out_f (_T(" [H] %08X\n"), get_long_debug (list));
  4273. node = get_long_debug (list + 8);
  4274. if (node) {
  4275. uae_u8 *addr = get_real_address_debug(get_long_debug (node + 10));
  4276. TCHAR *name = addr ? au ((char*)addr) : au("<null>");
  4277. console_out_f (_T(" %08X (C=%08X D=%08X) '%s'\n"), node, get_long_debug (list + 4), get_long_debug (list), name);
  4278. xfree (name);
  4279. }
  4280. } else {
  4281. int cnt = 0;
  4282. node = get_long_debug (list);
  4283. node = get_long_debug (node);
  4284. while (get_long_debug (node)) {
  4285. uae_u8 *addr = get_real_address_debug(get_long_debug (node + 10));
  4286. TCHAR *name = addr ? au ((char*)addr) : au("<null>");
  4287. uae_s8 pri = get_byte_debug(node + 9);
  4288. console_out_f (_T(" [S] %08x %+03d (C=%08x D=%08X) '%s'\n"), node, pri, get_long_debug (node + 18), get_long_debug (node + 14), name);
  4289. if (i == 4 - 1 || i == 14 - 1) {
  4290. if (!_tcsicmp (name, _T("cia-a")) || !_tcsicmp (name, _T("cia-b"))) {
  4291. static const TCHAR *ciai[] = { _T("A"), _T("B"), _T("ALRM"), _T("SP"), _T("FLG") };
  4292. uaecptr cia = node + 22;
  4293. for (int j = 0; j < 5; j++) {
  4294. uaecptr ciap = get_long_debug (cia);
  4295. console_out_f (_T(" %5s: %08x"), ciai[j], ciap);
  4296. if (ciap) {
  4297. uae_u8 *addr2 = get_real_address_debug(get_long_debug (ciap + 10));
  4298. TCHAR *name2 = addr ? au ((char*)addr2) : au("<null>");
  4299. console_out_f (_T(" (C=%08x D=%08X) '%s'"), get_long_debug (ciap + 18), get_long_debug (ciap + 14), name2);
  4300. xfree (name2);
  4301. }
  4302. console_out_f (_T("\n"));
  4303. cia += 4;
  4304. }
  4305. }
  4306. }
  4307. xfree (name);
  4308. node = get_long_debug (node);
  4309. cnt++;
  4310. }
  4311. if (!cnt)
  4312. console_out_f (_T(" [S] <none>\n"));
  4313. }
  4314. list += 12;
  4315. }
  4316. return;
  4317. } else if (c == 'e') { // expansion
  4318. uaecptr expbase = get_base("expansion.library", 378);
  4319. if (expbase) {
  4320. if (t[1] == 'm') {
  4321. uaecptr list = get_long_debug(expbase + 74);
  4322. while (list && get_long_debug(list)) {
  4323. uaecptr name = get_long(list + 10);
  4324. uae_s8 pri = get_byte(list + 9);
  4325. uae_u16 flags = get_word_debug(list + 14);
  4326. uae_u32 dn = get_long_debug(list + 16);
  4327. uae_u8 *addr = get_real_address_debug(name);
  4328. TCHAR *name1 = addr ? au((char*)addr) : au("<null>");
  4329. my_trim(name1);
  4330. console_out_f(_T("%08x %04x %08x %d %s\n"), list, flags, dn, pri, name1);
  4331. xfree(name1);
  4332. list = get_long_debug(list);
  4333. }
  4334. } else {
  4335. list = get_long_debug(expbase + 60);
  4336. while (list && get_long_debug(list)) {
  4337. uae_u32 addr = get_long_debug(list + 32);
  4338. uae_u16 rom_vector = get_word_debug(list + 16 + 10);
  4339. uae_u8 type = get_byte_debug(list + 16 + 0);
  4340. console_out_f(_T("%02x %02x %08x %08x %04x %02x %08x %04x (%u/%u)\n"),
  4341. type, get_byte_debug(list + 16 + 2),
  4342. addr, get_long_debug(list + 36),
  4343. get_word_debug(list + 16 + 4), get_byte_debug(list + 16 + 1),
  4344. get_long_debug(list + 16 + 6), rom_vector,
  4345. get_word_debug(list + 16 + 4), get_byte_debug(list + 16 + 1));
  4346. for (int i = 0; i < 16; i++) {
  4347. console_out_f(_T("%02x"), get_byte_debug(list + 16 + i));
  4348. if (i < 15)
  4349. console_out_f(_T("."));
  4350. }
  4351. console_out_f(_T("\n"));
  4352. if ((type & 0x10)) {
  4353. uae_u8 diagarea[256];
  4354. uae_u16 nameoffset;
  4355. uaecptr rom = addr + rom_vector;
  4356. uae_u8 config = get_byte_debug(rom);
  4357. copyromdata(config, rom, 0, diagarea, 16);
  4358. nameoffset = (diagarea[8] << 8) | diagarea[9];
  4359. console_out_f(_T(" %02x %02x Size %04x Diag %04x Boot %04x Name %04x %04x %04x\n"),
  4360. diagarea[0], diagarea[1],
  4361. (diagarea[2] << 8) | diagarea[3],
  4362. (diagarea[4] << 8) | diagarea[5],
  4363. (diagarea[6] << 8) | diagarea[7],
  4364. nameoffset,
  4365. (diagarea[10] << 8) | diagarea[11],
  4366. (diagarea[12] << 8) | diagarea[13]);
  4367. if (nameoffset != 0 && nameoffset != 0xffff) {
  4368. copyromdata(config, rom, nameoffset, diagarea, 256);
  4369. diagarea[sizeof diagarea - 1] = 0;
  4370. TCHAR *str = au((char*)diagarea);
  4371. console_out_f(_T(" '%s'\n"), str);
  4372. xfree(str);
  4373. }
  4374. }
  4375. list = get_long_debug(list);
  4376. }
  4377. }
  4378. }
  4379. return;
  4380. } else if (c == 'R') { // residents
  4381. list = get_long_debug(execbase + 300);
  4382. while (list) {
  4383. uaecptr resident = get_long_debug (list);
  4384. if (!resident)
  4385. break;
  4386. if (resident & 0x80000000) {
  4387. console_out_f (_T("-> %08X\n"), resident & 0x7fffffff);
  4388. list = resident & 0x7fffffff;
  4389. continue;
  4390. }
  4391. uae_u8 *addr;
  4392. addr = get_real_address_debug(get_long_debug (resident + 14));
  4393. TCHAR *name1 = addr ? au ((char*)addr) : au("<null>");
  4394. my_trim (name1);
  4395. addr = get_real_address_debug(get_long_debug (resident + 18));
  4396. TCHAR *name2 = addr ? au ((char*)addr) : au("<null>");
  4397. my_trim (name2);
  4398. console_out_f (_T("%08X %08X: %02X %3d %02X %+3.3d '%s' ('%s')\n"),
  4399. list, resident,
  4400. get_byte_debug (resident + 10), get_byte_debug (resident + 11),
  4401. get_byte_debug (resident + 12), (uae_s8)get_byte_debug (resident + 13),
  4402. name1, name2);
  4403. xfree (name2);
  4404. xfree (name1);
  4405. list += 4;
  4406. }
  4407. return;
  4408. } else if (c == 'f' || c== 'F') { // filesystem.resource
  4409. uaecptr fs = get_base ("FileSystem.resource", 336);
  4410. if (fs) {
  4411. static const TCHAR *fsnames[] = {
  4412. _T("DosType"),
  4413. _T("Version"),
  4414. _T("PatchFlags"),
  4415. _T("Type"),
  4416. _T("Task"),
  4417. _T("Lock"),
  4418. _T("Handler"),
  4419. _T("StackSize"),
  4420. _T("Priority"),
  4421. _T("Startup"),
  4422. _T("SegList"),
  4423. _T("GlobalVec"),
  4424. NULL
  4425. };
  4426. uae_u8 *addr = get_real_address_debug(get_long_debug (fs + 14));
  4427. TCHAR *name = addr ? au ((char*)addr) : au ("<null>");
  4428. my_trim (name);
  4429. console_out_f (_T("%08x: '%s'\n"), fs, name);
  4430. xfree (name);
  4431. node = get_long_debug (fs + 18);
  4432. while (get_long_debug (node)) {
  4433. TCHAR *name = au ((char*)get_real_address_debug(get_long_debug (node + 10)));
  4434. my_trim (name);
  4435. console_out_f (_T("%08x: '%s'\n"), node, name);
  4436. xfree (name);
  4437. for (int i = 0; fsnames[i]; i++) {
  4438. uae_u32 v = get_long_debug (node + 14 + i * 4);
  4439. console_out_f (_T("%16s = %08x %d\n"), fsnames[i], v, v);
  4440. }
  4441. console_out_f (_T("\n"));
  4442. node = get_long_debug (node);
  4443. }
  4444. } else {
  4445. console_out_f (_T("FileSystem.resource not found.\n"));
  4446. }
  4447. return;
  4448. } else if (c == 'm' || c == 'M') { // memory
  4449. list = execbase + 322;
  4450. node = get_long_debug (list);
  4451. while (get_long_debug (node)) {
  4452. TCHAR *name = au ((char*)get_real_address_debug(get_long_debug (node + 10)));
  4453. uae_u16 v = get_word_debug (node + 8);
  4454. console_out_f (_T("%08x %d %d %s\n"), node, (int)((v >> 8) & 0xff), (uae_s8)(v & 0xff), name);
  4455. xfree (name);
  4456. console_out_f (_T("Attributes %04x First %08x Lower %08x Upper %08x Free %d\n"),
  4457. get_word_debug (node + 14), get_long_debug (node + 16), get_long_debug (node + 20),
  4458. get_long_debug (node + 24), get_long_debug (node + 28));
  4459. uaecptr mc = get_long_debug (node + 16);
  4460. while (mc) {
  4461. uae_u32 mc1 = get_long_debug (mc);
  4462. uae_u32 mc2 = get_long_debug (mc + 4);
  4463. console_out_f (_T(" %08x: %08x-%08x,%08x,%08x (%d)\n"), mc, mc, mc + mc2, mc1, mc2, mc2);
  4464. mc = mc1;
  4465. }
  4466. console_out_f (_T("\n"));
  4467. node = get_long_debug (node);
  4468. }
  4469. return;
  4470. }
  4471. bool full = false;
  4472. switch (c)
  4473. {
  4474. case 'r': // resources
  4475. list = execbase + 336;
  4476. break;
  4477. case 'd': // devices
  4478. list = execbase + 350;
  4479. full = true;
  4480. break;
  4481. case 'l': // libraries
  4482. list = execbase + 378;
  4483. full = true;
  4484. break;
  4485. case 'p': // ports
  4486. list = execbase + 392;
  4487. break;
  4488. case 's': // semaphores
  4489. list = execbase + 532;
  4490. break;
  4491. }
  4492. if (list == 0)
  4493. return;
  4494. node = get_long_debug (list);
  4495. while (get_long_debug (node)) {
  4496. TCHAR *name = au ((char*)get_real_address_debug(get_long_debug (node + 10)));
  4497. uae_u16 v = get_word_debug (node + 8);
  4498. console_out_f (_T("%08x %d %d"), node, (int)((v >> 8) & 0xff), (uae_s8)(v & 0xff));
  4499. if (full) {
  4500. uae_u16 ver = get_word_debug(node + 20);
  4501. uae_u16 rev = get_word_debug(node + 22);
  4502. uae_u32 op = get_word_debug(node + 32);
  4503. console_out_f(_T(" %d.%d %d"), ver, rev, op);
  4504. }
  4505. console_out_f(_T(" %s"), name);
  4506. xfree (name);
  4507. if (full) {
  4508. uaecptr idstring = get_long_debug(node + 24);
  4509. if (idstring) {
  4510. name = au((char*)get_real_address_debug(idstring));
  4511. console_out_f(_T(" (%s)"), name);
  4512. xfree(name);
  4513. }
  4514. }
  4515. console_out_f(_T("\n"));
  4516. node = get_long_debug (node);
  4517. }
  4518. }
  4519. static int debug_vpos = -1;
  4520. static int debug_hpos = -1;
  4521. static void breakfunc(uae_u32 v)
  4522. {
  4523. write_log(_T("Cycle breakpoint hit\n"));
  4524. debugging = 1;
  4525. debug_vpos = -1;
  4526. debug_hpos = -1;
  4527. set_special(SPCFLAG_BRK);
  4528. }
  4529. void debug_hsync(void)
  4530. {
  4531. if (debug_vpos < 0) {
  4532. return;
  4533. }
  4534. if (debug_vpos != vpos) {
  4535. return;
  4536. }
  4537. if (debug_hpos <= 0) {
  4538. breakfunc(0);
  4539. } else {
  4540. if (current_hpos() < debug_hpos) {
  4541. event2_newevent_x(-1, debug_hpos - current_hpos(), 0, breakfunc);
  4542. } else {
  4543. breakfunc(0);
  4544. }
  4545. }
  4546. }
  4547. static int cycle_breakpoint(TCHAR **c)
  4548. {
  4549. TCHAR nc = (*c)[0];
  4550. next_char(c);
  4551. if (more_params(c)) {
  4552. int count = readint(c);
  4553. if (nc == 's') {
  4554. if (more_params(c)) {
  4555. debug_vpos = count;
  4556. debug_hpos = readint(c);
  4557. if (debug_vpos == vpos && debug_hpos > current_hpos()) {
  4558. debug_vpos = -1;
  4559. count = debug_hpos - current_hpos();
  4560. debug_hpos = -1;
  4561. } else {
  4562. return 1;
  4563. }
  4564. } else {
  4565. count *= maxhpos;
  4566. }
  4567. }
  4568. if (count > 0) {
  4569. event2_newevent_x(-1, count, 0, breakfunc);
  4570. }
  4571. return 1;
  4572. }
  4573. return 0;
  4574. }
  4575. #if 0
  4576. static int trace_same_insn_count;
  4577. static uae_u8 trace_insn_copy[10];
  4578. static struct regstruct trace_prev_regs;
  4579. #endif
  4580. static uaecptr nextpc;
  4581. int instruction_breakpoint (TCHAR **c)
  4582. {
  4583. struct breakpoint_node *bpn;
  4584. int i;
  4585. if (more_params (c)) {
  4586. TCHAR nc = _totupper ((*c)[0]);
  4587. if (nc == 'O') {
  4588. // bpnum register operation value1 [mask value2]
  4589. next_char(c);
  4590. if (more_params(c)) {
  4591. int bpidx = readint(c);
  4592. if (more_params(c) && bpidx >= 0 && bpidx < BREAKPOINT_TOTAL) {
  4593. bpn = &bpnodes[bpidx];
  4594. int regid = getregidx(c);
  4595. if (regid >= 0) {
  4596. bpn->type = regid;
  4597. bpn->mask = 0xffffffff;
  4598. if (more_params(c)) {
  4599. int operid = getoperidx(c);
  4600. if (more_params(c) && operid >= 0) {
  4601. bpn->oper = operid;
  4602. bpn->value1 = readhex(c);
  4603. bpn->enabled = 1;
  4604. if (more_params(c)) {
  4605. bpn->mask = readhex(c);
  4606. if (more_params(c)) {
  4607. bpn->value2 = readhex(c);
  4608. }
  4609. }
  4610. console_out(_T("Breakpoint added.\n"));
  4611. }
  4612. }
  4613. }
  4614. }
  4615. }
  4616. return 0;
  4617. } else if (nc == 'I') {
  4618. uae_u16 opcodes[32];
  4619. next_char(c);
  4620. ignore_ws(c);
  4621. trace_param[1] = 0x10000;
  4622. trace_param[2] = 0x10000;
  4623. int w = m68k_asm(*c, opcodes, 0);
  4624. if (w > 0) {
  4625. trace_param[0] = opcodes[0];
  4626. if (w > 1) {
  4627. trace_param[1] = opcodes[1];
  4628. if (w > 2) {
  4629. trace_param[2] = opcodes[2];
  4630. }
  4631. }
  4632. } else {
  4633. if (more_params(c)) {
  4634. trace_param[0] = readhex(c);
  4635. if (more_params(c)) {
  4636. trace_param[1] = readhex(c);
  4637. }
  4638. if (more_params(c)) {
  4639. trace_param[2] = readhex(c);
  4640. }
  4641. } else {
  4642. trace_param[0] = 0x10000;
  4643. }
  4644. }
  4645. trace_mode = TRACE_MATCH_INS;
  4646. return 1;
  4647. } else if (nc == 'D' && (*c)[1] == 0) {
  4648. for (i = 0; i < BREAKPOINT_TOTAL; i++)
  4649. bpnodes[i].enabled = 0;
  4650. console_out(_T("All breakpoints removed.\n"));
  4651. return 0;
  4652. } else if (nc == 'R' && (*c)[1] == 0) {
  4653. if (more_params(c)) {
  4654. int bpnum = readint(c);
  4655. if (bpnum >= 0 && bpnum < BREAKPOINT_TOTAL) {
  4656. bpnodes[bpnum].enabled = 0;
  4657. console_out_f(_T("Breakpoint %d removed.\n"), bpnum);
  4658. }
  4659. }
  4660. return 0;
  4661. } else if (nc == 'L') {
  4662. int got = 0;
  4663. for (i = 0; i < BREAKPOINT_TOTAL; i++) {
  4664. bpn = &bpnodes[i];
  4665. if (!bpn->enabled)
  4666. continue;
  4667. console_out_f (_T("%d: %s %s %08x [%08x %08x]\n"), i, debugregs[bpn->type], debugoper[bpn->oper], bpn->value1, bpn->mask, bpn->value2);
  4668. got = 1;
  4669. }
  4670. if (!got)
  4671. console_out (_T("No breakpoints.\n"));
  4672. else
  4673. console_out (_T("\n"));
  4674. return 0;
  4675. }
  4676. trace_mode = TRACE_RANGE_PC;
  4677. trace_param[0] = readhex (c);
  4678. if (more_params (c)) {
  4679. trace_param[1] = readhex (c);
  4680. return 1;
  4681. } else {
  4682. for (i = 0; i < BREAKPOINT_TOTAL; i++) {
  4683. bpn = &bpnodes[i];
  4684. if (bpn->enabled && bpn->value1 == trace_param[0]) {
  4685. bpn->enabled = 0;
  4686. console_out (_T("Breakpoint removed.\n"));
  4687. trace_mode = 0;
  4688. return 0;
  4689. }
  4690. }
  4691. for (i = 0; i < BREAKPOINT_TOTAL; i++) {
  4692. bpn = &bpnodes[i];
  4693. if (bpn->enabled)
  4694. continue;
  4695. bpn->value1 = trace_param[0];
  4696. bpn->type = BREAKPOINT_REG_PC;
  4697. bpn->oper = BREAKPOINT_CMP_EQUAL;
  4698. bpn->enabled = 1;
  4699. console_out (_T("Breakpoint added.\n"));
  4700. trace_mode = 0;
  4701. break;
  4702. }
  4703. return 0;
  4704. }
  4705. }
  4706. trace_mode = TRACE_RAM_PC;
  4707. return 1;
  4708. }
  4709. static int process_breakpoint (TCHAR **c)
  4710. {
  4711. processptr = 0;
  4712. xfree (processname);
  4713. processname = NULL;
  4714. if (!more_params (c))
  4715. return 0;
  4716. if (**c == '\"') {
  4717. TCHAR pn[200];
  4718. next_string (c, pn, 200, 0);
  4719. processname = ua (pn);
  4720. } else {
  4721. processptr = readhex (c);
  4722. }
  4723. trace_mode = TRACE_CHECKONLY;
  4724. return 1;
  4725. }
  4726. static void saveloadmem (TCHAR **cc, bool save)
  4727. {
  4728. uae_u8 b;
  4729. uae_u32 src, src2;
  4730. int len, len2;
  4731. TCHAR *name;
  4732. FILE *fp;
  4733. if (!more_params (cc))
  4734. goto S_argh;
  4735. name = *cc;
  4736. while (**cc != '\0' && !isspace (**cc))
  4737. (*cc)++;
  4738. if (!isspace (**cc))
  4739. goto S_argh;
  4740. **cc = '\0';
  4741. (*cc)++;
  4742. if (!more_params (cc))
  4743. goto S_argh;
  4744. src2 = src = readhex (cc);
  4745. if (save) {
  4746. if (!more_params(cc))
  4747. goto S_argh;
  4748. }
  4749. len2 = len = -1;
  4750. if (more_params(cc)) {
  4751. len2 = len = readhex (cc);
  4752. }
  4753. fp = uae_tfopen (name, save ? _T("wb") : _T("rb"));
  4754. if (fp == NULL) {
  4755. console_out_f (_T("Couldn't open file '%s'.\n"), name);
  4756. return;
  4757. }
  4758. if (save) {
  4759. while (len > 0) {
  4760. b = get_byte_debug (src);
  4761. src++;
  4762. len--;
  4763. if (fwrite (&b, 1, 1, fp) != 1) {
  4764. console_out (_T("Error writing file.\n"));
  4765. break;
  4766. }
  4767. }
  4768. if (len == 0)
  4769. console_out_f (_T("Wrote %08X - %08X (%d bytes) to '%s'.\n"),
  4770. src2, src2 + len2, len2, name);
  4771. } else {
  4772. len2 = 0;
  4773. while (len != 0) {
  4774. if (fread(&b, 1, 1, fp) != 1) {
  4775. if (len > 0)
  4776. console_out (_T("Unexpected end of file.\n"));
  4777. len = 0;
  4778. break;
  4779. }
  4780. put_byte (src, b);
  4781. src++;
  4782. if (len > 0)
  4783. len--;
  4784. len2++;
  4785. }
  4786. if (len == 0)
  4787. console_out_f (_T("Read %08X - %08X (%d bytes) to '%s'.\n"),
  4788. src2, src2 + len2, len2, name);
  4789. }
  4790. fclose (fp);
  4791. return;
  4792. S_argh:
  4793. console_out (_T("Command needs more arguments!\n"));
  4794. }
  4795. static void searchmem (TCHAR **cc)
  4796. {
  4797. int i, sslen, got, val, stringmode;
  4798. uae_u8 ss[256];
  4799. uae_u32 addr, endaddr;
  4800. TCHAR nc;
  4801. got = 0;
  4802. sslen = 0;
  4803. stringmode = 0;
  4804. ignore_ws (cc);
  4805. if (**cc == '"') {
  4806. stringmode = 1;
  4807. (*cc)++;
  4808. while (**cc != '"' && **cc != 0) {
  4809. ss[sslen++] = tolower (**cc);
  4810. (*cc)++;
  4811. }
  4812. if (**cc != 0)
  4813. (*cc)++;
  4814. } else {
  4815. for (;;) {
  4816. if (**cc == 32 || **cc == 0)
  4817. break;
  4818. nc = _totupper (next_char (cc));
  4819. if (isspace (nc))
  4820. break;
  4821. if (isdigit(nc))
  4822. val = nc - '0';
  4823. else
  4824. val = nc - 'A' + 10;
  4825. if (val < 0 || val > 15)
  4826. return;
  4827. val *= 16;
  4828. if (**cc == 32 || **cc == 0)
  4829. break;
  4830. nc = _totupper (next_char (cc));
  4831. if (isspace (nc))
  4832. break;
  4833. if (isdigit(nc))
  4834. val += nc - '0';
  4835. else
  4836. val += nc - 'A' + 10;
  4837. if (val < 0 || val > 255)
  4838. return;
  4839. ss[sslen++] = (uae_u8)val;
  4840. }
  4841. }
  4842. if (sslen == 0)
  4843. return;
  4844. ignore_ws (cc);
  4845. addr = 0xffffffff;
  4846. endaddr = lastaddr ();
  4847. if (more_params (cc)) {
  4848. addr = readhex (cc);
  4849. addr--;
  4850. if (more_params(cc)) {
  4851. endaddr = readhex(cc);
  4852. }
  4853. }
  4854. console_out_f (_T("Searching from %08X to %08X..\n"), addr + 1, endaddr);
  4855. while ((addr = nextaddr (addr, endaddr, NULL, true)) != 0xffffffff) {
  4856. if (addr == endaddr)
  4857. break;
  4858. for (i = 0; i < sslen; i++) {
  4859. uae_u8 b = get_byte_debug (addr + i);
  4860. if (stringmode) {
  4861. if (tolower (b) != ss[i])
  4862. break;
  4863. } else {
  4864. if (b != ss[i])
  4865. break;
  4866. }
  4867. }
  4868. if (i == sslen) {
  4869. got++;
  4870. console_out_f (_T(" %08X"), addr);
  4871. if (got > 100) {
  4872. console_out (_T("\nMore than 100 results, aborting.."));
  4873. break;
  4874. }
  4875. }
  4876. if (iscancel (65536)) {
  4877. console_out_f (_T("Aborted at %08X\n"), addr);
  4878. break;
  4879. }
  4880. }
  4881. if (!got)
  4882. console_out (_T("nothing found"));
  4883. console_out (_T("\n"));
  4884. }
  4885. static int staterecorder (TCHAR **cc)
  4886. {
  4887. #if 0
  4888. TCHAR nc;
  4889. if (!more_params (cc)) {
  4890. if (savestate_dorewind (1)) {
  4891. debug_rewind = 1;
  4892. return 1;
  4893. }
  4894. return 0;
  4895. }
  4896. nc = next_char (cc);
  4897. if (nc == 'l') {
  4898. savestate_listrewind ();
  4899. return 0;
  4900. }
  4901. #endif
  4902. return 0;
  4903. }
  4904. static int debugtest_modes[DEBUGTEST_MAX];
  4905. static const TCHAR *debugtest_names[] = {
  4906. _T("Blitter"), _T("Keyboard"), _T("Floppy")
  4907. };
  4908. void debugtest (enum debugtest_item di, const TCHAR *format, ...)
  4909. {
  4910. va_list parms;
  4911. TCHAR buffer[1000];
  4912. if (!debugtest_modes[di])
  4913. return;
  4914. va_start (parms, format);
  4915. _vsntprintf (buffer, 1000 - 1, format, parms);
  4916. va_end (parms);
  4917. write_log (_T("%s PC=%08X: %s\n"), debugtest_names[di], M68K_GETPC, buffer);
  4918. if (debugtest_modes[di] == 2)
  4919. activate_debugger_new();
  4920. }
  4921. static void debugtest_set (TCHAR **inptr)
  4922. {
  4923. int i, val, val2;
  4924. ignore_ws (inptr);
  4925. val2 = 1;
  4926. if (!more_params (inptr)) {
  4927. for (i = 0; i < DEBUGTEST_MAX; i++)
  4928. debugtest_modes[i] = 0;
  4929. console_out (_T("All debugtests disabled\n"));
  4930. return;
  4931. }
  4932. val = readint (inptr);
  4933. if (more_params (inptr)) {
  4934. val2 = readint (inptr);
  4935. if (val2 > 0)
  4936. val2 = 2;
  4937. }
  4938. if (val < 0) {
  4939. for (i = 0; i < DEBUGTEST_MAX; i++)
  4940. debugtest_modes[i] = val2;
  4941. console_out (_T("All debugtests enabled\n"));
  4942. return;
  4943. }
  4944. if (val >= 0 && val < DEBUGTEST_MAX) {
  4945. if (debugtest_modes[val])
  4946. debugtest_modes[val] = 0;
  4947. else
  4948. debugtest_modes[val] = val2;
  4949. console_out_f (_T("Debugtest '%s': %s. break = %s\n"),
  4950. debugtest_names[val], debugtest_modes[val] ? _T("on") :_T("off"), val2 == 2 ? _T("on") : _T("off"));
  4951. }
  4952. }
  4953. static void debug_sprite (TCHAR **inptr)
  4954. {
  4955. uaecptr saddr, addr, addr2;
  4956. int xpos, xpos_ecs;
  4957. int ypos, ypos_ecs;
  4958. int ypose, ypose_ecs;
  4959. int attach;
  4960. uae_u64 w1, w2, ww1, ww2;
  4961. int size = 1, width;
  4962. int ecs, sh10;
  4963. int y, i;
  4964. TCHAR tmp[80];
  4965. int max = 2;
  4966. addr2 = 0;
  4967. ignore_ws (inptr);
  4968. addr = readhex (inptr);
  4969. ignore_ws (inptr);
  4970. if (more_params (inptr))
  4971. size = readhex (inptr);
  4972. if (size != 1 && size != 2 && size != 4) {
  4973. addr2 = size;
  4974. ignore_ws (inptr);
  4975. if (more_params (inptr))
  4976. size = readint (inptr);
  4977. if (size != 1 && size != 2 && size != 4)
  4978. size = 1;
  4979. }
  4980. for (;;) {
  4981. ecs = 0;
  4982. sh10 = 0;
  4983. saddr = addr;
  4984. width = size * 16;
  4985. w1 = get_word_debug (addr);
  4986. w2 = get_word_debug (addr + size * 2);
  4987. console_out_f (_T(" %06X "), addr);
  4988. for (i = 0; i < size * 2; i++)
  4989. console_out_f (_T("%04X "), get_word_debug (addr + i * 2));
  4990. console_out_f (_T("\n"));
  4991. ypos = w1 >> 8;
  4992. xpos = w1 & 255;
  4993. ypose = w2 >> 8;
  4994. attach = (w2 & 0x80) ? 1 : 0;
  4995. if (w2 & 4)
  4996. ypos |= 256;
  4997. if (w2 & 2)
  4998. ypose |= 256;
  4999. ypos_ecs = ypos;
  5000. ypose_ecs = ypose;
  5001. if (w2 & 0x40)
  5002. ypos_ecs |= 512;
  5003. if (w2 & 0x20)
  5004. ypose_ecs |= 512;
  5005. xpos <<= 1;
  5006. if (w2 & 0x01)
  5007. xpos |= 1;
  5008. xpos_ecs = xpos << 2;
  5009. if (w2 & 0x10)
  5010. xpos_ecs |= 2;
  5011. if (w2 & 0x08)
  5012. xpos_ecs |= 1;
  5013. if (w2 & (0x40 | 0x20 | 0x10 | 0x08))
  5014. ecs = 1;
  5015. if (w1 & 0x80)
  5016. sh10 = 1;
  5017. if (ypose < ypos)
  5018. ypose += 256;
  5019. for (y = ypos; y < ypose; y++) {
  5020. int x;
  5021. addr += size * 4;
  5022. if (addr2)
  5023. addr2 += size * 4;
  5024. if (size == 1) {
  5025. w1 = get_word_debug (addr);
  5026. w2 = get_word_debug (addr + 2);
  5027. if (addr2) {
  5028. ww1 = get_word_debug (addr2);
  5029. ww2 = get_word_debug (addr2 + 2);
  5030. }
  5031. } else if (size == 2) {
  5032. w1 = get_long_debug (addr);
  5033. w2 = get_long_debug (addr + 4);
  5034. if (addr2) {
  5035. ww1 = get_long_debug (addr2);
  5036. ww2 = get_long_debug (addr2 + 4);
  5037. }
  5038. } else if (size == 4) {
  5039. w1 = get_long_debug (addr + 0);
  5040. w2 = get_long_debug (addr + 8);
  5041. w1 <<= 32;
  5042. w2 <<= 32;
  5043. w1 |= get_long_debug (addr + 4);
  5044. w2 |= get_long_debug (addr + 12);
  5045. if (addr2) {
  5046. ww1 = get_long_debug (addr2 + 0);
  5047. ww2 = get_long_debug (addr2 + 8);
  5048. ww1 <<= 32;
  5049. ww2 <<= 32;
  5050. ww1 |= get_long_debug (addr2 + 4);
  5051. ww2 |= get_long_debug (addr2 + 12);
  5052. }
  5053. }
  5054. width = size * 16;
  5055. for (x = 0; x < width; x++) {
  5056. int v1 = w1 & 1;
  5057. int v2 = w2 & 1;
  5058. int v = v1 * 2 + v2;
  5059. w1 >>= 1;
  5060. w2 >>= 1;
  5061. if (addr2) {
  5062. int vv1 = ww1 & 1;
  5063. int vv2 = ww2 & 1;
  5064. int vv = vv1 * 2 + vv2;
  5065. vv1 >>= 1;
  5066. vv2 >>= 1;
  5067. v *= 4;
  5068. v += vv;
  5069. tmp[width - (x + 1)] = v >= 10 ? 'A' + v - 10 : v + '0';
  5070. } else {
  5071. tmp[width - (x + 1)] = v + '0';
  5072. }
  5073. }
  5074. tmp[width] = 0;
  5075. console_out_f (_T("%3d %06X %s\n"), y, addr, tmp);
  5076. }
  5077. console_out_f (_T("Sprite address %08X, width = %d\n"), saddr, size * 16);
  5078. console_out_f (_T("OCS: StartX=%d StartY=%d EndY=%d\n"), xpos, ypos, ypose);
  5079. console_out_f (_T("ECS: StartX=%d (%d.%d) StartY=%d EndY=%d%s\n"), xpos_ecs, xpos_ecs / 4, xpos_ecs & 3, ypos_ecs, ypose_ecs, ecs ? _T(" (*)") : _T(""));
  5080. console_out_f (_T("Attach: %d. AGA SSCAN/SH10 bit: %d\n"), attach, sh10);
  5081. addr += size * 4;
  5082. if (get_word_debug (addr) == 0 && get_word_debug (addr + size * 4) == 0)
  5083. break;
  5084. max--;
  5085. if (max <= 0)
  5086. break;
  5087. }
  5088. }
  5089. int debug_write_memory_16 (uaecptr addr, uae_u16 v)
  5090. {
  5091. addrbank *ad;
  5092. ad = &get_mem_bank (addr);
  5093. if (ad) {
  5094. ad->wput (addr, v);
  5095. return 1;
  5096. }
  5097. return -1;
  5098. }
  5099. int debug_write_memory_8 (uaecptr addr, uae_u8 v)
  5100. {
  5101. addrbank *ad;
  5102. ad = &get_mem_bank (addr);
  5103. if (ad) {
  5104. ad->bput (addr, v);
  5105. return 1;
  5106. }
  5107. return -1;
  5108. }
  5109. int debug_peek_memory_16 (uaecptr addr)
  5110. {
  5111. addrbank *ad;
  5112. ad = &get_mem_bank (addr);
  5113. if (ad->flags & (ABFLAG_RAM | ABFLAG_ROM | ABFLAG_ROMIN | ABFLAG_SAFE))
  5114. return ad->wget (addr);
  5115. if (ad == &custom_bank) {
  5116. addr &= 0x1fe;
  5117. return (ar_custom[addr + 0] << 8) | ar_custom[addr + 1];
  5118. }
  5119. return -1;
  5120. }
  5121. int debug_read_memory_16 (uaecptr addr)
  5122. {
  5123. addrbank *ad;
  5124. ad = &get_mem_bank (addr);
  5125. if (ad)
  5126. return ad->wget (addr);
  5127. return -1;
  5128. }
  5129. int debug_read_memory_8 (uaecptr addr)
  5130. {
  5131. addrbank *ad;
  5132. ad = &get_mem_bank (addr);
  5133. if (ad)
  5134. return ad->bget (addr);
  5135. return -1;
  5136. }
  5137. static void disk_debug (TCHAR **inptr)
  5138. {
  5139. TCHAR parm[10];
  5140. int i;
  5141. if (**inptr == 'd') {
  5142. (*inptr)++;
  5143. ignore_ws (inptr);
  5144. disk_debug_logging = readint (inptr);
  5145. console_out_f (_T("Disk logging level %d\n"), disk_debug_logging);
  5146. return;
  5147. }
  5148. disk_debug_mode = 0;
  5149. disk_debug_track = -1;
  5150. ignore_ws (inptr);
  5151. if (!next_string (inptr, parm, sizeof (parm) / sizeof (TCHAR), 1))
  5152. goto end;
  5153. for (i = 0; i < _tcslen(parm); i++) {
  5154. if (parm[i] == 'R')
  5155. disk_debug_mode |= DISK_DEBUG_DMA_READ;
  5156. if (parm[i] == 'W')
  5157. disk_debug_mode |= DISK_DEBUG_DMA_WRITE;
  5158. if (parm[i] == 'P')
  5159. disk_debug_mode |= DISK_DEBUG_PIO;
  5160. }
  5161. if (more_params(inptr))
  5162. disk_debug_track = readint (inptr);
  5163. if (disk_debug_track < 0 || disk_debug_track > 2 * 83)
  5164. disk_debug_track = -1;
  5165. if (disk_debug_logging == 0)
  5166. disk_debug_logging = 1;
  5167. end:
  5168. console_out_f (_T("Disk breakpoint mode %c%c%c track %d\n"),
  5169. disk_debug_mode & DISK_DEBUG_DMA_READ ? 'R' : '-',
  5170. disk_debug_mode & DISK_DEBUG_DMA_WRITE ? 'W' : '-',
  5171. disk_debug_mode & DISK_DEBUG_PIO ? 'P' : '-',
  5172. disk_debug_track);
  5173. }
  5174. static void find_ea (TCHAR **inptr)
  5175. {
  5176. uae_u32 ea, sea, dea;
  5177. uaecptr addr, end, end2;
  5178. int hits = 0;
  5179. addr = 0xffffffff;
  5180. end = lastaddr ();
  5181. ea = readhex (inptr);
  5182. if (more_params(inptr)) {
  5183. addr = readhex (inptr);
  5184. addr--;
  5185. if (more_params(inptr)) {
  5186. end = readhex(inptr);
  5187. }
  5188. }
  5189. console_out_f (_T("Searching from %08X to %08X\n"), addr + 1, end);
  5190. end2 = 0;
  5191. while((addr = nextaddr (addr, end, &end2, true)) != 0xffffffff) {
  5192. if ((addr & 1) == 0 && addr + 6 <= end2) {
  5193. sea = 0xffffffff;
  5194. dea = 0xffffffff;
  5195. m68k_disasm_ea (addr, NULL, 1, &sea, &dea, 0xffffffff);
  5196. if (ea == sea || ea == dea) {
  5197. m68k_disasm (addr, NULL, 0xffffffff, 1);
  5198. hits++;
  5199. if (hits > 100) {
  5200. console_out_f (_T("Too many hits. End addr = %08X\n"), addr);
  5201. break;
  5202. }
  5203. }
  5204. if (iscancel (65536)) {
  5205. console_out_f (_T("Aborted at %08X\n"), addr);
  5206. break;
  5207. }
  5208. }
  5209. }
  5210. }
  5211. static void m68k_modify (TCHAR **inptr)
  5212. {
  5213. uae_u32 v;
  5214. TCHAR parm[10];
  5215. TCHAR c1, c2;
  5216. int i;
  5217. if (!next_string (inptr, parm, sizeof (parm) / sizeof (TCHAR), 1))
  5218. return;
  5219. c1 = _totupper (parm[0]);
  5220. c2 = 99;
  5221. if (c1 == 'A' || c1 == 'D' || c1 == 'P') {
  5222. c2 = _totupper (parm[1]);
  5223. if (isdigit (c2))
  5224. c2 -= '0';
  5225. else
  5226. c2 = 99;
  5227. }
  5228. v = readhex (inptr);
  5229. if (c1 == 'A' && c2 < 8)
  5230. regs.regs[8 + c2] = v;
  5231. else if (c1 == 'D' && c2 < 8)
  5232. regs.regs[c2] = v;
  5233. else if (c1 == 'P' && c2 == 0)
  5234. regs.irc = v;
  5235. else if (c1 == 'P' && c2 == 1)
  5236. regs.ir = v;
  5237. else if (!_tcscmp (parm, _T("SR"))) {
  5238. regs.sr = v;
  5239. MakeFromSR ();
  5240. } else if (!_tcscmp (parm, _T("CCR"))) {
  5241. regs.sr = (regs.sr & ~31) | (v & 31);
  5242. MakeFromSR ();
  5243. } else if (!_tcscmp (parm, _T("USP"))) {
  5244. regs.usp = v;
  5245. } else if (!_tcscmp (parm, _T("ISP"))) {
  5246. regs.isp = v;
  5247. } else if (!_tcscmp (parm, _T("PC"))) {
  5248. m68k_setpc (v);
  5249. fill_prefetch ();
  5250. } else {
  5251. for (i = 0; m2cregs[i].regname; i++) {
  5252. if (!_tcscmp (parm, m2cregs[i].regname))
  5253. val_move2c2 (m2cregs[i].regno, v);
  5254. }
  5255. }
  5256. }
  5257. static void ppc_disasm(uaecptr addr, uaecptr *nextpc, int cnt)
  5258. {
  5259. PPCD_CB disa;
  5260. while(cnt-- > 0) {
  5261. uae_u32 instr = get_long_debug(addr);
  5262. disa.pc = addr;
  5263. disa.instr = instr;
  5264. PPCDisasm(&disa);
  5265. TCHAR *mnemo = au(disa.mnemonic);
  5266. TCHAR *ops = au(disa.operands);
  5267. console_out_f(_T("%08X %08X %-12s%-30s\n"), addr, instr, mnemo, ops);
  5268. xfree(ops);
  5269. xfree(mnemo);
  5270. addr += 4;
  5271. }
  5272. if (nextpc)
  5273. *nextpc = addr;
  5274. }
  5275. static void dma_disasm(int frames, int vp, int hp, int frames_end, int vp_end, int hp_end)
  5276. {
  5277. if (!dma_record[0] || frames < 0 || vp < 0 || hp < 0)
  5278. return;
  5279. for (;;) {
  5280. struct dma_rec *dr = NULL;
  5281. if (dma_record_frame[0] == frames)
  5282. dr = &dma_record[0][vp * NR_DMA_REC_HPOS + hp];
  5283. else if (dma_record_frame[1] == frames)
  5284. dr = &dma_record[1][vp * NR_DMA_REC_HPOS + hp];
  5285. if (!dr)
  5286. return;
  5287. TCHAR l1[16], l2[16], l3[16], l4[16];
  5288. if (get_record_dma_info(dr, hp, vp, 0, l1, l2, l3, l4, NULL)) {
  5289. console_out_f(_T(" - %02X %s %s %s\n"), hp, l2, l3, l4);
  5290. }
  5291. hp++;
  5292. if (hp >= maxhpos) {
  5293. hp = 0;
  5294. vp++;
  5295. if (vp >= maxvpos + 1) {
  5296. vp = 0;
  5297. frames++;
  5298. break;
  5299. }
  5300. }
  5301. if ((frames == frames_end && vp == vp_end && hp == hp_end) || frames > frames_end)
  5302. break;
  5303. if (vp_end < 0 || hp_end < 0 || frames_end < 0)
  5304. break;
  5305. }
  5306. }
  5307. static uaecptr nxdis, nxmem, asmaddr;
  5308. static bool ppcmode, asmmode;
  5309. static bool debug_line (TCHAR *input)
  5310. {
  5311. TCHAR cmd, *inptr;
  5312. uaecptr addr;
  5313. inptr = input;
  5314. if (asmmode) {
  5315. if (more_params(&inptr)) {
  5316. if (!_tcsicmp(inptr, _T("x"))) {
  5317. asmmode = false;
  5318. return false;
  5319. }
  5320. uae_u16 asmout[16];
  5321. int inss = m68k_asm(inptr, asmout, asmaddr);
  5322. if (inss > 0) {
  5323. for (int i = 0; i < inss; i++) {
  5324. put_word(asmaddr + i * 2, asmout[i]);
  5325. }
  5326. m68k_disasm(asmaddr, &nxdis, 0xffffffff, 1);
  5327. asmaddr = nxdis;
  5328. }
  5329. console_out_f(_T("%08X "), asmaddr);
  5330. return false;
  5331. } else {
  5332. asmmode = false;
  5333. return false;
  5334. }
  5335. }
  5336. cmd = next_char (&inptr);
  5337. switch (cmd)
  5338. {
  5339. case 'I':
  5340. if (more_params (&inptr)) {
  5341. static int recursive;
  5342. if (!recursive) {
  5343. recursive++;
  5344. handle_custom_event(inptr, 0);
  5345. device_check_config();
  5346. recursive--;
  5347. }
  5348. }
  5349. break;
  5350. case 'c': dumpcia (); dumpdisk (_T("DEBUG")); dumpcustom (); break;
  5351. case 'i':
  5352. {
  5353. if (*inptr == 'l') {
  5354. next_char (&inptr);
  5355. if (more_params (&inptr)) {
  5356. debug_illegal_mask = readhex (&inptr);
  5357. if (more_params(&inptr))
  5358. debug_illegal_mask |= ((uae_u64)readhex(&inptr)) << 32;
  5359. } else {
  5360. debug_illegal_mask = debug_illegal ? 0 : -1;
  5361. debug_illegal_mask &= ~((uae_u64)255 << 24); // mask interrupts
  5362. }
  5363. console_out_f (_T("Exception breakpoint mask: %08X %08X\n"), (uae_u32)(debug_illegal_mask >> 32), (uae_u32)debug_illegal_mask);
  5364. debug_illegal = debug_illegal_mask ? 1 : 0;
  5365. } else {
  5366. addr = 0xffffffff;
  5367. if (more_params (&inptr))
  5368. addr = readhex (&inptr);
  5369. dump_vectors (addr);
  5370. }
  5371. break;
  5372. }
  5373. case 'e':
  5374. {
  5375. bool aga = tolower(*inptr) == 'a';
  5376. if (aga)
  5377. next_char(&inptr);
  5378. bool ext = tolower(*inptr) == 'x';
  5379. dump_custom_regs(aga, ext);
  5380. }
  5381. break;
  5382. case 'r':
  5383. {
  5384. if (*inptr == 'c') {
  5385. next_char(&inptr);
  5386. m68k_dumpcache(*inptr == 'd');
  5387. } else if (*inptr == 's') {
  5388. if (*(inptr + 1) == 's')
  5389. debugmem_list_stackframe(true);
  5390. else
  5391. debugmem_list_stackframe(false);
  5392. } else if (more_params(&inptr)) {
  5393. m68k_modify(&inptr);
  5394. } else {
  5395. m68k_dumpstate(&nextpc, 0xffffffff);
  5396. }
  5397. }
  5398. break;
  5399. case 'D': deepcheatsearch (&inptr); break;
  5400. case 'C': cheatsearch (&inptr); break;
  5401. case 'W': writeintomem (&inptr); break;
  5402. case 'w': memwatch (&inptr); break;
  5403. case 'S': saveloadmem (&inptr, true); break;
  5404. case 'L': saveloadmem (&inptr, false); break;
  5405. case 's':
  5406. if (*inptr == 'e' && *(inptr + 1) == 'g') {
  5407. next_char(&inptr);
  5408. next_char(&inptr);
  5409. addr = 0xffffffff;
  5410. if (*inptr == 's') {
  5411. debugmem_list_segment(1, addr);
  5412. } else {
  5413. if (more_params(&inptr)) {
  5414. addr = readhex(&inptr);
  5415. }
  5416. debugmem_list_segment(0, addr);
  5417. }
  5418. } else if (*inptr == 'c') {
  5419. screenshot(-1, 1, 1);
  5420. } else if (*inptr == 'p') {
  5421. inptr++;
  5422. debug_sprite (&inptr);
  5423. } else if (*inptr == 'm') {
  5424. if (*(inptr + 1) == 'c') {
  5425. next_char (&inptr);
  5426. next_char (&inptr);
  5427. if (!smc_table)
  5428. smc_detect_init (&inptr);
  5429. else
  5430. smc_free ();
  5431. }
  5432. } else {
  5433. searchmem (&inptr);
  5434. }
  5435. break;
  5436. case 'a':
  5437. asmaddr = nxdis;
  5438. if (more_params(&inptr)) {
  5439. asmaddr = readhex(&inptr);
  5440. if (more_params(&inptr)) {
  5441. uae_u16 asmout[16];
  5442. int inss = m68k_asm(inptr, asmout, asmaddr);
  5443. if (inss > 0) {
  5444. for (int i = 0; i < inss; i++) {
  5445. put_word(asmaddr + i * 2, asmout[i]);
  5446. }
  5447. m68k_disasm(asmaddr, &nxdis, 1, 0xffffffff);
  5448. asmaddr = nxdis;
  5449. return false;
  5450. }
  5451. }
  5452. }
  5453. asmmode = true;
  5454. console_out_f(_T("%08X "), asmaddr);
  5455. break;
  5456. case 'd':
  5457. {
  5458. if (*inptr == 'i') {
  5459. next_char (&inptr);
  5460. disk_debug (&inptr);
  5461. } else if (*inptr == 'j') {
  5462. inptr++;
  5463. inputdevice_logging = 1 | 2;
  5464. if (more_params (&inptr))
  5465. inputdevice_logging = readint (&inptr);
  5466. console_out_f (_T("Input logging level %d\n"), inputdevice_logging);
  5467. } else if (*inptr == 'm') {
  5468. memory_map_dump_2 (0);
  5469. } else if (*inptr == 't') {
  5470. next_char (&inptr);
  5471. debugtest_set (&inptr);
  5472. #ifdef _WIN32
  5473. } else if (*inptr == 'g') {
  5474. extern void update_disassembly (uae_u32);
  5475. next_char (&inptr);
  5476. if (more_params (&inptr))
  5477. update_disassembly (readhex (&inptr));
  5478. #endif
  5479. } else {
  5480. uae_u32 daddr;
  5481. int count;
  5482. if (*inptr == 'p' && inptr[1] == 'p' && inptr[2] == 'c') {
  5483. ppcmode = true;
  5484. next_char(&inptr);
  5485. } else if(*inptr == 'o') {
  5486. ppcmode = false;
  5487. next_char(&inptr);
  5488. }
  5489. if (more_params (&inptr))
  5490. daddr = readhex (&inptr);
  5491. else
  5492. daddr = nxdis;
  5493. if (more_params (&inptr))
  5494. count = readhex (&inptr);
  5495. else
  5496. count = 10;
  5497. if (ppcmode) {
  5498. ppc_disasm(daddr, &nxdis, count);
  5499. } else {
  5500. m68k_disasm (daddr, &nxdis, 0xffffffff, count);
  5501. }
  5502. }
  5503. }
  5504. break;
  5505. case 'T':
  5506. if (inptr[0] == 'L')
  5507. debugger_scan_libraries();
  5508. else if (inptr[0] == 't' || inptr[0] == 0)
  5509. show_exec_tasks ();
  5510. else
  5511. show_exec_lists (&inptr[0]);
  5512. break;
  5513. case 't':
  5514. no_trace_exceptions = 0;
  5515. debug_cycles();
  5516. trace_param[0] = trace_param[1] = 0;
  5517. if (*inptr == 't') {
  5518. no_trace_exceptions = 1;
  5519. inptr++;
  5520. }
  5521. if (*inptr == 'r') {
  5522. // break when PC in debugmem
  5523. if (debugmem_get_range(&trace_param[0], &trace_param[1])) {
  5524. trace_mode = TRACE_RANGE_PC;
  5525. return true;
  5526. }
  5527. } else if (*inptr == 's') {
  5528. if (*(inptr + 1) == 'e') {
  5529. debugmem_enable_stackframe(true);
  5530. } else if (*(inptr + 1) == 'd') {
  5531. debugmem_enable_stackframe(false);
  5532. } else if (*(inptr + 1) == 'p') {
  5533. if (debugmem_break_stack_pop()) {
  5534. debugger_active = 0;
  5535. return true;
  5536. }
  5537. } else {
  5538. if (debugmem_break_stack_pop()) {
  5539. debugger_active = 0;
  5540. return true;
  5541. }
  5542. }
  5543. } else if (*inptr == 'l') {
  5544. // skip next source line
  5545. if (debugmem_isactive()) {
  5546. trace_mode = TRACE_SKIP_LINE;
  5547. trace_param[0] = 1;
  5548. trace_param[1] = debugmem_get_sourceline(M68K_GETPC, NULL, 0);
  5549. return true;
  5550. }
  5551. } else {
  5552. if (more_params(&inptr))
  5553. trace_param[0] = readint(&inptr);
  5554. if (trace_param[0] <= 0 || trace_param[0] > 10000)
  5555. trace_param[0] = 1;
  5556. trace_mode = TRACE_SKIP_INS;
  5557. exception_debugging = 1;
  5558. return true;
  5559. }
  5560. break;
  5561. case 'z':
  5562. trace_mode = TRACE_MATCH_PC;
  5563. trace_param[0] = nextpc;
  5564. exception_debugging = 1;
  5565. debug_cycles();
  5566. return true;
  5567. case 'f':
  5568. if (inptr[0] == 'a') {
  5569. next_char (&inptr);
  5570. find_ea (&inptr);
  5571. } else if (inptr[0] == 'p') {
  5572. inptr++;
  5573. if (process_breakpoint (&inptr))
  5574. return true;
  5575. } else if (inptr[0] == 'c' || inptr[0] == 's') {
  5576. if (cycle_breakpoint(&inptr))
  5577. return true;
  5578. } else if (inptr[0] == 'e' && inptr[1] == 'n') {
  5579. break_if_enforcer = break_if_enforcer ? false : true;
  5580. console_out_f(_T("Break when enforcer hit: %s\n"), break_if_enforcer ? _T("enabled") : _T("disabled"));
  5581. } else {
  5582. if (instruction_breakpoint(&inptr)) {
  5583. debug_cycles();
  5584. return true;
  5585. }
  5586. }
  5587. break;
  5588. case 'q':
  5589. uae_quit();
  5590. deactivate_debugger();
  5591. return true;
  5592. case 'g':
  5593. if (more_params (&inptr)) {
  5594. m68k_setpc (readhex (&inptr));
  5595. fill_prefetch ();
  5596. }
  5597. deactivate_debugger();
  5598. return true;
  5599. case 'x':
  5600. if (_totupper(inptr[0]) == 'X') {
  5601. debugger_change(-1);
  5602. } else {
  5603. deactivate_debugger();
  5604. close_console();
  5605. return true;
  5606. }
  5607. break;
  5608. case 'H':
  5609. {
  5610. int count, temp, badly, skip;
  5611. uae_u32 addr = 0;
  5612. uae_u32 oldpc = m68k_getpc ();
  5613. int lastframes, lastvpos, lasthpos;
  5614. struct regstruct save_regs = regs;
  5615. badly = 0;
  5616. if (inptr[0] == 'H') {
  5617. badly = 1;
  5618. inptr++;
  5619. }
  5620. if (more_params(&inptr))
  5621. count = readint (&inptr);
  5622. else
  5623. count = 10;
  5624. if (count > 1000) {
  5625. addr = count;
  5626. count = MAX_HIST;
  5627. }
  5628. if (count < 0)
  5629. break;
  5630. skip = count;
  5631. if (more_params (&inptr))
  5632. skip = count - readint (&inptr);
  5633. temp = lasthist;
  5634. while (count-- > 0 && temp != firsthist) {
  5635. if (temp == 0)
  5636. temp = MAX_HIST - 1;
  5637. else
  5638. temp--;
  5639. }
  5640. lastframes = lastvpos = lasthpos = -1;
  5641. while (temp != lasthist) {
  5642. regs = history[temp].regs;
  5643. if (regs.pc == addr || addr == 0) {
  5644. m68k_setpc (regs.pc);
  5645. if (badly) {
  5646. m68k_dumpstate(NULL, 0xffffffff);
  5647. } else {
  5648. if (lastvpos >= 0) {
  5649. dma_disasm(lastframes, lastvpos, lasthpos, history[temp].fp, history[temp].vpos, history[temp].hpos);
  5650. }
  5651. lastframes = history[temp].fp;
  5652. lastvpos = history[temp].vpos;
  5653. lasthpos = history[temp].hpos;
  5654. console_out_f(_T("%2d "), regs.intmask ? regs.intmask : (regs.s ? -1 : 0));
  5655. m68k_disasm (regs.pc, NULL, 0xffffffff, 1);
  5656. }
  5657. if (addr && regs.pc == addr)
  5658. break;
  5659. }
  5660. if (skip-- < 0)
  5661. break;
  5662. if (++temp == MAX_HIST)
  5663. temp = 0;
  5664. }
  5665. regs = save_regs;
  5666. m68k_setpc (oldpc);
  5667. }
  5668. break;
  5669. case 'M':
  5670. if (more_params (&inptr)) {
  5671. switch (next_char (&inptr))
  5672. {
  5673. case 'a':
  5674. if (more_params (&inptr))
  5675. audio_channel_mask = readhex (&inptr);
  5676. console_out_f (_T("Audio mask = %02X\n"), audio_channel_mask);
  5677. break;
  5678. case 's':
  5679. if (more_params (&inptr))
  5680. debug_sprite_mask = readhex (&inptr);
  5681. console_out_f (_T("Sprite mask: %02X\n"), debug_sprite_mask);
  5682. break;
  5683. case 'b':
  5684. if (more_params (&inptr)) {
  5685. debug_bpl_mask = readhex (&inptr) & 0xff;
  5686. if (more_params (&inptr))
  5687. debug_bpl_mask_one = readhex (&inptr) & 0xff;
  5688. notice_screen_contents_lost(0);
  5689. }
  5690. console_out_f (_T("Bitplane mask: %02X (%02X)\n"), debug_bpl_mask, debug_bpl_mask_one);
  5691. break;
  5692. }
  5693. }
  5694. break;
  5695. case 'm':
  5696. {
  5697. uae_u32 maddr;
  5698. int lines;
  5699. #ifdef _WIN32
  5700. if (*inptr == 'g') {
  5701. extern void update_memdump (uae_u32);
  5702. next_char (&inptr);
  5703. if (more_params (&inptr))
  5704. update_memdump (readhex (&inptr));
  5705. break;
  5706. }
  5707. #endif
  5708. if (*inptr == 'm' && inptr[1] == 'u') {
  5709. inptr += 2;
  5710. if (inptr[0] == 'd') {
  5711. if (currprefs.mmu_model >= 68040)
  5712. mmu_dump_tables();
  5713. } else {
  5714. if (currprefs.mmu_model) {
  5715. if (more_params (&inptr))
  5716. debug_mmu_mode = readint (&inptr);
  5717. else
  5718. debug_mmu_mode = 0;
  5719. console_out_f (_T("MMU translation function code = %d\n"), debug_mmu_mode);
  5720. }
  5721. }
  5722. break;
  5723. }
  5724. if (more_params (&inptr)) {
  5725. maddr = readhex (&inptr);
  5726. } else {
  5727. maddr = nxmem;
  5728. }
  5729. if (more_params (&inptr))
  5730. lines = readhex (&inptr);
  5731. else
  5732. lines = 20;
  5733. dumpmem (maddr, &nxmem, lines);
  5734. }
  5735. break;
  5736. case 'v':
  5737. case 'V':
  5738. {
  5739. int v1 = vpos, v2 = 0;
  5740. if (*inptr == 'h') {
  5741. inptr++;
  5742. if (more_params(&inptr) && *inptr == '?') {
  5743. mw_help();
  5744. } else if (!heatmap) {
  5745. debug_heatmap = 1;
  5746. init_heatmap();
  5747. if (more_params(&inptr)) {
  5748. v1 = readint(&inptr);
  5749. if (v1 < 0) {
  5750. debug_heatmap = 2;
  5751. }
  5752. }
  5753. TCHAR buf[200];
  5754. TCHAR *pbuf;
  5755. _stprintf(buf, _T("0 dff000 200 NONE"));
  5756. pbuf = buf;
  5757. memwatch(&pbuf);
  5758. _stprintf(buf, _T("1 0 %08x NONE"), currprefs.chipmem.size);
  5759. pbuf = buf;
  5760. memwatch(&pbuf);
  5761. if (currprefs.bogomem.size) {
  5762. _stprintf(buf, _T("2 c00000 %08x NONE"), currprefs.bogomem.size);
  5763. pbuf = buf;
  5764. memwatch(&pbuf);
  5765. }
  5766. console_out_f(_T("Heatmap enabled\n"));
  5767. } else {
  5768. if (*inptr == 'd') {
  5769. console_out_f(_T("Heatmap disabled\n"));
  5770. free_heatmap();
  5771. } else {
  5772. heatmap_stats(&inptr);
  5773. }
  5774. }
  5775. } else if (*inptr == 'o') {
  5776. if (debug_dma) {
  5777. console_out_f (_T("DMA debugger disabled\n"), debug_dma);
  5778. record_dma_reset();
  5779. reset_drawing();
  5780. debug_dma = 0;
  5781. }
  5782. } else if (*inptr == 'm') {
  5783. set_debug_colors();
  5784. inptr++;
  5785. if (more_params(&inptr)) {
  5786. v1 = readint(&inptr);
  5787. if (v1 >= 0 && v1 < DMARECORD_MAX) {
  5788. v2 = readint(&inptr);
  5789. if (v2 >= 0 && v2 <= DMARECORD_SUBITEMS) {
  5790. if (more_params(&inptr)) {
  5791. uae_u32 rgb = readhex(&inptr);
  5792. if (v2 == 0) {
  5793. for (int i = 0; i < DMARECORD_SUBITEMS; i++) {
  5794. debug_colors[v1].l[i] = rgb;
  5795. }
  5796. } else {
  5797. v2--;
  5798. debug_colors[v1].l[v2] = rgb;
  5799. }
  5800. debug_colors[v1].enabled = true;
  5801. } else {
  5802. debug_colors[v1].enabled = !debug_colors[v1].enabled;
  5803. }
  5804. console_out_f(_T("%d,%d: %08x %s %s\n"), v1, v2, debug_colors[v1].l[v2], debug_colors[v1].enabled ? _T("*") : _T(" "), debug_colors[v1].name);
  5805. }
  5806. }
  5807. } else {
  5808. for (int i = 0; i < DMARECORD_MAX; i++) {
  5809. for (int j = 0; j < DMARECORD_SUBITEMS; j++) {
  5810. if (j < debug_colors[i].max) {
  5811. console_out_f(_T("%d,%d: %08x %s %s\n"), i, j, debug_colors[i].l[j], debug_colors[i].enabled ? _T("*") : _T(" "), debug_colors[i].name);
  5812. }
  5813. }
  5814. }
  5815. }
  5816. } else {
  5817. if (more_params(&inptr) && *inptr == '?') {
  5818. mw_help();
  5819. } else {
  5820. free_heatmap();
  5821. int nextcmd = peekchar(&inptr);
  5822. if (nextcmd == 'l') {
  5823. next_char(&inptr);
  5824. }
  5825. if (more_params (&inptr))
  5826. v1 = readint (&inptr);
  5827. if (more_params (&inptr))
  5828. v2 = readint (&inptr);
  5829. if (debug_dma && v1 >= 0 && v2 >= 0) {
  5830. decode_dma_record (v2, v1, cmd == 'v', nextcmd == 'l');
  5831. } else {
  5832. if (debug_dma) {
  5833. record_dma_reset();
  5834. reset_drawing();
  5835. }
  5836. debug_dma = v1 < 0 ? -v1 : 1;
  5837. console_out_f (_T("DMA debugger enabled, mode=%d.\n"), debug_dma);
  5838. }
  5839. }
  5840. }
  5841. }
  5842. break;
  5843. case 'o':
  5844. {
  5845. if (copper_debugger (&inptr)) {
  5846. debugger_active = 0;
  5847. debugging = 0;
  5848. return true;
  5849. }
  5850. break;
  5851. }
  5852. case 'O':
  5853. break;
  5854. case 'b':
  5855. if (staterecorder (&inptr))
  5856. return true;
  5857. break;
  5858. case 'u':
  5859. {
  5860. if (more_params(&inptr)) {
  5861. if (*inptr == 'a') {
  5862. debugmem_inhibit_break(1);
  5863. console_out(_T("All break to debugger methods inhibited.\n"));
  5864. } else if (*inptr == 'c') {
  5865. debugmem_inhibit_break(-1);
  5866. console_out(_T("All break to debugger methods allowed.\n"));
  5867. }
  5868. } else {
  5869. if (debugmem_inhibit_break(0)) {
  5870. console_out(_T("Current break to debugger method inhibited.\n"));
  5871. } else {
  5872. console_out(_T("Current break to debugger method allowed.\n"));
  5873. }
  5874. }
  5875. }
  5876. break;
  5877. case 'U':
  5878. if (currprefs.mmu_model && more_params (&inptr)) {
  5879. int i;
  5880. uaecptr addrl = readhex (&inptr);
  5881. uaecptr addrp;
  5882. console_out_f (_T("%08X translates to:\n"), addrl);
  5883. for (i = 0; i < 4; i++) {
  5884. bool super = (i & 2) != 0;
  5885. bool data = (i & 1) != 0;
  5886. console_out_f (_T("S%dD%d="), super, data);
  5887. TRY(prb) {
  5888. if (currprefs.mmu_model >= 68040)
  5889. addrp = mmu_translate (addrl, 0, super, data, false, sz_long);
  5890. else
  5891. addrp = mmu030_translate (addrl, super, data, false);
  5892. console_out_f (_T("%08X"), addrp);
  5893. TRY(prb2) {
  5894. if (currprefs.mmu_model >= 68040)
  5895. addrp = mmu_translate (addrl, 0, super, data, true, sz_long);
  5896. else
  5897. addrp = mmu030_translate (addrl, super, data, true);
  5898. console_out_f (_T(" RW"));
  5899. } CATCH(prb2) {
  5900. console_out_f (_T(" RO"));
  5901. } ENDTRY
  5902. } CATCH(prb) {
  5903. console_out_f (_T("***********"));
  5904. } ENDTRY
  5905. console_out_f (_T(" "));
  5906. }
  5907. console_out_f (_T("\n"));
  5908. }
  5909. break;
  5910. case 'h':
  5911. case '?':
  5912. if (more_params (&inptr))
  5913. converter (&inptr);
  5914. else
  5915. debug_help ();
  5916. break;
  5917. }
  5918. return false;
  5919. }
  5920. static void debug_1 (void)
  5921. {
  5922. TCHAR input[MAX_LINEWIDTH];
  5923. m68k_dumpstate(&nextpc, debug_pc);
  5924. debug_pc = 0xffffffff;
  5925. nxdis = nextpc; nxmem = 0;
  5926. debugger_active = 1;
  5927. for (;;) {
  5928. int v;
  5929. if (!debugger_active)
  5930. return;
  5931. update_debug_info ();
  5932. console_out (_T(">"));
  5933. console_flush ();
  5934. debug_linecounter = 0;
  5935. v = console_get (input, MAX_LINEWIDTH);
  5936. if (v < 0)
  5937. return;
  5938. if (v == 0)
  5939. continue;
  5940. if (debug_line (input))
  5941. return;
  5942. }
  5943. }
  5944. static void addhistory (void)
  5945. {
  5946. uae_u32 pc = currprefs.cpu_model >= 68020 && currprefs.cpu_compatible ? regs.instruction_pc : m68k_getpc();
  5947. history[lasthist].regs = regs;
  5948. history[lasthist].regs.pc = pc;
  5949. history[lasthist].vpos = vpos;
  5950. history[lasthist].hpos = current_hpos();
  5951. history[lasthist].fp = timeframes;
  5952. if (++lasthist == MAX_HIST)
  5953. lasthist = 0;
  5954. if (lasthist == firsthist) {
  5955. if (++firsthist == MAX_HIST) firsthist = 0;
  5956. }
  5957. }
  5958. static void debug_continue(void)
  5959. {
  5960. set_special (SPCFLAG_BRK);
  5961. }
  5962. void debug (void)
  5963. {
  5964. int i;
  5965. int wasactive;
  5966. if (savestate_state)
  5967. return;
  5968. bogusframe = 1;
  5969. addhistory ();
  5970. #if 0
  5971. if (do_skip && skipaddr_start == 0xC0DEDBAD) {
  5972. if (trace_same_insn_count > 0) {
  5973. if (memcmp (trace_insn_copy, regs.pc_p, 10) == 0
  5974. && memcmp (trace_prev_regs.regs, regs.regs, sizeof regs.regs) == 0)
  5975. {
  5976. trace_same_insn_count++;
  5977. return;
  5978. }
  5979. }
  5980. if (trace_same_insn_count > 1)
  5981. fprintf (logfile, "[ repeated %d times ]\n", trace_same_insn_count);
  5982. m68k_dumpstate (logfile, &nextpc);
  5983. trace_same_insn_count = 1;
  5984. memcpy (trace_insn_copy, regs.pc_p, 10);
  5985. memcpy (&trace_prev_regs, &regs, sizeof regs);
  5986. }
  5987. #endif
  5988. if (!memwatch_triggered) {
  5989. if (trace_mode) {
  5990. uae_u32 pc;
  5991. uae_u16 opcode;
  5992. int bp = 0;
  5993. pc = munge24 (m68k_getpc ());
  5994. opcode = currprefs.cpu_model < 68020 && (currprefs.cpu_compatible || currprefs.cpu_cycle_exact) ? regs.ir : get_word_debug (pc);
  5995. for (i = 0; i < BREAKPOINT_TOTAL; i++) {
  5996. struct breakpoint_node *bpn = &bpnodes[i];
  5997. if (!bpn->enabled)
  5998. continue;
  5999. if (bpn->type == BREAKPOINT_REG_PC) {
  6000. if (bpn->value1 == pc) {
  6001. bp = 1;
  6002. break;
  6003. }
  6004. } else if (bpn->type >= 0 && bpn->type < BREAKPOINT_REG_END) {
  6005. uae_u32 value1 = bpn->value1 & bpn->mask;
  6006. uae_u32 value2 = bpn->value2 & bpn->mask;
  6007. uae_u32 cval = returnregx(bpn->type) & bpn->mask;
  6008. switch (bpn->oper)
  6009. {
  6010. case BREAKPOINT_CMP_EQUAL:
  6011. if (cval == value1)
  6012. bp = i + 1;
  6013. break;
  6014. case BREAKPOINT_CMP_NEQUAL:
  6015. if (cval != value1)
  6016. bp = i + 1;
  6017. break;
  6018. case BREAKPOINT_CMP_SMALLER:
  6019. if (cval <= value1)
  6020. bp = i + 1;
  6021. break;
  6022. case BREAKPOINT_CMP_LARGER:
  6023. if (cval >= value1)
  6024. bp = i + 1;
  6025. break;
  6026. case BREAKPOINT_CMP_RANGE:
  6027. if (cval >= value1 && cval <= value2)
  6028. bp = i + 1;
  6029. break;
  6030. case BREAKPOINT_CMP_NRANGE:
  6031. if (cval <= value1 || cval >= value2)
  6032. bp = i + 1;
  6033. break;
  6034. }
  6035. }
  6036. }
  6037. if (trace_mode) {
  6038. if (trace_mode == TRACE_MATCH_PC && trace_param[0] == pc)
  6039. bp = -1;
  6040. if (trace_mode == TRACE_RAM_PC) {
  6041. addrbank *ab = &get_mem_bank(pc);
  6042. if (ab->flags & ABFLAG_RAM) {
  6043. uae_u16 ins = get_word_debug(pc);
  6044. // skip JMP xxxxxx (LVOs)
  6045. if (ins != 0x4ef9) {
  6046. bp = -1;
  6047. }
  6048. }
  6049. }
  6050. if ((processptr || processname) && notinrom()) {
  6051. uaecptr execbase = get_long_debug (4);
  6052. uaecptr activetask = get_long_debug (execbase + 276);
  6053. int process = get_byte_debug (activetask + 8) == 13 ? 1 : 0;
  6054. char *name = (char*)get_real_address_debug(get_long_debug (activetask + 10));
  6055. if (process) {
  6056. uaecptr cli = BPTR2APTR(get_long_debug (activetask + 172));
  6057. uaecptr seglist = 0;
  6058. uae_char *command = NULL;
  6059. if (cli) {
  6060. if (processname)
  6061. command = (char*)get_real_address_debug(BPTR2APTR(get_long_debug (cli + 16)));
  6062. seglist = BPTR2APTR(get_long_debug (cli + 60));
  6063. } else {
  6064. seglist = BPTR2APTR(get_long_debug (activetask + 128));
  6065. seglist = BPTR2APTR(get_long_debug (seglist + 12));
  6066. }
  6067. if (activetask == processptr || (processname && (!stricmp (name, processname) || (command && command[0] && !strnicmp (command + 1, processname, command[0]) && processname[command[0]] == 0)))) {
  6068. while (seglist) {
  6069. uae_u32 size = get_long_debug (seglist - 4) - 4;
  6070. if (pc >= (seglist + 4) && pc < (seglist + size)) {
  6071. bp = 1;
  6072. break;
  6073. }
  6074. seglist = BPTR2APTR(get_long_debug (seglist));
  6075. }
  6076. }
  6077. }
  6078. } else if (trace_mode == TRACE_MATCH_INS) {
  6079. if (trace_param[0] == 0x10000) {
  6080. if (opcode == 0x4e75 || opcode == 0x4e73 || opcode == 0x4e77)
  6081. bp = -1;
  6082. } else if (opcode == trace_param[0]) {
  6083. bp = -1;
  6084. for (int op = 1; op < 3; op++) {
  6085. if (trace_param[op] != 0x10000) {
  6086. uae_u16 w = 0xffff;
  6087. debug_get_prefetch(op, &w);
  6088. if (w != trace_param[op])
  6089. bp = 0;
  6090. }
  6091. }
  6092. }
  6093. } else if (trace_mode == TRACE_SKIP_INS) {
  6094. if (trace_param[0] != 0)
  6095. trace_param[0]--;
  6096. if (trace_param[0] == 0) {
  6097. bp = -1;
  6098. }
  6099. #if 0
  6100. } else if (skipaddr_start == 0xffffffff && skipaddr_doskip > 0) {
  6101. bp = -1;
  6102. #endif
  6103. } else if (trace_mode == TRACE_RANGE_PC) {
  6104. if (pc >= trace_param[0] && pc < trace_param[1])
  6105. bp = -1;
  6106. } else if (trace_mode == TRACE_SKIP_LINE) {
  6107. if (trace_param[0] != 0)
  6108. trace_param[0]--;
  6109. if (trace_param[0] == 0) {
  6110. int line = debugmem_get_sourceline(pc, NULL, 0);
  6111. if (line > 0 && line != trace_param[1])
  6112. bp = -1;
  6113. }
  6114. }
  6115. }
  6116. if (!bp) {
  6117. debug_continue();
  6118. return;
  6119. }
  6120. if (bp > 0)
  6121. console_out_f(_T("Breakpoint %d triggered.\n"), bp - 1);
  6122. debug_cycles();
  6123. }
  6124. } else {
  6125. memwatch_hit_msg(memwatch_triggered - 1);
  6126. memwatch_triggered = 0;
  6127. }
  6128. wasactive = ismouseactive ();
  6129. #ifdef WITH_PPC
  6130. uae_ppc_pause(1);
  6131. #endif
  6132. inputdevice_unacquire ();
  6133. pause_sound ();
  6134. setmouseactive(0, 0);
  6135. activate_console ();
  6136. trace_mode = 0;
  6137. exception_debugging = 0;
  6138. debug_rewind = 0;
  6139. processptr = 0;
  6140. #if 0
  6141. if (!currprefs.statecapture) {
  6142. changed_prefs.statecapture = currprefs.statecapture = 1;
  6143. savestate_init ();
  6144. }
  6145. #endif
  6146. debugmem_disable();
  6147. if (trace_cycles && last_frame >= 0) {
  6148. if (last_frame + 2 >= timeframes) {
  6149. console_out_f(_T("Cycles: %d Chip, %d CPU. (V=%d H=%d -> V=%d H=%d)\n"),
  6150. (last_cycles2 - last_cycles1) / CYCLE_UNIT,
  6151. (last_cycles2 - last_cycles1) / cpucycleunit,
  6152. last_vpos1, last_hpos1,
  6153. last_vpos2, last_hpos2);
  6154. }
  6155. }
  6156. trace_cycles = 0;
  6157. debug_1 ();
  6158. debugmem_enable();
  6159. if (!debug_rewind && !currprefs.cachesize
  6160. #ifdef FILESYS
  6161. && nr_units () == 0
  6162. #endif
  6163. ) {
  6164. savestate_capture (1);
  6165. }
  6166. if (!trace_mode) {
  6167. for (i = 0; i < BREAKPOINT_TOTAL; i++) {
  6168. if (bpnodes[i].enabled)
  6169. trace_mode = TRACE_CHECKONLY;
  6170. }
  6171. }
  6172. if (trace_mode) {
  6173. set_special (SPCFLAG_BRK);
  6174. debugging = -1;
  6175. }
  6176. resume_sound ();
  6177. inputdevice_acquire (TRUE);
  6178. #ifdef WITH_PPC
  6179. uae_ppc_pause(0);
  6180. #endif
  6181. setmouseactive(0, wasactive ? 2 : 0);
  6182. last_cycles1 = get_cycles();
  6183. last_vpos1 = vpos;
  6184. last_hpos1 = current_hpos();
  6185. last_frame = timeframes;
  6186. }
  6187. const TCHAR *debuginfo (int mode)
  6188. {
  6189. static TCHAR txt[100];
  6190. uae_u32 pc = M68K_GETPC;
  6191. _stprintf (txt, _T("PC=%08X INS=%04X %04X %04X"),
  6192. pc, get_word_debug (pc), get_word_debug (pc + 2), get_word_debug (pc + 4));
  6193. return txt;
  6194. }
  6195. void mmu_disasm (uaecptr pc, int lines)
  6196. {
  6197. debug_mmu_mode = regs.s ? 6 : 2;
  6198. m68k_dumpstate(NULL, 0xffffffff);
  6199. m68k_disasm (pc, NULL, 0xffffffff, lines);
  6200. }
  6201. static int mmu_logging;
  6202. #define MMU_PAGE_SHIFT 16
  6203. struct mmudata {
  6204. uae_u32 flags;
  6205. uae_u32 addr;
  6206. uae_u32 len;
  6207. uae_u32 remap;
  6208. uae_u32 p_addr;
  6209. };
  6210. static struct mmudata *mmubanks;
  6211. static uae_u32 mmu_struct, mmu_callback, mmu_regs;
  6212. static uae_u32 mmu_fault_bank_addr, mmu_fault_addr;
  6213. static int mmu_fault_size, mmu_fault_rw;
  6214. static int mmu_slots;
  6215. static struct regstruct mmur;
  6216. struct mmunode {
  6217. struct mmudata *mmubank;
  6218. struct mmunode *next;
  6219. };
  6220. static struct mmunode **mmunl;
  6221. extern regstruct mmu_backup_regs;
  6222. #define MMU_READ_U (1 << 0)
  6223. #define MMU_WRITE_U (1 << 1)
  6224. #define MMU_READ_S (1 << 2)
  6225. #define MMU_WRITE_S (1 << 3)
  6226. #define MMU_READI_U (1 << 4)
  6227. #define MMU_READI_S (1 << 5)
  6228. #define MMU_MAP_READ_U (1 << 8)
  6229. #define MMU_MAP_WRITE_U (1 << 9)
  6230. #define MMU_MAP_READ_S (1 << 10)
  6231. #define MMU_MAP_WRITE_S (1 << 11)
  6232. #define MMU_MAP_READI_U (1 << 12)
  6233. #define MMU_MAP_READI_S (1 << 13)
  6234. void mmu_do_hit (void)
  6235. {
  6236. int i;
  6237. uaecptr p;
  6238. uae_u32 pc;
  6239. mmu_triggered = 0;
  6240. pc = m68k_getpc ();
  6241. p = mmu_regs + 18 * 4;
  6242. put_long (p, pc);
  6243. regs = mmu_backup_regs;
  6244. regs.intmask = 7;
  6245. regs.t0 = regs.t1 = 0;
  6246. if (!regs.s) {
  6247. regs.usp = m68k_areg (regs, 7);
  6248. if (currprefs.cpu_model >= 68020)
  6249. m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
  6250. else
  6251. m68k_areg (regs, 7) = regs.isp;
  6252. regs.s = 1;
  6253. }
  6254. MakeSR ();
  6255. m68k_setpc (mmu_callback);
  6256. fill_prefetch ();
  6257. if (currprefs.cpu_model > 68000) {
  6258. for (i = 0 ; i < 9; i++) {
  6259. m68k_areg (regs, 7) -= 4;
  6260. put_long (m68k_areg (regs, 7), 0);
  6261. }
  6262. m68k_areg (regs, 7) -= 4;
  6263. put_long (m68k_areg (regs, 7), mmu_fault_addr);
  6264. m68k_areg (regs, 7) -= 2;
  6265. put_word (m68k_areg (regs, 7), 0); /* WB1S */
  6266. m68k_areg (regs, 7) -= 2;
  6267. put_word (m68k_areg (regs, 7), 0); /* WB2S */
  6268. m68k_areg (regs, 7) -= 2;
  6269. put_word (m68k_areg (regs, 7), 0); /* WB3S */
  6270. m68k_areg (regs, 7) -= 2;
  6271. put_word (m68k_areg (regs, 7),
  6272. (mmu_fault_rw ? 0 : 0x100) | (mmu_fault_size << 5)); /* SSW */
  6273. m68k_areg (regs, 7) -= 4;
  6274. put_long (m68k_areg (regs, 7), mmu_fault_bank_addr);
  6275. m68k_areg (regs, 7) -= 2;
  6276. put_word (m68k_areg (regs, 7), 0x7002);
  6277. }
  6278. m68k_areg (regs, 7) -= 4;
  6279. put_long (m68k_areg (regs, 7), get_long_debug (p - 4));
  6280. m68k_areg (regs, 7) -= 2;
  6281. put_word (m68k_areg (regs, 7), mmur.sr);
  6282. #ifdef JIT
  6283. set_special(SPCFLAG_END_COMPILE);
  6284. #endif
  6285. }
  6286. static void mmu_do_hit_pre (struct mmudata *md, uaecptr addr, int size, int rwi, uae_u32 v)
  6287. {
  6288. uae_u32 p, pc;
  6289. int i;
  6290. mmur = regs;
  6291. pc = m68k_getpc ();
  6292. if (mmu_logging)
  6293. console_out_f (_T("MMU: hit %08X SZ=%d RW=%d V=%08X PC=%08X\n"), addr, size, rwi, v, pc);
  6294. p = mmu_regs;
  6295. put_long (p, 0); p += 4;
  6296. for (i = 0; i < 16; i++) {
  6297. put_long (p, regs.regs[i]);
  6298. p += 4;
  6299. }
  6300. put_long (p, pc); p += 4;
  6301. put_long (p, 0); p += 4;
  6302. put_long (p, regs.usp); p += 4;
  6303. put_long (p, regs.isp); p += 4;
  6304. put_long (p, regs.msp); p += 4;
  6305. put_word (p, regs.sr); p += 2;
  6306. put_word (p, (size << 1) | ((rwi & 2) ? 1 : 0)); /* size and rw */ p += 2;
  6307. put_long (p, addr); /* fault address */ p += 4;
  6308. put_long (p, md->p_addr); /* bank address */ p += 4;
  6309. put_long (p, v); p += 4;
  6310. mmu_fault_addr = addr;
  6311. mmu_fault_bank_addr = md->p_addr;
  6312. mmu_fault_size = size;
  6313. mmu_fault_rw = rwi;
  6314. mmu_triggered = 1;
  6315. }
  6316. static int mmu_hit (uaecptr addr, int size, int rwi, uae_u32 *v)
  6317. {
  6318. int s, trig;
  6319. uae_u32 flags;
  6320. struct mmudata *md;
  6321. struct mmunode *mn;
  6322. if (mmu_triggered)
  6323. return 1;
  6324. mn = mmunl[addr >> MMU_PAGE_SHIFT];
  6325. if (mn == NULL)
  6326. return 0;
  6327. s = regs.s;
  6328. while (mn) {
  6329. md = mn->mmubank;
  6330. if (addr >= md->addr && addr < md->addr + md->len) {
  6331. flags = md->flags;
  6332. if (flags & (MMU_MAP_READ_U | MMU_MAP_WRITE_U | MMU_MAP_READ_S | MMU_MAP_WRITE_S | MMU_MAP_READI_U | MMU_MAP_READI_S)) {
  6333. trig = 0;
  6334. if (!s && (flags & MMU_MAP_READ_U) && (rwi & 1))
  6335. trig = 1;
  6336. if (!s && (flags & MMU_MAP_WRITE_U) && (rwi & 2))
  6337. trig = 1;
  6338. if (s && (flags & MMU_MAP_READ_S) && (rwi & 1))
  6339. trig = 1;
  6340. if (s && (flags & MMU_MAP_WRITE_S) && (rwi & 2))
  6341. trig = 1;
  6342. if (!s && (flags & MMU_MAP_READI_U) && (rwi & 4))
  6343. trig = 1;
  6344. if (s && (flags & MMU_MAP_READI_S) && (rwi & 4))
  6345. trig = 1;
  6346. if (trig) {
  6347. uaecptr maddr = md->remap + (addr - md->addr);
  6348. if (maddr == addr) /* infinite mmu hit loop? no thanks.. */
  6349. return 1;
  6350. if (mmu_logging)
  6351. console_out_f (_T("MMU: remap %08X -> %08X SZ=%d RW=%d\n"), addr, maddr, size, rwi);
  6352. if ((rwi & 2)) {
  6353. switch (size)
  6354. {
  6355. case 4:
  6356. put_long (maddr, *v);
  6357. break;
  6358. case 2:
  6359. put_word (maddr, *v);
  6360. break;
  6361. case 1:
  6362. put_byte (maddr, *v);
  6363. break;
  6364. }
  6365. } else {
  6366. switch (size)
  6367. {
  6368. case 4:
  6369. *v = get_long_debug (maddr);
  6370. break;
  6371. case 2:
  6372. *v = get_word_debug (maddr);
  6373. break;
  6374. case 1:
  6375. *v = get_byte_debug (maddr);
  6376. break;
  6377. }
  6378. }
  6379. return 1;
  6380. }
  6381. }
  6382. if (flags & (MMU_READ_U | MMU_WRITE_U | MMU_READ_S | MMU_WRITE_S | MMU_READI_U | MMU_READI_S)) {
  6383. trig = 0;
  6384. if (!s && (flags & MMU_READ_U) && (rwi & 1))
  6385. trig = 1;
  6386. if (!s && (flags & MMU_WRITE_U) && (rwi & 2))
  6387. trig = 1;
  6388. if (s && (flags & MMU_READ_S) && (rwi & 1))
  6389. trig = 1;
  6390. if (s && (flags & MMU_WRITE_S) && (rwi & 2))
  6391. trig = 1;
  6392. if (!s && (flags & MMU_READI_U) && (rwi & 4))
  6393. trig = 1;
  6394. if (s && (flags & MMU_READI_S) && (rwi & 4))
  6395. trig = 1;
  6396. if (trig) {
  6397. mmu_do_hit_pre (md, addr, size, rwi, *v);
  6398. return 1;
  6399. }
  6400. }
  6401. }
  6402. mn = mn->next;
  6403. }
  6404. return 0;
  6405. }
  6406. #ifdef JIT
  6407. static void mmu_free_node(struct mmunode *mn)
  6408. {
  6409. if (!mn)
  6410. return;
  6411. mmu_free_node (mn->next);
  6412. xfree (mn);
  6413. }
  6414. static void mmu_free(void)
  6415. {
  6416. struct mmunode *mn;
  6417. int i;
  6418. for (i = 0; i < mmu_slots; i++) {
  6419. mn = mmunl[i];
  6420. mmu_free_node (mn);
  6421. }
  6422. xfree (mmunl);
  6423. mmunl = NULL;
  6424. xfree (mmubanks);
  6425. mmubanks = NULL;
  6426. }
  6427. #endif
  6428. static int getmmubank(struct mmudata *snptr, uaecptr p)
  6429. {
  6430. snptr->flags = get_long_debug (p);
  6431. if (snptr->flags == 0xffffffff)
  6432. return 1;
  6433. snptr->addr = get_long_debug (p + 4);
  6434. snptr->len = get_long_debug (p + 8);
  6435. snptr->remap = get_long_debug (p + 12);
  6436. snptr->p_addr = p;
  6437. return 0;
  6438. }
  6439. int mmu_init(int mode, uaecptr parm, uaecptr parm2)
  6440. {
  6441. uaecptr p, p2, banks;
  6442. int size;
  6443. struct mmudata *snptr;
  6444. struct mmunode *mn;
  6445. #ifdef JIT
  6446. static int wasjit;
  6447. if (currprefs.cachesize) {
  6448. wasjit = currprefs.cachesize;
  6449. changed_prefs.cachesize = 0;
  6450. console_out (_T("MMU: JIT disabled\n"));
  6451. check_prefs_changed_comp(false);
  6452. }
  6453. if (mode == 0) {
  6454. if (mmu_enabled) {
  6455. mmu_free ();
  6456. deinitialize_memwatch ();
  6457. console_out (_T("MMU: disabled\n"));
  6458. changed_prefs.cachesize = wasjit;
  6459. }
  6460. mmu_logging = 0;
  6461. return 1;
  6462. }
  6463. #endif
  6464. if (mode == 1) {
  6465. if (!mmu_enabled)
  6466. return 0xffffffff;
  6467. return mmu_struct;
  6468. }
  6469. p = parm;
  6470. mmu_struct = p;
  6471. if (get_long_debug (p) != 1) {
  6472. console_out_f (_T("MMU: version mismatch %d <> %d\n"), get_long_debug (p), 1);
  6473. return 0;
  6474. }
  6475. p += 4;
  6476. mmu_logging = get_long_debug (p) & 1;
  6477. p += 4;
  6478. mmu_callback = get_long_debug (p);
  6479. p += 4;
  6480. mmu_regs = get_long_debug (p);
  6481. p += 4;
  6482. if (mode == 3) {
  6483. int off;
  6484. uaecptr addr = get_long_debug (parm2 + 4);
  6485. if (!mmu_enabled)
  6486. return 0;
  6487. off = addr >> MMU_PAGE_SHIFT;
  6488. mn = mmunl[off];
  6489. while (mn) {
  6490. if (mn->mmubank->p_addr == parm2) {
  6491. getmmubank(mn->mmubank, parm2);
  6492. if (mmu_logging)
  6493. console_out_f (_T("MMU: bank update %08X: %08X - %08X %08X\n"),
  6494. mn->mmubank->flags, mn->mmubank->addr, mn->mmubank->len + mn->mmubank->addr,
  6495. mn->mmubank->remap);
  6496. }
  6497. mn = mn->next;
  6498. }
  6499. return 1;
  6500. }
  6501. mmu_slots = 1 << ((currprefs.address_space_24 ? 24 : 32) - MMU_PAGE_SHIFT);
  6502. mmunl = xcalloc (struct mmunode*, mmu_slots);
  6503. size = 1;
  6504. p2 = get_long_debug (p);
  6505. while (get_long_debug (p2) != 0xffffffff) {
  6506. p2 += 16;
  6507. size++;
  6508. }
  6509. p = banks = get_long_debug (p);
  6510. snptr = mmubanks = xmalloc (struct mmudata, size);
  6511. for (;;) {
  6512. int off;
  6513. if (getmmubank(snptr, p))
  6514. break;
  6515. p += 16;
  6516. off = snptr->addr >> MMU_PAGE_SHIFT;
  6517. if (mmunl[off] == NULL) {
  6518. mn = mmunl[off] = xcalloc (struct mmunode, 1);
  6519. } else {
  6520. mn = mmunl[off];
  6521. while (mn->next)
  6522. mn = mn->next;
  6523. mn = mn->next = xcalloc (struct mmunode, 1);
  6524. }
  6525. mn->mmubank = snptr;
  6526. snptr++;
  6527. }
  6528. initialize_memwatch (1);
  6529. console_out_f (_T("MMU: enabled, %d banks, CB=%08X S=%08X BNK=%08X SF=%08X, %d*%d\n"),
  6530. size - 1, mmu_callback, parm, banks, mmu_regs, mmu_slots, 1 << MMU_PAGE_SHIFT);
  6531. set_special (SPCFLAG_BRK);
  6532. return 1;
  6533. }
  6534. void debug_parser (const TCHAR *cmd, TCHAR *out, uae_u32 outsize)
  6535. {
  6536. TCHAR empty[2] = { 0 };
  6537. TCHAR *input = my_strdup (cmd);
  6538. if (out == NULL && outsize == 0) {
  6539. setconsolemode (empty, 1);
  6540. } else if (out != NULL && outsize > 0) {
  6541. out[0] = 0;
  6542. setconsolemode (out, outsize);
  6543. }
  6544. debug_line (input);
  6545. setconsolemode (NULL, 0);
  6546. xfree (input);
  6547. }
  6548. /*
  6549. trainer file is .ini file with following one or more [patch] sections.
  6550. Each [patch] section describes single trainer option.
  6551. After [patch] section must come at least one patch descriptor.
  6552. [patch]
  6553. name=name
  6554. enable=true/false
  6555. event=KEY_F1
  6556. ; patch descriptor
  6557. data=200e46802d400026200cxx02 ; this is comment
  6558. offset=2
  6559. access=write
  6560. setvalue=<value>
  6561. type=nop/freeze/set/setonce
  6562. ; patch descriptor
  6563. data=11223344556677889900
  6564. offset=10
  6565. replacedata=4e71
  6566. replaceoffset=4
  6567. ; next patch section
  6568. [patch]
  6569. name: name of the option (appears in GUI in the future)
  6570. enable: true = automatically enabled at startup. (false=manually activated using key shortcut etc.., will be implemented later)
  6571. event: inputevents.def event name
  6572. data: match data, when emulated CPU executes first opcode of this data and following words also match: match is detected. x = anything.
  6573. offset: word offset from beginning of "data" that points to memory read/write instruction that you want to "patch". Default=0.
  6574. access: read=read access, write=write access. Default: write if instruction does both memory read and write, read if read-only.
  6575. setvalue: value to write if type is set or setonce.
  6576. type=nop: found instruction's write does nothing. This instruction only. Other instruction(s) modifying same memory location are not skipped.
  6577. type=freeze: found instruction's memory read always returns value in memory. Write does nothing.
  6578. type=set: found instruction's memory read always returns "setvalue" contents. Write works normally.
  6579. type=setonce: "setvalue" contents are written to memory when patch is detected.
  6580. replacedata: data to be copied over data + replaceoffset. x masking is also supported. Memory is modified.
  6581. replaceoffset: word offset from data.
  6582. ---
  6583. Internally it uses debugger memory watch points to modify/freeze memory contents. No memory or code is modified.
  6584. Only type=setonce and replacedata modifies memory.
  6585. When CPU emulator current to be executed instruction's matches contents of data[offset], other words of data are also checked.
  6586. If all words match: instruction's effective address(es) are calculated and matching (read/write) EA is stored. Matching part
  6587. of patch is now done.
  6588. Reason for this complexity is to enable single patch to work even if game is relocatable or it uses different memory
  6589. locations depending on hardware config.
  6590. If type=nop/freeze/set: debugger memwatch point is set that handles faking of read/write access.
  6591. If type=setonce: "setvalue" contents gets written to detected effective address.
  6592. If replacedata is set: copy code.
  6593. Detection phase may cause increased CPU load, this may get optimized more but it shouldn't be (too) noticeable in basic
  6594. A500 or A1200 modes.
  6595. */
  6596. #define TRAINER_NOP 0
  6597. #define TRAINER_FREEZE 1
  6598. #define TRAINER_SET 2
  6599. #define TRAINER_SETONCE 3
  6600. struct trainerpatch
  6601. {
  6602. TCHAR *name;
  6603. uae_u16 *data;
  6604. uae_u16 *maskdata;
  6605. uae_u16 *replacedata;
  6606. uae_u16 *replacemaskdata;
  6607. uae_u16 *replacedata_original;
  6608. uae_u16 first;
  6609. int length;
  6610. int offset;
  6611. int access;
  6612. int replacelength;
  6613. int replaceoffset;
  6614. uaecptr addr;
  6615. uaecptr varaddr;
  6616. int varsize;
  6617. uae_u32 oldval;
  6618. int patchtype;
  6619. int setvalue;
  6620. int *events;
  6621. int eventcount;
  6622. int memwatchindex;
  6623. bool enabledatstart;
  6624. bool enabled;
  6625. };
  6626. static struct trainerpatch **tpptr;
  6627. static int tpptrcnt;
  6628. bool debug_opcode_watch;
  6629. static int debug_trainer_get_ea(struct trainerpatch *tp, uaecptr pc, uae_u16 opcode, uaecptr *addr)
  6630. {
  6631. struct instr *dp = table68k + opcode;
  6632. uae_u32 sea = 0, dea = 0;
  6633. uaecptr spc = 0, dpc = 0;
  6634. uaecptr pc2 = pc + 2;
  6635. if (dp->suse) {
  6636. spc = pc2;
  6637. pc2 = ShowEA(NULL, pc2, opcode, dp->sreg, dp->smode, dp->size, NULL, &sea, NULL, 1);
  6638. if (sea == spc)
  6639. spc = 0xffffffff;
  6640. }
  6641. if (dp->duse) {
  6642. dpc = pc2;
  6643. pc2 = ShowEA(NULL, pc2, opcode, dp->dreg, dp->dmode, dp->size, NULL, &dea, NULL, 1);
  6644. if (dea == dpc)
  6645. dpc = 0xffffffff;
  6646. }
  6647. if (dea && dpc != 0xffffffff && tp->access == 1) {
  6648. *addr = dea;
  6649. return 1 << dp->size;
  6650. }
  6651. if (sea && spc != 0xffffffff && tp->access == 0) {
  6652. *addr = sea;
  6653. return 1 << dp->size;
  6654. }
  6655. if (dea && tp->access > 1) {
  6656. *addr = dea;
  6657. return 1 << dp->size;
  6658. }
  6659. if (sea && tp->access > 1) {
  6660. *addr = sea;
  6661. return 1 << dp->size;
  6662. }
  6663. return 0;
  6664. }
  6665. static void debug_trainer_enable(struct trainerpatch *tp, bool enable)
  6666. {
  6667. if (tp->enabled == enable)
  6668. return;
  6669. if (tp->replacedata) {
  6670. if (enable) {
  6671. bool first = false;
  6672. if (!tp->replacedata_original) {
  6673. tp->replacedata_original = xcalloc(uae_u16, tp->replacelength);
  6674. first = true;
  6675. }
  6676. for (int j = 0; j < tp->replacelength; j++) {
  6677. uae_u16 v = tp->replacedata[j];
  6678. uae_u16 m = tp->replacemaskdata[j];
  6679. uaecptr addr = (tp->addr - tp->offset * 2) + j * 2 + tp->replaceoffset * 2;
  6680. if (m == 0xffff) {
  6681. x_put_word(addr, v);
  6682. } else {
  6683. uae_u16 vo = x_get_word(addr);
  6684. x_put_word(addr, (vo & ~m) | (v & m));
  6685. if (first)
  6686. tp->replacedata_original[j] = vo;
  6687. }
  6688. }
  6689. } else if (tp->replacedata_original) {
  6690. for (int j = 0; j < tp->replacelength; j++) {
  6691. uae_u16 m = tp->replacemaskdata[j];
  6692. uaecptr addr = (tp->addr - tp->offset * 2) + j * 2 + tp->replaceoffset * 2;
  6693. if (m != 0xffff) {
  6694. x_put_word(addr, tp->replacedata_original[j]);
  6695. }
  6696. }
  6697. }
  6698. }
  6699. if (tp->patchtype == TRAINER_SETONCE && tp->varaddr != 0xffffffff) {
  6700. uae_u32 v = enable ? tp->setvalue : tp->oldval;
  6701. switch (tp->varsize)
  6702. {
  6703. case 1:
  6704. x_put_byte(tp->varaddr, tp->setvalue);
  6705. break;
  6706. case 2:
  6707. x_put_word(tp->varaddr, tp->setvalue);
  6708. break;
  6709. case 4:
  6710. x_put_long(tp->varaddr, tp->setvalue);
  6711. break;
  6712. }
  6713. }
  6714. if ((tp->patchtype == TRAINER_NOP || tp->patchtype == TRAINER_FREEZE || tp->patchtype == TRAINER_SET) && tp->varaddr != 0xffffffff) {
  6715. struct memwatch_node *mwn;
  6716. if (!memwatch_enabled)
  6717. initialize_memwatch(0);
  6718. if (enable) {
  6719. int i;
  6720. for (i = MEMWATCH_TOTAL - 1; i >= 0; i--) {
  6721. mwn = &mwnodes[i];
  6722. if (!mwn->size)
  6723. break;
  6724. }
  6725. if (i < 0) {
  6726. write_log(_T("Trainer out of free memwatchpoints ('%s' %08x\n).\n"), tp->name, tp->addr);
  6727. } else {
  6728. mwn->addr = tp->varaddr;
  6729. mwn->size = tp->varsize;
  6730. mwn->rwi = 1 | 2;
  6731. mwn->access_mask = MW_MASK_CPU_D_R | MW_MASK_CPU_D_W;
  6732. mwn->reg = 0xffffffff;
  6733. mwn->pc = tp->patchtype == TRAINER_NOP ? tp->addr : 0xffffffff;
  6734. mwn->frozen = tp->patchtype == TRAINER_FREEZE || tp->patchtype == TRAINER_NOP;
  6735. mwn->modval_written = 0;
  6736. mwn->val_enabled = 0;
  6737. mwn->val_mask = 0xffffffff;
  6738. mwn->val = 0;
  6739. mwn->reportonly = false;
  6740. if (tp->patchtype == TRAINER_SET) {
  6741. mwn->val_enabled = 1;
  6742. mwn->val = tp->setvalue;
  6743. }
  6744. mwn->nobreak = true;
  6745. memwatch_setup();
  6746. TCHAR buf[256];
  6747. memwatch_dump2(buf, sizeof(buf) / sizeof(TCHAR), i);
  6748. write_log(_T("%s"), buf);
  6749. }
  6750. } else {
  6751. mwn = &mwnodes[tp->memwatchindex];
  6752. mwn->size = 0;
  6753. memwatch_setup();
  6754. }
  6755. }
  6756. write_log(_T("Trainer '%s' %s (addr=%08x)\n"), tp->name, enable ? _T("enabled") : _T("disabled"), tp->addr);
  6757. tp->enabled = enable;
  6758. }
  6759. void debug_trainer_match(void)
  6760. {
  6761. uaecptr pc = m68k_getpc();
  6762. uae_u16 opcode = x_get_word(pc);
  6763. for (int i = 0; i < tpptrcnt; i++) {
  6764. struct trainerpatch *tp = tpptr[i];
  6765. if (tp->first != opcode)
  6766. continue;
  6767. if (tp->addr)
  6768. continue;
  6769. int j;
  6770. for (j = 0; j < tp->length; j++) {
  6771. uae_u16 d = x_get_word(pc + (j - tp->offset) * 2);
  6772. if ((d & tp->maskdata[j]) != tp->data[j])
  6773. break;
  6774. }
  6775. if (j < tp->length)
  6776. continue;
  6777. tp->first = 0xffff;
  6778. tp->addr = pc;
  6779. tp->varsize = -1;
  6780. tp->varaddr = 0xffffffff;
  6781. tp->oldval = 0xffffffff;
  6782. if (tp->access >= 0) {
  6783. tp->varsize = debug_trainer_get_ea(tp, pc, opcode, &tp->varaddr);
  6784. switch (tp->varsize)
  6785. {
  6786. case 1:
  6787. tp->oldval = x_get_byte(tp->varaddr);
  6788. break;
  6789. case 2:
  6790. tp->oldval = x_get_word(tp->varaddr);
  6791. break;
  6792. case 4:
  6793. tp->oldval = x_get_long(tp->varaddr);
  6794. break;
  6795. }
  6796. }
  6797. write_log(_T("Patch %d match at %08x. Addr %08x, size %d, val %08x\n"), i, pc, tp->varaddr, tp->varsize, tp->oldval);
  6798. if (tp->enabledatstart)
  6799. debug_trainer_enable(tp, true);
  6800. // all detected?
  6801. for (j = 0; j < tpptrcnt; j++) {
  6802. struct trainerpatch *tp = tpptr[j];
  6803. if (!tp->addr)
  6804. break;
  6805. }
  6806. if (j == tpptrcnt)
  6807. debug_opcode_watch = false;
  6808. }
  6809. }
  6810. static int parsetrainerdata(const TCHAR *data, uae_u16 *outdata, uae_u16 *outmask)
  6811. {
  6812. int len = _tcslen(data);
  6813. uae_u16 v = 0, vm = 0;
  6814. int j = 0;
  6815. for (int i = 0; i < len; ) {
  6816. TCHAR c1 = _totupper(data[i + 0]);
  6817. TCHAR c2 = _totupper(data[i + 1]);
  6818. if (c1 > 0 && c1 <= ' ') {
  6819. i++;
  6820. continue;
  6821. }
  6822. if (i + 1 >= len)
  6823. return 0;
  6824. vm <<= 8;
  6825. vm |= 0xff;
  6826. if (c1 == 'X' || c1 == '?')
  6827. vm &= 0x0f;
  6828. if (c2 == 'X' || c2 == '?')
  6829. vm &= 0xf0;
  6830. if (c1 >= 'A')
  6831. c1 -= 'A' - 10;
  6832. else if (c1 >= '0')
  6833. c1 -= '0';
  6834. if (c2 >= 'A')
  6835. c2 -= 'A' - 10;
  6836. else if (c2 >= '0')
  6837. c2 -= '0';
  6838. v <<= 8;
  6839. if (c1 >= 0 && c1 < 16)
  6840. v |= c1 << 4;
  6841. if (c2 >= 0 && c2 < 16)
  6842. v |= c2;
  6843. if (i & 2) {
  6844. outdata[j] = v;
  6845. outmask[j] = vm;
  6846. j++;
  6847. }
  6848. i += 2;
  6849. }
  6850. return j;
  6851. }
  6852. void debug_init_trainer(const TCHAR *file)
  6853. {
  6854. TCHAR section[256];
  6855. int cnt = 1;
  6856. struct ini_data *ini = ini_load(file, false);
  6857. if (!ini)
  6858. return;
  6859. write_log(_T("Loaded '%s'\n"), file);
  6860. _tcscpy(section, _T("patch"));
  6861. for (;;) {
  6862. struct ini_context ictx;
  6863. ini_initcontext(ini, &ictx);
  6864. for (;;) {
  6865. TCHAR *name = NULL;
  6866. TCHAR *data;
  6867. ini_getstring_multi(ini, section, _T("name"), &name, &ictx);
  6868. if (!ini_getstring_multi(ini, section, _T("data"), &data, &ictx))
  6869. break;
  6870. ini_setcurrentasstart(ini, &ictx);
  6871. ini_setlast(ini, section, _T("data"), &ictx);
  6872. TCHAR *p = _tcschr(data, ';');
  6873. if (p)
  6874. *p = 0;
  6875. my_trim(data);
  6876. struct trainerpatch *tp = xcalloc(struct trainerpatch, 1);
  6877. int datalen = (_tcslen(data) + 3) / 4;
  6878. tp->data = xcalloc(uae_u16, datalen);
  6879. tp->maskdata = xcalloc(uae_u16, datalen);
  6880. tp->length = parsetrainerdata(data, tp->data, tp->maskdata);
  6881. xfree(data);
  6882. ini_getval_multi(ini, section, _T("offset"), &tp->offset, &ictx);
  6883. if (tp->offset < 0 || tp->offset >= tp->length)
  6884. tp->offset = 0;
  6885. if (ini_getstring_multi(ini, section, _T("replacedata"), &data, &ictx)) {
  6886. int replacedatalen = (_tcslen(data) + 3) / 4;
  6887. tp->replacedata = xcalloc(uae_u16, replacedatalen);
  6888. tp->replacemaskdata = xcalloc(uae_u16, replacedatalen);
  6889. tp->replacelength = parsetrainerdata(data, tp->replacedata, tp->replacemaskdata);
  6890. ini_getval_multi(ini, section, _T("replaceoffset"), &tp->offset, &ictx);
  6891. if (tp->replaceoffset < 0 || tp->replaceoffset >= tp->length)
  6892. tp->replaceoffset = 0;
  6893. tp->access = -1;
  6894. xfree(data);
  6895. }
  6896. tp->access = 2;
  6897. if (ini_getstring_multi(ini, section, _T("access"), &data, &ictx)) {
  6898. if (!_tcsicmp(data, _T("read")))
  6899. tp->access = 0;
  6900. else if (!_tcsicmp(data, _T("write")))
  6901. tp->access = 1;
  6902. xfree(data);
  6903. }
  6904. if (ini_getstring_multi(ini, section, _T("type"), &data, &ictx)) {
  6905. if (!_tcsicmp(data, _T("freeze")))
  6906. tp->patchtype = TRAINER_FREEZE;
  6907. else if (!_tcsicmp(data, _T("nop")))
  6908. tp->patchtype = TRAINER_NOP;
  6909. else if (!_tcsicmp(data, _T("set")))
  6910. tp->patchtype = TRAINER_SET;
  6911. else if (!_tcsicmp(data, _T("setonce")))
  6912. tp->patchtype = TRAINER_SETONCE;
  6913. xfree(data);
  6914. }
  6915. if (ini_getstring_multi(ini, section, _T("setvalue"), &data, &ictx)) {
  6916. TCHAR *endptr;
  6917. if (data[0] == '$') {
  6918. tp->setvalue = _tcstol(data + 1, &endptr, 16);
  6919. } else if (_tcslen(data) > 2 && data[0] == '0' && _totupper(data[1]) == 'x') {
  6920. tp->setvalue = _tcstol(data + 2, &endptr, 16);
  6921. } else {
  6922. tp->setvalue = _tcstol(data, &endptr, 10);
  6923. }
  6924. xfree(data);
  6925. }
  6926. if (ini_getstring(ini, section, _T("enable"), &data)) {
  6927. if (!_tcsicmp(data, _T("true")))
  6928. tp->enabledatstart = true;
  6929. xfree(data);
  6930. }
  6931. if (ini_getstring(ini, section, _T("event"), &data)) {
  6932. TCHAR *s = data;
  6933. _tcscat(s, _T(","));
  6934. while (*s) {
  6935. bool end = false;
  6936. while (*s == ' ')
  6937. s++;
  6938. TCHAR *se = _tcschr(s, ',');
  6939. if (se) {
  6940. *se = 0;
  6941. } else {
  6942. end = true;
  6943. }
  6944. TCHAR *se2 = se - 1;
  6945. while (se2 > s) {
  6946. if (*se2 != ' ')
  6947. break;
  6948. *se2 = 0;
  6949. se2--;
  6950. }
  6951. int evt = inputdevice_geteventid(s);
  6952. if (evt > 0) {
  6953. if (tp->events) {
  6954. tp->events = xrealloc(int, tp->events, tp->eventcount + 1);
  6955. } else {
  6956. tp->events = xmalloc(int, 1);
  6957. }
  6958. tp->events[tp->eventcount++] = evt;
  6959. } else {
  6960. write_log(_T("Unknown event '%s'\n"), s);
  6961. }
  6962. if (end)
  6963. break;
  6964. s = se + 1;
  6965. }
  6966. xfree(data);
  6967. }
  6968. tp->first = tp->data[tp->offset];
  6969. tp->name = name;
  6970. if (tpptrcnt)
  6971. tpptr = xrealloc(struct trainerpatch*, tpptr, tpptrcnt + 1);
  6972. else
  6973. tpptr = xcalloc(struct trainerpatch*, tpptrcnt + 1);
  6974. tpptr[tpptrcnt++] = tp;
  6975. write_log(_T("%d: '%s' parsed and enabled\n"), cnt, tp->name ? tp->name : _T("<no name>"));
  6976. cnt++;
  6977. ini_setlastasstart(ini, &ictx);
  6978. }
  6979. if (!ini_nextsection(ini, section))
  6980. break;
  6981. }
  6982. if (tpptrcnt > 0)
  6983. debug_opcode_watch = true;
  6984. ini_free(ini);
  6985. }
  6986. bool debug_trainer_event(int evt, int state)
  6987. {
  6988. for (int i = 0; i < tpptrcnt; i++) {
  6989. struct trainerpatch *tp = tpptr[i];
  6990. for (int j = 0; j < tp->eventcount; j++) {
  6991. if (tp->events[j] <= 0)
  6992. continue;
  6993. if (tp->events[j] == evt) {
  6994. if (!state)
  6995. return true;
  6996. write_log(_T("Trainer %d ('%s') -> %s\n"), i, tp->name, tp->enabled ? _T("off") : _T("on"));
  6997. debug_trainer_enable(tp, !tp->enabled);
  6998. return true;
  6999. }
  7000. }
  7001. }
  7002. return false;
  7003. }
  7004. bool debug_get_prefetch(int idx, uae_u16 *opword)
  7005. {
  7006. if (currprefs.cpu_compatible) {
  7007. if (currprefs.cpu_model < 68020) {
  7008. if (idx == 0) {
  7009. *opword = regs.ir;
  7010. return true;
  7011. }
  7012. if (idx == 1) {
  7013. *opword = regs.irc;
  7014. return true;
  7015. }
  7016. *opword = get_word_debug(m68k_getpc() + idx * 2);
  7017. return false;
  7018. } else {
  7019. if (regs.prefetch020_valid[idx]) {
  7020. *opword = regs.prefetch020[idx];
  7021. return true;
  7022. }
  7023. *opword = get_word_debug(m68k_getpc() + idx * 2);
  7024. return false;
  7025. }
  7026. } else {
  7027. *opword = get_word_debug(m68k_getpc() + idx * 2);
  7028. return false;
  7029. }
  7030. }
  7031. #define DEBUGSPRINTF_SIZE 32
  7032. static int debugsprintf_cnt;
  7033. struct dsprintfstack
  7034. {
  7035. uae_u32 val;
  7036. int size;
  7037. };
  7038. static dsprintfstack debugsprintf_stack[DEBUGSPRINTF_SIZE];
  7039. static uae_u16 debugsprintf_latch, debugsprintf_latched;
  7040. static uae_u32 debugsprintf_cycles, debugsprintf_cycles_set;
  7041. static uaecptr debugsprintf_va;
  7042. static int debugsprintf_mode;
  7043. static void read_bstring(char *out, int max, uae_u32 addr)
  7044. {
  7045. out[0] = 0;
  7046. if (!valid_address(addr, 1))
  7047. return;
  7048. uae_u8 l = get_byte(addr);
  7049. if (l > max)
  7050. l = max;
  7051. addr++;
  7052. for (int i = 0; i < l && i < max; i++) {
  7053. uae_u8 c = 0;
  7054. if (valid_address(addr, 1)) {
  7055. c = get_byte(addr);
  7056. }
  7057. if (c == 0) {
  7058. c = '.';
  7059. }
  7060. addr++;
  7061. out[i] = c;
  7062. out[i + 1] = 0;
  7063. }
  7064. }
  7065. static void read_string(char *out, int max, uae_u32 addr)
  7066. {
  7067. out[0] = 0;
  7068. for (int i = 0; i < max; i++) {
  7069. uae_u8 c = 0;
  7070. if (valid_address(addr, 1)) {
  7071. c = get_byte(addr);
  7072. }
  7073. addr++;
  7074. out[i] = c;
  7075. out[i + 1] = 0;
  7076. if (!c)
  7077. break;
  7078. }
  7079. }
  7080. static void parse_custom(char *out, int buffersize, char *format, char *p, char c)
  7081. {
  7082. bool gotv = false;
  7083. bool gots = false;
  7084. out[0] = 0;
  7085. uae_u32 v = 0;
  7086. char s[256];
  7087. if (!strcmp(p, "CYCLES")) {
  7088. if (debugsprintf_cycles_set) {
  7089. v = (get_cycles() - debugsprintf_cycles) / CYCLE_UNIT;
  7090. } else {
  7091. v = 0xffffffff;
  7092. }
  7093. gotv = true;
  7094. }
  7095. if (gotv) {
  7096. if (c == 'x' || c == 'X' || c == 'd' || c == 'i' || c == 'u' || c == 'o') {
  7097. char *fs = format + strlen(format);
  7098. *fs++ = c;
  7099. *fs = 0;
  7100. snprintf(out, buffersize, format, v);
  7101. } else {
  7102. strcpy(s, "****");
  7103. gots = true;
  7104. }
  7105. }
  7106. if (gots) {
  7107. char *fs = format + strlen(format);
  7108. *fs++ = 's';
  7109. *fs = 0;
  7110. snprintf(out, buffersize, format, s);
  7111. }
  7112. }
  7113. static uae_u32 get_value(struct dsprintfstack **stackp, uae_u32 *sizep, uaecptr *ptrp, uae_u32 size)
  7114. {
  7115. if (debugsprintf_mode) {
  7116. uae_u32 v;
  7117. uaecptr ptr = *ptrp;
  7118. if (size == sz_long) {
  7119. v = get_long_debug(ptr);
  7120. ptr += 4;
  7121. } else if (size == sz_word) {
  7122. v = get_word_debug(ptr);
  7123. ptr += 2;
  7124. } else {
  7125. v = get_byte_debug(ptr);
  7126. ptr++;
  7127. }
  7128. *ptrp = ptr;
  7129. *sizep = size;
  7130. return v;
  7131. } else {
  7132. struct dsprintfstack *stack = *stackp;
  7133. uae_u32 v = stack->val;
  7134. if (stack->size == 0)
  7135. v &= 0xff;
  7136. else if (stack->size == 1)
  7137. v &= 0xffff;
  7138. if (size == 1)
  7139. v &= 0xffff;
  7140. *sizep = size;
  7141. stack++;
  7142. *stackp = stack;
  7143. return v;
  7144. }
  7145. }
  7146. static void debug_sprintf_do(uae_u32 s)
  7147. {
  7148. int cnt = 0;
  7149. char format[MAX_DPATH];
  7150. char out[MAX_DPATH];
  7151. read_string(format, MAX_DPATH - 1, s);
  7152. char *p = format;
  7153. char *d = out;
  7154. bool gotm = false;
  7155. bool l = false;
  7156. uaecptr ptr = debugsprintf_va;
  7157. struct dsprintfstack *stack = debugsprintf_stack;
  7158. char fstr[100], *fstrp;
  7159. int buffersize = MAX_DPATH - 1;
  7160. fstrp = fstr;
  7161. *d = 0;
  7162. for (;;) {
  7163. char c = *p++;
  7164. if (c == 0)
  7165. break;
  7166. if (gotm) {
  7167. bool got = false;
  7168. buffersize = MAX_DPATH - strlen(out);
  7169. if (buffersize <= 1)
  7170. break;
  7171. if (c == '%') {
  7172. *d++ = '%';
  7173. gotm = false;
  7174. } else if (c == 'l') {
  7175. l = true;
  7176. } else if (c == 'c') {
  7177. uae_u32 size;
  7178. uae_u32 val = get_value(&stack, &size, &ptr, l ? sz_long : sz_word);
  7179. *fstrp++ = c;
  7180. *fstrp = 0;
  7181. snprintf(d, buffersize, fstr, val);
  7182. got = true;
  7183. } else if (c == 'b') {
  7184. uae_u32 size;
  7185. uae_u32 val = get_value(&stack, &size, &ptr, sz_long);
  7186. char tmp[MAX_DPATH];
  7187. read_bstring(tmp, MAX_DPATH - 1, val);
  7188. *fstrp++ = 's';
  7189. *fstrp = 0;
  7190. snprintf(d, buffersize, fstr, tmp);
  7191. got = true;
  7192. } else if (c == 's') {
  7193. uae_u32 size;
  7194. uae_u32 val = get_value(&stack, &size, &ptr, sz_long);
  7195. char tmp[MAX_DPATH];
  7196. read_string(tmp, MAX_DPATH - 1, val);
  7197. *fstrp++ = c;
  7198. *fstrp = 0;
  7199. snprintf(d, buffersize, fstr, tmp);
  7200. got = true;
  7201. } else if (c == 'p') {
  7202. uae_u32 size;
  7203. uae_u32 val = get_value(&stack, &size, &ptr, sz_long);
  7204. snprintf(d, buffersize, "$%08x", val);
  7205. got = true;
  7206. } else if (c == 'x' || c == 'X' || c == 'd' || c == 'i' || c == 'u' || c == 'o') {
  7207. uae_u32 size;
  7208. uae_u32 val = get_value(&stack, &size, &ptr, l ? sz_long : sz_word);
  7209. if (c == 'd' || c == 'i') {
  7210. if (size == sz_word && (val & 0x8000)) {
  7211. val = (uae_s32)(uae_s16)val;
  7212. }
  7213. }
  7214. *fstrp++ = c;
  7215. *fstrp = 0;
  7216. snprintf(d, buffersize, fstr, val);
  7217. got = true;
  7218. } else if (c == '[') {
  7219. char *next = strchr(p, ']');
  7220. if (next && next[1]) {
  7221. char customout[MAX_DPATH];
  7222. customout[0] = 0;
  7223. *next = 0;
  7224. parse_custom(d, buffersize, fstr, p, next[1]);
  7225. p = next + 2;
  7226. got = true;
  7227. } else {
  7228. gotm = false;
  7229. }
  7230. } else {
  7231. if (fstrp - fstr < sizeof(fstr) - 1) {
  7232. *fstrp++ = c;
  7233. *fstrp = 0;
  7234. }
  7235. }
  7236. if (got) {
  7237. d += strlen(d);
  7238. gotm = false;
  7239. }
  7240. } else if (c == '%') {
  7241. l = false;
  7242. fstrp = fstr;
  7243. *fstrp++ = c;
  7244. *fstrp = 0;
  7245. gotm = true;
  7246. } else {
  7247. *d++ = c;
  7248. }
  7249. *d = 0;
  7250. }
  7251. write_log("%s", out);
  7252. }
  7253. bool debug_sprintf(uaecptr addr, uae_u32 val, int size)
  7254. {
  7255. if (!currprefs.debug_mem)
  7256. return false;
  7257. uae_u32 v = val;
  7258. if (size == sz_word && currprefs.cpu_model < 68020) {
  7259. v &= 0xffff;
  7260. if (!(addr & 2)) {
  7261. debugsprintf_latch = v;
  7262. debugsprintf_latched = 1;
  7263. } else if (debugsprintf_latched) {
  7264. v |= debugsprintf_latch << 16;
  7265. size = sz_long;
  7266. if (!(addr & 4) && debugsprintf_cnt > 0) {
  7267. debugsprintf_cnt--;
  7268. }
  7269. }
  7270. }
  7271. if (size != sz_word) {
  7272. debugsprintf_latched = 0;
  7273. }
  7274. if ((addr & (8 | 4)) == 4) {
  7275. if (size != sz_long)
  7276. return true;
  7277. debug_sprintf_do(v);
  7278. debugsprintf_cnt = 0;
  7279. debugsprintf_latched = 0;
  7280. debugsprintf_cycles = get_cycles();
  7281. debugsprintf_cycles_set = 1;
  7282. } else if ((addr & (8 | 4)) == 8) {
  7283. if (size != sz_long)
  7284. return true;
  7285. debugsprintf_va = val;
  7286. debugsprintf_mode = 1;
  7287. } else {
  7288. if (debugsprintf_cnt < DEBUGSPRINTF_SIZE) {
  7289. debugsprintf_stack[debugsprintf_cnt].val = v;
  7290. debugsprintf_stack[debugsprintf_cnt].size = size;
  7291. debugsprintf_cnt++;
  7292. }
  7293. debugsprintf_mode = 0;
  7294. }
  7295. return true;
  7296. }