/3rd_party/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
C++ | 11051 lines | 7632 code | 1358 blank | 2061 comment | 3191 complexity | 9168f24fe989eb6a6817a65e823725b7 MD5 | raw file
Possible License(s): LGPL-2.1, BSD-3-Clause, JSON, MPL-2.0-no-copyleft-exception, GPL-2.0, GPL-3.0, LGPL-3.0, BSD-2-Clause
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11// both before and after the DAG is legalized.
12//
13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14// primarily intended to handle simplification opportunities that are implicit
15// in the LLVM IR and exposed by the various codegen lowering phases.
16//
17//===----------------------------------------------------------------------===//
18
19#define DEBUG_TYPE "dagcombine"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/IR/DerivedTypes.h"
28#include "llvm/IR/Function.h"
29#include "llvm/IR/LLVMContext.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetLowering.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/Target/TargetRegisterInfo.h"
39#include "llvm/Target/TargetSubtargetInfo.h"
40#include <algorithm>
41using namespace llvm;
42
43STATISTIC(NodesCombined , "Number of dag nodes combined");
44STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
45STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
46STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
47STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48STATISTIC(SlicedLoads, "Number of load sliced");
49
50namespace {
51 static cl::opt<bool>
52 CombinerAA("combiner-alias-analysis", cl::Hidden,
53 cl::desc("Turn on alias analysis during testing"));
54
55 static cl::opt<bool>
56 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
57 cl::desc("Include global information in alias analysis"));
58
59 /// Hidden option to stress test load slicing, i.e., when this option
60 /// is enabled, load slicing bypasses most of its profitability guards.
61 static cl::opt<bool>
62 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
63 cl::desc("Bypass the profitability model of load "
64 "slicing"),
65 cl::init(false));
66
67//------------------------------ DAGCombiner ---------------------------------//
68
69 class DAGCombiner {
70 SelectionDAG &DAG;
71 const TargetLowering &TLI;
72 CombineLevel Level;
73 CodeGenOpt::Level OptLevel;
74 bool LegalOperations;
75 bool LegalTypes;
76 bool ForCodeSize;
77
78 // Worklist of all of the nodes that need to be simplified.
79 //
80 // This has the semantics that when adding to the worklist,
81 // the item added must be next to be processed. It should
82 // also only appear once. The naive approach to this takes
83 // linear time.
84 //
85 // To reduce the insert/remove time to logarithmic, we use
86 // a set and a vector to maintain our worklist.
87 //
88 // The set contains the items on the worklist, but does not
89 // maintain the order they should be visited.
90 //
91 // The vector maintains the order nodes should be visited, but may
92 // contain duplicate or removed nodes. When choosing a node to
93 // visit, we pop off the order stack until we find an item that is
94 // also in the contents set. All operations are O(log N).
95 SmallPtrSet<SDNode*, 64> WorkListContents;
96 SmallVector<SDNode*, 64> WorkListOrder;
97
98 // AA - Used for DAG load/store alias analysis.
99 AliasAnalysis &AA;
100
101 /// AddUsersToWorkList - When an instruction is simplified, add all users of
102 /// the instruction to the work lists because they might get more simplified
103 /// now.
104 ///
105 void AddUsersToWorkList(SDNode *N) {
106 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
107 UI != UE; ++UI)
108 AddToWorkList(*UI);
109 }
110
111 /// visit - call the node-specific routine that knows how to fold each
112 /// particular type of node.
113 SDValue visit(SDNode *N);
114
115 public:
116 /// AddToWorkList - Add to the work list making sure its instance is at the
117 /// back (next to be processed.)
118 void AddToWorkList(SDNode *N) {
119 WorkListContents.insert(N);
120 WorkListOrder.push_back(N);
121 }
122
123 /// removeFromWorkList - remove all instances of N from the worklist.
124 ///
125 void removeFromWorkList(SDNode *N) {
126 WorkListContents.erase(N);
127 }
128
129 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
130 bool AddTo = true);
131
132 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
133 return CombineTo(N, &Res, 1, AddTo);
134 }
135
136 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
137 bool AddTo = true) {
138 SDValue To[] = { Res0, Res1 };
139 return CombineTo(N, To, 2, AddTo);
140 }
141
142 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
143
144 private:
145
146 /// SimplifyDemandedBits - Check the specified integer node value to see if
147 /// it can be simplified or if things it uses can be simplified by bit
148 /// propagation. If so, return true.
149 bool SimplifyDemandedBits(SDValue Op) {
150 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
151 APInt Demanded = APInt::getAllOnesValue(BitWidth);
152 return SimplifyDemandedBits(Op, Demanded);
153 }
154
155 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
156
157 bool CombineToPreIndexedLoadStore(SDNode *N);
158 bool CombineToPostIndexedLoadStore(SDNode *N);
159 bool SliceUpLoad(SDNode *N);
160
161 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
162 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
163 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
164 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
165 SDValue PromoteIntBinOp(SDValue Op);
166 SDValue PromoteIntShiftOp(SDValue Op);
167 SDValue PromoteExtend(SDValue Op);
168 bool PromoteLoad(SDValue Op);
169
170 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
171 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
172 ISD::NodeType ExtType);
173
174 /// combine - call the node-specific routine that knows how to fold each
175 /// particular type of node. If that doesn't do anything, try the
176 /// target-specific DAG combines.
177 SDValue combine(SDNode *N);
178
179 // Visitation implementation - Implement dag node combining for different
180 // node types. The semantics are as follows:
181 // Return Value:
182 // SDValue.getNode() == 0 - No change was made
183 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
184 // otherwise - N should be replaced by the returned Operand.
185 //
186 SDValue visitTokenFactor(SDNode *N);
187 SDValue visitMERGE_VALUES(SDNode *N);
188 SDValue visitADD(SDNode *N);
189 SDValue visitSUB(SDNode *N);
190 SDValue visitADDC(SDNode *N);
191 SDValue visitSUBC(SDNode *N);
192 SDValue visitADDE(SDNode *N);
193 SDValue visitSUBE(SDNode *N);
194 SDValue visitMUL(SDNode *N);
195 SDValue visitSDIV(SDNode *N);
196 SDValue visitUDIV(SDNode *N);
197 SDValue visitSREM(SDNode *N);
198 SDValue visitUREM(SDNode *N);
199 SDValue visitMULHU(SDNode *N);
200 SDValue visitMULHS(SDNode *N);
201 SDValue visitSMUL_LOHI(SDNode *N);
202 SDValue visitUMUL_LOHI(SDNode *N);
203 SDValue visitSMULO(SDNode *N);
204 SDValue visitUMULO(SDNode *N);
205 SDValue visitSDIVREM(SDNode *N);
206 SDValue visitUDIVREM(SDNode *N);
207 SDValue visitAND(SDNode *N);
208 SDValue visitOR(SDNode *N);
209 SDValue visitXOR(SDNode *N);
210 SDValue SimplifyVBinOp(SDNode *N);
211 SDValue SimplifyVUnaryOp(SDNode *N);
212 SDValue visitSHL(SDNode *N);
213 SDValue visitSRA(SDNode *N);
214 SDValue visitSRL(SDNode *N);
215 SDValue visitCTLZ(SDNode *N);
216 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
217 SDValue visitCTTZ(SDNode *N);
218 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
219 SDValue visitCTPOP(SDNode *N);
220 SDValue visitSELECT(SDNode *N);
221 SDValue visitVSELECT(SDNode *N);
222 SDValue visitSELECT_CC(SDNode *N);
223 SDValue visitSETCC(SDNode *N);
224 SDValue visitSIGN_EXTEND(SDNode *N);
225 SDValue visitZERO_EXTEND(SDNode *N);
226 SDValue visitANY_EXTEND(SDNode *N);
227 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
228 SDValue visitTRUNCATE(SDNode *N);
229 SDValue visitBITCAST(SDNode *N);
230 SDValue visitBUILD_PAIR(SDNode *N);
231 SDValue visitFADD(SDNode *N);
232 SDValue visitFSUB(SDNode *N);
233 SDValue visitFMUL(SDNode *N);
234 SDValue visitFMA(SDNode *N);
235 SDValue visitFDIV(SDNode *N);
236 SDValue visitFREM(SDNode *N);
237 SDValue visitFCOPYSIGN(SDNode *N);
238 SDValue visitSINT_TO_FP(SDNode *N);
239 SDValue visitUINT_TO_FP(SDNode *N);
240 SDValue visitFP_TO_SINT(SDNode *N);
241 SDValue visitFP_TO_UINT(SDNode *N);
242 SDValue visitFP_ROUND(SDNode *N);
243 SDValue visitFP_ROUND_INREG(SDNode *N);
244 SDValue visitFP_EXTEND(SDNode *N);
245 SDValue visitFNEG(SDNode *N);
246 SDValue visitFABS(SDNode *N);
247 SDValue visitFCEIL(SDNode *N);
248 SDValue visitFTRUNC(SDNode *N);
249 SDValue visitFFLOOR(SDNode *N);
250 SDValue visitBRCOND(SDNode *N);
251 SDValue visitBR_CC(SDNode *N);
252 SDValue visitLOAD(SDNode *N);
253 SDValue visitSTORE(SDNode *N);
254 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
255 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
256 SDValue visitBUILD_VECTOR(SDNode *N);
257 SDValue visitCONCAT_VECTORS(SDNode *N);
258 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
259 SDValue visitVECTOR_SHUFFLE(SDNode *N);
260
261 SDValue XformToShuffleWithZero(SDNode *N);
262 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
263
264 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
265
266 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
267 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
268 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
269 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
270 SDValue N3, ISD::CondCode CC,
271 bool NotExtCompare = false);
272 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
273 SDLoc DL, bool foldBooleans = true);
274 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
275 unsigned HiOp);
276 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
277 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
278 SDValue BuildSDIV(SDNode *N);
279 SDValue BuildUDIV(SDNode *N);
280 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
281 bool DemandHighBits = true);
282 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
283 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
284 SDValue ReduceLoadWidth(SDNode *N);
285 SDValue ReduceLoadOpStoreWidth(SDNode *N);
286 SDValue TransformFPLoadStorePair(SDNode *N);
287 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
288 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
289
290 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
291
292 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
293 /// looking for aliasing nodes and adding them to the Aliases vector.
294 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
295 SmallVectorImpl<SDValue> &Aliases);
296
297 /// isAlias - Return true if there is any possibility that the two addresses
298 /// overlap.
299 bool isAlias(SDValue Ptr1, int64_t Size1, bool IsVolatile1,
300 const Value *SrcValue1, int SrcValueOffset1,
301 unsigned SrcValueAlign1,
302 const MDNode *TBAAInfo1,
303 SDValue Ptr2, int64_t Size2, bool IsVolatile2,
304 const Value *SrcValue2, int SrcValueOffset2,
305 unsigned SrcValueAlign2,
306 const MDNode *TBAAInfo2) const;
307
308 /// isAlias - Return true if there is any possibility that the two addresses
309 /// overlap.
310 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
311
312 /// FindAliasInfo - Extracts the relevant alias information from the memory
313 /// node. Returns true if the operand was a load.
314 bool FindAliasInfo(SDNode *N,
315 SDValue &Ptr, int64_t &Size, bool &IsVolatile,
316 const Value *&SrcValue, int &SrcValueOffset,
317 unsigned &SrcValueAlignment,
318 const MDNode *&TBAAInfo) const;
319
320 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
321 /// looking for a better chain (aliasing node.)
322 SDValue FindBetterChain(SDNode *N, SDValue Chain);
323
324 /// Merge consecutive store operations into a wide store.
325 /// This optimization uses wide integers or vectors when possible.
326 /// \return True if some memory operations were changed.
327 bool MergeConsecutiveStores(StoreSDNode *N);
328
329 public:
330 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
331 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
332 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
333 AttributeSet FnAttrs =
334 DAG.getMachineFunction().getFunction()->getAttributes();
335 ForCodeSize =
336 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
337 Attribute::OptimizeForSize) ||
338 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
339 }
340
341 /// Run - runs the dag combiner on all nodes in the work list
342 void Run(CombineLevel AtLevel);
343
344 SelectionDAG &getDAG() const { return DAG; }
345
346 /// getShiftAmountTy - Returns a type large enough to hold any valid
347 /// shift amount - before type legalization these can be huge.
348 EVT getShiftAmountTy(EVT LHSTy) {
349 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
350 if (LHSTy.isVector())
351 return LHSTy;
352 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
353 : TLI.getPointerTy();
354 }
355
356 /// isTypeLegal - This method returns true if we are running before type
357 /// legalization or if the specified VT is legal.
358 bool isTypeLegal(const EVT &VT) {
359 if (!LegalTypes) return true;
360 return TLI.isTypeLegal(VT);
361 }
362
363 /// getSetCCResultType - Convenience wrapper around
364 /// TargetLowering::getSetCCResultType
365 EVT getSetCCResultType(EVT VT) const {
366 return TLI.getSetCCResultType(*DAG.getContext(), VT);
367 }
368 };
369}
370
371
372namespace {
373/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
374/// nodes from the worklist.
375class WorkListRemover : public SelectionDAG::DAGUpdateListener {
376 DAGCombiner &DC;
377public:
378 explicit WorkListRemover(DAGCombiner &dc)
379 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
380
381 virtual void NodeDeleted(SDNode *N, SDNode *E) {
382 DC.removeFromWorkList(N);
383 }
384};
385}
386
387//===----------------------------------------------------------------------===//
388// TargetLowering::DAGCombinerInfo implementation
389//===----------------------------------------------------------------------===//
390
391void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
392 ((DAGCombiner*)DC)->AddToWorkList(N);
393}
394
395void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
396 ((DAGCombiner*)DC)->removeFromWorkList(N);
397}
398
399SDValue TargetLowering::DAGCombinerInfo::
400CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
401 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
402}
403
404SDValue TargetLowering::DAGCombinerInfo::
405CombineTo(SDNode *N, SDValue Res, bool AddTo) {
406 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
407}
408
409
410SDValue TargetLowering::DAGCombinerInfo::
411CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
412 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
413}
414
415void TargetLowering::DAGCombinerInfo::
416CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
417 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
418}
419
420//===----------------------------------------------------------------------===//
421// Helper Functions
422//===----------------------------------------------------------------------===//
423
424/// isNegatibleForFree - Return 1 if we can compute the negated form of the
425/// specified expression for the same cost as the expression itself, or 2 if we
426/// can compute the negated form more cheaply than the expression itself.
427static char isNegatibleForFree(SDValue Op, bool LegalOperations,
428 const TargetLowering &TLI,
429 const TargetOptions *Options,
430 unsigned Depth = 0) {
431 // fneg is removable even if it has multiple uses.
432 if (Op.getOpcode() == ISD::FNEG) return 2;
433
434 // Don't allow anything with multiple uses.
435 if (!Op.hasOneUse()) return 0;
436
437 // Don't recurse exponentially.
438 if (Depth > 6) return 0;
439
440 switch (Op.getOpcode()) {
441 default: return false;
442 case ISD::ConstantFP:
443 // Don't invert constant FP values after legalize. The negated constant
444 // isn't necessarily legal.
445 return LegalOperations ? 0 : 1;
446 case ISD::FADD:
447 // FIXME: determine better conditions for this xform.
448 if (!Options->UnsafeFPMath) return 0;
449
450 // After operation legalization, it might not be legal to create new FSUBs.
451 if (LegalOperations &&
452 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
453 return 0;
454
455 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
456 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
457 Options, Depth + 1))
458 return V;
459 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
460 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
461 Depth + 1);
462 case ISD::FSUB:
463 // We can't turn -(A-B) into B-A when we honor signed zeros.
464 if (!Options->UnsafeFPMath) return 0;
465
466 // fold (fneg (fsub A, B)) -> (fsub B, A)
467 return 1;
468
469 case ISD::FMUL:
470 case ISD::FDIV:
471 if (Options->HonorSignDependentRoundingFPMath()) return 0;
472
473 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
474 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
475 Options, Depth + 1))
476 return V;
477
478 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
479 Depth + 1);
480
481 case ISD::FP_EXTEND:
482 case ISD::FP_ROUND:
483 case ISD::FSIN:
484 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
485 Depth + 1);
486 }
487}
488
489/// GetNegatedExpression - If isNegatibleForFree returns true, this function
490/// returns the newly negated expression.
491static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
492 bool LegalOperations, unsigned Depth = 0) {
493 // fneg is removable even if it has multiple uses.
494 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
495
496 // Don't allow anything with multiple uses.
497 assert(Op.hasOneUse() && "Unknown reuse!");
498
499 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
500 switch (Op.getOpcode()) {
501 default: llvm_unreachable("Unknown code");
502 case ISD::ConstantFP: {
503 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
504 V.changeSign();
505 return DAG.getConstantFP(V, Op.getValueType());
506 }
507 case ISD::FADD:
508 // FIXME: determine better conditions for this xform.
509 assert(DAG.getTarget().Options.UnsafeFPMath);
510
511 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
512 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
513 DAG.getTargetLoweringInfo(),
514 &DAG.getTarget().Options, Depth+1))
515 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
516 GetNegatedExpression(Op.getOperand(0), DAG,
517 LegalOperations, Depth+1),
518 Op.getOperand(1));
519 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
520 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
521 GetNegatedExpression(Op.getOperand(1), DAG,
522 LegalOperations, Depth+1),
523 Op.getOperand(0));
524 case ISD::FSUB:
525 // We can't turn -(A-B) into B-A when we honor signed zeros.
526 assert(DAG.getTarget().Options.UnsafeFPMath);
527
528 // fold (fneg (fsub 0, B)) -> B
529 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
530 if (N0CFP->getValueAPF().isZero())
531 return Op.getOperand(1);
532
533 // fold (fneg (fsub A, B)) -> (fsub B, A)
534 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
535 Op.getOperand(1), Op.getOperand(0));
536
537 case ISD::FMUL:
538 case ISD::FDIV:
539 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
540
541 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
542 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
543 DAG.getTargetLoweringInfo(),
544 &DAG.getTarget().Options, Depth+1))
545 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
546 GetNegatedExpression(Op.getOperand(0), DAG,
547 LegalOperations, Depth+1),
548 Op.getOperand(1));
549
550 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
551 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
552 Op.getOperand(0),
553 GetNegatedExpression(Op.getOperand(1), DAG,
554 LegalOperations, Depth+1));
555
556 case ISD::FP_EXTEND:
557 case ISD::FSIN:
558 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
559 GetNegatedExpression(Op.getOperand(0), DAG,
560 LegalOperations, Depth+1));
561 case ISD::FP_ROUND:
562 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
563 GetNegatedExpression(Op.getOperand(0), DAG,
564 LegalOperations, Depth+1),
565 Op.getOperand(1));
566 }
567}
568
569
570// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
571// that selects between the values 1 and 0, making it equivalent to a setcc.
572// Also, set the incoming LHS, RHS, and CC references to the appropriate
573// nodes based on the type of node we are checking. This simplifies life a
574// bit for the callers.
575static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
576 SDValue &CC) {
577 if (N.getOpcode() == ISD::SETCC) {
578 LHS = N.getOperand(0);
579 RHS = N.getOperand(1);
580 CC = N.getOperand(2);
581 return true;
582 }
583 if (N.getOpcode() == ISD::SELECT_CC &&
584 N.getOperand(2).getOpcode() == ISD::Constant &&
585 N.getOperand(3).getOpcode() == ISD::Constant &&
586 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
587 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
588 LHS = N.getOperand(0);
589 RHS = N.getOperand(1);
590 CC = N.getOperand(4);
591 return true;
592 }
593 return false;
594}
595
596// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
597// one use. If this is true, it allows the users to invert the operation for
598// free when it is profitable to do so.
599static bool isOneUseSetCC(SDValue N) {
600 SDValue N0, N1, N2;
601 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
602 return true;
603 return false;
604}
605
606SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
607 SDValue N0, SDValue N1) {
608 EVT VT = N0.getValueType();
609 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
610 if (isa<ConstantSDNode>(N1)) {
611 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
612 SDValue OpNode =
613 DAG.FoldConstantArithmetic(Opc, VT,
614 cast<ConstantSDNode>(N0.getOperand(1)),
615 cast<ConstantSDNode>(N1));
616 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
617 }
618 if (N0.hasOneUse()) {
619 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
620 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
621 N0.getOperand(0), N1);
622 AddToWorkList(OpNode.getNode());
623 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
624 }
625 }
626
627 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
628 if (isa<ConstantSDNode>(N0)) {
629 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
630 SDValue OpNode =
631 DAG.FoldConstantArithmetic(Opc, VT,
632 cast<ConstantSDNode>(N1.getOperand(1)),
633 cast<ConstantSDNode>(N0));
634 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
635 }
636 if (N1.hasOneUse()) {
637 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
638 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
639 N1.getOperand(0), N0);
640 AddToWorkList(OpNode.getNode());
641 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
642 }
643 }
644
645 return SDValue();
646}
647
648SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
649 bool AddTo) {
650 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
651 ++NodesCombined;
652 DEBUG(dbgs() << "\nReplacing.1 ";
653 N->dump(&DAG);
654 dbgs() << "\nWith: ";
655 To[0].getNode()->dump(&DAG);
656 dbgs() << " and " << NumTo-1 << " other values\n";
657 for (unsigned i = 0, e = NumTo; i != e; ++i)
658 assert((!To[i].getNode() ||
659 N->getValueType(i) == To[i].getValueType()) &&
660 "Cannot combine value to value of different type!"));
661 WorkListRemover DeadNodes(*this);
662 DAG.ReplaceAllUsesWith(N, To);
663 if (AddTo) {
664 // Push the new nodes and any users onto the worklist
665 for (unsigned i = 0, e = NumTo; i != e; ++i) {
666 if (To[i].getNode()) {
667 AddToWorkList(To[i].getNode());
668 AddUsersToWorkList(To[i].getNode());
669 }
670 }
671 }
672
673 // Finally, if the node is now dead, remove it from the graph. The node
674 // may not be dead if the replacement process recursively simplified to
675 // something else needing this node.
676 if (N->use_empty()) {
677 // Nodes can be reintroduced into the worklist. Make sure we do not
678 // process a node that has been replaced.
679 removeFromWorkList(N);
680
681 // Finally, since the node is now dead, remove it from the graph.
682 DAG.DeleteNode(N);
683 }
684 return SDValue(N, 0);
685}
686
687void DAGCombiner::
688CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
689 // Replace all uses. If any nodes become isomorphic to other nodes and
690 // are deleted, make sure to remove them from our worklist.
691 WorkListRemover DeadNodes(*this);
692 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
693
694 // Push the new node and any (possibly new) users onto the worklist.
695 AddToWorkList(TLO.New.getNode());
696 AddUsersToWorkList(TLO.New.getNode());
697
698 // Finally, if the node is now dead, remove it from the graph. The node
699 // may not be dead if the replacement process recursively simplified to
700 // something else needing this node.
701 if (TLO.Old.getNode()->use_empty()) {
702 removeFromWorkList(TLO.Old.getNode());
703
704 // If the operands of this node are only used by the node, they will now
705 // be dead. Make sure to visit them first to delete dead nodes early.
706 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
707 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
708 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
709
710 DAG.DeleteNode(TLO.Old.getNode());
711 }
712}
713
714/// SimplifyDemandedBits - Check the specified integer node value to see if
715/// it can be simplified or if things it uses can be simplified by bit
716/// propagation. If so, return true.
717bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
718 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
719 APInt KnownZero, KnownOne;
720 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
721 return false;
722
723 // Revisit the node.
724 AddToWorkList(Op.getNode());
725
726 // Replace the old value with the new one.
727 ++NodesCombined;
728 DEBUG(dbgs() << "\nReplacing.2 ";
729 TLO.Old.getNode()->dump(&DAG);
730 dbgs() << "\nWith: ";
731 TLO.New.getNode()->dump(&DAG);
732 dbgs() << '\n');
733
734 CommitTargetLoweringOpt(TLO);
735 return true;
736}
737
738void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
739 SDLoc dl(Load);
740 EVT VT = Load->getValueType(0);
741 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
742
743 DEBUG(dbgs() << "\nReplacing.9 ";
744 Load->dump(&DAG);
745 dbgs() << "\nWith: ";
746 Trunc.getNode()->dump(&DAG);
747 dbgs() << '\n');
748 WorkListRemover DeadNodes(*this);
749 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
750 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
751 removeFromWorkList(Load);
752 DAG.DeleteNode(Load);
753 AddToWorkList(Trunc.getNode());
754}
755
756SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
757 Replace = false;
758 SDLoc dl(Op);
759 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
760 EVT MemVT = LD->getMemoryVT();
761 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
762 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
763 : ISD::EXTLOAD)
764 : LD->getExtensionType();
765 Replace = true;
766 return DAG.getExtLoad(ExtType, dl, PVT,
767 LD->getChain(), LD->getBasePtr(),
768 MemVT, LD->getMemOperand());
769 }
770
771 unsigned Opc = Op.getOpcode();
772 switch (Opc) {
773 default: break;
774 case ISD::AssertSext:
775 return DAG.getNode(ISD::AssertSext, dl, PVT,
776 SExtPromoteOperand(Op.getOperand(0), PVT),
777 Op.getOperand(1));
778 case ISD::AssertZext:
779 return DAG.getNode(ISD::AssertZext, dl, PVT,
780 ZExtPromoteOperand(Op.getOperand(0), PVT),
781 Op.getOperand(1));
782 case ISD::Constant: {
783 unsigned ExtOpc =
784 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
785 return DAG.getNode(ExtOpc, dl, PVT, Op);
786 }
787 }
788
789 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
790 return SDValue();
791 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
792}
793
794SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
795 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
796 return SDValue();
797 EVT OldVT = Op.getValueType();
798 SDLoc dl(Op);
799 bool Replace = false;
800 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
801 if (NewOp.getNode() == 0)
802 return SDValue();
803 AddToWorkList(NewOp.getNode());
804
805 if (Replace)
806 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
807 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
808 DAG.getValueType(OldVT));
809}
810
811SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
812 EVT OldVT = Op.getValueType();
813 SDLoc dl(Op);
814 bool Replace = false;
815 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
816 if (NewOp.getNode() == 0)
817 return SDValue();
818 AddToWorkList(NewOp.getNode());
819
820 if (Replace)
821 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
822 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
823}
824
825/// PromoteIntBinOp - Promote the specified integer binary operation if the
826/// target indicates it is beneficial. e.g. On x86, it's usually better to
827/// promote i16 operations to i32 since i16 instructions are longer.
828SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
829 if (!LegalOperations)
830 return SDValue();
831
832 EVT VT = Op.getValueType();
833 if (VT.isVector() || !VT.isInteger())
834 return SDValue();
835
836 // If operation type is 'undesirable', e.g. i16 on x86, consider
837 // promoting it.
838 unsigned Opc = Op.getOpcode();
839 if (TLI.isTypeDesirableForOp(Opc, VT))
840 return SDValue();
841
842 EVT PVT = VT;
843 // Consult target whether it is a good idea to promote this operation and
844 // what's the right type to promote it to.
845 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
846 assert(PVT != VT && "Don't know what type to promote to!");
847
848 bool Replace0 = false;
849 SDValue N0 = Op.getOperand(0);
850 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
851 if (NN0.getNode() == 0)
852 return SDValue();
853
854 bool Replace1 = false;
855 SDValue N1 = Op.getOperand(1);
856 SDValue NN1;
857 if (N0 == N1)
858 NN1 = NN0;
859 else {
860 NN1 = PromoteOperand(N1, PVT, Replace1);
861 if (NN1.getNode() == 0)
862 return SDValue();
863 }
864
865 AddToWorkList(NN0.getNode());
866 if (NN1.getNode())
867 AddToWorkList(NN1.getNode());
868
869 if (Replace0)
870 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
871 if (Replace1)
872 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
873
874 DEBUG(dbgs() << "\nPromoting ";
875 Op.getNode()->dump(&DAG));
876 SDLoc dl(Op);
877 return DAG.getNode(ISD::TRUNCATE, dl, VT,
878 DAG.getNode(Opc, dl, PVT, NN0, NN1));
879 }
880 return SDValue();
881}
882
883/// PromoteIntShiftOp - Promote the specified integer shift operation if the
884/// target indicates it is beneficial. e.g. On x86, it's usually better to
885/// promote i16 operations to i32 since i16 instructions are longer.
886SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
887 if (!LegalOperations)
888 return SDValue();
889
890 EVT VT = Op.getValueType();
891 if (VT.isVector() || !VT.isInteger())
892 return SDValue();
893
894 // If operation type is 'undesirable', e.g. i16 on x86, consider
895 // promoting it.
896 unsigned Opc = Op.getOpcode();
897 if (TLI.isTypeDesirableForOp(Opc, VT))
898 return SDValue();
899
900 EVT PVT = VT;
901 // Consult target whether it is a good idea to promote this operation and
902 // what's the right type to promote it to.
903 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
904 assert(PVT != VT && "Don't know what type to promote to!");
905
906 bool Replace = false;
907 SDValue N0 = Op.getOperand(0);
908 if (Opc == ISD::SRA)
909 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
910 else if (Opc == ISD::SRL)
911 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
912 else
913 N0 = PromoteOperand(N0, PVT, Replace);
914 if (N0.getNode() == 0)
915 return SDValue();
916
917 AddToWorkList(N0.getNode());
918 if (Replace)
919 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
920
921 DEBUG(dbgs() << "\nPromoting ";
922 Op.getNode()->dump(&DAG));
923 SDLoc dl(Op);
924 return DAG.getNode(ISD::TRUNCATE, dl, VT,
925 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
926 }
927 return SDValue();
928}
929
930SDValue DAGCombiner::PromoteExtend(SDValue Op) {
931 if (!LegalOperations)
932 return SDValue();
933
934 EVT VT = Op.getValueType();
935 if (VT.isVector() || !VT.isInteger())
936 return SDValue();
937
938 // If operation type is 'undesirable', e.g. i16 on x86, consider
939 // promoting it.
940 unsigned Opc = Op.getOpcode();
941 if (TLI.isTypeDesirableForOp(Opc, VT))
942 return SDValue();
943
944 EVT PVT = VT;
945 // Consult target whether it is a good idea to promote this operation and
946 // what's the right type to promote it to.
947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
948 assert(PVT != VT && "Don't know what type to promote to!");
949 // fold (aext (aext x)) -> (aext x)
950 // fold (aext (zext x)) -> (zext x)
951 // fold (aext (sext x)) -> (sext x)
952 DEBUG(dbgs() << "\nPromoting ";
953 Op.getNode()->dump(&DAG));
954 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
955 }
956 return SDValue();
957}
958
959bool DAGCombiner::PromoteLoad(SDValue Op) {
960 if (!LegalOperations)
961 return false;
962
963 EVT VT = Op.getValueType();
964 if (VT.isVector() || !VT.isInteger())
965 return false;
966
967 // If operation type is 'undesirable', e.g. i16 on x86, consider
968 // promoting it.
969 unsigned Opc = Op.getOpcode();
970 if (TLI.isTypeDesirableForOp(Opc, VT))
971 return false;
972
973 EVT PVT = VT;
974 // Consult target whether it is a good idea to promote this operation and
975 // what's the right type to promote it to.
976 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
977 assert(PVT != VT && "Don't know what type to promote to!");
978
979 SDLoc dl(Op);
980 SDNode *N = Op.getNode();
981 LoadSDNode *LD = cast<LoadSDNode>(N);
982 EVT MemVT = LD->getMemoryVT();
983 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
984 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
985 : ISD::EXTLOAD)
986 : LD->getExtensionType();
987 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
988 LD->getChain(), LD->getBasePtr(),
989 MemVT, LD->getMemOperand());
990 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
991
992 DEBUG(dbgs() << "\nPromoting ";
993 N->dump(&DAG);
994 dbgs() << "\nTo: ";
995 Result.getNode()->dump(&DAG);
996 dbgs() << '\n');
997 WorkListRemover DeadNodes(*this);
998 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
999 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1000 removeFromWorkList(N);
1001 DAG.DeleteNode(N);
1002 AddToWorkList(Result.getNode());
1003 return true;
1004 }
1005 return false;
1006}
1007
1008
1009//===----------------------------------------------------------------------===//
1010// Main DAG Combiner implementation
1011//===----------------------------------------------------------------------===//
1012
1013void DAGCombiner::Run(CombineLevel AtLevel) {
1014 // set the instance variables, so that the various visit routines may use it.
1015 Level = AtLevel;
1016 LegalOperations = Level >= AfterLegalizeVectorOps;
1017 LegalTypes = Level >= AfterLegalizeTypes;
1018
1019 // Add all the dag nodes to the worklist.
1020 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1021 E = DAG.allnodes_end(); I != E; ++I)
1022 AddToWorkList(I);
1023
1024 // Create a dummy node (which is not added to allnodes), that adds a reference
1025 // to the root node, preventing it from being deleted, and tracking any
1026 // changes of the root.
1027 HandleSDNode Dummy(DAG.getRoot());
1028
1029 // The root of the dag may dangle to deleted nodes until the dag combiner is
1030 // done. Set it to null to avoid confusion.
1031 DAG.setRoot(SDValue());
1032
1033 // while the worklist isn't empty, find a node and
1034 // try and combine it.
1035 while (!WorkListContents.empty()) {
1036 SDNode *N;
1037 // The WorkListOrder holds the SDNodes in order, but it may contain
1038 // duplicates.
1039 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1040 // worklist *should* contain, and check the node we want to visit is should
1041 // actually be visited.
1042 do {
1043 N = WorkListOrder.pop_back_val();
1044 } while (!WorkListContents.erase(N));
1045
1046 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1047 // N is deleted from the DAG, since they too may now be dead or may have a
1048 // reduced number of uses, allowing other xforms.
1049 if (N->use_empty() && N != &Dummy) {
1050 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1051 AddToWorkList(N->getOperand(i).getNode());
1052
1053 DAG.DeleteNode(N);
1054 continue;
1055 }
1056
1057 SDValue RV = combine(N);
1058
1059 if (RV.getNode() == 0)
1060 continue;
1061
1062 ++NodesCombined;
1063
1064 // If we get back the same node we passed in, rather than a new node or
1065 // zero, we know that the node must have defined multiple values and
1066 // CombineTo was used. Since CombineTo takes care of the worklist
1067 // mechanics for us, we have no work to do in this case.
1068 if (RV.getNode() == N)
1069 continue;
1070
1071 assert(N->getOpcode() != ISD::DELETED_NODE &&
1072 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1073 "Node was deleted but visit returned new node!");
1074
1075 DEBUG(dbgs() << "\nReplacing.3 ";
1076 N->dump(&DAG);
1077 dbgs() << "\nWith: ";
1078 RV.getNode()->dump(&DAG);
1079 dbgs() << '\n');
1080
1081 // Transfer debug value.
1082 DAG.TransferDbgValues(SDValue(N, 0), RV);
1083 WorkListRemover DeadNodes(*this);
1084 if (N->getNumValues() == RV.getNode()->getNumValues())
1085 DAG.ReplaceAllUsesWith(N, RV.getNode());
1086 else {
1087 assert(N->getValueType(0) == RV.getValueType() &&
1088 N->getNumValues() == 1 && "Type mismatch");
1089 SDValue OpV = RV;
1090 DAG.ReplaceAllUsesWith(N, &OpV);
1091 }
1092
1093 // Push the new node and any users onto the worklist
1094 AddToWorkList(RV.getNode());
1095 AddUsersToWorkList(RV.getNode());
1096
1097 // Add any uses of the old node to the worklist in case this node is the
1098 // last one that uses them. They may become dead after this node is
1099 // deleted.
1100 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1101 AddToWorkList(N->getOperand(i).getNode());
1102
1103 // Finally, if the node is now dead, remove it from the graph. The node
1104 // may not be dead if the replacement process recursively simplified to
1105 // something else needing this node.
1106 if (N->use_empty()) {
1107 // Nodes can be reintroduced into the worklist. Make sure we do not
1108 // process a node that has been replaced.
1109 removeFromWorkList(N);
1110
1111 // Finally, since the node is now dead, remove it from the graph.
1112 DAG.DeleteNode(N);
1113 }
1114 }
1115
1116 // If the root changed (e.g. it was a dead load, update the root).
1117 DAG.setRoot(Dummy.getValue());
1118 DAG.RemoveDeadNodes();
1119}
1120
1121SDValue DAGCombiner::visit(SDNode *N) {
1122 switch (N->getOpcode()) {
1123 default: break;
1124 case ISD::TokenFactor: return visitTokenFactor(N);
1125 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1126 case ISD::ADD: return visitADD(N);
1127 case ISD::SUB: return visitSUB(N);
1128 case ISD::ADDC: return visitADDC(N);
1129 case ISD::SUBC: return visitSUBC(N);
1130 case ISD::ADDE: return visitADDE(N);
1131 case ISD::SUBE: return visitSUBE(N);
1132 case ISD::MUL: return visitMUL(N);
1133 case ISD::SDIV: return visitSDIV(N);
1134 case ISD::UDIV: return visitUDIV(N);
1135 case ISD::SREM: return visitSREM(N);
1136 case ISD::UREM: return visitUREM(N);
1137 case ISD::MULHU: return visitMULHU(N);
1138 case ISD::MULHS: return visitMULHS(N);
1139 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1140 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1141 case ISD::SMULO: return visitSMULO(N);
1142 case ISD::UMULO: return visitUMULO(N);
1143 case ISD::SDIVREM: return visitSDIVREM(N);
1144 case ISD::UDIVREM: return visitUDIVREM(N);
1145 case ISD::AND: return visitAND(N);
1146 case ISD::OR: return visitOR(N);
1147 case ISD::XOR: return visitXOR(N);
1148 case ISD::SHL: return visitSHL(N);
1149 case ISD::SRA: return visitSRA(N);
1150 case ISD::SRL: return visitSRL(N);
1151 case ISD::CTLZ: return visitCTLZ(N);
1152 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1153 case ISD::CTTZ: return visitCTTZ(N);
1154 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1155 case ISD::CTPOP: return visitCTPOP(N);
1156 case ISD::SELECT: return visitSELECT(N);
1157 case ISD::VSELECT: return visitVSELECT(N);
1158 case ISD::SELECT_CC: return visitSELECT_CC(N);
1159 case ISD::SETCC: return visitSETCC(N);
1160 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1161 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1162 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1163 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1164 case ISD::TRUNCATE: return visitTRUNCATE(N);
1165 case ISD::BITCAST: return visitBITCAST(N);
1166 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1167 case ISD::FADD: return visitFADD(N);
1168 case ISD::FSUB: return visitFSUB(N);
1169 case ISD::FMUL: return visitFMUL(N);
1170 case ISD::FMA: return visitFMA(N);
1171 case ISD::FDIV: return visitFDIV(N);
1172 case ISD::FREM: return visitFREM(N);
1173 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1174 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1175 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1176 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1177 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1178 case ISD::FP_ROUND: return visitFP_ROUND(N);
1179 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1180 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1181 case ISD::FNEG: return visitFNEG(N);
1182 case ISD::FABS: return visitFABS(N);
1183 case ISD::FFLOOR: return visitFFLOOR(N);
1184 case ISD::FCEIL: return visitFCEIL(N);
1185 case ISD::FTRUNC: return visitFTRUNC(N);
1186 case ISD::BRCOND: return visitBRCOND(N);
1187 case ISD::BR_CC: return visitBR_CC(N);
1188 case ISD::LOAD: return visitLOAD(N);
1189 case ISD::STORE: return visitSTORE(N);
1190 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1191 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1192 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1193 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1194 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1195 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1196 }
1197 return SDValue();
1198}
1199
1200SDValue DAGCombiner::combine(SDNode *N) {
1201 SDValue RV = visit(N);
1202
1203 // If nothing happened, try a target-specific DAG combine.
1204 if (RV.getNode() == 0) {
1205 assert(N->getOpcode() != ISD::DELETED_NODE &&
1206 "Node was deleted but visit returned NULL!");
1207
1208 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1209 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1210
1211 // Expose the DAG combiner to the target combiner impls.
1212 TargetLowering::DAGCombinerInfo
1213 DagCombineInfo(DAG, Level, false, this);
1214
1215 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1216 }
1217 }
1218
1219 // If nothing happened still, try promoting the operation.
1220 if (RV.getNode() == 0) {
1221 switch (N->getOpcode()) {
1222 default: break;
1223 case ISD::ADD:
1224 case ISD::SUB:
1225 case ISD::MUL:
1226 case ISD::AND:
1227 case ISD::OR:
1228 case ISD::XOR:
1229 RV = PromoteIntBinOp(SDValue(N, 0));
1230 break;
1231 case ISD::SHL:
1232 case ISD::SRA:
1233 case ISD::SRL:
1234 RV = PromoteIntShiftOp(SDValue(N, 0));
1235 break;
1236 case ISD::SIGN_EXTEND:
1237 case ISD::ZERO_EXTEND:
1238 case ISD::ANY_EXTEND:
1239 RV = PromoteExtend(SDValue(N, 0));
1240 break;
1241 case ISD::LOAD:
1242 if (PromoteLoad(SDValue(N, 0)))
1243 RV = SDValue(N, 0);
1244 break;
1245 }
1246 }
1247
1248 // If N is a commutative binary node, try commuting it to enable more
1249 // sdisel CSE.
1250 if (RV.getNode() == 0 &&
1251 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1252 N->getNumValues() == 1) {
1253 SDValue N0 = N->getOperand(0);
1254 SDValue N1 = N->getOperand(1);
1255
1256 // Constant operands are canonicalized to RHS.
1257 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1258 SDValue Ops[] = { N1, N0 };
1259 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1260 Ops, 2);
1261 if (CSENode)
1262 return SDValue(CSENode, 0);
1263 }
1264 }
1265
1266 return RV;
1267}
1268
1269/// getInputChainForNode - Given a node, return its input chain if it has one,
1270/// otherwise return a null sd operand.
1271static SDValue getInputChainForNode(SDNode *N) {
1272 if (unsigned NumOps = N->getNumOperands()) {
1273 if (N->getOperand(0).getValueType() == MVT::Other)
1274 return N->getOperand(0);
1275 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1276 return N->getOperand(NumOps-1);
1277 for (unsigned i = 1; i < NumOps-1; ++i)
1278 if (N->getOperand(i).getValueType() == MVT::Other)
1279 return N->getOperand(i);
1280 }
1281 return SDValue();
1282}
1283
1284SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1285 // If N has two operands, where one has an input chain equal to the other,
1286 // the 'other' chain is redundant.
1287 if (N->getNumOperands() == 2) {
1288 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1289 return N->getOperand(0);
1290 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1291 return N->getOperand(1);
1292 }
1293
1294 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1295 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1296 SmallPtrSet<SDNode*, 16> SeenOps;
1297 bool Changed = false; // If we should replace this token factor.
1298
1299 // Start out with this token factor.
1300 TFs.push_back(N);
1301
1302 // Iterate through token factors. The TFs grows when new token factors are
1303 // encountered.
1304 for (unsigned i = 0; i < TFs.size(); ++i) {
1305 SDNode *TF = TFs[i];
1306
1307 // Check each of the operands.
1308 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1309 SDValue Op = TF->getOperand(i);
1310
1311 switch (Op.getOpcode()) {
1312 case ISD::EntryToken:
1313 // Entry tokens don't need to be added to the list. They are
1314 // rededundant.
1315 Changed = true;
1316 break;
1317
1318 case ISD::TokenFactor:
1319 if (Op.hasOneUse() &&
1320 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1321 // Queue up for processing.
1322 TFs.push_back(Op.getNode());
1323 // Clean up in case the token factor is removed.
1324 AddToWorkList(Op.getNode());
1325 Changed = true;
1326 break;
1327 }
1328 // Fall thru
1329
1330 default:
1331 // Only add if it isn't already in the list.
1332 if (SeenOps.insert(Op.getNode()))
1333 Ops.push_back(Op);
1334 else
1335 Changed = true;
1336 break;
1337 }
1338 }
1339 }
1340
1341 SDValue Result;
1342
1343 // If we've change things around then replace token factor.
1344 if (Changed) {
1345 if (Ops.empty()) {
1346 // The entry token is the only possible outcome.
1347 Result = DAG.getEntryNode();
1348 } else {
1349 // New and improved token factor.
1350 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N),
1351 MVT::Other, &Ops[0], Ops.size());
1352 }
1353
1354 // Don't add users to work list.
1355 return CombineTo(N, Result, false);
1356 }
1357
1358 return Result;
1359}
1360
1361/// MERGE_VALUES can always be eliminated.
1362SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1363 WorkListRemover DeadNodes(*this);
1364 // Replacing results may cause a different MERGE_VALUES to suddenly
1365 // be CSE'd with N, and carry its uses with it. Iterate until no
1366 // uses remain, to ensure that the node can be safely deleted.
1367 // First add the users of this node to the work list so that they
1368 // can be tried again once they have new operands.
1369 AddUsersToWorkList(N);
1370 do {
1371 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1372 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1373 } while (!N->use_empty());
1374 removeFromWorkList(N);
1375 DAG.DeleteNode(N);
1376 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1377}
1378
1379static
1380SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1,
1381 SelectionDAG &DAG) {
1382 EVT VT = N0.getValueType();
1383 SDValue N00 = N0.getOperand(0);
1384 SDValue N01 = N0.getOperand(1);
1385 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1386
1387 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1388 isa<ConstantSDNode>(N00.getOperand(1))) {
1389 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1390 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT,
1391 DAG.getNode(ISD::SHL, SDLoc(N00), VT,
1392 N00.getOperand(0), N01),
1393 DAG.getNode(ISD::SHL, SDLoc(N01), VT,
1394 N00.getOperand(1), N01));
1395 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1396 }
1397
1398 return SDValue();
1399}
1400
1401SDValue DAGCombiner::visitADD(SDNode *N) {
1402 SDValue N0 = N->getOperand(0);
1403 SDValue N1 = N->getOperand(1);
1404 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1405 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1406 EVT VT = N0.getValueType();
1407
1408 // fold vector ops
1409 if (VT.isVector()) {
1410 SDValue FoldedVOp = SimplifyVBinOp(N);
1411 if (FoldedVOp.getNode()) return FoldedVOp;
1412
1413 // fold (add x, 0) -> x, vector edition
1414 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1415 return N0;
1416 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1417 return N1;
1418 }
1419
1420 // fold (add x, undef) -> undef
1421 if (N0.getOpcode() == ISD::UNDEF)
1422 return N0;
1423 if (N1.getOpcode() == ISD::UNDEF)
1424 return N1;
1425 // fold (add c1, c2) -> c1+c2
1426 if (N0C && N1C)
1427 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1428 // canonicalize constant to RHS
1429 if (N0C && !N1C)
1430 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1431 // fold (add x, 0) -> x
1432 if (N1C && N1C->isNullValue())
1433 return N0;
1434 // fold (add Sym, c) -> Sym+c
1435 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1436 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1437 GA->getOpcode() == ISD::GlobalAddress)
1438 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1439 GA->getOffset() +
1440 (uint64_t)N1C->getSExtValue());
1441 // fold ((c1-A)+c2) -> (c1+c2)-A
1442 if (N1C && N0.getOpcode() == ISD::SUB)
1443 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1444 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1445 DAG.getConstant(N1C->getAPIntValue()+
1446 N0C->getAPIntValue(), VT),
1447 N0.getOperand(1));
1448 // reassociate add
1449 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1450 if (RADD.getNode() != 0)
1451 return RADD;
1452 // fold ((0-A) + B) -> B-A
1453 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1454 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1455 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1456 // fold (A + (0-B)) -> A-B
1457 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1458 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1459 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1460 // fold (A+(B-A)) -> B
1461 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1462 return N1.getOperand(0);
1463 // fold ((B-A)+A) -> B
1464 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1465 return N0.getOperand(0);
1466 // fold (A+(B-(A+C))) to (B-C)
1467 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1468 N0 == N1.getOperand(1).getOperand(0))
1469 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1470 N1.getOperand(1).getOperand(1));
1471 // fold (A+(B-(C+A))) to (B-C)
1472 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1473 N0 == N1.getOperand(1).getOperand(1))
1474 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1475 N1.getOperand(1).getOperand(0));
1476 // fold (A+((B-A)+or-C)) to (B+or-C)
1477 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1478 N1.getOperand(0).getOpcode() == ISD::SUB &&
1479 N0 == N1.getOperand(0).getOperand(1))
1480 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1481 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1482
1483 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1484 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1485 SDValue N00 = N0.getOperand(0);
1486 SDValue N01 = N0.getOperand(1);
1487 SDValue N10 = N1.getOperand(0);
1488 SDValue N11 = N1.getOperand(1);
1489
1490 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1491 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1492 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1493 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1494 }
1495
1496 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1497 return SDValue(N, 0);
1498
1499 // fold (a+b) -> (a|b) iff a and b share no bits.
1500 if (VT.isInteger() && !VT.isVector()) {
1501 APInt LHSZero, LHSOne;
1502 APInt RHSZero, RHSOne;
1503 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1504
1505 if (LHSZero.getBoolValue()) {
1506 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1507
1508 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1509 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1510 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1511 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1512 }
1513 }
1514
1515 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1516 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1517 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG);
1518 if (Result.getNode()) return Result;
1519 }
1520 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1521 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG);
1522 if (Result.getNode()) return Result;
1523 }
1524
1525 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1526 if (N1.getOpcode() == ISD::SHL &&
1527 N1.getOperand(0).getOpcode() == ISD::SUB)
1528 if (ConstantSDNode *C =
1529 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1530 if (C->getAPIntValue() == 0)
1531 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1532 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1533 N1.getOperand(0).getOperand(1),
1534 N1.getOperand(1)));
1535 if (N0.getOpcode() == ISD::SHL &&
1536 N0.getOperand(0).getOpcode() == ISD::SUB)
1537 if (ConstantSDNode *C =
1538 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1539 if (C->getAPIntValue() == 0)
1540 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1541 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1542 N0.getOperand(0).getOperand(1),
1543 N0.getOperand(1)));
1544
1545 if (N1.getOpcode() == ISD::AND) {
1546 SDValue AndOp0 = N1.getOperand(0);
1547 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1548 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1549 unsigned DestBits = VT.getScalarType().getSizeInBits();
1550
1551 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1552 // and similar xforms where the inner op is either ~0 or 0.
1553 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1554 SDLoc DL(N);
1555 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1556 }
1557 }
1558
1559 // add (sext i1), X -> sub X, (zext i1)
1560 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1561 N0.getOperand(0).getValueType() == MVT::i1 &&
1562 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1563 SDLoc DL(N);
1564 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1565 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1566 }
1567
1568 return SDValue();
1569}
1570
1571SDValue DAGCombiner::visitADDC(SDNode *N) {
1572 SDValue N0 = N->getOperand(0);
1573 SDValue N1 = N->getOperand(1);
1574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1576 EVT VT = N0.getValueType();
1577
1578 // If the flag result is dead, turn this into an ADD.
1579 if (!N->hasAnyUseOfValue(1))
1580 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1581 DAG.getNode(ISD::CARRY_FALSE,
1582 SDLoc(N), MVT::Glue));
1583
1584 // canonicalize constant to RHS.
1585 if (N0C && !N1C)
1586 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1587
1588 // fold (addc x, 0) -> x + no carry out
1589 if (N1C && N1C->isNullValue())
1590 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1591 SDLoc(N), MVT::Glue));
1592
1593 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1594 APInt LHSZero, LHSOne;
1595 APInt RHSZero, RHSOne;
1596 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1597
1598 if (LHSZero.getBoolValue()) {
1599 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1600
1601 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1602 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1603 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1604 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1605 DAG.getNode(ISD::CARRY_FALSE,
1606 SDLoc(N), MVT::Glue));
1607 }
1608
1609 return SDValue();
1610}
1611
1612SDValue DAGCombiner::visitADDE(SDNode *N) {
1613 SDValue N0 = N->getOperand(0);
1614 SDValue N1 = N->getOperand(1);
1615 SDValue CarryIn = N->getOperand(2);
1616 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1617 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1618
1619 // canonicalize constant to RHS
1620 if (N0C && !N1C)
1621 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1622 N1, N0, CarryIn);
1623
1624 // fold (adde x, y, false) -> (addc x, y)
1625 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1626 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1627
1628 return SDValue();
1629}
1630
1631// Since it may not be valid to emit a fold to zero for vector initializers
1632// check if we can before folding.
1633static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1634 SelectionDAG &DAG,
1635 bool LegalOperations, bool LegalTypes) {
1636 if (!VT.isVector())
1637 return DAG.getConstant(0, VT);
1638 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1639 return DAG.getConstant(0, VT);
1640 return SDValue();
1641}
1642
1643SDValue DAGCombiner::visitSUB(SDNode *N) {
1644 SDValue N0 = N->getOperand(0);
1645 SDValue N1 = N->getOperand(1);
1646 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1647 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1648 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1649 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1650 EVT VT = N0.getValueType();
1651
1652 // fold vector ops
1653 if (VT.isVector()) {
1654 SDValue FoldedVOp = SimplifyVBinOp(N);
1655 if (FoldedVOp.getNode()) return FoldedVOp;
1656
1657 // fold (sub x, 0) -> x, vector edition
1658 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1659 return N0;
1660 }
1661
1662 // fold (sub x, x) -> 0
1663 // FIXME: Refactor this and xor and other similar operations together.
1664 if (N0 == N1)
1665 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1666 // fold (sub c1, c2) -> c1-c2
1667 if (N0C && N1C)
1668 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1669 // fold (sub x, c) -> (add x, -c)
1670 if (N1C)
1671 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1672 DAG.getConstant(-N1C->getAPIntValue(), VT));
1673 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1674 if (N0C && N0C->isAllOnesValue())
1675 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1676 // fold A-(A-B) -> B
1677 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1678 return N1.getOperand(1);
1679 // fold (A+B)-A -> B
1680 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1681 return N0.getOperand(1);
1682 // fold (A+B)-B -> A
1683 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1684 return N0.getOperand(0);
1685 // fold C2-(A+C1) -> (C2-C1)-A
1686 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1687 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1688 VT);
1689 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1690 N1.getOperand(0));
1691 }
1692 // fold ((A+(B+or-C))-B) -> A+or-C
1693 if (N0.getOpcode() == ISD::ADD &&
1694 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1695 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1696 N0.getOperand(1).getOperand(0) == N1)
1697 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1698 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1699 // fold ((A+(C+B))-B) -> A+C
1700 if (N0.getOpcode() == ISD::ADD &&
1701 N0.getOperand(1).getOpcode() == ISD::ADD &&
1702 N0.getOperand(1).getOperand(1) == N1)
1703 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1704 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1705 // fold ((A-(B-C))-C) -> A-B
1706 if (N0.getOpcode() == ISD::SUB &&
1707 N0.getOperand(1).getOpcode() == ISD::SUB &&
1708 N0.getOperand(1).getOperand(1) == N1)
1709 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1710 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1711
1712 // If either operand of a sub is undef, the result is undef
1713 if (N0.getOpcode() == ISD::UNDEF)
1714 return N0;
1715 if (N1.getOpcode() == ISD::UNDEF)
1716 return N1;
1717
1718 // If the relocation model supports it, consider symbol offsets.
1719 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1720 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1721 // fold (sub Sym, c) -> Sym-c
1722 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1723 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1724 GA->getOffset() -
1725 (uint64_t)N1C->getSExtValue());
1726 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1727 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1728 if (GA->getGlobal() == GB->getGlobal())
1729 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1730 VT);
1731 }
1732
1733 return SDValue();
1734}
1735
1736SDValue DAGCombiner::visitSUBC(SDNode *N) {
1737 SDValue N0 = N->getOperand(0);
1738 SDValue N1 = N->getOperand(1);
1739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1741 EVT VT = N0.getValueType();
1742
1743 // If the flag result is dead, turn this into an SUB.
1744 if (!N->hasAnyUseOfValue(1))
1745 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1746 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1747 MVT::Glue));
1748
1749 // fold (subc x, x) -> 0 + no borrow
1750 if (N0 == N1)
1751 return CombineTo(N, DAG.getConstant(0, VT),
1752 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1753 MVT::Glue));
1754
1755 // fold (subc x, 0) -> x + no borrow
1756 if (N1C && N1C->isNullValue())
1757 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1758 MVT::Glue));
1759
1760 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1761 if (N0C && N0C->isAllOnesValue())
1762 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1763 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1764 MVT::Glue));
1765
1766 return SDValue();
1767}
1768
1769SDValue DAGCombiner::visitSUBE(SDNode *N) {
1770 SDValue N0 = N->getOperand(0);
1771 SDValue N1 = N->getOperand(1);
1772 SDValue CarryIn = N->getOperand(2);
1773
1774 // fold (sube x, y, false) -> (subc x, y)
1775 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1776 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1777
1778 return SDValue();
1779}
1780
1781/// isConstantSplatVector - Returns true if N is a BUILD_VECTOR node whose
1782/// elements are all the same constant or undefined.
1783static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
1784 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
1785 if (!C)
1786 return false;
1787
1788 APInt SplatUndef;
1789 unsigned SplatBitSize;
1790 bool HasAnyUndefs;
1791 EVT EltVT = N->getValueType(0).getVectorElementType();
1792 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1793 HasAnyUndefs) &&
1794 EltVT.getSizeInBits() >= SplatBitSize);
1795}
1796
1797SDValue DAGCombiner::visitMUL(SDNode *N) {
1798 SDValue N0 = N->getOperand(0);
1799 SDValue N1 = N->getOperand(1);
1800 EVT VT = N0.getValueType();
1801
1802 // fold (mul x, undef) -> 0
1803 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1804 return DAG.getConstant(0, VT);
1805
1806 bool N0IsConst = false;
1807 bool N1IsConst = false;
1808 APInt ConstValue0, ConstValue1;
1809 // fold vector ops
1810 if (VT.isVector()) {
1811 SDValue FoldedVOp = SimplifyVBinOp(N);
1812 if (FoldedVOp.getNode()) return FoldedVOp;
1813
1814 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1815 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
1816 } else {
1817 N0IsConst = dyn_cast<ConstantSDNode>(N0) != 0;
1818 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
1819 : APInt();
1820 N1IsConst = dyn_cast<ConstantSDNode>(N1) != 0;
1821 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
1822 : APInt();
1823 }
1824
1825 // fold (mul c1, c2) -> c1*c2
1826 if (N0IsConst && N1IsConst)
1827 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1828
1829 // canonicalize constant to RHS
1830 if (N0IsConst && !N1IsConst)
1831 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1832 // fold (mul x, 0) -> 0
1833 if (N1IsConst && ConstValue1 == 0)
1834 return N1;
1835 // We require a splat of the entire scalar bit width for non-contiguous
1836 // bit patterns.
1837 bool IsFullSplat =
1838 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
1839 // fold (mul x, 1) -> x
1840 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
1841 return N0;
1842 // fold (mul x, -1) -> 0-x
1843 if (N1IsConst && ConstValue1.isAllOnesValue())
1844 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1845 DAG.getConstant(0, VT), N0);
1846 // fold (mul x, (1 << c)) -> x << c
1847 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat)
1848 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1849 DAG.getConstant(ConstValue1.logBase2(),
1850 getShiftAmountTy(N0.getValueType())));
1851 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1852 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) {
1853 unsigned Log2Val = (-ConstValue1).logBase2();
1854 // FIXME: If the input is something that is easily negated (e.g. a
1855 // single-use add), we should put the negate there.
1856 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1857 DAG.getConstant(0, VT),
1858 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1859 DAG.getConstant(Log2Val,
1860 getShiftAmountTy(N0.getValueType()))));
1861 }
1862
1863 APInt Val;
1864 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1865 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
1866 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1867 isa<ConstantSDNode>(N0.getOperand(1)))) {
1868 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
1869 N1, N0.getOperand(1));
1870 AddToWorkList(C3.getNode());
1871 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
1872 N0.getOperand(0), C3);
1873 }
1874
1875 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1876 // use.
1877 {
1878 SDValue Sh(0,0), Y(0,0);
1879 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1880 if (N0.getOpcode() == ISD::SHL &&
1881 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1882 isa<ConstantSDNode>(N0.getOperand(1))) &&
1883 N0.getNode()->hasOneUse()) {
1884 Sh = N0; Y = N1;
1885 } else if (N1.getOpcode() == ISD::SHL &&
1886 isa<ConstantSDNode>(N1.getOperand(1)) &&
1887 N1.getNode()->hasOneUse()) {
1888 Sh = N1; Y = N0;
1889 }
1890
1891 if (Sh.getNode()) {
1892 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
1893 Sh.getOperand(0), Y);
1894 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
1895 Mul, Sh.getOperand(1));
1896 }
1897 }
1898
1899 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1900 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1901 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1902 isa<ConstantSDNode>(N0.getOperand(1))))
1903 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1904 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
1905 N0.getOperand(0), N1),
1906 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
1907 N0.getOperand(1), N1));
1908
1909 // reassociate mul
1910 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
1911 if (RMUL.getNode() != 0)
1912 return RMUL;
1913
1914 return SDValue();
1915}
1916
1917SDValue DAGCombiner::visitSDIV(SDNode *N) {
1918 SDValue N0 = N->getOperand(0);
1919 SDValue N1 = N->getOperand(1);
1920 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1922 EVT VT = N->getValueType(0);
1923
1924 // fold vector ops
1925 if (VT.isVector()) {
1926 SDValue FoldedVOp = SimplifyVBinOp(N);
1927 if (FoldedVOp.getNode()) return FoldedVOp;
1928 }
1929
1930 // fold (sdiv c1, c2) -> c1/c2
1931 if (N0C && N1C && !N1C->isNullValue())
1932 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1933 // fold (sdiv X, 1) -> X
1934 if (N1C && N1C->getAPIntValue() == 1LL)
1935 return N0;
1936 // fold (sdiv X, -1) -> 0-X
1937 if (N1C && N1C->isAllOnesValue())
1938 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1939 DAG.getConstant(0, VT), N0);
1940 // If we know the sign bits of both operands are zero, strength reduce to a
1941 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1942 if (!VT.isVector()) {
1943 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1944 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
1945 N0, N1);
1946 }
1947 // fold (sdiv X, pow2) -> simple ops after legalize
1948 if (N1C && !N1C->isNullValue() &&
1949 (N1C->getAPIntValue().isPowerOf2() ||
1950 (-N1C->getAPIntValue()).isPowerOf2())) {
1951 // If dividing by powers of two is cheap, then don't perform the following
1952 // fold.
1953 if (TLI.isPow2DivCheap())
1954 return SDValue();
1955
1956 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1957
1958 // Splat the sign bit into the register
1959 SDValue SGN = DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
1960 DAG.getConstant(VT.getSizeInBits()-1,
1961 getShiftAmountTy(N0.getValueType())));
1962 AddToWorkList(SGN.getNode());
1963
1964 // Add (N0 < 0) ? abs2 - 1 : 0;
1965 SDValue SRL = DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
1966 DAG.getConstant(VT.getSizeInBits() - lg2,
1967 getShiftAmountTy(SGN.getValueType())));
1968 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
1969 AddToWorkList(SRL.getNode());
1970 AddToWorkList(ADD.getNode()); // Divide by pow2
1971 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
1972 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1973
1974 // If we're dividing by a positive value, we're done. Otherwise, we must
1975 // negate the result.
1976 if (N1C->getAPIntValue().isNonNegative())
1977 return SRA;
1978
1979 AddToWorkList(SRA.getNode());
1980 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1981 DAG.getConstant(0, VT), SRA);
1982 }
1983
1984 // if integer divide is expensive and we satisfy the requirements, emit an
1985 // alternate sequence.
1986 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1987 SDValue Op = BuildSDIV(N);
1988 if (Op.getNode()) return Op;
1989 }
1990
1991 // undef / X -> 0
1992 if (N0.getOpcode() == ISD::UNDEF)
1993 return DAG.getConstant(0, VT);
1994 // X / undef -> undef
1995 if (N1.getOpcode() == ISD::UNDEF)
1996 return N1;
1997
1998 return SDValue();
1999}
2000
2001SDValue DAGCombiner::visitUDIV(SDNode *N) {
2002 SDValue N0 = N->getOperand(0);
2003 SDValue N1 = N->getOperand(1);
2004 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
2005 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2006 EVT VT = N->getValueType(0);
2007
2008 // fold vector ops
2009 if (VT.isVector()) {
2010 SDValue FoldedVOp = SimplifyVBinOp(N);
2011 if (FoldedVOp.getNode()) return FoldedVOp;
2012 }
2013
2014 // fold (udiv c1, c2) -> c1/c2
2015 if (N0C && N1C && !N1C->isNullValue())
2016 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2017 // fold (udiv x, (1 << c)) -> x >>u c
2018 if (N1C && N1C->getAPIntValue().isPowerOf2())
2019 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2020 DAG.getConstant(N1C->getAPIntValue().logBase2(),
2021 getShiftAmountTy(N0.getValueType())));
2022 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2023 if (N1.getOpcode() == ISD::SHL) {
2024 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2025 if (SHC->getAPIntValue().isPowerOf2()) {
2026 EVT ADDVT = N1.getOperand(1).getValueType();
2027 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2028 N1.getOperand(1),
2029 DAG.getConstant(SHC->getAPIntValue()
2030 .logBase2(),
2031 ADDVT));
2032 AddToWorkList(Add.getNode());
2033 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2034 }
2035 }
2036 }
2037 // fold (udiv x, c) -> alternate
2038 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
2039 SDValue Op = BuildUDIV(N);
2040 if (Op.getNode()) return Op;
2041 }
2042
2043 // undef / X -> 0
2044 if (N0.getOpcode() == ISD::UNDEF)
2045 return DAG.getConstant(0, VT);
2046 // X / undef -> undef
2047 if (N1.getOpcode() == ISD::UNDEF)
2048 return N1;
2049
2050 return SDValue();
2051}
2052
2053SDValue DAGCombiner::visitSREM(SDNode *N) {
2054 SDValue N0 = N->getOperand(0);
2055 SDValue N1 = N->getOperand(1);
2056 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2057 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2058 EVT VT = N->getValueType(0);
2059
2060 // fold (srem c1, c2) -> c1%c2
2061 if (N0C && N1C && !N1C->isNullValue())
2062 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2063 // If we know the sign bits of both operands are zero, strength reduce to a
2064 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2065 if (!VT.isVector()) {
2066 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2067 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2068 }
2069
2070 // If X/C can be simplified by the division-by-constant logic, lower
2071 // X%C to the equivalent of X-X/C*C.
2072 if (N1C && !N1C->isNullValue()) {
2073 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2074 AddToWorkList(Div.getNode());
2075 SDValue OptimizedDiv = combine(Div.getNode());
2076 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2077 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2078 OptimizedDiv, N1);
2079 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2080 AddToWorkList(Mul.getNode());
2081 return Sub;
2082 }
2083 }
2084
2085 // undef % X -> 0
2086 if (N0.getOpcode() == ISD::UNDEF)
2087 return DAG.getConstant(0, VT);
2088 // X % undef -> undef
2089 if (N1.getOpcode() == ISD::UNDEF)
2090 return N1;
2091
2092 return SDValue();
2093}
2094
2095SDValue DAGCombiner::visitUREM(SDNode *N) {
2096 SDValue N0 = N->getOperand(0);
2097 SDValue N1 = N->getOperand(1);
2098 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2100 EVT VT = N->getValueType(0);
2101
2102 // fold (urem c1, c2) -> c1%c2
2103 if (N0C && N1C && !N1C->isNullValue())
2104 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2105 // fold (urem x, pow2) -> (and x, pow2-1)
2106 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2107 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2108 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2109 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2110 if (N1.getOpcode() == ISD::SHL) {
2111 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2112 if (SHC->getAPIntValue().isPowerOf2()) {
2113 SDValue Add =
2114 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2115 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2116 VT));
2117 AddToWorkList(Add.getNode());
2118 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2119 }
2120 }
2121 }
2122
2123 // If X/C can be simplified by the division-by-constant logic, lower
2124 // X%C to the equivalent of X-X/C*C.
2125 if (N1C && !N1C->isNullValue()) {
2126 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2127 AddToWorkList(Div.getNode());
2128 SDValue OptimizedDiv = combine(Div.getNode());
2129 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2130 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2131 OptimizedDiv, N1);
2132 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2133 AddToWorkList(Mul.getNode());
2134 return Sub;
2135 }
2136 }
2137
2138 // undef % X -> 0
2139 if (N0.getOpcode() == ISD::UNDEF)
2140 return DAG.getConstant(0, VT);
2141 // X % undef -> undef
2142 if (N1.getOpcode() == ISD::UNDEF)
2143 return N1;
2144
2145 return SDValue();
2146}
2147
2148SDValue DAGCombiner::visitMULHS(SDNode *N) {
2149 SDValue N0 = N->getOperand(0);
2150 SDValue N1 = N->getOperand(1);
2151 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2152 EVT VT = N->getValueType(0);
2153 SDLoc DL(N);
2154
2155 // fold (mulhs x, 0) -> 0
2156 if (N1C && N1C->isNullValue())
2157 return N1;
2158 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2159 if (N1C && N1C->getAPIntValue() == 1)
2160 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2161 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2162 getShiftAmountTy(N0.getValueType())));
2163 // fold (mulhs x, undef) -> 0
2164 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2165 return DAG.getConstant(0, VT);
2166
2167 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2168 // plus a shift.
2169 if (VT.isSimple() && !VT.isVector()) {
2170 MVT Simple = VT.getSimpleVT();
2171 unsigned SimpleSize = Simple.getSizeInBits();
2172 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2173 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2174 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2175 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2176 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2177 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2178 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2179 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2180 }
2181 }
2182
2183 return SDValue();
2184}
2185
2186SDValue DAGCombiner::visitMULHU(SDNode *N) {
2187 SDValue N0 = N->getOperand(0);
2188 SDValue N1 = N->getOperand(1);
2189 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2190 EVT VT = N->getValueType(0);
2191 SDLoc DL(N);
2192
2193 // fold (mulhu x, 0) -> 0
2194 if (N1C && N1C->isNullValue())
2195 return N1;
2196 // fold (mulhu x, 1) -> 0
2197 if (N1C && N1C->getAPIntValue() == 1)
2198 return DAG.getConstant(0, N0.getValueType());
2199 // fold (mulhu x, undef) -> 0
2200 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2201 return DAG.getConstant(0, VT);
2202
2203 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2204 // plus a shift.
2205 if (VT.isSimple() && !VT.isVector()) {
2206 MVT Simple = VT.getSimpleVT();
2207 unsigned SimpleSize = Simple.getSizeInBits();
2208 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2209 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2210 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2211 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2212 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2213 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2214 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2215 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2216 }
2217 }
2218
2219 return SDValue();
2220}
2221
2222/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2223/// compute two values. LoOp and HiOp give the opcodes for the two computations
2224/// that are being performed. Return true if a simplification was made.
2225///
2226SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2227 unsigned HiOp) {
2228 // If the high half is not needed, just compute the low half.
2229 bool HiExists = N->hasAnyUseOfValue(1);
2230 if (!HiExists &&
2231 (!LegalOperations ||
2232 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2233 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0),
2234 N->op_begin(), N->getNumOperands());
2235 return CombineTo(N, Res, Res);
2236 }
2237
2238 // If the low half is not needed, just compute the high half.
2239 bool LoExists = N->hasAnyUseOfValue(0);
2240 if (!LoExists &&
2241 (!LegalOperations ||
2242 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2243 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1),
2244 N->op_begin(), N->getNumOperands());
2245 return CombineTo(N, Res, Res);
2246 }
2247
2248 // If both halves are used, return as it is.
2249 if (LoExists && HiExists)
2250 return SDValue();
2251
2252 // If the two computed results can be simplified separately, separate them.
2253 if (LoExists) {
2254 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0),
2255 N->op_begin(), N->getNumOperands());
2256 AddToWorkList(Lo.getNode());
2257 SDValue LoOpt = combine(Lo.getNode());
2258 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2259 (!LegalOperations ||
2260 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2261 return CombineTo(N, LoOpt, LoOpt);
2262 }
2263
2264 if (HiExists) {
2265 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1),
2266 N->op_begin(), N->getNumOperands());
2267 AddToWorkList(Hi.getNode());
2268 SDValue HiOpt = combine(Hi.getNode());
2269 if (HiOpt.getNode() && HiOpt != Hi &&
2270 (!LegalOperations ||
2271 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2272 return CombineTo(N, HiOpt, HiOpt);
2273 }
2274
2275 return SDValue();
2276}
2277
2278SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2279 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2280 if (Res.getNode()) return Res;
2281
2282 EVT VT = N->getValueType(0);
2283 SDLoc DL(N);
2284
2285 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2286 // plus a shift.
2287 if (VT.isSimple() && !VT.isVector()) {
2288 MVT Simple = VT.getSimpleVT();
2289 unsigned SimpleSize = Simple.getSizeInBits();
2290 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2291 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2292 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2293 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2294 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2295 // Compute the high part as N1.
2296 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2297 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2298 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2299 // Compute the low part as N0.
2300 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2301 return CombineTo(N, Lo, Hi);
2302 }
2303 }
2304
2305 return SDValue();
2306}
2307
2308SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2309 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2310 if (Res.getNode()) return Res;
2311
2312 EVT VT = N->getValueType(0);
2313 SDLoc DL(N);
2314
2315 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2316 // plus a shift.
2317 if (VT.isSimple() && !VT.isVector()) {
2318 MVT Simple = VT.getSimpleVT();
2319 unsigned SimpleSize = Simple.getSizeInBits();
2320 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2321 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2322 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2323 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2324 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2325 // Compute the high part as N1.
2326 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2327 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2328 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2329 // Compute the low part as N0.
2330 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2331 return CombineTo(N, Lo, Hi);
2332 }
2333 }
2334
2335 return SDValue();
2336}
2337
2338SDValue DAGCombiner::visitSMULO(SDNode *N) {
2339 // (smulo x, 2) -> (saddo x, x)
2340 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2341 if (C2->getAPIntValue() == 2)
2342 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2343 N->getOperand(0), N->getOperand(0));
2344
2345 return SDValue();
2346}
2347
2348SDValue DAGCombiner::visitUMULO(SDNode *N) {
2349 // (umulo x, 2) -> (uaddo x, x)
2350 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2351 if (C2->getAPIntValue() == 2)
2352 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2353 N->getOperand(0), N->getOperand(0));
2354
2355 return SDValue();
2356}
2357
2358SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2359 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2360 if (Res.getNode()) return Res;
2361
2362 return SDValue();
2363}
2364
2365SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2366 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2367 if (Res.getNode()) return Res;
2368
2369 return SDValue();
2370}
2371
2372/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2373/// two operands of the same opcode, try to simplify it.
2374SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2375 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2376 EVT VT = N0.getValueType();
2377 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2378
2379 // Bail early if none of these transforms apply.
2380 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2381
2382 // For each of OP in AND/OR/XOR:
2383 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2384 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2385 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2386 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2387 //
2388 // do not sink logical op inside of a vector extend, since it may combine
2389 // into a vsetcc.
2390 EVT Op0VT = N0.getOperand(0).getValueType();
2391 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2392 N0.getOpcode() == ISD::SIGN_EXTEND ||
2393 // Avoid infinite looping with PromoteIntBinOp.
2394 (N0.getOpcode() == ISD::ANY_EXTEND &&
2395 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2396 (N0.getOpcode() == ISD::TRUNCATE &&
2397 (!TLI.isZExtFree(VT, Op0VT) ||
2398 !TLI.isTruncateFree(Op0VT, VT)) &&
2399 TLI.isTypeLegal(Op0VT))) &&
2400 !VT.isVector() &&
2401 Op0VT == N1.getOperand(0).getValueType() &&
2402 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2403 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2404 N0.getOperand(0).getValueType(),
2405 N0.getOperand(0), N1.getOperand(0));
2406 AddToWorkList(ORNode.getNode());
2407 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2408 }
2409
2410 // For each of OP in SHL/SRL/SRA/AND...
2411 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2412 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2413 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2414 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2415 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2416 N0.getOperand(1) == N1.getOperand(1)) {
2417 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2418 N0.getOperand(0).getValueType(),
2419 N0.getOperand(0), N1.getOperand(0));
2420 AddToWorkList(ORNode.getNode());
2421 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2422 ORNode, N0.getOperand(1));
2423 }
2424
2425 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2426 // Only perform this optimization after type legalization and before
2427 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2428 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2429 // we don't want to undo this promotion.
2430 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2431 // on scalars.
2432 if ((N0.getOpcode() == ISD::BITCAST ||
2433 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2434 Level == AfterLegalizeTypes) {
2435 SDValue In0 = N0.getOperand(0);
2436 SDValue In1 = N1.getOperand(0);
2437 EVT In0Ty = In0.getValueType();
2438 EVT In1Ty = In1.getValueType();
2439 SDLoc DL(N);
2440 // If both incoming values are integers, and the original types are the
2441 // same.
2442 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2443 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2444 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2445 AddToWorkList(Op.getNode());
2446 return BC;
2447 }
2448 }
2449
2450 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2451 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2452 // If both shuffles use the same mask, and both shuffle within a single
2453 // vector, then it is worthwhile to move the swizzle after the operation.
2454 // The type-legalizer generates this pattern when loading illegal
2455 // vector types from memory. In many cases this allows additional shuffle
2456 // optimizations.
2457 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2458 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2459 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2460 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2461 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2462
2463 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2464 "Inputs to shuffles are not the same type");
2465
2466 unsigned NumElts = VT.getVectorNumElements();
2467
2468 // Check that both shuffles use the same mask. The masks are known to be of
2469 // the same length because the result vector type is the same.
2470 bool SameMask = true;
2471 for (unsigned i = 0; i != NumElts; ++i) {
2472 int Idx0 = SVN0->getMaskElt(i);
2473 int Idx1 = SVN1->getMaskElt(i);
2474 if (Idx0 != Idx1) {
2475 SameMask = false;
2476 break;
2477 }
2478 }
2479
2480 if (SameMask) {
2481 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2482 N0.getOperand(0), N1.getOperand(0));
2483 AddToWorkList(Op.getNode());
2484 return DAG.getVectorShuffle(VT, SDLoc(N), Op,
2485 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2486 }
2487 }
2488
2489 return SDValue();
2490}
2491
2492SDValue DAGCombiner::visitAND(SDNode *N) {
2493 SDValue N0 = N->getOperand(0);
2494 SDValue N1 = N->getOperand(1);
2495 SDValue LL, LR, RL, RR, CC0, CC1;
2496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2498 EVT VT = N1.getValueType();
2499 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2500
2501 // fold vector ops
2502 if (VT.isVector()) {
2503 SDValue FoldedVOp = SimplifyVBinOp(N);
2504 if (FoldedVOp.getNode()) return FoldedVOp;
2505
2506 // fold (and x, 0) -> 0, vector edition
2507 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2508 return N0;
2509 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2510 return N1;
2511
2512 // fold (and x, -1) -> x, vector edition
2513 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2514 return N1;
2515 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2516 return N0;
2517 }
2518
2519 // fold (and x, undef) -> 0
2520 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2521 return DAG.getConstant(0, VT);
2522 // fold (and c1, c2) -> c1&c2
2523 if (N0C && N1C)
2524 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2525 // canonicalize constant to RHS
2526 if (N0C && !N1C)
2527 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2528 // fold (and x, -1) -> x
2529 if (N1C && N1C->isAllOnesValue())
2530 return N0;
2531 // if (and x, c) is known to be zero, return 0
2532 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2533 APInt::getAllOnesValue(BitWidth)))
2534 return DAG.getConstant(0, VT);
2535 // reassociate and
2536 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2537 if (RAND.getNode() != 0)
2538 return RAND;
2539 // fold (and (or x, C), D) -> D if (C & D) == D
2540 if (N1C && N0.getOpcode() == ISD::OR)
2541 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2542 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2543 return N1;
2544 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2545 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2546 SDValue N0Op0 = N0.getOperand(0);
2547 APInt Mask = ~N1C->getAPIntValue();
2548 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2549 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2550 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2551 N0.getValueType(), N0Op0);
2552
2553 // Replace uses of the AND with uses of the Zero extend node.
2554 CombineTo(N, Zext);
2555
2556 // We actually want to replace all uses of the any_extend with the
2557 // zero_extend, to avoid duplicating things. This will later cause this
2558 // AND to be folded.
2559 CombineTo(N0.getNode(), Zext);
2560 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2561 }
2562 }
2563 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2564 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2565 // already be zero by virtue of the width of the base type of the load.
2566 //
2567 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2568 // more cases.
2569 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2570 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2571 N0.getOpcode() == ISD::LOAD) {
2572 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2573 N0 : N0.getOperand(0) );
2574
2575 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2576 // This can be a pure constant or a vector splat, in which case we treat the
2577 // vector as a scalar and use the splat value.
2578 APInt Constant = APInt::getNullValue(1);
2579 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2580 Constant = C->getAPIntValue();
2581 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2582 APInt SplatValue, SplatUndef;
2583 unsigned SplatBitSize;
2584 bool HasAnyUndefs;
2585 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2586 SplatBitSize, HasAnyUndefs);
2587 if (IsSplat) {
2588 // Undef bits can contribute to a possible optimisation if set, so
2589 // set them.
2590 SplatValue |= SplatUndef;
2591
2592 // The splat value may be something like "0x00FFFFFF", which means 0 for
2593 // the first vector value and FF for the rest, repeating. We need a mask
2594 // that will apply equally to all members of the vector, so AND all the
2595 // lanes of the constant together.
2596 EVT VT = Vector->getValueType(0);
2597 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2598
2599 // If the splat value has been compressed to a bitlength lower
2600 // than the size of the vector lane, we need to re-expand it to
2601 // the lane size.
2602 if (BitWidth > SplatBitSize)
2603 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2604 SplatBitSize < BitWidth;
2605 SplatBitSize = SplatBitSize * 2)
2606 SplatValue |= SplatValue.shl(SplatBitSize);
2607
2608 Constant = APInt::getAllOnesValue(BitWidth);
2609 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2610 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2611 }
2612 }
2613
2614 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2615 // actually legal and isn't going to get expanded, else this is a false
2616 // optimisation.
2617 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2618 Load->getMemoryVT());
2619
2620 // Resize the constant to the same size as the original memory access before
2621 // extension. If it is still the AllOnesValue then this AND is completely
2622 // unneeded.
2623 Constant =
2624 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2625
2626 bool B;
2627 switch (Load->getExtensionType()) {
2628 default: B = false; break;
2629 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2630 case ISD::ZEXTLOAD:
2631 case ISD::NON_EXTLOAD: B = true; break;
2632 }
2633
2634 if (B && Constant.isAllOnesValue()) {
2635 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2636 // preserve semantics once we get rid of the AND.
2637 SDValue NewLoad(Load, 0);
2638 if (Load->getExtensionType() == ISD::EXTLOAD) {
2639 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2640 Load->getValueType(0), SDLoc(Load),
2641 Load->getChain(), Load->getBasePtr(),
2642 Load->getOffset(), Load->getMemoryVT(),
2643 Load->getMemOperand());
2644 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2645 if (Load->getNumValues() == 3) {
2646 // PRE/POST_INC loads have 3 values.
2647 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2648 NewLoad.getValue(2) };
2649 CombineTo(Load, To, 3, true);
2650 } else {
2651 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2652 }
2653 }
2654
2655 // Fold the AND away, taking care not to fold to the old load node if we
2656 // replaced it.
2657 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2658
2659 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2660 }
2661 }
2662 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2663 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2664 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2665 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2666
2667 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2668 LL.getValueType().isInteger()) {
2669 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2670 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2671 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2672 LR.getValueType(), LL, RL);
2673 AddToWorkList(ORNode.getNode());
2674 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2675 }
2676 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2677 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2678 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2679 LR.getValueType(), LL, RL);
2680 AddToWorkList(ANDNode.getNode());
2681 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2682 }
2683 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2684 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2685 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2686 LR.getValueType(), LL, RL);
2687 AddToWorkList(ORNode.getNode());
2688 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2689 }
2690 }
2691 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2692 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2693 Op0 == Op1 && LL.getValueType().isInteger() &&
2694 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2695 cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
2696 (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2697 cast<ConstantSDNode>(RR)->isNullValue()))) {
2698 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2699 LL, DAG.getConstant(1, LL.getValueType()));
2700 AddToWorkList(ADDNode.getNode());
2701 return DAG.getSetCC(SDLoc(N), VT, ADDNode,
2702 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2703 }
2704 // canonicalize equivalent to ll == rl
2705 if (LL == RR && LR == RL) {
2706 Op1 = ISD::getSetCCSwappedOperands(Op1);
2707 std::swap(RL, RR);
2708 }
2709 if (LL == RL && LR == RR) {
2710 bool isInteger = LL.getValueType().isInteger();
2711 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2712 if (Result != ISD::SETCC_INVALID &&
2713 (!LegalOperations ||
2714 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2715 TLI.isOperationLegal(ISD::SETCC,
2716 getSetCCResultType(N0.getSimpleValueType())))))
2717 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2718 LL, LR, Result);
2719 }
2720 }
2721
2722 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2723 if (N0.getOpcode() == N1.getOpcode()) {
2724 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2725 if (Tmp.getNode()) return Tmp;
2726 }
2727
2728 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2729 // fold (and (sra)) -> (and (srl)) when possible.
2730 if (!VT.isVector() &&
2731 SimplifyDemandedBits(SDValue(N, 0)))
2732 return SDValue(N, 0);
2733
2734 // fold (zext_inreg (extload x)) -> (zextload x)
2735 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2736 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2737 EVT MemVT = LN0->getMemoryVT();
2738 // If we zero all the possible extended bits, then we can turn this into
2739 // a zextload if we are running before legalize or the operation is legal.
2740 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2741 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2742 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2743 ((!LegalOperations && !LN0->isVolatile()) ||
2744 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2745 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2746 LN0->getChain(), LN0->getBasePtr(),
2747 MemVT, LN0->getMemOperand());
2748 AddToWorkList(N);
2749 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2750 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2751 }
2752 }
2753 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2754 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2755 N0.hasOneUse()) {
2756 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2757 EVT MemVT = LN0->getMemoryVT();
2758 // If we zero all the possible extended bits, then we can turn this into
2759 // a zextload if we are running before legalize or the operation is legal.
2760 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2761 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2762 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2763 ((!LegalOperations && !LN0->isVolatile()) ||
2764 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2765 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2766 LN0->getChain(), LN0->getBasePtr(),
2767 MemVT, LN0->getMemOperand());
2768 AddToWorkList(N);
2769 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2770 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2771 }
2772 }
2773
2774 // fold (and (load x), 255) -> (zextload x, i8)
2775 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2776 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2777 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2778 (N0.getOpcode() == ISD::ANY_EXTEND &&
2779 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2780 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2781 LoadSDNode *LN0 = HasAnyExt
2782 ? cast<LoadSDNode>(N0.getOperand(0))
2783 : cast<LoadSDNode>(N0);
2784 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2785 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2786 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2787 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2788 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2789 EVT LoadedVT = LN0->getMemoryVT();
2790
2791 if (ExtVT == LoadedVT &&
2792 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2793 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2794
2795 SDValue NewLoad =
2796 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2797 LN0->getChain(), LN0->getBasePtr(), ExtVT,
2798 LN0->getMemOperand());
2799 AddToWorkList(N);
2800 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2801 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2802 }
2803
2804 // Do not change the width of a volatile load.
2805 // Do not generate loads of non-round integer types since these can
2806 // be expensive (and would be wrong if the type is not byte sized).
2807 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2808 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2809 EVT PtrType = LN0->getOperand(1).getValueType();
2810
2811 unsigned Alignment = LN0->getAlignment();
2812 SDValue NewPtr = LN0->getBasePtr();
2813
2814 // For big endian targets, we need to add an offset to the pointer
2815 // to load the correct bytes. For little endian systems, we merely
2816 // need to read fewer bytes from the same pointer.
2817 if (TLI.isBigEndian()) {
2818 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2819 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2820 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2821 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
2822 NewPtr, DAG.getConstant(PtrOff, PtrType));
2823 Alignment = MinAlign(Alignment, PtrOff);
2824 }
2825
2826 AddToWorkList(NewPtr.getNode());
2827
2828 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2829 SDValue Load =
2830 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2831 LN0->getChain(), NewPtr,
2832 LN0->getPointerInfo(),
2833 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2834 Alignment, LN0->getTBAAInfo());
2835 AddToWorkList(N);
2836 CombineTo(LN0, Load, Load.getValue(1));
2837 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2838 }
2839 }
2840 }
2841 }
2842
2843 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2844 VT.getSizeInBits() <= 64) {
2845 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2846 APInt ADDC = ADDI->getAPIntValue();
2847 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2848 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2849 // immediate for an add, but it is legal if its top c2 bits are set,
2850 // transform the ADD so the immediate doesn't need to be materialized
2851 // in a register.
2852 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2853 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2854 SRLI->getZExtValue());
2855 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2856 ADDC |= Mask;
2857 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2858 SDValue NewAdd =
2859 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
2860 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2861 CombineTo(N0.getNode(), NewAdd);
2862 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2863 }
2864 }
2865 }
2866 }
2867 }
2868 }
2869
2870 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
2871 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
2872 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
2873 N0.getOperand(1), false);
2874 if (BSwap.getNode())
2875 return BSwap;
2876 }
2877
2878 return SDValue();
2879}
2880
2881/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2882///
2883SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2884 bool DemandHighBits) {
2885 if (!LegalOperations)
2886 return SDValue();
2887
2888 EVT VT = N->getValueType(0);
2889 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2890 return SDValue();
2891 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2892 return SDValue();
2893
2894 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2895 bool LookPassAnd0 = false;
2896 bool LookPassAnd1 = false;
2897 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2898 std::swap(N0, N1);
2899 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2900 std::swap(N0, N1);
2901 if (N0.getOpcode() == ISD::AND) {
2902 if (!N0.getNode()->hasOneUse())
2903 return SDValue();
2904 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2905 if (!N01C || N01C->getZExtValue() != 0xFF00)
2906 return SDValue();
2907 N0 = N0.getOperand(0);
2908 LookPassAnd0 = true;
2909 }
2910
2911 if (N1.getOpcode() == ISD::AND) {
2912 if (!N1.getNode()->hasOneUse())
2913 return SDValue();
2914 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2915 if (!N11C || N11C->getZExtValue() != 0xFF)
2916 return SDValue();
2917 N1 = N1.getOperand(0);
2918 LookPassAnd1 = true;
2919 }
2920
2921 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2922 std::swap(N0, N1);
2923 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2924 return SDValue();
2925 if (!N0.getNode()->hasOneUse() ||
2926 !N1.getNode()->hasOneUse())
2927 return SDValue();
2928
2929 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2930 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2931 if (!N01C || !N11C)
2932 return SDValue();
2933 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2934 return SDValue();
2935
2936 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2937 SDValue N00 = N0->getOperand(0);
2938 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2939 if (!N00.getNode()->hasOneUse())
2940 return SDValue();
2941 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2942 if (!N001C || N001C->getZExtValue() != 0xFF)
2943 return SDValue();
2944 N00 = N00.getOperand(0);
2945 LookPassAnd0 = true;
2946 }
2947
2948 SDValue N10 = N1->getOperand(0);
2949 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2950 if (!N10.getNode()->hasOneUse())
2951 return SDValue();
2952 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2953 if (!N101C || N101C->getZExtValue() != 0xFF00)
2954 return SDValue();
2955 N10 = N10.getOperand(0);
2956 LookPassAnd1 = true;
2957 }
2958
2959 if (N00 != N10)
2960 return SDValue();
2961
2962 // Make sure everything beyond the low halfword gets set to zero since the SRL
2963 // 16 will clear the top bits.
2964 unsigned OpSizeInBits = VT.getSizeInBits();
2965 if (DemandHighBits && OpSizeInBits > 16) {
2966 // If the left-shift isn't masked out then the only way this is a bswap is
2967 // if all bits beyond the low 8 are 0. In that case the entire pattern
2968 // reduces to a left shift anyway: leave it for other parts of the combiner.
2969 if (!LookPassAnd0)
2970 return SDValue();
2971
2972 // However, if the right shift isn't masked out then it might be because
2973 // it's not needed. See if we can spot that too.
2974 if (!LookPassAnd1 &&
2975 !DAG.MaskedValueIsZero(
2976 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
2977 return SDValue();
2978 }
2979
2980 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
2981 if (OpSizeInBits > 16)
2982 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
2983 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2984 return Res;
2985}
2986
2987/// isBSwapHWordElement - Return true if the specified node is an element
2988/// that makes up a 32-bit packed halfword byteswap. i.e.
2989/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2990static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) {
2991 if (!N.getNode()->hasOneUse())
2992 return false;
2993
2994 unsigned Opc = N.getOpcode();
2995 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2996 return false;
2997
2998 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2999 if (!N1C)
3000 return false;
3001
3002 unsigned Num;
3003 switch (N1C->getZExtValue()) {
3004 default:
3005 return false;
3006 case 0xFF: Num = 0; break;
3007 case 0xFF00: Num = 1; break;
3008 case 0xFF0000: Num = 2; break;
3009 case 0xFF000000: Num = 3; break;
3010 }
3011
3012 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3013 SDValue N0 = N.getOperand(0);
3014 if (Opc == ISD::AND) {
3015 if (Num == 0 || Num == 2) {
3016 // (x >> 8) & 0xff
3017 // (x >> 8) & 0xff0000
3018 if (N0.getOpcode() != ISD::SRL)
3019 return false;
3020 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3021 if (!C || C->getZExtValue() != 8)
3022 return false;
3023 } else {
3024 // (x << 8) & 0xff00
3025 // (x << 8) & 0xff000000
3026 if (N0.getOpcode() != ISD::SHL)
3027 return false;
3028 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3029 if (!C || C->getZExtValue() != 8)
3030 return false;
3031 }
3032 } else if (Opc == ISD::SHL) {
3033 // (x & 0xff) << 8
3034 // (x & 0xff0000) << 8
3035 if (Num != 0 && Num != 2)
3036 return false;
3037 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3038 if (!C || C->getZExtValue() != 8)
3039 return false;
3040 } else { // Opc == ISD::SRL
3041 // (x & 0xff00) >> 8
3042 // (x & 0xff000000) >> 8
3043 if (Num != 1 && Num != 3)
3044 return false;
3045 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3046 if (!C || C->getZExtValue() != 8)
3047 return false;
3048 }
3049
3050 if (Parts[Num])
3051 return false;
3052
3053 Parts[Num] = N0.getOperand(0).getNode();
3054 return true;
3055}
3056
3057/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
3058/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
3059/// => (rotl (bswap x), 16)
3060SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3061 if (!LegalOperations)
3062 return SDValue();
3063
3064 EVT VT = N->getValueType(0);
3065 if (VT != MVT::i32)
3066 return SDValue();
3067 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3068 return SDValue();
3069
3070 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
3071 // Look for either
3072 // (or (or (and), (and)), (or (and), (and)))
3073 // (or (or (or (and), (and)), (and)), (and))
3074 if (N0.getOpcode() != ISD::OR)
3075 return SDValue();
3076 SDValue N00 = N0.getOperand(0);
3077 SDValue N01 = N0.getOperand(1);
3078
3079 if (N1.getOpcode() == ISD::OR &&
3080 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3081 // (or (or (and), (and)), (or (and), (and)))
3082 SDValue N000 = N00.getOperand(0);
3083 if (!isBSwapHWordElement(N000, Parts))
3084 return SDValue();
3085
3086 SDValue N001 = N00.getOperand(1);
3087 if (!isBSwapHWordElement(N001, Parts))
3088 return SDValue();
3089 SDValue N010 = N01.getOperand(0);
3090 if (!isBSwapHWordElement(N010, Parts))
3091 return SDValue();
3092 SDValue N011 = N01.getOperand(1);
3093 if (!isBSwapHWordElement(N011, Parts))
3094 return SDValue();
3095 } else {
3096 // (or (or (or (and), (and)), (and)), (and))
3097 if (!isBSwapHWordElement(N1, Parts))
3098 return SDValue();
3099 if (!isBSwapHWordElement(N01, Parts))
3100 return SDValue();
3101 if (N00.getOpcode() != ISD::OR)
3102 return SDValue();
3103 SDValue N000 = N00.getOperand(0);
3104 if (!isBSwapHWordElement(N000, Parts))
3105 return SDValue();
3106 SDValue N001 = N00.getOperand(1);
3107 if (!isBSwapHWordElement(N001, Parts))
3108 return SDValue();
3109 }
3110
3111 // Make sure the parts are all coming from the same node.
3112 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3113 return SDValue();
3114
3115 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3116 SDValue(Parts[0],0));
3117
3118 // Result of the bswap should be rotated by 16. If it's not legal, then
3119 // do (x << 16) | (x >> 16).
3120 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3121 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3122 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3123 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3124 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3125 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3126 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3127 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3128}
3129
3130SDValue DAGCombiner::visitOR(SDNode *N) {
3131 SDValue N0 = N->getOperand(0);
3132 SDValue N1 = N->getOperand(1);
3133 SDValue LL, LR, RL, RR, CC0, CC1;
3134 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3135 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3136 EVT VT = N1.getValueType();
3137
3138 // fold vector ops
3139 if (VT.isVector()) {
3140 SDValue FoldedVOp = SimplifyVBinOp(N);
3141 if (FoldedVOp.getNode()) return FoldedVOp;
3142
3143 // fold (or x, 0) -> x, vector edition
3144 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3145 return N1;
3146 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3147 return N0;
3148
3149 // fold (or x, -1) -> -1, vector edition
3150 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3151 return N0;
3152 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3153 return N1;
3154 }
3155
3156 // fold (or x, undef) -> -1
3157 if (!LegalOperations &&
3158 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3159 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3160 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3161 }
3162 // fold (or c1, c2) -> c1|c2
3163 if (N0C && N1C)
3164 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3165 // canonicalize constant to RHS
3166 if (N0C && !N1C)
3167 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3168 // fold (or x, 0) -> x
3169 if (N1C && N1C->isNullValue())
3170 return N0;
3171 // fold (or x, -1) -> -1
3172 if (N1C && N1C->isAllOnesValue())
3173 return N1;
3174 // fold (or x, c) -> c iff (x & ~c) == 0
3175 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3176 return N1;
3177
3178 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3179 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3180 if (BSwap.getNode() != 0)
3181 return BSwap;
3182 BSwap = MatchBSwapHWordLow(N, N0, N1);
3183 if (BSwap.getNode() != 0)
3184 return BSwap;
3185
3186 // reassociate or
3187 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3188 if (ROR.getNode() != 0)
3189 return ROR;
3190 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3191 // iff (c1 & c2) == 0.
3192 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3193 isa<ConstantSDNode>(N0.getOperand(1))) {
3194 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3195 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3196 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3197 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3198 N0.getOperand(0), N1),
3199 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3200 }
3201 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3202 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3203 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3204 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3205
3206 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3207 LL.getValueType().isInteger()) {
3208 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3209 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3210 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3211 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3212 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3213 LR.getValueType(), LL, RL);
3214 AddToWorkList(ORNode.getNode());
3215 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3216 }
3217 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3218 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3219 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3220 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3221 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3222 LR.getValueType(), LL, RL);
3223 AddToWorkList(ANDNode.getNode());
3224 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3225 }
3226 }
3227 // canonicalize equivalent to ll == rl
3228 if (LL == RR && LR == RL) {
3229 Op1 = ISD::getSetCCSwappedOperands(Op1);
3230 std::swap(RL, RR);
3231 }
3232 if (LL == RL && LR == RR) {
3233 bool isInteger = LL.getValueType().isInteger();
3234 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3235 if (Result != ISD::SETCC_INVALID &&
3236 (!LegalOperations ||
3237 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3238 TLI.isOperationLegal(ISD::SETCC,
3239 getSetCCResultType(N0.getValueType())))))
3240 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3241 LL, LR, Result);
3242 }
3243 }
3244
3245 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3246 if (N0.getOpcode() == N1.getOpcode()) {
3247 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3248 if (Tmp.getNode()) return Tmp;
3249 }
3250
3251 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3252 if (N0.getOpcode() == ISD::AND &&
3253 N1.getOpcode() == ISD::AND &&
3254 N0.getOperand(1).getOpcode() == ISD::Constant &&
3255 N1.getOperand(1).getOpcode() == ISD::Constant &&
3256 // Don't increase # computations.
3257 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3258 // We can only do this xform if we know that bits from X that are set in C2
3259 // but not in C1 are already zero. Likewise for Y.
3260 const APInt &LHSMask =
3261 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3262 const APInt &RHSMask =
3263 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3264
3265 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3266 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3267 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3268 N0.getOperand(0), N1.getOperand(0));
3269 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3270 DAG.getConstant(LHSMask | RHSMask, VT));
3271 }
3272 }
3273
3274 // See if this is some rotate idiom.
3275 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3276 return SDValue(Rot, 0);
3277
3278 // Simplify the operands using demanded-bits information.
3279 if (!VT.isVector() &&
3280 SimplifyDemandedBits(SDValue(N, 0)))
3281 return SDValue(N, 0);
3282
3283 return SDValue();
3284}
3285
3286/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3287static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3288 if (Op.getOpcode() == ISD::AND) {
3289 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3290 Mask = Op.getOperand(1);
3291 Op = Op.getOperand(0);
3292 } else {
3293 return false;
3294 }
3295 }
3296
3297 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3298 Shift = Op;
3299 return true;
3300 }
3301
3302 return false;
3303}
3304
3305// MatchRotate - Handle an 'or' of two operands. If this is one of the many
3306// idioms for rotate, and if the target supports rotation instructions, generate
3307// a rot[lr].
3308SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3309 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3310 EVT VT = LHS.getValueType();
3311 if (!TLI.isTypeLegal(VT)) return 0;
3312
3313 // The target must have at least one rotate flavor.
3314 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3315 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3316 if (!HasROTL && !HasROTR) return 0;
3317
3318 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3319 SDValue LHSShift; // The shift.
3320 SDValue LHSMask; // AND value if any.
3321 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3322 return 0; // Not part of a rotate.
3323
3324 SDValue RHSShift; // The shift.
3325 SDValue RHSMask; // AND value if any.
3326 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3327 return 0; // Not part of a rotate.
3328
3329 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3330 return 0; // Not shifting the same value.
3331
3332 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3333 return 0; // Shifts must disagree.
3334
3335 // Canonicalize shl to left side in a shl/srl pair.
3336 if (RHSShift.getOpcode() == ISD::SHL) {
3337 std::swap(LHS, RHS);
3338 std::swap(LHSShift, RHSShift);
3339 std::swap(LHSMask , RHSMask );
3340 }
3341
3342 unsigned OpSizeInBits = VT.getSizeInBits();
3343 SDValue LHSShiftArg = LHSShift.getOperand(0);
3344 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3345 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3346
3347 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3348 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3349 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3350 RHSShiftAmt.getOpcode() == ISD::Constant) {
3351 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3352 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3353 if ((LShVal + RShVal) != OpSizeInBits)
3354 return 0;
3355
3356 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3357 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3358
3359 // If there is an AND of either shifted operand, apply it to the result.
3360 if (LHSMask.getNode() || RHSMask.getNode()) {
3361 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3362
3363 if (LHSMask.getNode()) {
3364 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3365 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3366 }
3367 if (RHSMask.getNode()) {
3368 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3369 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3370 }
3371
3372 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3373 }
3374
3375 return Rot.getNode();
3376 }
3377
3378 // If there is a mask here, and we have a variable shift, we can't be sure
3379 // that we're masking out the right stuff.
3380 if (LHSMask.getNode() || RHSMask.getNode())
3381 return 0;
3382
3383 // If the shift amount is sign/zext/any-extended just peel it off.
3384 SDValue LExtOp0 = LHSShiftAmt;
3385 SDValue RExtOp0 = RHSShiftAmt;
3386 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3387 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3388 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3389 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3390 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3391 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3392 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3393 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3394 LExtOp0 = LHSShiftAmt.getOperand(0);
3395 RExtOp0 = RHSShiftAmt.getOperand(0);
3396 }
3397
3398 if (RExtOp0.getOpcode() == ISD::SUB && RExtOp0.getOperand(1) == LExtOp0) {
3399 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3400 // (rotl x, y)
3401 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3402 // (rotr x, (sub 32, y))
3403 if (ConstantSDNode *SUBC =
3404 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0)))
3405 if (SUBC->getAPIntValue() == OpSizeInBits)
3406 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3407 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3408 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3409 RExtOp0 == LExtOp0.getOperand(1)) {
3410 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3411 // (rotr x, y)
3412 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3413 // (rotl x, (sub 32, y))
3414 if (ConstantSDNode *SUBC =
3415 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0)))
3416 if (SUBC->getAPIntValue() == OpSizeInBits)
3417 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3418 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3419 }
3420
3421 return 0;
3422}
3423
3424SDValue DAGCombiner::visitXOR(SDNode *N) {
3425 SDValue N0 = N->getOperand(0);
3426 SDValue N1 = N->getOperand(1);
3427 SDValue LHS, RHS, CC;
3428 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3429 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3430 EVT VT = N0.getValueType();
3431
3432 // fold vector ops
3433 if (VT.isVector()) {
3434 SDValue FoldedVOp = SimplifyVBinOp(N);
3435 if (FoldedVOp.getNode()) return FoldedVOp;
3436
3437 // fold (xor x, 0) -> x, vector edition
3438 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3439 return N1;
3440 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3441 return N0;
3442 }
3443
3444 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3445 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3446 return DAG.getConstant(0, VT);
3447 // fold (xor x, undef) -> undef
3448 if (N0.getOpcode() == ISD::UNDEF)
3449 return N0;
3450 if (N1.getOpcode() == ISD::UNDEF)
3451 return N1;
3452 // fold (xor c1, c2) -> c1^c2
3453 if (N0C && N1C)
3454 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3455 // canonicalize constant to RHS
3456 if (N0C && !N1C)
3457 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3458 // fold (xor x, 0) -> x
3459 if (N1C && N1C->isNullValue())
3460 return N0;
3461<