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/3rd_party/llvm/lib/Target/Mips/MipsInstrInfo.td

https://code.google.com/p/softart/
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Possible License(s): LGPL-2.1, BSD-3-Clause, JSON, MPL-2.0-no-copyleft-exception, GPL-2.0, GPL-3.0, LGPL-3.0, BSD-2-Clause
  1. //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This file contains the Mips implementation of the TargetInstrInfo class.
  11. //
  12. //===----------------------------------------------------------------------===//
  13. //===----------------------------------------------------------------------===//
  14. // Mips profiles and nodes
  15. //===----------------------------------------------------------------------===//
  16. def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
  17. def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
  18. SDTCisSameAs<1, 2>,
  19. SDTCisSameAs<3, 4>,
  20. SDTCisInt<4>]>;
  21. def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
  22. def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
  23. def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
  24. def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  25. SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
  26. def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
  27. SDTCisSameAs<1, 2>]>;
  28. def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
  29. [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  30. SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  31. def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
  32. def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
  33. def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
  34. def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
  35. SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
  36. def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
  37. SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
  38. SDTCisSameAs<0, 4>]>;
  39. def SDTMipsLoadLR : SDTypeProfile<1, 2,
  40. [SDTCisInt<0>, SDTCisPtrTy<1>,
  41. SDTCisSameAs<0, 2>]>;
  42. // Call
  43. def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
  44. [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
  45. SDNPVariadic]>;
  46. // Tail call
  47. def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
  48. [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
  49. // Hi and Lo nodes are used to handle global addresses. Used on
  50. // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
  51. // static model. (nothing to do with Mips Registers Hi and Lo)
  52. def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
  53. def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
  54. def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
  55. // TlsGd node is used to handle General Dynamic TLS
  56. def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
  57. // TprelHi and TprelLo nodes are used to handle Local Exec TLS
  58. def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
  59. def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
  60. // Thread pointer
  61. def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
  62. // Return
  63. def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
  64. [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
  65. // These are target-independent nodes, but have target-specific formats.
  66. def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
  67. [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
  68. def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
  69. [SDNPHasChain, SDNPSideEffect,
  70. SDNPOptInGlue, SDNPOutGlue]>;
  71. // Nodes used to extract LO/HI registers.
  72. def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
  73. def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
  74. // Node used to insert 32-bit integers to LOHI register pair.
  75. def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
  76. // Mult nodes.
  77. def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
  78. def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
  79. // MAdd*/MSub* nodes
  80. def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
  81. def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
  82. def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
  83. def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
  84. // DivRem(u) nodes
  85. def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
  86. def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
  87. def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
  88. [SDNPOutGlue]>;
  89. def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
  90. [SDNPOutGlue]>;
  91. // Target constant nodes that are not part of any isel patterns and remain
  92. // unchanged can cause instructions with illegal operands to be emitted.
  93. // Wrapper node patterns give the instruction selector a chance to replace
  94. // target constant nodes that would otherwise remain unchanged with ADDiu
  95. // nodes. Without these wrapper node patterns, the following conditional move
  96. // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
  97. // compiled:
  98. // movn %got(d)($gp), %got(c)($gp), $4
  99. // This instruction is illegal since movn can take only register operands.
  100. def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
  101. def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
  102. def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
  103. def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
  104. def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
  105. [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
  106. def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
  107. [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
  108. def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
  109. [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
  110. def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
  111. [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
  112. def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
  113. [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
  114. def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
  115. [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
  116. def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
  117. [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
  118. def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
  119. [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
  120. //===----------------------------------------------------------------------===//
  121. // Mips Instruction Predicate Definitions.
  122. //===----------------------------------------------------------------------===//
  123. def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
  124. AssemblerPredicate<"FeatureSEInReg">;
  125. def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
  126. AssemblerPredicate<"FeatureBitCount">;
  127. def HasSwap : Predicate<"Subtarget.hasSwap()">,
  128. AssemblerPredicate<"FeatureSwap">;
  129. def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
  130. AssemblerPredicate<"FeatureCondMov">;
  131. def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
  132. AssemblerPredicate<"FeatureFPIdx">;
  133. def HasMips32 : Predicate<"Subtarget.hasMips32()">,
  134. AssemblerPredicate<"FeatureMips32">;
  135. def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
  136. AssemblerPredicate<"FeatureMips32r2">;
  137. def HasMips64 : Predicate<"Subtarget.hasMips64()">,
  138. AssemblerPredicate<"FeatureMips64">;
  139. def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
  140. AssemblerPredicate<"!FeatureMips64">;
  141. def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
  142. AssemblerPredicate<"FeatureMips64r2">;
  143. def IsN64 : Predicate<"Subtarget.isABI_N64()">,
  144. AssemblerPredicate<"FeatureN64">;
  145. def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
  146. AssemblerPredicate<"!FeatureN64">;
  147. def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
  148. AssemblerPredicate<"FeatureMips16">;
  149. def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
  150. AssemblerPredicate<"FeatureMips32">;
  151. def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
  152. AssemblerPredicate<"FeatureMips32">;
  153. def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
  154. AssemblerPredicate<"FeatureMips32">;
  155. def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
  156. AssemblerPredicate<"!FeatureMips16">;
  157. def NotDSP : Predicate<"!Subtarget.hasDSP()">;
  158. def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
  159. AssemblerPredicate<"FeatureMicroMips">;
  160. def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
  161. AssemblerPredicate<"!FeatureMicroMips">;
  162. def IsLE : Predicate<"Subtarget.isLittle()">;
  163. def IsBE : Predicate<"!Subtarget.isLittle()">;
  164. class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
  165. let Predicates = [HasStdEnc];
  166. }
  167. class IsCommutable {
  168. bit isCommutable = 1;
  169. }
  170. class IsBranch {
  171. bit isBranch = 1;
  172. }
  173. class IsReturn {
  174. bit isReturn = 1;
  175. }
  176. class IsCall {
  177. bit isCall = 1;
  178. }
  179. class IsTailCall {
  180. bit isCall = 1;
  181. bit isTerminator = 1;
  182. bit isReturn = 1;
  183. bit isBarrier = 1;
  184. bit hasExtraSrcRegAllocReq = 1;
  185. bit isCodeGenOnly = 1;
  186. }
  187. class IsAsCheapAsAMove {
  188. bit isAsCheapAsAMove = 1;
  189. }
  190. class NeverHasSideEffects {
  191. bit neverHasSideEffects = 1;
  192. }
  193. //===----------------------------------------------------------------------===//
  194. // Instruction format superclass
  195. //===----------------------------------------------------------------------===//
  196. include "MipsInstrFormats.td"
  197. //===----------------------------------------------------------------------===//
  198. // Mips Operand, Complex Patterns and Transformations Definitions.
  199. //===----------------------------------------------------------------------===//
  200. // Instruction operand types
  201. def jmptarget : Operand<OtherVT> {
  202. let EncoderMethod = "getJumpTargetOpValue";
  203. }
  204. def brtarget : Operand<OtherVT> {
  205. let EncoderMethod = "getBranchTargetOpValue";
  206. let OperandType = "OPERAND_PCREL";
  207. let DecoderMethod = "DecodeBranchTarget";
  208. }
  209. def calltarget : Operand<iPTR> {
  210. let EncoderMethod = "getJumpTargetOpValue";
  211. }
  212. def simm16 : Operand<i32> {
  213. let DecoderMethod= "DecodeSimm16";
  214. }
  215. def simm20 : Operand<i32> {
  216. }
  217. def uimm20 : Operand<i32> {
  218. }
  219. def uimm10 : Operand<i32> {
  220. }
  221. def simm16_64 : Operand<i64> {
  222. let DecoderMethod = "DecodeSimm16";
  223. }
  224. // Unsigned Operand
  225. def uimm5 : Operand<i32> {
  226. let PrintMethod = "printUnsignedImm";
  227. }
  228. def uimm6 : Operand<i32> {
  229. let PrintMethod = "printUnsignedImm";
  230. }
  231. def uimm16 : Operand<i32> {
  232. let PrintMethod = "printUnsignedImm";
  233. }
  234. def pcrel16 : Operand<i32> {
  235. }
  236. def MipsMemAsmOperand : AsmOperandClass {
  237. let Name = "Mem";
  238. let ParserMethod = "parseMemOperand";
  239. }
  240. def MipsInvertedImmoperand : AsmOperandClass {
  241. let Name = "InvNum";
  242. let RenderMethod = "addImmOperands";
  243. let ParserMethod = "parseInvNum";
  244. }
  245. def PtrRegAsmOperand : AsmOperandClass {
  246. let Name = "PtrReg";
  247. let ParserMethod = "parsePtrReg";
  248. }
  249. def InvertedImOperand : Operand<i32> {
  250. let ParserMatchClass = MipsInvertedImmoperand;
  251. }
  252. // Address operand
  253. def mem : Operand<iPTR> {
  254. let PrintMethod = "printMemOperand";
  255. let MIOperandInfo = (ops ptr_rc, simm16);
  256. let EncoderMethod = "getMemEncoding";
  257. let ParserMatchClass = MipsMemAsmOperand;
  258. let OperandType = "OPERAND_MEMORY";
  259. }
  260. def mem_ea : Operand<iPTR> {
  261. let PrintMethod = "printMemOperandEA";
  262. let MIOperandInfo = (ops ptr_rc, simm16);
  263. let EncoderMethod = "getMemEncoding";
  264. let OperandType = "OPERAND_MEMORY";
  265. }
  266. def PtrRC : Operand<iPTR> {
  267. let MIOperandInfo = (ops ptr_rc);
  268. let DecoderMethod = "DecodePtrRegisterClass";
  269. let ParserMatchClass = PtrRegAsmOperand;
  270. }
  271. // size operand of ext instruction
  272. def size_ext : Operand<i32> {
  273. let EncoderMethod = "getSizeExtEncoding";
  274. let DecoderMethod = "DecodeExtSize";
  275. }
  276. // size operand of ins instruction
  277. def size_ins : Operand<i32> {
  278. let EncoderMethod = "getSizeInsEncoding";
  279. let DecoderMethod = "DecodeInsSize";
  280. }
  281. // Transformation Function - get the lower 16 bits.
  282. def LO16 : SDNodeXForm<imm, [{
  283. return getImm(N, N->getZExtValue() & 0xFFFF);
  284. }]>;
  285. // Transformation Function - get the higher 16 bits.
  286. def HI16 : SDNodeXForm<imm, [{
  287. return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
  288. }]>;
  289. // Plus 1.
  290. def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
  291. // Node immediate fits as 16-bit sign extended on target immediate.
  292. // e.g. addi, andi
  293. def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
  294. // Node immediate fits as 16-bit sign extended on target immediate.
  295. // e.g. addi, andi
  296. def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
  297. // Node immediate fits as 15-bit sign extended on target immediate.
  298. // e.g. addi, andi
  299. def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
  300. // Node immediate fits as 16-bit zero extended on target immediate.
  301. // The LO16 param means that only the lower 16 bits of the node
  302. // immediate are caught.
  303. // e.g. addiu, sltiu
  304. def immZExt16 : PatLeaf<(imm), [{
  305. if (N->getValueType(0) == MVT::i32)
  306. return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
  307. else
  308. return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
  309. }], LO16>;
  310. // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
  311. def immLow16Zero : PatLeaf<(imm), [{
  312. int64_t Val = N->getSExtValue();
  313. return isInt<32>(Val) && !(Val & 0xffff);
  314. }]>;
  315. // shamt field must fit in 5 bits.
  316. def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
  317. // True if (N + 1) fits in 16-bit field.
  318. def immSExt16Plus1 : PatLeaf<(imm), [{
  319. return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
  320. }]>;
  321. // Mips Address Mode! SDNode frameindex could possibily be a match
  322. // since load and store instructions from stack used it.
  323. def addr :
  324. ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
  325. def addrRegImm :
  326. ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
  327. def addrRegReg :
  328. ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
  329. def addrDefault :
  330. ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
  331. //===----------------------------------------------------------------------===//
  332. // Instructions specific format
  333. //===----------------------------------------------------------------------===//
  334. // Arithmetic and logical instructions with 3 register operands.
  335. class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
  336. InstrItinClass Itin = NoItinerary,
  337. SDPatternOperator OpNode = null_frag>:
  338. InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
  339. !strconcat(opstr, "\t$rd, $rs, $rt"),
  340. [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
  341. let isCommutable = isComm;
  342. let isReMaterializable = 1;
  343. }
  344. // Arithmetic and logical instructions with 2 register operands.
  345. class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
  346. InstrItinClass Itin = NoItinerary,
  347. SDPatternOperator imm_type = null_frag,
  348. SDPatternOperator OpNode = null_frag> :
  349. InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
  350. !strconcat(opstr, "\t$rt, $rs, $imm16"),
  351. [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
  352. Itin, FrmI, opstr> {
  353. let isReMaterializable = 1;
  354. let TwoOperandAliasConstraint = "$rs = $rt";
  355. }
  356. // Arithmetic Multiply ADD/SUB
  357. class MArithR<string opstr, bit isComm = 0> :
  358. InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
  359. !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
  360. let Defs = [HI0, LO0];
  361. let Uses = [HI0, LO0];
  362. let isCommutable = isComm;
  363. }
  364. // Logical
  365. class LogicNOR<string opstr, RegisterOperand RO>:
  366. InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
  367. !strconcat(opstr, "\t$rd, $rs, $rt"),
  368. [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
  369. let isCommutable = 1;
  370. }
  371. // Shifts
  372. class shift_rotate_imm<string opstr, Operand ImmOpnd,
  373. RegisterOperand RO, SDPatternOperator OpNode = null_frag,
  374. SDPatternOperator PF = null_frag> :
  375. InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
  376. !strconcat(opstr, "\t$rd, $rt, $shamt"),
  377. [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
  378. class shift_rotate_reg<string opstr, RegisterOperand RO,
  379. SDPatternOperator OpNode = null_frag>:
  380. InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
  381. !strconcat(opstr, "\t$rd, $rt, $rs"),
  382. [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
  383. // Load Upper Imediate
  384. class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
  385. InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
  386. [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
  387. let neverHasSideEffects = 1;
  388. let isReMaterializable = 1;
  389. }
  390. // Memory Load/Store
  391. class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
  392. InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
  393. InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
  394. [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
  395. let DecoderMethod = "DecodeMem";
  396. let canFoldAsLoad = 1;
  397. let mayLoad = 1;
  398. }
  399. class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
  400. InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
  401. InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
  402. [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
  403. let DecoderMethod = "DecodeMem";
  404. let mayStore = 1;
  405. }
  406. // Load/Store Left/Right
  407. let canFoldAsLoad = 1 in
  408. class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
  409. InstrItinClass Itin> :
  410. InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
  411. !strconcat(opstr, "\t$rt, $addr"),
  412. [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
  413. let DecoderMethod = "DecodeMem";
  414. string Constraints = "$src = $rt";
  415. }
  416. class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
  417. InstrItinClass Itin> :
  418. InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
  419. [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
  420. let DecoderMethod = "DecodeMem";
  421. }
  422. // Conditional Branch
  423. class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
  424. RegisterOperand RO> :
  425. InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
  426. !strconcat(opstr, "\t$rs, $rt, $offset"),
  427. [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
  428. FrmI, opstr> {
  429. let isBranch = 1;
  430. let isTerminator = 1;
  431. let hasDelaySlot = 1;
  432. let Defs = [AT];
  433. }
  434. class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
  435. RegisterOperand RO> :
  436. InstSE<(outs), (ins RO:$rs, opnd:$offset),
  437. !strconcat(opstr, "\t$rs, $offset"),
  438. [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
  439. FrmI, opstr> {
  440. let isBranch = 1;
  441. let isTerminator = 1;
  442. let hasDelaySlot = 1;
  443. let Defs = [AT];
  444. }
  445. // SetCC
  446. class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
  447. InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
  448. !strconcat(opstr, "\t$rd, $rs, $rt"),
  449. [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
  450. IIslt, FrmR, opstr>;
  451. class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
  452. RegisterOperand RO>:
  453. InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
  454. !strconcat(opstr, "\t$rt, $rs, $imm16"),
  455. [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
  456. IIslt, FrmI, opstr>;
  457. // Jump
  458. class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
  459. SDPatternOperator targetoperator, string bopstr> :
  460. InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
  461. [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
  462. let isTerminator=1;
  463. let isBarrier=1;
  464. let hasDelaySlot = 1;
  465. let DecoderMethod = "DecodeJumpTarget";
  466. let Defs = [AT];
  467. }
  468. // Unconditional branch
  469. class UncondBranch<Instruction BEQInst> :
  470. PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
  471. PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
  472. let isBranch = 1;
  473. let isTerminator = 1;
  474. let isBarrier = 1;
  475. let hasDelaySlot = 1;
  476. let Predicates = [RelocPIC, HasStdEnc];
  477. let Defs = [AT];
  478. }
  479. // Base class for indirect branch and return instruction classes.
  480. let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
  481. class JumpFR<string opstr, RegisterOperand RO,
  482. SDPatternOperator operator = null_frag>:
  483. InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
  484. FrmR, opstr>;
  485. // Indirect branch
  486. class IndirectBranch<string opstr, RegisterOperand RO> :
  487. JumpFR<opstr, RO, brind> {
  488. let isBranch = 1;
  489. let isIndirectBranch = 1;
  490. }
  491. // Return instruction
  492. class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
  493. let isReturn = 1;
  494. let isCodeGenOnly = 1;
  495. let hasCtrlDep = 1;
  496. let hasExtraSrcRegAllocReq = 1;
  497. }
  498. // Jump and Link (Call)
  499. let isCall=1, hasDelaySlot=1, Defs = [RA] in {
  500. class JumpLink<string opstr, DAGOperand opnd> :
  501. InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
  502. [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
  503. let DecoderMethod = "DecodeJumpTarget";
  504. }
  505. class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
  506. Register RetReg, RegisterOperand ResRO = RO>:
  507. PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
  508. PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
  509. class JumpLinkReg<string opstr, RegisterOperand RO>:
  510. InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
  511. [], IIBranch, FrmR, opstr>;
  512. class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
  513. InstSE<(outs), (ins RO:$rs, opnd:$offset),
  514. !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
  515. }
  516. class BAL_BR_Pseudo<Instruction RealInst> :
  517. PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
  518. PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
  519. let isBranch = 1;
  520. let isTerminator = 1;
  521. let isBarrier = 1;
  522. let hasDelaySlot = 1;
  523. let Defs = [RA];
  524. }
  525. // Syscall
  526. class SYS_FT<string opstr> :
  527. InstSE<(outs), (ins uimm20:$code_),
  528. !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
  529. // Break
  530. class BRK_FT<string opstr> :
  531. InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
  532. !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
  533. // (D)Eret
  534. class ER_FT<string opstr> :
  535. InstSE<(outs), (ins),
  536. opstr, [], NoItinerary, FrmOther>;
  537. // Interrupts
  538. class DEI_FT<string opstr, RegisterOperand RO> :
  539. InstSE<(outs RO:$rt), (ins),
  540. !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
  541. // Wait
  542. class WAIT_FT<string opstr> :
  543. InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
  544. let Inst{31-26} = 0x10;
  545. let Inst{25} = 1;
  546. let Inst{24-6} = 0;
  547. let Inst{5-0} = 0x20;
  548. }
  549. // Sync
  550. let hasSideEffects = 1 in
  551. class SYNC_FT :
  552. InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
  553. NoItinerary, FrmOther>;
  554. let hasSideEffects = 1 in
  555. class TEQ_FT<string opstr, RegisterOperand RO> :
  556. InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
  557. !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
  558. FrmI, opstr>;
  559. class TEQI_FT<string opstr, RegisterOperand RO> :
  560. InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
  561. !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
  562. // Mul, Div
  563. class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
  564. list<Register> DefRegs> :
  565. InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
  566. itin, FrmR, opstr> {
  567. let isCommutable = 1;
  568. let Defs = DefRegs;
  569. let neverHasSideEffects = 1;
  570. }
  571. // Pseudo multiply/divide instruction with explicit accumulator register
  572. // operands.
  573. class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
  574. SDPatternOperator OpNode, InstrItinClass Itin,
  575. bit IsComm = 1, bit HasSideEffects = 0,
  576. bit UsesCustomInserter = 0> :
  577. PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
  578. [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
  579. PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
  580. let isCommutable = IsComm;
  581. let hasSideEffects = HasSideEffects;
  582. let usesCustomInserter = UsesCustomInserter;
  583. }
  584. // Pseudo multiply add/sub instruction with explicit accumulator register
  585. // operands.
  586. class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
  587. : PseudoSE<(outs ACC64:$ac),
  588. (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
  589. [(set ACC64:$ac,
  590. (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
  591. IIImult>,
  592. PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
  593. string Constraints = "$acin = $ac";
  594. }
  595. class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
  596. list<Register> DefRegs> :
  597. InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
  598. [], itin, FrmR, opstr> {
  599. let Defs = DefRegs;
  600. }
  601. // Move from Hi/Lo
  602. class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
  603. : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
  604. [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>;
  605. class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
  606. InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR,
  607. opstr> {
  608. let Uses = [UseReg];
  609. let neverHasSideEffects = 1;
  610. }
  611. class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
  612. : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
  613. [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>;
  614. class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
  615. InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
  616. FrmR, opstr> {
  617. let Defs = DefRegs;
  618. let neverHasSideEffects = 1;
  619. }
  620. class EffectiveAddress<string opstr, RegisterOperand RO> :
  621. InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
  622. [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
  623. let isCodeGenOnly = 1;
  624. let DecoderMethod = "DecodeMem";
  625. }
  626. // Count Leading Ones/Zeros in Word
  627. class CountLeading0<string opstr, RegisterOperand RO>:
  628. InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
  629. [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
  630. Requires<[HasBitCount, HasStdEnc]>;
  631. class CountLeading1<string opstr, RegisterOperand RO>:
  632. InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
  633. [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
  634. Requires<[HasBitCount, HasStdEnc]>;
  635. // Sign Extend in Register.
  636. class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
  637. InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
  638. [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
  639. let Predicates = [HasSEInReg, HasStdEnc];
  640. }
  641. // Subword Swap
  642. class SubwordSwap<string opstr, RegisterOperand RO>:
  643. InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
  644. NoItinerary, FrmR, opstr> {
  645. let Predicates = [HasSwap, HasStdEnc];
  646. let neverHasSideEffects = 1;
  647. }
  648. // Read Hardware
  649. class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
  650. InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
  651. IIArith, FrmR>;
  652. // Ext and Ins
  653. class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
  654. SDPatternOperator Op = null_frag>:
  655. InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
  656. !strconcat(opstr, " $rt, $rs, $pos, $size"),
  657. [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
  658. FrmR, opstr> {
  659. let Predicates = [HasMips32r2, HasStdEnc];
  660. }
  661. class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
  662. SDPatternOperator Op = null_frag>:
  663. InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
  664. !strconcat(opstr, " $rt, $rs, $pos, $size"),
  665. [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
  666. NoItinerary, FrmR, opstr> {
  667. let Predicates = [HasMips32r2, HasStdEnc];
  668. let Constraints = "$src = $rt";
  669. }
  670. // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
  671. class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
  672. PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
  673. [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
  674. // Atomic Compare & Swap.
  675. class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
  676. PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
  677. [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
  678. class LLBase<string opstr, RegisterOperand RO> :
  679. InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
  680. [], NoItinerary, FrmI> {
  681. let DecoderMethod = "DecodeMem";
  682. let mayLoad = 1;
  683. }
  684. class SCBase<string opstr, RegisterOperand RO> :
  685. InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
  686. !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
  687. let DecoderMethod = "DecodeMem";
  688. let mayStore = 1;
  689. let Constraints = "$rt = $dst";
  690. }
  691. class MFC3OP<string asmstr, RegisterOperand RO> :
  692. InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
  693. !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
  694. class TrapBase<Instruction RealInst>
  695. : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
  696. PseudoInstExpansion<(RealInst 0, 0)> {
  697. let isBarrier = 1;
  698. let isTerminator = 1;
  699. let isCodeGenOnly = 1;
  700. }
  701. //===----------------------------------------------------------------------===//
  702. // Pseudo instructions
  703. //===----------------------------------------------------------------------===//
  704. // Return RA.
  705. let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
  706. def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
  707. let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
  708. def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
  709. [(callseq_start timm:$amt)]>;
  710. def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
  711. [(callseq_end timm:$amt1, timm:$amt2)]>;
  712. }
  713. let usesCustomInserter = 1 in {
  714. def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
  715. def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
  716. def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
  717. def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
  718. def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
  719. def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
  720. def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
  721. def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
  722. def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
  723. def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
  724. def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
  725. def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
  726. def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
  727. def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
  728. def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
  729. def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
  730. def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
  731. def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
  732. def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
  733. def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
  734. def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
  735. def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
  736. def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
  737. def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
  738. }
  739. /// Pseudo instructions for loading and storing accumulator registers.
  740. let isPseudo = 1, isCodeGenOnly = 1 in {
  741. def LOAD_ACC64 : Load<"", ACC64>;
  742. def STORE_ACC64 : Store<"", ACC64>;
  743. }
  744. //===----------------------------------------------------------------------===//
  745. // Instruction definition
  746. //===----------------------------------------------------------------------===//
  747. //===----------------------------------------------------------------------===//
  748. // MipsI Instructions
  749. //===----------------------------------------------------------------------===//
  750. /// Arithmetic Instructions (ALU Immediate)
  751. def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
  752. add>,
  753. ADDI_FM<0x9>, IsAsCheapAsAMove;
  754. def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
  755. def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
  756. SLTI_FM<0xa>;
  757. def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
  758. SLTI_FM<0xb>;
  759. def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
  760. and>,
  761. ADDI_FM<0xc>;
  762. def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
  763. or>,
  764. ADDI_FM<0xd>;
  765. def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
  766. xor>,
  767. ADDI_FM<0xe>;
  768. def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
  769. /// Arithmetic Instructions (3-Operand, R-Type)
  770. def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
  771. ADD_FM<0, 0x21>;
  772. def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
  773. ADD_FM<0, 0x23>;
  774. let Defs = [HI0, LO0] in
  775. def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
  776. ADD_FM<0x1c, 2>;
  777. def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
  778. def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
  779. def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
  780. def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
  781. def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
  782. ADD_FM<0, 0x24>;
  783. def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
  784. ADD_FM<0, 0x25>;
  785. def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
  786. ADD_FM<0, 0x26>;
  787. def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
  788. /// Shift Instructions
  789. def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
  790. SRA_FM<0, 0>;
  791. def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
  792. SRA_FM<2, 0>;
  793. def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
  794. SRA_FM<3, 0>;
  795. def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
  796. def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
  797. def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
  798. // Rotate Instructions
  799. let Predicates = [HasMips32r2, HasStdEnc] in {
  800. def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
  801. immZExt5>,
  802. SRA_FM<2, 1>;
  803. def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
  804. SRLV_FM<6, 1>;
  805. }
  806. /// Load and Store Instructions
  807. /// aligned
  808. def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
  809. def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
  810. LW_FM<0x24>;
  811. def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
  812. LW_FM<0x21>;
  813. def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
  814. def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
  815. LW_FM<0x23>;
  816. def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
  817. def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
  818. def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
  819. /// load/store left/right
  820. let Predicates = [NotInMicroMips] in {
  821. def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
  822. def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
  823. def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
  824. def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
  825. }
  826. def SYNC : SYNC_FT, SYNC_FM;
  827. def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
  828. def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
  829. def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
  830. def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
  831. def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
  832. def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
  833. def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
  834. def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
  835. def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
  836. def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
  837. def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
  838. def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
  839. def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
  840. def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
  841. def TRAP : TrapBase<BREAK>;
  842. def ERET : ER_FT<"eret">, ER_FM<0x18>;
  843. def DERET : ER_FT<"deret">, ER_FM<0x1f>;
  844. def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
  845. def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
  846. def WAIT : WAIT_FT<"wait">;
  847. /// Load-linked, Store-conditional
  848. def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
  849. def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
  850. /// Jump and Branch Instructions
  851. def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
  852. Requires<[RelocStatic, HasStdEnc]>, IsBranch;
  853. def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
  854. def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
  855. def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
  856. def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
  857. BGEZ_FM<1, 1>;
  858. def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
  859. BGEZ_FM<7, 0>;
  860. def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
  861. BGEZ_FM<6, 0>;
  862. def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
  863. BGEZ_FM<1, 0>;
  864. def B : UncondBranch<BEQ>;
  865. def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
  866. def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
  867. def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
  868. def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
  869. def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
  870. def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
  871. def TAILCALL : MMRel, JumpFJ<calltarget, "j", MipsTailCall, imm, "tcall">,
  872. FJ<2>, IsTailCall;
  873. def TAILCALL_R : MMRel, JumpFR<"tcallr", GPR32Opnd, MipsTailCall>, MTLO_FM<8>,
  874. IsTailCall;
  875. def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
  876. // Exception handling related node and instructions.
  877. // The conversion sequence is:
  878. // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
  879. // MIPSeh_return -> (stack change + indirect branch)
  880. //
  881. // MIPSeh_return takes the place of regular return instruction
  882. // but takes two arguments (V1, V0) which are used for storing
  883. // the offset and return address respectively.
  884. def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
  885. def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
  886. [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
  887. let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
  888. def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
  889. [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
  890. def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
  891. GPR64:$dst),
  892. [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
  893. }
  894. /// Multiply and Divide Instructions.
  895. def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
  896. MULT_FM<0, 0x18>;
  897. def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
  898. MULT_FM<0, 0x19>;
  899. def SDIV : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
  900. MULT_FM<0, 0x1a>;
  901. def UDIV : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
  902. MULT_FM<0, 0x1b>;
  903. def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
  904. def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
  905. def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
  906. def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
  907. /// Sign Ext In Register Instructions.
  908. def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
  909. def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
  910. /// Count Leading
  911. def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
  912. def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
  913. /// Word Swap Bytes Within Halfwords
  914. def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
  915. /// No operation.
  916. def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
  917. // FrameIndexes are legalized when they are operands from load/store
  918. // instructions. The same not happens for stack address copies, so an
  919. // add op with mem ComplexPattern is used and the stack address copy
  920. // can be matched. It's similar to Sparc LEA_ADDRi
  921. def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
  922. // MADD*/MSUB*
  923. def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
  924. def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
  925. def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
  926. def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
  927. let Predicates = [HasStdEnc, NotDSP] in {
  928. def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
  929. def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
  930. def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
  931. def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
  932. def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
  933. def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
  934. def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
  935. def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
  936. def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
  937. }
  938. def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
  939. 0, 1, 1>;
  940. def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
  941. 0, 1, 1>;
  942. def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
  943. def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
  944. def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
  945. /// Move Control Registers From/To CPU Registers
  946. def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
  947. def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
  948. def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
  949. def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
  950. //===----------------------------------------------------------------------===//
  951. // Instruction aliases
  952. //===----------------------------------------------------------------------===//
  953. def : InstAlias<"move $dst, $src",
  954. (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
  955. Requires<[NotMips64]>;
  956. def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
  957. def : InstAlias<"addu $rs, $rt, $imm",
  958. (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
  959. def : InstAlias<"add $rs, $rt, $imm",
  960. (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
  961. def : InstAlias<"and $rs, $rt, $imm",
  962. (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
  963. def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
  964. def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
  965. def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
  966. def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
  967. def : InstAlias<"not $rt, $rs",
  968. (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
  969. def : InstAlias<"neg $rt, $rs",
  970. (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
  971. def : InstAlias<"negu $rt, $rs",
  972. (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
  973. def : InstAlias<"slt $rs, $rt, $imm",
  974. (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
  975. def : InstAlias<"xor $rs, $rt, $imm",
  976. (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
  977. def : InstAlias<"or $rs, $rt, $imm",
  978. (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
  979. def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
  980. def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
  981. def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
  982. def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
  983. def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
  984. def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
  985. def : InstAlias<"bnez $rs,$offset",
  986. (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
  987. def : InstAlias<"beqz $rs,$offset",
  988. (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
  989. def : InstAlias<"syscall", (SYSCALL 0), 1>;
  990. def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
  991. def : InstAlias<"break", (BREAK 0, 0), 1>;
  992. def : InstAlias<"ei", (EI ZERO), 1>;
  993. def : InstAlias<"di", (DI ZERO), 1>;
  994. def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
  995. def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
  996. def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
  997. def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
  998. def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
  999. def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
  1000. def : InstAlias<"sub, $rd, $rs, $imm",
  1001. (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
  1002. def : InstAlias<"subu, $rd, $rs, $imm",
  1003. (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
  1004. //===----------------------------------------------------------------------===//
  1005. // Assembler Pseudo Instructions
  1006. //===----------------------------------------------------------------------===//
  1007. class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
  1008. MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
  1009. !strconcat(instr_asm, "\t$rt, $imm32")> ;
  1010. def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
  1011. class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
  1012. MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
  1013. !strconcat(instr_asm, "\t$rt, $addr")> ;
  1014. def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
  1015. class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
  1016. MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
  1017. !strconcat(instr_asm, "\t$rt, $imm32")> ;
  1018. def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
  1019. //===----------------------------------------------------------------------===//
  1020. // Arbitrary patterns that map to one or more instructions
  1021. //===----------------------------------------------------------------------===//
  1022. // Load/store pattern templates.
  1023. class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
  1024. MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
  1025. class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
  1026. MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
  1027. // Small immediates
  1028. def : MipsPat<(i32 immSExt16:$in),
  1029. (ADDiu ZERO, imm:$in)>;
  1030. def : MipsPat<(i32 immZExt16:$in),
  1031. (ORi ZERO, imm:$in)>;
  1032. def : MipsPat<(i32 immLow16Zero:$in),
  1033. (LUi (HI16 imm:$in))>;
  1034. // Arbitrary immediates
  1035. def : MipsPat<(i32 imm:$imm),
  1036. (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
  1037. // Carry MipsPatterns
  1038. def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
  1039. (SUBu GPR32:$lhs, GPR32:$rhs)>;
  1040. let Predicates = [HasStdEnc, NotDSP] in {
  1041. def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
  1042. (ADDu GPR32:$lhs, GPR32:$rhs)>;
  1043. def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
  1044. (ADDiu GPR32:$src, imm:$imm)>;
  1045. }
  1046. // Call
  1047. def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
  1048. (JAL tglobaladdr:$dst)>;
  1049. def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
  1050. (JAL texternalsym:$dst)>;
  1051. //def : MipsPat<(MipsJmpLink GPR32:$dst),
  1052. // (JALR GPR32:$dst)>;
  1053. // Tail call
  1054. def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
  1055. (TAILCALL tglobaladdr:$dst)>;
  1056. def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
  1057. (TAILCALL texternalsym:$dst)>;
  1058. // hi/lo relocs
  1059. def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
  1060. def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
  1061. def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
  1062. def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
  1063. def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
  1064. def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
  1065. def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
  1066. def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
  1067. def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
  1068. def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
  1069. def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
  1070. def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
  1071. def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
  1072. (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
  1073. def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
  1074. (ADDiu GPR32:$hi, tblockaddress:$lo)>;
  1075. def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
  1076. (ADDiu GPR32:$hi, tjumptable:$lo)>;
  1077. def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
  1078. (ADDiu GPR32:$hi, tconstpool:$lo)>;
  1079. def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
  1080. (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
  1081. // gp_rel relocs
  1082. def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
  1083. (ADDiu GPR32:$gp, tglobaladdr:$in)>;
  1084. def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
  1085. (ADDiu GPR32:$gp, tconstpool:$in)>;
  1086. // wrapper_pic
  1087. class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
  1088. MipsPat<(MipsWrapper RC:$gp, node:$in),
  1089. (ADDiuOp RC:$gp, node:$in)>;
  1090. def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
  1091. def : WrapperPat<tconstpool, ADDiu, GPR32>;
  1092. def : WrapperPat<texternalsym, ADDiu, GPR32>;
  1093. def : WrapperPat<tblockaddress, ADDiu, GPR32>;
  1094. def : WrapperPat<tjumptable, ADDiu, GPR32>;
  1095. def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
  1096. // Mips does not have "not", so we expand our way
  1097. def : MipsPat<(not GPR32:$in),
  1098. (NOR GPR32Opnd:$in, ZERO)>;
  1099. // extended loads
  1100. let Predicates = [HasStdEnc] in {
  1101. def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
  1102. def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
  1103. def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
  1104. }
  1105. // peepholes
  1106. let Predicates = [HasStdEnc] in
  1107. def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
  1108. // brcond patterns
  1109. multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
  1110. Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
  1111. Instruction SLTiuOp, Register ZEROReg> {
  1112. def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
  1113. (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
  1114. def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
  1115. (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
  1116. def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
  1117. (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
  1118. def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
  1119. (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
  1120. def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
  1121. (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
  1122. def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
  1123. (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
  1124. def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
  1125. (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
  1126. def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
  1127. (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
  1128. def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
  1129. (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
  1130. def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
  1131. (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
  1132. def : MipsPat<(brcond RC:$cond, bb:$dst),
  1133. (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
  1134. }
  1135. defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
  1136. def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
  1137. (BLEZ i32:$lhs, bb:$dst)>;
  1138. def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
  1139. (BGEZ i32:$lhs, bb:$dst)>;
  1140. // setcc patterns
  1141. multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
  1142. Instruction SLTuOp, Register ZEROReg> {
  1143. def : MipsPat<(seteq RC:$lhs, 0),
  1144. (SLTiuOp RC:$lhs, 1)>;
  1145. def : MipsPat<(setne RC:$lhs, 0),
  1146. (SLTuOp ZEROReg, RC:$lhs)>;
  1147. def : MipsPat<(seteq RC:$lhs, RC:$rhs),
  1148. (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
  1149. def : MipsPat<(setne RC:$lhs, RC:$rhs),
  1150. (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
  1151. }
  1152. multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
  1153. def : MipsPat<(setle RC:$lhs, RC:$rhs),
  1154. (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
  1155. def : MipsPat<(setule RC:$lhs, RC:$rhs),
  1156. (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
  1157. }
  1158. multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
  1159. def : MipsPat<(setgt RC:$lhs, RC:$rhs),
  1160. (SLTOp RC:$rhs, RC:$lhs)>;
  1161. def : MipsPat<(setugt RC:$lhs, RC:$rhs),
  1162. (SLTuOp RC:$rhs, RC:$lhs)>;
  1163. }
  1164. multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
  1165. def : MipsPat<(setge RC:$lhs, RC:$rhs),
  1166. (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
  1167. def : MipsPat<(setuge RC:$lhs, RC:$rhs),
  1168. (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
  1169. }
  1170. multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
  1171. Instruction SLTiuOp> {
  1172. def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
  1173. (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
  1174. def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
  1175. (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
  1176. }
  1177. defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
  1178. defm : SetlePats<GPR32, SLT, SLTu>;
  1179. defm : SetgtPats<GPR32, SLT, SLTu>;
  1180. defm : SetgePats<GPR32, SLT, SLTu>;
  1181. defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
  1182. // bswap pattern
  1183. def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
  1184. // Load halfword/word patterns.
  1185. let AddedComplexity = 40 in {
  1186. let Predicates = [HasStdEnc] in {
  1187. def : LoadRegImmPat<LBu, i32, zextloadi8>;
  1188. def : LoadRegImmPat<LH, i32, sextloadi16>;
  1189. def : LoadRegImmPat<LW, i32, load>;
  1190. }
  1191. }
  1192. //===----------------------------------------------------------------------===//
  1193. // Floating Point Support
  1194. //===----------------------------------------------------------------------===//
  1195. include "MipsInstrFPU.td"
  1196. include "Mips64InstrInfo.td"
  1197. include "MipsCondMov.td"
  1198. //
  1199. // Mips16
  1200. include "Mips16InstrFormats.td"
  1201. include "Mips16InstrInfo.td"
  1202. // DSP
  1203. include "MipsDSPInstrFormats.td"
  1204. include "MipsDSPInstrInfo.td"
  1205. // MSA
  1206. include "MipsMSAInstrFormats.td"
  1207. include "MipsMSAInstrInfo.td"
  1208. // Micromips
  1209. include "MicroMipsInstrFormats.td"
  1210. include "MicroMipsInstrInfo.td"