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/drivers/gpu/drm/amd/amdgpu/si.c

https://gitlab.com/sunny256/linux
C | 2004 lines | 1801 code | 165 blank | 38 comment | 161 complexity | 281ef626c773d5ca3dfa04647af64c36 MD5 | raw file
Possible License(s): GPL-2.0
  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/firmware.h>
  24. #include <linux/slab.h>
  25. #include <linux/module.h>
  26. #include <drm/drmP.h>
  27. #include "amdgpu.h"
  28. #include "amdgpu_atombios.h"
  29. #include "amdgpu_ih.h"
  30. #include "amdgpu_uvd.h"
  31. #include "amdgpu_vce.h"
  32. #include "atom.h"
  33. #include "amdgpu_powerplay.h"
  34. #include "sid.h"
  35. #include "si_ih.h"
  36. #include "gfx_v6_0.h"
  37. #include "gmc_v6_0.h"
  38. #include "si_dma.h"
  39. #include "dce_v6_0.h"
  40. #include "si.h"
  41. #include "dce_virtual.h"
  42. #include "gca/gfx_6_0_d.h"
  43. #include "oss/oss_1_0_d.h"
  44. #include "gmc/gmc_6_0_d.h"
  45. #include "dce/dce_6_0_d.h"
  46. #include "uvd/uvd_4_0_d.h"
  47. #include "bif/bif_3_0_d.h"
  48. static const u32 tahiti_golden_registers[] =
  49. {
  50. mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
  51. mmCB_HW_CONTROL, 0x00010000, 0x00018208,
  52. mmDB_DEBUG, 0xffffffff, 0x00000000,
  53. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  54. mmDB_DEBUG3, 0x0002021c, 0x00020200,
  55. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  56. 0x340c, 0x000000c0, 0x00800040,
  57. 0x360c, 0x000000c0, 0x00800040,
  58. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  59. mmFBC_MISC, 0x00200000, 0x50100000,
  60. mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
  61. mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff,
  62. mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
  63. mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
  64. mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
  65. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  66. mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
  67. mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
  68. 0x000c, 0xffffffff, 0x0040,
  69. 0x000d, 0x00000040, 0x00004040,
  70. mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
  71. mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
  72. mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
  73. mmSX_DEBUG_1, 0x0000007f, 0x00000020,
  74. mmTA_CNTL_AUX, 0x00010000, 0x00010000,
  75. mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb,
  76. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
  77. mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
  78. mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40,
  79. mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
  80. mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8,
  81. mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
  82. mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
  83. mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  84. mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  85. mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  86. };
  87. static const u32 tahiti_golden_registers2[] =
  88. {
  89. mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001,
  90. };
  91. static const u32 tahiti_golden_rlc_registers[] =
  92. {
  93. mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
  94. mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
  95. 0x311f, 0xffffffff, 0x10104040,
  96. 0x3122, 0xffffffff, 0x0100000a,
  97. mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
  98. mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
  99. mmUVD_CGC_GATE, 0x00000008, 0x00000000,
  100. };
  101. static const u32 pitcairn_golden_registers[] =
  102. {
  103. mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
  104. mmCB_HW_CONTROL, 0x00010000, 0x00018208,
  105. mmDB_DEBUG, 0xffffffff, 0x00000000,
  106. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  107. mmDB_DEBUG3, 0x0002021c, 0x00020200,
  108. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  109. 0x340c, 0x000300c0, 0x00800040,
  110. 0x360c, 0x000300c0, 0x00800040,
  111. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  112. mmFBC_MISC, 0x00200000, 0x50100000,
  113. mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
  114. mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
  115. mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
  116. mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
  117. mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
  118. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  119. mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
  120. mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
  121. 0x000c, 0xffffffff, 0x0040,
  122. 0x000d, 0x00000040, 0x00004040,
  123. mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
  124. mmSX_DEBUG_1, 0x0000007f, 0x00000020,
  125. mmTA_CNTL_AUX, 0x00010000, 0x00010000,
  126. mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
  127. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
  128. mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
  129. mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
  130. mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
  131. mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
  132. mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  133. mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  134. mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  135. };
  136. static const u32 pitcairn_golden_rlc_registers[] =
  137. {
  138. mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
  139. mmRLC_LB_PARAMS, 0xffffffff, 0x00601004,
  140. 0x311f, 0xffffffff, 0x10102020,
  141. 0x3122, 0xffffffff, 0x01000020,
  142. mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
  143. mmRLC_LB_CNTL, 0xffffffff, 0x800000a4,
  144. };
  145. static const u32 verde_pg_init[] =
  146. {
  147. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000,
  148. mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff,
  149. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  150. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  151. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  152. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  153. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  154. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007,
  155. mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff,
  156. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  157. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  158. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  159. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  160. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  161. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000,
  162. mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff,
  163. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  164. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  165. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  166. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  167. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  168. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200,
  169. mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff,
  170. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  171. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  172. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  173. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  174. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  175. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16,
  176. mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff,
  177. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  178. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  179. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  180. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  181. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  182. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e,
  183. mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff,
  184. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  185. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  186. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  187. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  188. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  189. mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
  190. mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff,
  191. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0,
  192. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800,
  193. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
  194. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
  195. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4,
  196. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e,
  197. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
  198. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
  199. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8,
  200. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500,
  201. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12,
  202. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c,
  203. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d,
  204. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c,
  205. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a,
  206. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e,
  207. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d,
  208. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546,
  209. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30,
  210. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e,
  211. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c,
  212. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f,
  213. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f,
  214. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567,
  215. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42,
  216. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f,
  217. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45,
  218. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572,
  219. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48,
  220. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575,
  221. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c,
  222. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801,
  223. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67,
  224. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a,
  225. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a,
  226. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d,
  227. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87,
  228. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851,
  229. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba,
  230. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891,
  231. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc,
  232. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893,
  233. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe,
  234. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895,
  235. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2,
  236. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899,
  237. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6,
  238. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d,
  239. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca,
  240. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1,
  241. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc,
  242. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3,
  243. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce,
  244. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5,
  245. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3,
  246. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd,
  247. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142,
  248. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a,
  249. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1,
  250. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144,
  251. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b,
  252. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165,
  253. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d,
  254. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173,
  255. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d,
  256. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184,
  257. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f,
  258. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b,
  259. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998,
  260. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9,
  261. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7,
  262. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af,
  263. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc,
  264. mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1,
  265. mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800,
  266. mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000,
  267. mmGMCON_MISC2, 0xfc00, 0x2000,
  268. mmGMCON_MISC3, 0xffffffff, 0xfc0,
  269. mmMC_PMG_AUTO_CFG, 0x00000100, 0x100,
  270. };
  271. static const u32 verde_golden_rlc_registers[] =
  272. {
  273. mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
  274. mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005,
  275. 0x311f, 0xffffffff, 0x10808020,
  276. 0x3122, 0xffffffff, 0x00800008,
  277. mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000,
  278. mmRLC_LB_CNTL, 0xffffffff, 0x80010014,
  279. };
  280. static const u32 verde_golden_registers[] =
  281. {
  282. mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
  283. mmCB_HW_CONTROL, 0x00010000, 0x00018208,
  284. mmDB_DEBUG, 0xffffffff, 0x00000000,
  285. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  286. mmDB_DEBUG3, 0x0002021c, 0x00020200,
  287. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  288. 0x340c, 0x000300c0, 0x00800040,
  289. 0x360c, 0x000300c0, 0x00800040,
  290. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  291. mmFBC_MISC, 0x00200000, 0x50100000,
  292. mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
  293. mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
  294. mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
  295. mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
  296. mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
  297. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  298. mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
  299. mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a,
  300. 0x000c, 0xffffffff, 0x0040,
  301. 0x000d, 0x00000040, 0x00004040,
  302. mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
  303. mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
  304. mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
  305. mmSX_DEBUG_1, 0x0000007f, 0x00000020,
  306. mmTA_CNTL_AUX, 0x00010000, 0x00010000,
  307. mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003,
  308. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
  309. mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032,
  310. mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
  311. mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
  312. mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
  313. mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  314. mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  315. mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  316. };
  317. static const u32 oland_golden_registers[] =
  318. {
  319. mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
  320. mmCB_HW_CONTROL, 0x00010000, 0x00018208,
  321. mmDB_DEBUG, 0xffffffff, 0x00000000,
  322. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  323. mmDB_DEBUG3, 0x0002021c, 0x00020200,
  324. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  325. 0x340c, 0x000300c0, 0x00800040,
  326. 0x360c, 0x000300c0, 0x00800040,
  327. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  328. mmFBC_MISC, 0x00200000, 0x50100000,
  329. mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
  330. mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
  331. mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
  332. mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
  333. mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
  334. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  335. mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
  336. mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082,
  337. 0x000c, 0xffffffff, 0x0040,
  338. 0x000d, 0x00000040, 0x00004040,
  339. mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
  340. mmSX_DEBUG_1, 0x0000007f, 0x00000020,
  341. mmTA_CNTL_AUX, 0x00010000, 0x00010000,
  342. mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
  343. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
  344. mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
  345. mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
  346. mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
  347. mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
  348. mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  349. mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  350. mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  351. };
  352. static const u32 oland_golden_rlc_registers[] =
  353. {
  354. mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
  355. mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
  356. 0x311f, 0xffffffff, 0x10104040,
  357. 0x3122, 0xffffffff, 0x0100000a,
  358. mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
  359. mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
  360. };
  361. static const u32 hainan_golden_registers[] =
  362. {
  363. 0x17bc, 0x00000030, 0x00000011,
  364. mmCB_HW_CONTROL, 0x00010000, 0x00018208,
  365. mmDB_DEBUG, 0xffffffff, 0x00000000,
  366. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  367. mmDB_DEBUG3, 0x0002021c, 0x00020200,
  368. 0x031e, 0x00000080, 0x00000000,
  369. 0x3430, 0xff000fff, 0x00000100,
  370. 0x340c, 0x000300c0, 0x00800040,
  371. 0x3630, 0xff000fff, 0x00000100,
  372. 0x360c, 0x000300c0, 0x00800040,
  373. 0x16ec, 0x000000f0, 0x00000070,
  374. 0x16f0, 0x00200000, 0x50100000,
  375. 0x1c0c, 0x31000311, 0x00000011,
  376. mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
  377. mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
  378. mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
  379. mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
  380. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  381. mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
  382. mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000,
  383. 0x000c, 0xffffffff, 0x0040,
  384. 0x000d, 0x00000040, 0x00004040,
  385. mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000,
  386. mmSX_DEBUG_1, 0x0000007f, 0x00000020,
  387. mmTA_CNTL_AUX, 0x00010000, 0x00010000,
  388. mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
  389. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
  390. mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
  391. mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
  392. mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
  393. mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
  394. mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  395. mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  396. mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  397. };
  398. static const u32 hainan_golden_registers2[] =
  399. {
  400. mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003,
  401. };
  402. static const u32 tahiti_mgcg_cgcg_init[] =
  403. {
  404. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
  405. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  406. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  407. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  408. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  409. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  410. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  411. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  412. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  413. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  414. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  415. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  416. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  417. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  418. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  419. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  420. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  421. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  422. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  423. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  424. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  425. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  426. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  427. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  428. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  429. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  430. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  431. 0x2458, 0xffffffff, 0x00010000,
  432. 0x2459, 0xffffffff, 0x00030002,
  433. 0x245a, 0xffffffff, 0x00040007,
  434. 0x245b, 0xffffffff, 0x00060005,
  435. 0x245c, 0xffffffff, 0x00090008,
  436. 0x245d, 0xffffffff, 0x00020001,
  437. 0x245e, 0xffffffff, 0x00040003,
  438. 0x245f, 0xffffffff, 0x00000007,
  439. 0x2460, 0xffffffff, 0x00060005,
  440. 0x2461, 0xffffffff, 0x00090008,
  441. 0x2462, 0xffffffff, 0x00030002,
  442. 0x2463, 0xffffffff, 0x00050004,
  443. 0x2464, 0xffffffff, 0x00000008,
  444. 0x2465, 0xffffffff, 0x00070006,
  445. 0x2466, 0xffffffff, 0x000a0009,
  446. 0x2467, 0xffffffff, 0x00040003,
  447. 0x2468, 0xffffffff, 0x00060005,
  448. 0x2469, 0xffffffff, 0x00000009,
  449. 0x246a, 0xffffffff, 0x00080007,
  450. 0x246b, 0xffffffff, 0x000b000a,
  451. 0x246c, 0xffffffff, 0x00050004,
  452. 0x246d, 0xffffffff, 0x00070006,
  453. 0x246e, 0xffffffff, 0x0008000b,
  454. 0x246f, 0xffffffff, 0x000a0009,
  455. 0x2470, 0xffffffff, 0x000d000c,
  456. 0x2471, 0xffffffff, 0x00060005,
  457. 0x2472, 0xffffffff, 0x00080007,
  458. 0x2473, 0xffffffff, 0x0000000b,
  459. 0x2474, 0xffffffff, 0x000a0009,
  460. 0x2475, 0xffffffff, 0x000d000c,
  461. 0x2476, 0xffffffff, 0x00070006,
  462. 0x2477, 0xffffffff, 0x00090008,
  463. 0x2478, 0xffffffff, 0x0000000c,
  464. 0x2479, 0xffffffff, 0x000b000a,
  465. 0x247a, 0xffffffff, 0x000e000d,
  466. 0x247b, 0xffffffff, 0x00080007,
  467. 0x247c, 0xffffffff, 0x000a0009,
  468. 0x247d, 0xffffffff, 0x0000000d,
  469. 0x247e, 0xffffffff, 0x000c000b,
  470. 0x247f, 0xffffffff, 0x000f000e,
  471. 0x2480, 0xffffffff, 0x00090008,
  472. 0x2481, 0xffffffff, 0x000b000a,
  473. 0x2482, 0xffffffff, 0x000c000f,
  474. 0x2483, 0xffffffff, 0x000e000d,
  475. 0x2484, 0xffffffff, 0x00110010,
  476. 0x2485, 0xffffffff, 0x000a0009,
  477. 0x2486, 0xffffffff, 0x000c000b,
  478. 0x2487, 0xffffffff, 0x0000000f,
  479. 0x2488, 0xffffffff, 0x000e000d,
  480. 0x2489, 0xffffffff, 0x00110010,
  481. 0x248a, 0xffffffff, 0x000b000a,
  482. 0x248b, 0xffffffff, 0x000d000c,
  483. 0x248c, 0xffffffff, 0x00000010,
  484. 0x248d, 0xffffffff, 0x000f000e,
  485. 0x248e, 0xffffffff, 0x00120011,
  486. 0x248f, 0xffffffff, 0x000c000b,
  487. 0x2490, 0xffffffff, 0x000e000d,
  488. 0x2491, 0xffffffff, 0x00000011,
  489. 0x2492, 0xffffffff, 0x0010000f,
  490. 0x2493, 0xffffffff, 0x00130012,
  491. 0x2494, 0xffffffff, 0x000d000c,
  492. 0x2495, 0xffffffff, 0x000f000e,
  493. 0x2496, 0xffffffff, 0x00100013,
  494. 0x2497, 0xffffffff, 0x00120011,
  495. 0x2498, 0xffffffff, 0x00150014,
  496. 0x2499, 0xffffffff, 0x000e000d,
  497. 0x249a, 0xffffffff, 0x0010000f,
  498. 0x249b, 0xffffffff, 0x00000013,
  499. 0x249c, 0xffffffff, 0x00120011,
  500. 0x249d, 0xffffffff, 0x00150014,
  501. 0x249e, 0xffffffff, 0x000f000e,
  502. 0x249f, 0xffffffff, 0x00110010,
  503. 0x24a0, 0xffffffff, 0x00000014,
  504. 0x24a1, 0xffffffff, 0x00130012,
  505. 0x24a2, 0xffffffff, 0x00160015,
  506. 0x24a3, 0xffffffff, 0x0010000f,
  507. 0x24a4, 0xffffffff, 0x00120011,
  508. 0x24a5, 0xffffffff, 0x00000015,
  509. 0x24a6, 0xffffffff, 0x00140013,
  510. 0x24a7, 0xffffffff, 0x00170016,
  511. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
  512. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  513. mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
  514. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
  515. 0x000c, 0xffffffff, 0x0000001c,
  516. 0x000d, 0x000f0000, 0x000f0000,
  517. 0x0583, 0xffffffff, 0x00000100,
  518. mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
  519. mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
  520. mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
  521. mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
  522. mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
  523. mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
  524. 0x157a, 0x00000001, 0x00000001,
  525. mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
  526. mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
  527. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  528. 0x3430, 0xfffffff0, 0x00000100,
  529. 0x3630, 0xfffffff0, 0x00000100,
  530. };
  531. static const u32 pitcairn_mgcg_cgcg_init[] =
  532. {
  533. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
  534. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  535. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  536. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  537. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  538. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  539. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  540. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  541. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  542. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  543. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  544. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  545. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  546. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  547. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  548. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  549. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  550. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  551. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  552. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  553. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  554. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  555. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  556. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  557. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  558. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  559. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  560. 0x2458, 0xffffffff, 0x00010000,
  561. 0x2459, 0xffffffff, 0x00030002,
  562. 0x245a, 0xffffffff, 0x00040007,
  563. 0x245b, 0xffffffff, 0x00060005,
  564. 0x245c, 0xffffffff, 0x00090008,
  565. 0x245d, 0xffffffff, 0x00020001,
  566. 0x245e, 0xffffffff, 0x00040003,
  567. 0x245f, 0xffffffff, 0x00000007,
  568. 0x2460, 0xffffffff, 0x00060005,
  569. 0x2461, 0xffffffff, 0x00090008,
  570. 0x2462, 0xffffffff, 0x00030002,
  571. 0x2463, 0xffffffff, 0x00050004,
  572. 0x2464, 0xffffffff, 0x00000008,
  573. 0x2465, 0xffffffff, 0x00070006,
  574. 0x2466, 0xffffffff, 0x000a0009,
  575. 0x2467, 0xffffffff, 0x00040003,
  576. 0x2468, 0xffffffff, 0x00060005,
  577. 0x2469, 0xffffffff, 0x00000009,
  578. 0x246a, 0xffffffff, 0x00080007,
  579. 0x246b, 0xffffffff, 0x000b000a,
  580. 0x246c, 0xffffffff, 0x00050004,
  581. 0x246d, 0xffffffff, 0x00070006,
  582. 0x246e, 0xffffffff, 0x0008000b,
  583. 0x246f, 0xffffffff, 0x000a0009,
  584. 0x2470, 0xffffffff, 0x000d000c,
  585. 0x2480, 0xffffffff, 0x00090008,
  586. 0x2481, 0xffffffff, 0x000b000a,
  587. 0x2482, 0xffffffff, 0x000c000f,
  588. 0x2483, 0xffffffff, 0x000e000d,
  589. 0x2484, 0xffffffff, 0x00110010,
  590. 0x2485, 0xffffffff, 0x000a0009,
  591. 0x2486, 0xffffffff, 0x000c000b,
  592. 0x2487, 0xffffffff, 0x0000000f,
  593. 0x2488, 0xffffffff, 0x000e000d,
  594. 0x2489, 0xffffffff, 0x00110010,
  595. 0x248a, 0xffffffff, 0x000b000a,
  596. 0x248b, 0xffffffff, 0x000d000c,
  597. 0x248c, 0xffffffff, 0x00000010,
  598. 0x248d, 0xffffffff, 0x000f000e,
  599. 0x248e, 0xffffffff, 0x00120011,
  600. 0x248f, 0xffffffff, 0x000c000b,
  601. 0x2490, 0xffffffff, 0x000e000d,
  602. 0x2491, 0xffffffff, 0x00000011,
  603. 0x2492, 0xffffffff, 0x0010000f,
  604. 0x2493, 0xffffffff, 0x00130012,
  605. 0x2494, 0xffffffff, 0x000d000c,
  606. 0x2495, 0xffffffff, 0x000f000e,
  607. 0x2496, 0xffffffff, 0x00100013,
  608. 0x2497, 0xffffffff, 0x00120011,
  609. 0x2498, 0xffffffff, 0x00150014,
  610. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
  611. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  612. mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
  613. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
  614. 0x000c, 0xffffffff, 0x0000001c,
  615. 0x000d, 0x000f0000, 0x000f0000,
  616. 0x0583, 0xffffffff, 0x00000100,
  617. mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
  618. mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
  619. mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
  620. mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
  621. 0x157a, 0x00000001, 0x00000001,
  622. mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
  623. mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
  624. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  625. 0x3430, 0xfffffff0, 0x00000100,
  626. 0x3630, 0xfffffff0, 0x00000100,
  627. };
  628. static const u32 verde_mgcg_cgcg_init[] =
  629. {
  630. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
  631. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  632. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  633. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  634. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  635. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  636. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  637. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  638. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  639. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  640. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  641. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  642. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  643. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  644. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  645. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  646. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  647. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  648. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  649. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  650. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  651. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  652. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  653. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  654. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  655. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  656. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  657. 0x2458, 0xffffffff, 0x00010000,
  658. 0x2459, 0xffffffff, 0x00030002,
  659. 0x245a, 0xffffffff, 0x00040007,
  660. 0x245b, 0xffffffff, 0x00060005,
  661. 0x245c, 0xffffffff, 0x00090008,
  662. 0x245d, 0xffffffff, 0x00020001,
  663. 0x245e, 0xffffffff, 0x00040003,
  664. 0x245f, 0xffffffff, 0x00000007,
  665. 0x2460, 0xffffffff, 0x00060005,
  666. 0x2461, 0xffffffff, 0x00090008,
  667. 0x2462, 0xffffffff, 0x00030002,
  668. 0x2463, 0xffffffff, 0x00050004,
  669. 0x2464, 0xffffffff, 0x00000008,
  670. 0x2465, 0xffffffff, 0x00070006,
  671. 0x2466, 0xffffffff, 0x000a0009,
  672. 0x2467, 0xffffffff, 0x00040003,
  673. 0x2468, 0xffffffff, 0x00060005,
  674. 0x2469, 0xffffffff, 0x00000009,
  675. 0x246a, 0xffffffff, 0x00080007,
  676. 0x246b, 0xffffffff, 0x000b000a,
  677. 0x246c, 0xffffffff, 0x00050004,
  678. 0x246d, 0xffffffff, 0x00070006,
  679. 0x246e, 0xffffffff, 0x0008000b,
  680. 0x246f, 0xffffffff, 0x000a0009,
  681. 0x2470, 0xffffffff, 0x000d000c,
  682. 0x2480, 0xffffffff, 0x00090008,
  683. 0x2481, 0xffffffff, 0x000b000a,
  684. 0x2482, 0xffffffff, 0x000c000f,
  685. 0x2483, 0xffffffff, 0x000e000d,
  686. 0x2484, 0xffffffff, 0x00110010,
  687. 0x2485, 0xffffffff, 0x000a0009,
  688. 0x2486, 0xffffffff, 0x000c000b,
  689. 0x2487, 0xffffffff, 0x0000000f,
  690. 0x2488, 0xffffffff, 0x000e000d,
  691. 0x2489, 0xffffffff, 0x00110010,
  692. 0x248a, 0xffffffff, 0x000b000a,
  693. 0x248b, 0xffffffff, 0x000d000c,
  694. 0x248c, 0xffffffff, 0x00000010,
  695. 0x248d, 0xffffffff, 0x000f000e,
  696. 0x248e, 0xffffffff, 0x00120011,
  697. 0x248f, 0xffffffff, 0x000c000b,
  698. 0x2490, 0xffffffff, 0x000e000d,
  699. 0x2491, 0xffffffff, 0x00000011,
  700. 0x2492, 0xffffffff, 0x0010000f,
  701. 0x2493, 0xffffffff, 0x00130012,
  702. 0x2494, 0xffffffff, 0x000d000c,
  703. 0x2495, 0xffffffff, 0x000f000e,
  704. 0x2496, 0xffffffff, 0x00100013,
  705. 0x2497, 0xffffffff, 0x00120011,
  706. 0x2498, 0xffffffff, 0x00150014,
  707. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
  708. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  709. mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
  710. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
  711. 0x000c, 0xffffffff, 0x0000001c,
  712. 0x000d, 0x000f0000, 0x000f0000,
  713. 0x0583, 0xffffffff, 0x00000100,
  714. mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
  715. mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
  716. mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
  717. mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
  718. mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
  719. mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
  720. 0x157a, 0x00000001, 0x00000001,
  721. mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
  722. mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
  723. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  724. 0x3430, 0xfffffff0, 0x00000100,
  725. 0x3630, 0xfffffff0, 0x00000100,
  726. };
  727. static const u32 oland_mgcg_cgcg_init[] =
  728. {
  729. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
  730. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  731. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  732. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  733. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  734. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  735. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  736. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  737. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  738. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  739. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  740. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  741. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  742. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  743. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  744. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  745. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  746. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  747. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  748. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  749. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  750. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  751. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  752. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  753. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  754. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  755. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  756. 0x2458, 0xffffffff, 0x00010000,
  757. 0x2459, 0xffffffff, 0x00030002,
  758. 0x245a, 0xffffffff, 0x00040007,
  759. 0x245b, 0xffffffff, 0x00060005,
  760. 0x245c, 0xffffffff, 0x00090008,
  761. 0x245d, 0xffffffff, 0x00020001,
  762. 0x245e, 0xffffffff, 0x00040003,
  763. 0x245f, 0xffffffff, 0x00000007,
  764. 0x2460, 0xffffffff, 0x00060005,
  765. 0x2461, 0xffffffff, 0x00090008,
  766. 0x2462, 0xffffffff, 0x00030002,
  767. 0x2463, 0xffffffff, 0x00050004,
  768. 0x2464, 0xffffffff, 0x00000008,
  769. 0x2465, 0xffffffff, 0x00070006,
  770. 0x2466, 0xffffffff, 0x000a0009,
  771. 0x2467, 0xffffffff, 0x00040003,
  772. 0x2468, 0xffffffff, 0x00060005,
  773. 0x2469, 0xffffffff, 0x00000009,
  774. 0x246a, 0xffffffff, 0x00080007,
  775. 0x246b, 0xffffffff, 0x000b000a,
  776. 0x246c, 0xffffffff, 0x00050004,
  777. 0x246d, 0xffffffff, 0x00070006,
  778. 0x246e, 0xffffffff, 0x0008000b,
  779. 0x246f, 0xffffffff, 0x000a0009,
  780. 0x2470, 0xffffffff, 0x000d000c,
  781. 0x2471, 0xffffffff, 0x00060005,
  782. 0x2472, 0xffffffff, 0x00080007,
  783. 0x2473, 0xffffffff, 0x0000000b,
  784. 0x2474, 0xffffffff, 0x000a0009,
  785. 0x2475, 0xffffffff, 0x000d000c,
  786. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
  787. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  788. mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
  789. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
  790. 0x000c, 0xffffffff, 0x0000001c,
  791. 0x000d, 0x000f0000, 0x000f0000,
  792. 0x0583, 0xffffffff, 0x00000100,
  793. mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
  794. mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
  795. mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
  796. mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
  797. mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
  798. mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
  799. 0x157a, 0x00000001, 0x00000001,
  800. mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
  801. mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
  802. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  803. 0x3430, 0xfffffff0, 0x00000100,
  804. 0x3630, 0xfffffff0, 0x00000100,
  805. };
  806. static const u32 hainan_mgcg_cgcg_init[] =
  807. {
  808. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
  809. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  810. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  811. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  812. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  813. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  814. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  815. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  816. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  817. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  818. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  819. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  820. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  821. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  822. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  823. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  824. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  825. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  826. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  827. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  828. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  829. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  830. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  831. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  832. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  833. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  834. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  835. 0x2458, 0xffffffff, 0x00010000,
  836. 0x2459, 0xffffffff, 0x00030002,
  837. 0x245a, 0xffffffff, 0x00040007,
  838. 0x245b, 0xffffffff, 0x00060005,
  839. 0x245c, 0xffffffff, 0x00090008,
  840. 0x245d, 0xffffffff, 0x00020001,
  841. 0x245e, 0xffffffff, 0x00040003,
  842. 0x245f, 0xffffffff, 0x00000007,
  843. 0x2460, 0xffffffff, 0x00060005,
  844. 0x2461, 0xffffffff, 0x00090008,
  845. 0x2462, 0xffffffff, 0x00030002,
  846. 0x2463, 0xffffffff, 0x00050004,
  847. 0x2464, 0xffffffff, 0x00000008,
  848. 0x2465, 0xffffffff, 0x00070006,
  849. 0x2466, 0xffffffff, 0x000a0009,
  850. 0x2467, 0xffffffff, 0x00040003,
  851. 0x2468, 0xffffffff, 0x00060005,
  852. 0x2469, 0xffffffff, 0x00000009,
  853. 0x246a, 0xffffffff, 0x00080007,
  854. 0x246b, 0xffffffff, 0x000b000a,
  855. 0x246c, 0xffffffff, 0x00050004,
  856. 0x246d, 0xffffffff, 0x00070006,
  857. 0x246e, 0xffffffff, 0x0008000b,
  858. 0x246f, 0xffffffff, 0x000a0009,
  859. 0x2470, 0xffffffff, 0x000d000c,
  860. 0x2471, 0xffffffff, 0x00060005,
  861. 0x2472, 0xffffffff, 0x00080007,
  862. 0x2473, 0xffffffff, 0x0000000b,
  863. 0x2474, 0xffffffff, 0x000a0009,
  864. 0x2475, 0xffffffff, 0x000d000c,
  865. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
  866. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  867. mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
  868. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
  869. 0x000c, 0xffffffff, 0x0000001c,
  870. 0x000d, 0x000f0000, 0x000f0000,
  871. 0x0583, 0xffffffff, 0x00000100,
  872. 0x0409, 0xffffffff, 0x00000100,
  873. mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
  874. mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
  875. mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
  876. mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
  877. mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
  878. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  879. 0x3430, 0xfffffff0, 0x00000100,
  880. 0x3630, 0xfffffff0, 0x00000100,
  881. };
  882. static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  883. {
  884. unsigned long flags;
  885. u32 r;
  886. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  887. WREG32(AMDGPU_PCIE_INDEX, reg);
  888. (void)RREG32(AMDGPU_PCIE_INDEX);
  889. r = RREG32(AMDGPU_PCIE_DATA);
  890. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  891. return r;
  892. }
  893. static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  894. {
  895. unsigned long flags;
  896. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  897. WREG32(AMDGPU_PCIE_INDEX, reg);
  898. (void)RREG32(AMDGPU_PCIE_INDEX);
  899. WREG32(AMDGPU_PCIE_DATA, v);
  900. (void)RREG32(AMDGPU_PCIE_DATA);
  901. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  902. }
  903. static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
  904. {
  905. unsigned long flags;
  906. u32 r;
  907. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  908. WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
  909. (void)RREG32(PCIE_PORT_INDEX);
  910. r = RREG32(PCIE_PORT_DATA);
  911. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  912. return r;
  913. }
  914. static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  915. {
  916. unsigned long flags;
  917. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  918. WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
  919. (void)RREG32(PCIE_PORT_INDEX);
  920. WREG32(PCIE_PORT_DATA, (v));
  921. (void)RREG32(PCIE_PORT_DATA);
  922. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  923. }
  924. static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
  925. {
  926. unsigned long flags;
  927. u32 r;
  928. spin_lock_irqsave(&adev->smc_idx_lock, flags);
  929. WREG32(SMC_IND_INDEX_0, (reg));
  930. r = RREG32(SMC_IND_DATA_0);
  931. spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
  932. return r;
  933. }
  934. static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  935. {
  936. unsigned long flags;
  937. spin_lock_irqsave(&adev->smc_idx_lock, flags);
  938. WREG32(SMC_IND_INDEX_0, (reg));
  939. WREG32(SMC_IND_DATA_0, (v));
  940. spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
  941. }
  942. static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
  943. {GRBM_STATUS},
  944. {GB_ADDR_CONFIG},
  945. {MC_ARB_RAMCFG},
  946. {GB_TILE_MODE0},
  947. {GB_TILE_MODE1},
  948. {GB_TILE_MODE2},
  949. {GB_TILE_MODE3},
  950. {GB_TILE_MODE4},
  951. {GB_TILE_MODE5},
  952. {GB_TILE_MODE6},
  953. {GB_TILE_MODE7},
  954. {GB_TILE_MODE8},
  955. {GB_TILE_MODE9},
  956. {GB_TILE_MODE10},
  957. {GB_TILE_MODE11},
  958. {GB_TILE_MODE12},
  959. {GB_TILE_MODE13},
  960. {GB_TILE_MODE14},
  961. {GB_TILE_MODE15},
  962. {GB_TILE_MODE16},
  963. {GB_TILE_MODE17},
  964. {GB_TILE_MODE18},
  965. {GB_TILE_MODE19},
  966. {GB_TILE_MODE20},
  967. {GB_TILE_MODE21},
  968. {GB_TILE_MODE22},
  969. {GB_TILE_MODE23},
  970. {GB_TILE_MODE24},
  971. {GB_TILE_MODE25},
  972. {GB_TILE_MODE26},
  973. {GB_TILE_MODE27},
  974. {GB_TILE_MODE28},
  975. {GB_TILE_MODE29},
  976. {GB_TILE_MODE30},
  977. {GB_TILE_MODE31},
  978. {CC_RB_BACKEND_DISABLE, true},
  979. {GC_USER_RB_BACKEND_DISABLE, true},
  980. {PA_SC_RASTER_CONFIG, true},
  981. };
  982. static uint32_t si_get_register_value(struct amdgpu_device *adev,
  983. bool indexed, u32 se_num,
  984. u32 sh_num, u32 reg_offset)
  985. {
  986. if (indexed) {
  987. uint32_t val;
  988. unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
  989. unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
  990. switch (reg_offset) {
  991. case mmCC_RB_BACKEND_DISABLE:
  992. return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
  993. case mmGC_USER_RB_BACKEND_DISABLE:
  994. return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
  995. case mmPA_SC_RASTER_CONFIG:
  996. return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
  997. }
  998. mutex_lock(&adev->grbm_idx_mutex);
  999. if (se_num != 0xffffffff || sh_num != 0xffffffff)
  1000. amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
  1001. val = RREG32(reg_offset);
  1002. if (se_num != 0xffffffff || sh_num != 0xffffffff)
  1003. amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  1004. mutex_unlock(&adev->grbm_idx_mutex);
  1005. return val;
  1006. } else {
  1007. unsigned idx;
  1008. switch (reg_offset) {
  1009. case mmGB_ADDR_CONFIG:
  1010. return adev->gfx.config.gb_addr_config;
  1011. case mmMC_ARB_RAMCFG:
  1012. return adev->gfx.config.mc_arb_ramcfg;
  1013. case mmGB_TILE_MODE0:
  1014. case mmGB_TILE_MODE1:
  1015. case mmGB_TILE_MODE2:
  1016. case mmGB_TILE_MODE3:
  1017. case mmGB_TILE_MODE4:
  1018. case mmGB_TILE_MODE5:
  1019. case mmGB_TILE_MODE6:
  1020. case mmGB_TILE_MODE7:
  1021. case mmGB_TILE_MODE8:
  1022. case mmGB_TILE_MODE9:
  1023. case mmGB_TILE_MODE10:
  1024. case mmGB_TILE_MODE11:
  1025. case mmGB_TILE_MODE12:
  1026. case mmGB_TILE_MODE13:
  1027. case mmGB_TILE_MODE14:
  1028. case mmGB_TILE_MODE15:
  1029. case mmGB_TILE_MODE16:
  1030. case mmGB_TILE_MODE17:
  1031. case mmGB_TILE_MODE18:
  1032. case mmGB_TILE_MODE19:
  1033. case mmGB_TILE_MODE20:
  1034. case mmGB_TILE_MODE21:
  1035. case mmGB_TILE_MODE22:
  1036. case mmGB_TILE_MODE23:
  1037. case mmGB_TILE_MODE24:
  1038. case mmGB_TILE_MODE25:
  1039. case mmGB_TILE_MODE26:
  1040. case mmGB_TILE_MODE27:
  1041. case mmGB_TILE_MODE28:
  1042. case mmGB_TILE_MODE29:
  1043. case mmGB_TILE_MODE30:
  1044. case mmGB_TILE_MODE31:
  1045. idx = (reg_offset - mmGB_TILE_MODE0);
  1046. return adev->gfx.config.tile_mode_array[idx];
  1047. default:
  1048. return RREG32(reg_offset);
  1049. }
  1050. }
  1051. }
  1052. static int si_read_register(struct amdgpu_device *adev, u32 se_num,
  1053. u32 sh_num, u32 reg_offset, u32 *value)
  1054. {
  1055. uint32_t i;
  1056. *value = 0;
  1057. for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
  1058. bool indexed = si_allowed_read_registers[i].grbm_indexed;
  1059. if (reg_offset != si_allowed_read_registers[i].reg_offset)
  1060. continue;
  1061. *value = si_get_register_value(adev, indexed, se_num, sh_num,
  1062. reg_offset);
  1063. return 0;
  1064. }
  1065. return -EINVAL;
  1066. }
  1067. static bool si_read_disabled_bios(struct amdgpu_device *adev)
  1068. {
  1069. u32 bus_cntl;
  1070. u32 d1vga_control = 0;
  1071. u32 d2vga_control = 0;
  1072. u32 vga_render_control = 0;
  1073. u32 rom_cntl;
  1074. bool r;
  1075. bus_cntl = RREG32(R600_BUS_CNTL);
  1076. if (adev->mode_info.num_crtc) {
  1077. d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  1078. d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  1079. vga_render_control = RREG32(VGA_RENDER_CONTROL);
  1080. }
  1081. rom_cntl = RREG32(R600_ROM_CNTL);
  1082. /* enable the rom */
  1083. WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
  1084. if (adev->mode_info.num_crtc) {
  1085. /* Disable VGA mode */
  1086. WREG32(AVIVO_D1VGA_CONTROL,
  1087. (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  1088. AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  1089. WREG32(AVIVO_D2VGA_CONTROL,
  1090. (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  1091. AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  1092. WREG32(VGA_RENDER_CONTROL,
  1093. (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
  1094. }
  1095. WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
  1096. r = amdgpu_read_bios(adev);
  1097. /* restore regs */
  1098. WREG32(R600_BUS_CNTL, bus_cntl);
  1099. if (adev->mode_info.num_crtc) {
  1100. WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  1101. WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  1102. WREG32(VGA_RENDER_CONTROL, vga_render_control);
  1103. }
  1104. WREG32(R600_ROM_CNTL, rom_cntl);
  1105. return r;
  1106. }
  1107. #define mmROM_INDEX 0x2A
  1108. #define mmROM_DATA 0x2B
  1109. static bool si_read_bios_from_rom(struct amdgpu_device *adev,
  1110. u8 *bios, u32 length_bytes)
  1111. {
  1112. u32 *dw_ptr;
  1113. u32 i, length_dw;
  1114. if (bios == NULL)
  1115. return false;
  1116. if (length_bytes == 0)
  1117. return false;
  1118. /* APU vbios image is part of sbios image */
  1119. if (adev->flags & AMD_IS_APU)
  1120. return false;
  1121. dw_ptr = (u32 *)bios;
  1122. length_dw = ALIGN(length_bytes, 4) / 4;
  1123. /* set rom index to 0 */
  1124. WREG32(mmROM_INDEX, 0);
  1125. for (i = 0; i < length_dw; i++)
  1126. dw_ptr[i] = RREG32(mmROM_DATA);
  1127. return true;
  1128. }
  1129. //xxx: not implemented
  1130. static int si_asic_reset(struct amdgpu_device *adev)
  1131. {
  1132. return 0;
  1133. }
  1134. static u32 si_get_config_memsize(struct amdgpu_device *adev)
  1135. {
  1136. return RREG32(mmCONFIG_MEMSIZE);
  1137. }
  1138. static void si_vga_set_state(struct amdgpu_device *adev, bool state)
  1139. {
  1140. uint32_t temp;
  1141. temp = RREG32(CONFIG_CNTL);
  1142. if (state == false) {
  1143. temp &= ~(1<<0);
  1144. temp |= (1<<1);
  1145. } else {
  1146. temp &= ~(1<<1);
  1147. }
  1148. WREG32(CONFIG_CNTL, temp);
  1149. }
  1150. static u32 si_get_xclk(struct amdgpu_device *adev)
  1151. {
  1152. u32 reference_clock = adev->clock.spll.reference_freq;
  1153. u32 tmp;
  1154. tmp = RREG32(CG_CLKPIN_CNTL_2);
  1155. if (tmp & MUX_TCLK_TO_XCLK)
  1156. return TCLK;
  1157. tmp = RREG32(CG_CLKPIN_CNTL);
  1158. if (tmp & XTALIN_DIVIDE)
  1159. return reference_clock / 4;
  1160. return reference_clock;
  1161. }
  1162. //xxx:not implemented
  1163. static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
  1164. {
  1165. return 0;
  1166. }
  1167. static void si_detect_hw_virtualization(struct amdgpu_device *adev)
  1168. {
  1169. if (is_virtual_machine()) /* passthrough mode */
  1170. adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
  1171. }
  1172. static const struct amdgpu_asic_funcs si_asic_funcs =
  1173. {
  1174. .read_disabled_bios = &si_read_disabled_bios,
  1175. .read_bios_from_rom = &si_read_bios_from_rom,
  1176. .read_register = &si_read_register,
  1177. .reset = &si_asic_reset,
  1178. .set_vga_state = &si_vga_set_state,
  1179. .get_xclk = &si_get_xclk,
  1180. .set_uvd_clocks = &si_set_uvd_clocks,
  1181. .set_vce_clocks = NULL,
  1182. .get_config_memsize = &si_get_config_memsize,
  1183. };
  1184. static uint32_t si_get_rev_id(struct amdgpu_device *adev)
  1185. {
  1186. return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
  1187. >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
  1188. }
  1189. static int si_common_early_init(void *handle)
  1190. {
  1191. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1192. adev->smc_rreg = &si_smc_rreg;
  1193. adev->smc_wreg = &si_smc_wreg;
  1194. adev->pcie_rreg = &si_pcie_rreg;
  1195. adev->pcie_wreg = &si_pcie_wreg;
  1196. adev->pciep_rreg = &si_pciep_rreg;
  1197. adev->pciep_wreg = &si_pciep_wreg;
  1198. adev->uvd_ctx_rreg = NULL;
  1199. adev->uvd_ctx_wreg = NULL;
  1200. adev->didt_rreg = NULL;
  1201. adev->didt_wreg = NULL;
  1202. adev->asic_funcs = &si_asic_funcs;
  1203. adev->rev_id = si_get_rev_id(adev);
  1204. adev->external_rev_id = 0xFF;
  1205. switch (adev->asic_type) {
  1206. case CHIP_TAHITI:
  1207. adev->cg_flags =
  1208. AMD_CG_SUPPORT_GFX_MGCG |
  1209. AMD_CG_SUPPORT_GFX_MGLS |
  1210. /*AMD_CG_SUPPORT_GFX_CGCG |*/
  1211. AMD_CG_SUPPORT_GFX_CGLS |
  1212. AMD_CG_SUPPORT_GFX_CGTS |
  1213. AMD_CG_SUPPORT_GFX_CP_LS |
  1214. AMD_CG_SUPPORT_MC_MGCG |
  1215. AMD_CG_SUPPORT_SDMA_MGCG |
  1216. AMD_CG_SUPPORT_BIF_LS |
  1217. AMD_CG_SUPPORT_VCE_MGCG |
  1218. AMD_CG_SUPPORT_UVD_MGCG |
  1219. AMD_CG_SUPPORT_HDP_LS |
  1220. AMD_CG_SUPPORT_HDP_MGCG;
  1221. adev->pg_flags = 0;
  1222. adev->external_rev_id = (adev->rev_id == 0) ? 1 :
  1223. (adev->rev_id == 1) ? 5 : 6;
  1224. break;
  1225. case CHIP_PITCAIRN:
  1226. adev->cg_flags =
  1227. AMD_CG_SUPPORT_GFX_MGCG |
  1228. AMD_CG_SUPPORT_GFX_MGLS |
  1229. /*AMD_CG_SUPPORT_GFX_CGCG |*/
  1230. AMD_CG_SUPPORT_GFX_CGLS |
  1231. AMD_CG_SUPPORT_GFX_CGTS |
  1232. AMD_CG_SUPPORT_GFX_CP_LS |
  1233. AMD_CG_SUPPORT_GFX_RLC_LS |
  1234. AMD_CG_SUPPORT_MC_LS |
  1235. AMD_CG_SUPPORT_MC_MGCG |
  1236. AMD_CG_SUPPORT_SDMA_MGCG |
  1237. AMD_CG_SUPPORT_BIF_LS |
  1238. AMD_CG_SUPPORT_VCE_MGCG |
  1239. AMD_CG_SUPPORT_UVD_MGCG |
  1240. AMD_CG_SUPPORT_HDP_LS |
  1241. AMD_CG_SUPPORT_HDP_MGCG;
  1242. adev->pg_flags = 0;
  1243. adev->external_rev_id = adev->rev_id + 20;
  1244. break;
  1245. case CHIP_VERDE:
  1246. adev->cg_flags =
  1247. AMD_CG_SUPPORT_GFX_MGCG |
  1248. AMD_CG_SUPPORT_GFX_MGLS |
  1249. AMD_CG_SUPPORT_GFX_CGLS |
  1250. AMD_CG_SUPPORT_GFX_CGTS |
  1251. AMD_CG_SUPPORT_GFX_CGTS_LS |
  1252. AMD_CG_SUPPORT_GFX_CP_LS |
  1253. AMD_CG_SUPPORT_MC_LS |
  1254. AMD_CG_SUPPORT_MC_MGCG |
  1255. AMD_CG_SUPPORT_SDMA_MGCG |
  1256. AMD_CG_SUPPORT_SDMA_LS |
  1257. AMD_CG_SUPPORT_BIF_LS |
  1258. AMD_CG_SUPPORT_VCE_MGCG |
  1259. AMD_CG_SUPPORT_UVD_MGCG |
  1260. AMD_CG_SUPPORT_HDP_LS |
  1261. AMD_CG_SUPPORT_HDP_MGCG;
  1262. adev->pg_flags = 0;
  1263. //???
  1264. adev->external_rev_id = adev->rev_id + 40;
  1265. break;
  1266. case CHIP_OLAND:
  1267. adev->cg_flags =
  1268. AMD_CG_SUPPORT_GFX_MGCG |
  1269. AMD_CG_SUPPORT_GFX_MGLS |
  1270. /*AMD_CG_SUPPORT_GFX_CGCG |*/
  1271. AMD_CG_SUPPORT_GFX_CGLS |
  1272. AMD_CG_SUPPORT_GFX_CGTS |
  1273. AMD_CG_SUPPORT_GFX_CP_LS |
  1274. AMD_CG_SUPPORT_GFX_RLC_LS |
  1275. AMD_CG_SUPPORT_MC_LS |
  1276. AMD_CG_SUPPORT_MC_MGCG |
  1277. AMD_CG_SUPPORT_SDMA_MGCG |
  1278. AMD_CG_SUPPORT_BIF_LS |
  1279. AMD_CG_SUPPORT_UVD_MGCG |
  1280. AMD_CG_SUPPORT_HDP_LS |
  1281. AMD_CG_SUPPORT_HDP_MGCG;
  1282. adev->pg_flags = 0;
  1283. adev->external_rev_id = 60;
  1284. break;
  1285. case CHIP_HAINAN:
  1286. adev->cg_flags =
  1287. AMD_CG_SUPPORT_GFX_MGCG |
  1288. AMD_CG_SUPPORT_GFX_MGLS |
  1289. /*AMD_CG_SUPPORT_GFX_CGCG |*/
  1290. AMD_CG_SUPPORT_GFX_CGLS |
  1291. AMD_CG_SUPPORT_GFX_CGTS |
  1292. AMD_CG_SUPPORT_GFX_CP_LS |
  1293. AMD_CG_SUPPORT_GFX_RLC_LS |
  1294. AMD_CG_SUPPORT_MC_LS |
  1295. AMD_CG_SUPPORT_MC_MGCG |
  1296. AMD_CG_SUPPORT_SDMA_MGCG |
  1297. AMD_CG_SUPPORT_BIF_LS |
  1298. AMD_CG_SUPPORT_HDP_LS |
  1299. AMD_CG_SUPPORT_HDP_MGCG;
  1300. adev->pg_flags = 0;
  1301. adev->external_rev_id = 70;
  1302. break;
  1303. default:
  1304. return -EINVAL;
  1305. }
  1306. return 0;
  1307. }
  1308. static int si_common_sw_init(void *handle)
  1309. {
  1310. return 0;
  1311. }
  1312. static int si_common_sw_fini(void *handle)
  1313. {
  1314. return 0;
  1315. }
  1316. static void si_init_golden_registers(struct amdgpu_device *adev)
  1317. {
  1318. switch (adev->asic_type) {
  1319. case CHIP_TAHITI:
  1320. amdgpu_program_register_sequence(adev,
  1321. tahiti_golden_registers,
  1322. (const u32)ARRAY_SIZE(tahiti_golden_registers));
  1323. amdgpu_program_register_sequence(adev,
  1324. tahiti_golden_rlc_registers,
  1325. (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
  1326. amdgpu_program_register_sequence(adev,
  1327. tahiti_mgcg_cgcg_init,
  1328. (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
  1329. amdgpu_program_register_sequence(adev,
  1330. tahiti_golden_registers2,
  1331. (const u32)ARRAY_SIZE(tahiti_golden_registers2));
  1332. break;
  1333. case CHIP_PITCAIRN:
  1334. amdgpu_program_register_sequence(adev,
  1335. pitcairn_golden_registers,
  1336. (const u32)ARRAY_SIZE(pitcairn_golden_registers));
  1337. amdgpu_program_register_sequence(adev,
  1338. pitcairn_golden_rlc_registers,
  1339. (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
  1340. amdgpu_program_register_sequence(adev,
  1341. pitcairn_mgcg_cgcg_init,
  1342. (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
  1343. break;
  1344. case CHIP_VERDE:
  1345. amdgpu_program_register_sequence(adev,
  1346. verde_golden_registers,
  1347. (const u32)ARRAY_SIZE(verde_golden_registers));
  1348. amdgpu_program_register_sequence(adev,
  1349. verde_golden_rlc_registers,
  1350. (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
  1351. amdgpu_program_register_sequence(adev,
  1352. verde_mgcg_cgcg_init,
  1353. (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
  1354. amdgpu_program_register_sequence(adev,
  1355. verde_pg_init,
  1356. (const u32)ARRAY_SIZE(verde_pg_init));
  1357. break;
  1358. case CHIP_OLAND:
  1359. amdgpu_program_register_sequence(adev,
  1360. oland_golden_registers,
  1361. (const u32)ARRAY_SIZE(oland_golden_registers));
  1362. amdgpu_program_register_sequence(adev,
  1363. oland_golden_rlc_registers,
  1364. (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
  1365. amdgpu_program_register_sequence(adev,
  1366. oland_mgcg_cgcg_init,
  1367. (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
  1368. break;
  1369. case CHIP_HAINAN:
  1370. amdgpu_program_register_sequence(adev,
  1371. hainan_golden_registers,
  1372. (const u32)ARRAY_SIZE(hainan_golden_registers));
  1373. amdgpu_program_register_sequence(adev,
  1374. hainan_golden_registers2,
  1375. (const u32)ARRAY_SIZE(hainan_golden_registers2));
  1376. amdgpu_program_register_sequence(adev,
  1377. hainan_mgcg_cgcg_init,
  1378. (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
  1379. break;
  1380. default:
  1381. BUG();
  1382. }
  1383. }
  1384. static void si_pcie_gen3_enable(struct amdgpu_device *adev)
  1385. {
  1386. struct pci_dev *root = adev->pdev->bus->self;
  1387. int bridge_pos, gpu_pos;
  1388. u32 speed_cntl, mask, current_data_rate;
  1389. int ret, i;
  1390. u16 tmp16;
  1391. if (pci_is_root_bus(adev->pdev->bus))
  1392. return;
  1393. if (amdgpu_pcie_gen2 == 0)
  1394. return;
  1395. if (adev->flags & AMD_IS_APU)
  1396. return;
  1397. ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
  1398. if (ret != 0)
  1399. return;
  1400. if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
  1401. return;
  1402. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1403. current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
  1404. LC_CURRENT_DATA_RATE_SHIFT;
  1405. if (mask & DRM_PCIE_SPEED_80) {
  1406. if (current_data_rate == 2) {
  1407. DRM_INFO("PCIE gen 3 link speeds already enabled\n");
  1408. return;
  1409. }
  1410. DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
  1411. } else if (mask & DRM_PCIE_SPEED_50) {
  1412. if (current_data_rate == 1) {
  1413. DRM_INFO("PCIE gen 2 link speeds already enabled\n");
  1414. return;
  1415. }
  1416. DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
  1417. }
  1418. bridge_pos = pci_pcie_cap(root);
  1419. if (!bridge_pos)
  1420. return;
  1421. gpu_pos = pci_pcie_cap(adev->pdev);
  1422. if (!gpu_pos)
  1423. return;
  1424. if (mask & DRM_PCIE_SPEED_80) {
  1425. if (current_data_rate != 2) {
  1426. u16 bridge_cfg, gpu_cfg;
  1427. u16 bridge_cfg2, gpu_cfg2;
  1428. u32 max_lw, current_lw, tmp;
  1429. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
  1430. pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
  1431. tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
  1432. pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
  1433. tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
  1434. pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
  1435. tmp = RREG32_PCIE(PCIE_LC_STATUS1);
  1436. max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
  1437. current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
  1438. if (current_lw < max_lw) {
  1439. tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
  1440. if (tmp & LC_RENEGOTIATION_SUPPORT) {
  1441. tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
  1442. tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
  1443. tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
  1444. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
  1445. }
  1446. }
  1447. for (i = 0; i < 10; i++) {
  1448. pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
  1449. if (tmp16 & PCI_EXP_DEVSTA_TRPND)
  1450. break;
  1451. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
  1452. pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
  1453. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
  1454. pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
  1455. tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
  1456. tmp |= LC_SET_QUIESCE;
  1457. WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
  1458. tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
  1459. tmp |= LC_REDO_EQ;
  1460. WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
  1461. mdelay(100);
  1462. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
  1463. tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
  1464. tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
  1465. pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
  1466. pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
  1467. tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
  1468. tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
  1469. pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
  1470. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
  1471. tmp16 &= ~((1 << 4) | (7 << 9));
  1472. tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
  1473. pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
  1474. pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
  1475. tmp16 &= ~((1 << 4) | (7 << 9));
  1476. tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
  1477. pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
  1478. tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
  1479. tmp &= ~LC_SET_QUIESCE;
  1480. WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
  1481. }
  1482. }
  1483. }
  1484. speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
  1485. speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
  1486. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  1487. pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
  1488. tmp16 &= ~0xf;
  1489. if (mask & DRM_PCIE_SPEED_80)
  1490. tmp16 |= 3;
  1491. else if (mask & DRM_PCIE_SPEED_50)
  1492. tmp16 |= 2;
  1493. else
  1494. tmp16 |= 1;
  1495. pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
  1496. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1497. speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
  1498. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  1499. for (i = 0; i < adev->usec_timeout; i++) {
  1500. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1501. if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
  1502. break;
  1503. udelay(1);
  1504. }
  1505. }
  1506. static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
  1507. {
  1508. unsigned long flags;
  1509. u32 r;
  1510. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  1511. WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
  1512. r = RREG32(EVERGREEN_PIF_PHY0_DATA);
  1513. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  1514. return r;
  1515. }
  1516. static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  1517. {
  1518. unsigned long flags;
  1519. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  1520. WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
  1521. WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
  1522. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  1523. }
  1524. static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
  1525. {
  1526. unsigned long flags;
  1527. u32 r;
  1528. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  1529. WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
  1530. r = RREG32(EVERGREEN_PIF_PHY1_DATA);
  1531. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  1532. return r;
  1533. }
  1534. static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  1535. {
  1536. unsigned long flags;
  1537. spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  1538. WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
  1539. WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
  1540. spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  1541. }
  1542. static void si_program_aspm(struct amdgpu_device *adev)
  1543. {
  1544. u32 data, orig;
  1545. bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
  1546. bool disable_clkreq = false;
  1547. if (amdgpu_aspm == 0)
  1548. return;
  1549. if (adev->flags & AMD_IS_APU)
  1550. return;
  1551. orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
  1552. data &= ~LC_XMIT_N_FTS_MASK;
  1553. data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
  1554. if (orig != data)
  1555. WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
  1556. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
  1557. data |= LC_GO_TO_RECOVERY;
  1558. if (orig != data)
  1559. WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
  1560. orig = data = RREG32_PCIE(PCIE_P_CNTL);
  1561. data |= P_IGNORE_EDB_ERR;
  1562. if (orig != data)
  1563. WREG32_PCIE(PCIE_P_CNTL, data);
  1564. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
  1565. data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
  1566. data |= LC_PMI_TO_L1_DIS;
  1567. if (!disable_l0s)
  1568. data |= LC_L0S_INACTIVITY(7);
  1569. if (!disable_l1) {
  1570. data |= LC_L1_INACTIVITY(7);
  1571. data &= ~LC_PMI_TO_L1_DIS;
  1572. if (orig != data)
  1573. WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
  1574. if (!disable_plloff_in_l1) {
  1575. bool clk_req_support;
  1576. orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
  1577. data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
  1578. data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
  1579. if (orig != data)
  1580. si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
  1581. orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
  1582. data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
  1583. data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
  1584. if (orig != data)
  1585. si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
  1586. orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
  1587. data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
  1588. data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
  1589. if (orig != data)
  1590. si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
  1591. orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
  1592. data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
  1593. data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
  1594. if (orig != data)
  1595. si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
  1596. if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
  1597. orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
  1598. data &= ~PLL_RAMP_UP_TIME_0_MASK;
  1599. if (orig != data)
  1600. si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
  1601. orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
  1602. data &= ~PLL_RAMP_UP_TIME_1_MASK;
  1603. if (orig != data)
  1604. si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
  1605. orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
  1606. data &= ~PLL_RAMP_UP_TIME_2_MASK;
  1607. if (orig != data)
  1608. si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
  1609. orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
  1610. data &= ~PLL_RAMP_UP_TIME_3_MASK;
  1611. if (orig != data)
  1612. si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
  1613. orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
  1614. data &= ~PLL_RAMP_UP_TIME_0_MASK;
  1615. if (orig != data)
  1616. si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
  1617. orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
  1618. data &= ~PLL_RAMP_UP_TIME_1_MASK;
  1619. if (orig != data)
  1620. si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
  1621. orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
  1622. data &= ~PLL_RAMP_UP_TIME_2_MASK;
  1623. if (orig != data)
  1624. si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
  1625. orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
  1626. data &= ~PLL_RAMP_UP_TIME_3_MASK;
  1627. if (orig != data)
  1628. si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
  1629. }
  1630. orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
  1631. data &= ~LC_DYN_LANES_PWR_STATE_MASK;
  1632. data |= LC_DYN_LANES_PWR_STATE(3);
  1633. if (orig != data)
  1634. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
  1635. orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
  1636. data &= ~LS2_EXIT_TIME_MASK;
  1637. if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
  1638. data |= LS2_EXIT_TIME(5);
  1639. if (orig != data)
  1640. si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
  1641. orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
  1642. data &= ~LS2_EXIT_TIME_MASK;
  1643. if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
  1644. data |= LS2_EXIT_TIME(5);
  1645. if (orig != data)
  1646. si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
  1647. if (!disable_clkreq &&
  1648. !pci_is_root_bus(adev->pdev->bus)) {
  1649. struct pci_dev *root = adev->pdev->bus->self;
  1650. u32 lnkcap;
  1651. clk_req_support = false;
  1652. pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
  1653. if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
  1654. clk_req_support = true;
  1655. } else {
  1656. clk_req_support = false;
  1657. }
  1658. if (clk_req_support) {
  1659. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
  1660. data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
  1661. if (orig != data)
  1662. WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
  1663. orig = data = RREG32(THM_CLK_CNTL);
  1664. data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
  1665. data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
  1666. if (orig != data)
  1667. WREG32(THM_CLK_CNTL, data);
  1668. orig = data = RREG32(MISC_CLK_CNTL);
  1669. data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
  1670. data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
  1671. if (orig != data)
  1672. WREG32(MISC_CLK_CNTL, data);
  1673. orig = data = RREG32(CG_CLKPIN_CNTL);
  1674. data &= ~BCLK_AS_XCLK;
  1675. if (orig != data)
  1676. WREG32(CG_CLKPIN_CNTL, data);
  1677. orig = data = RREG32(CG_CLKPIN_CNTL_2);
  1678. data &= ~FORCE_BIF_REFCLK_EN;
  1679. if (orig != data)
  1680. WREG32(CG_CLKPIN_CNTL_2, data);
  1681. orig = data = RREG32(MPLL_BYPASSCLK_SEL);
  1682. data &= ~MPLL_CLKOUT_SEL_MASK;
  1683. data |= MPLL_CLKOUT_SEL(4);
  1684. if (orig != data)
  1685. WREG32(MPLL_BYPASSCLK_SEL, data);
  1686. orig = data = RREG32(SPLL_CNTL_MODE);
  1687. data &= ~SPLL_REFCLK_SEL_MASK;
  1688. if (orig != data)
  1689. WREG32(SPLL_CNTL_MODE, data);
  1690. }
  1691. }
  1692. } else {
  1693. if (orig != data)
  1694. WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
  1695. }
  1696. orig = data = RREG32_PCIE(PCIE_CNTL2);
  1697. data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
  1698. if (orig != data)
  1699. WREG32_PCIE(PCIE_CNTL2, data);
  1700. if (!disable_l0s) {
  1701. data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
  1702. if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
  1703. data = RREG32_PCIE(PCIE_LC_STATUS1);
  1704. if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
  1705. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
  1706. data &= ~LC_L0S_INACTIVITY_MASK;
  1707. if (orig != data)
  1708. WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
  1709. }
  1710. }
  1711. }
  1712. }
  1713. static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
  1714. {
  1715. int readrq;
  1716. u16 v;
  1717. readrq = pcie_get_readrq(adev->pdev);
  1718. v = ffs(readrq) - 8;
  1719. if ((v == 0) || (v == 6) || (v == 7))
  1720. pcie_set_readrq(adev->pdev, 512);
  1721. }
  1722. static int si_common_hw_init(void *handle)
  1723. {
  1724. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1725. si_fix_pci_max_read_req_size(adev);
  1726. si_init_golden_registers(adev);
  1727. si_pcie_gen3_enable(adev);
  1728. si_program_aspm(adev);
  1729. return 0;
  1730. }
  1731. static int si_common_hw_fini(void *handle)
  1732. {
  1733. return 0;
  1734. }
  1735. static int si_common_suspend(void *handle)
  1736. {
  1737. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1738. return si_common_hw_fini(adev);
  1739. }
  1740. static int si_common_resume(void *handle)
  1741. {
  1742. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1743. return si_common_hw_init(adev);
  1744. }
  1745. static bool si_common_is_idle(void *handle)
  1746. {
  1747. return true;
  1748. }
  1749. static int si_common_wait_for_idle(void *handle)
  1750. {
  1751. return 0;
  1752. }
  1753. static int si_common_soft_reset(void *handle)
  1754. {
  1755. return 0;
  1756. }
  1757. static int si_common_set_clockgating_state(void *handle,
  1758. enum amd_clockgating_state state)
  1759. {
  1760. return 0;
  1761. }
  1762. static int si_common_set_powergating_state(void *handle,
  1763. enum amd_powergating_state state)
  1764. {
  1765. return 0;
  1766. }
  1767. static const struct amd_ip_funcs si_common_ip_funcs = {
  1768. .name = "si_common",
  1769. .early_init = si_common_early_init,
  1770. .late_init = NULL,
  1771. .sw_init = si_common_sw_init,
  1772. .sw_fini = si_common_sw_fini,
  1773. .hw_init = si_common_hw_init,
  1774. .hw_fini = si_common_hw_fini,
  1775. .suspend = si_common_suspend,
  1776. .resume = si_common_resume,
  1777. .is_idle = si_common_is_idle,
  1778. .wait_for_idle = si_common_wait_for_idle,
  1779. .soft_reset = si_common_soft_reset,
  1780. .set_clockgating_state = si_common_set_clockgating_state,
  1781. .set_powergating_state = si_common_set_powergating_state,
  1782. };
  1783. static const struct amdgpu_ip_block_version si_common_ip_block =
  1784. {
  1785. .type = AMD_IP_BLOCK_TYPE_COMMON,
  1786. .major = 1,
  1787. .minor = 0,
  1788. .rev = 0,
  1789. .funcs = &si_common_ip_funcs,
  1790. };
  1791. int si_set_ip_blocks(struct amdgpu_device *adev)
  1792. {
  1793. si_detect_hw_virtualization(adev);
  1794. switch (adev->asic_type) {
  1795. case CHIP_VERDE:
  1796. case CHIP_TAHITI:
  1797. case CHIP_PITCAIRN:
  1798. amdgpu_ip_block_add(adev, &si_common_ip_block);
  1799. amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
  1800. amdgpu_ip_block_add(adev, &si_ih_ip_block);
  1801. amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
  1802. if (adev->enable_virtual_display)
  1803. amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
  1804. else
  1805. amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
  1806. amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
  1807. amdgpu_ip_block_add(adev, &si_dma_ip_block);
  1808. /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
  1809. /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
  1810. break;
  1811. case CHIP_OLAND:
  1812. amdgpu_ip_block_add(adev, &si_common_ip_block);
  1813. amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
  1814. amdgpu_ip_block_add(adev, &si_ih_ip_block);
  1815. amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
  1816. if (adev->enable_virtual_display)
  1817. amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
  1818. else
  1819. amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
  1820. amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
  1821. amdgpu_ip_block_add(adev, &si_dma_ip_block);
  1822. /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
  1823. /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
  1824. break;
  1825. case CHIP_HAINAN:
  1826. amdgpu_ip_block_add(adev, &si_common_ip_block);
  1827. amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
  1828. amdgpu_ip_block_add(adev, &si_ih_ip_block);
  1829. amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
  1830. if (adev->enable_virtual_display)
  1831. amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
  1832. amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
  1833. amdgpu_ip_block_add(adev, &si_dma_ip_block);
  1834. break;
  1835. default:
  1836. BUG();
  1837. }
  1838. return 0;
  1839. }