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/drivers/net/niu.c

https://gitlab.com/TeamCarbonXtreme/android_kernel_samsung_bcm21553-common
C | 10280 lines | 8345 code | 1773 blank | 162 comment | 1373 complexity | d9a6bc9cffd37c042abc656e8c81341e MD5 | raw file
Possible License(s): GPL-2.0
  1. /* niu.c: Neptune ethernet driver.
  2. *
  3. * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
  4. */
  5. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/pci.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/netdevice.h>
  11. #include <linux/ethtool.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/delay.h>
  15. #include <linux/bitops.h>
  16. #include <linux/mii.h>
  17. #include <linux/if_ether.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/ip.h>
  20. #include <linux/in.h>
  21. #include <linux/ipv6.h>
  22. #include <linux/log2.h>
  23. #include <linux/jiffies.h>
  24. #include <linux/crc32.h>
  25. #include <linux/list.h>
  26. #include <linux/slab.h>
  27. #include <linux/io.h>
  28. #ifdef CONFIG_SPARC64
  29. #include <linux/of_device.h>
  30. #endif
  31. #include "niu.h"
  32. #define DRV_MODULE_NAME "niu"
  33. #define DRV_MODULE_VERSION "1.1"
  34. #define DRV_MODULE_RELDATE "Apr 22, 2010"
  35. static char version[] __devinitdata =
  36. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  37. MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  38. MODULE_DESCRIPTION("NIU ethernet driver");
  39. MODULE_LICENSE("GPL");
  40. MODULE_VERSION(DRV_MODULE_VERSION);
  41. #ifndef readq
  42. static u64 readq(void __iomem *reg)
  43. {
  44. return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  45. }
  46. static void writeq(u64 val, void __iomem *reg)
  47. {
  48. writel(val & 0xffffffff, reg);
  49. writel(val >> 32, reg + 0x4UL);
  50. }
  51. #endif
  52. static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
  53. {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  54. {}
  55. };
  56. MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  57. #define NIU_TX_TIMEOUT (5 * HZ)
  58. #define nr64(reg) readq(np->regs + (reg))
  59. #define nw64(reg, val) writeq((val), np->regs + (reg))
  60. #define nr64_mac(reg) readq(np->mac_regs + (reg))
  61. #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
  62. #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
  63. #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
  64. #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
  65. #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
  66. #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
  67. #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
  68. #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  69. static int niu_debug;
  70. static int debug = -1;
  71. module_param(debug, int, 0);
  72. MODULE_PARM_DESC(debug, "NIU debug level");
  73. #define niu_lock_parent(np, flags) \
  74. spin_lock_irqsave(&np->parent->lock, flags)
  75. #define niu_unlock_parent(np, flags) \
  76. spin_unlock_irqrestore(&np->parent->lock, flags)
  77. static int serdes_init_10g_serdes(struct niu *np);
  78. static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
  79. u64 bits, int limit, int delay)
  80. {
  81. while (--limit >= 0) {
  82. u64 val = nr64_mac(reg);
  83. if (!(val & bits))
  84. break;
  85. udelay(delay);
  86. }
  87. if (limit < 0)
  88. return -ENODEV;
  89. return 0;
  90. }
  91. static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
  92. u64 bits, int limit, int delay,
  93. const char *reg_name)
  94. {
  95. int err;
  96. nw64_mac(reg, bits);
  97. err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
  98. if (err)
  99. netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
  100. (unsigned long long)bits, reg_name,
  101. (unsigned long long)nr64_mac(reg));
  102. return err;
  103. }
  104. #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
  105. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  106. __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
  107. })
  108. static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
  109. u64 bits, int limit, int delay)
  110. {
  111. while (--limit >= 0) {
  112. u64 val = nr64_ipp(reg);
  113. if (!(val & bits))
  114. break;
  115. udelay(delay);
  116. }
  117. if (limit < 0)
  118. return -ENODEV;
  119. return 0;
  120. }
  121. static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
  122. u64 bits, int limit, int delay,
  123. const char *reg_name)
  124. {
  125. int err;
  126. u64 val;
  127. val = nr64_ipp(reg);
  128. val |= bits;
  129. nw64_ipp(reg, val);
  130. err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
  131. if (err)
  132. netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
  133. (unsigned long long)bits, reg_name,
  134. (unsigned long long)nr64_ipp(reg));
  135. return err;
  136. }
  137. #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
  138. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  139. __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
  140. })
  141. static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
  142. u64 bits, int limit, int delay)
  143. {
  144. while (--limit >= 0) {
  145. u64 val = nr64(reg);
  146. if (!(val & bits))
  147. break;
  148. udelay(delay);
  149. }
  150. if (limit < 0)
  151. return -ENODEV;
  152. return 0;
  153. }
  154. #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
  155. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  156. __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
  157. })
  158. static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
  159. u64 bits, int limit, int delay,
  160. const char *reg_name)
  161. {
  162. int err;
  163. nw64(reg, bits);
  164. err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
  165. if (err)
  166. netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
  167. (unsigned long long)bits, reg_name,
  168. (unsigned long long)nr64(reg));
  169. return err;
  170. }
  171. #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
  172. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  173. __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
  174. })
  175. static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
  176. {
  177. u64 val = (u64) lp->timer;
  178. if (on)
  179. val |= LDG_IMGMT_ARM;
  180. nw64(LDG_IMGMT(lp->ldg_num), val);
  181. }
  182. static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
  183. {
  184. unsigned long mask_reg, bits;
  185. u64 val;
  186. if (ldn < 0 || ldn > LDN_MAX)
  187. return -EINVAL;
  188. if (ldn < 64) {
  189. mask_reg = LD_IM0(ldn);
  190. bits = LD_IM0_MASK;
  191. } else {
  192. mask_reg = LD_IM1(ldn - 64);
  193. bits = LD_IM1_MASK;
  194. }
  195. val = nr64(mask_reg);
  196. if (on)
  197. val &= ~bits;
  198. else
  199. val |= bits;
  200. nw64(mask_reg, val);
  201. return 0;
  202. }
  203. static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
  204. {
  205. struct niu_parent *parent = np->parent;
  206. int i;
  207. for (i = 0; i <= LDN_MAX; i++) {
  208. int err;
  209. if (parent->ldg_map[i] != lp->ldg_num)
  210. continue;
  211. err = niu_ldn_irq_enable(np, i, on);
  212. if (err)
  213. return err;
  214. }
  215. return 0;
  216. }
  217. static int niu_enable_interrupts(struct niu *np, int on)
  218. {
  219. int i;
  220. for (i = 0; i < np->num_ldg; i++) {
  221. struct niu_ldg *lp = &np->ldg[i];
  222. int err;
  223. err = niu_enable_ldn_in_ldg(np, lp, on);
  224. if (err)
  225. return err;
  226. }
  227. for (i = 0; i < np->num_ldg; i++)
  228. niu_ldg_rearm(np, &np->ldg[i], on);
  229. return 0;
  230. }
  231. static u32 phy_encode(u32 type, int port)
  232. {
  233. return (type << (port * 2));
  234. }
  235. static u32 phy_decode(u32 val, int port)
  236. {
  237. return (val >> (port * 2)) & PORT_TYPE_MASK;
  238. }
  239. static int mdio_wait(struct niu *np)
  240. {
  241. int limit = 1000;
  242. u64 val;
  243. while (--limit > 0) {
  244. val = nr64(MIF_FRAME_OUTPUT);
  245. if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
  246. return val & MIF_FRAME_OUTPUT_DATA;
  247. udelay(10);
  248. }
  249. return -ENODEV;
  250. }
  251. static int mdio_read(struct niu *np, int port, int dev, int reg)
  252. {
  253. int err;
  254. nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
  255. err = mdio_wait(np);
  256. if (err < 0)
  257. return err;
  258. nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
  259. return mdio_wait(np);
  260. }
  261. static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
  262. {
  263. int err;
  264. nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
  265. err = mdio_wait(np);
  266. if (err < 0)
  267. return err;
  268. nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
  269. err = mdio_wait(np);
  270. if (err < 0)
  271. return err;
  272. return 0;
  273. }
  274. static int mii_read(struct niu *np, int port, int reg)
  275. {
  276. nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
  277. return mdio_wait(np);
  278. }
  279. static int mii_write(struct niu *np, int port, int reg, int data)
  280. {
  281. int err;
  282. nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
  283. err = mdio_wait(np);
  284. if (err < 0)
  285. return err;
  286. return 0;
  287. }
  288. static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
  289. {
  290. int err;
  291. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  292. ESR2_TI_PLL_TX_CFG_L(channel),
  293. val & 0xffff);
  294. if (!err)
  295. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  296. ESR2_TI_PLL_TX_CFG_H(channel),
  297. val >> 16);
  298. return err;
  299. }
  300. static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
  301. {
  302. int err;
  303. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  304. ESR2_TI_PLL_RX_CFG_L(channel),
  305. val & 0xffff);
  306. if (!err)
  307. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  308. ESR2_TI_PLL_RX_CFG_H(channel),
  309. val >> 16);
  310. return err;
  311. }
  312. /* Mode is always 10G fiber. */
  313. static int serdes_init_niu_10g_fiber(struct niu *np)
  314. {
  315. struct niu_link_config *lp = &np->link_config;
  316. u32 tx_cfg, rx_cfg;
  317. unsigned long i;
  318. tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
  319. rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
  320. PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
  321. PLL_RX_CFG_EQ_LP_ADAPTIVE);
  322. if (lp->loopback_mode == LOOPBACK_PHY) {
  323. u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
  324. mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  325. ESR2_TI_PLL_TEST_CFG_L, test_cfg);
  326. tx_cfg |= PLL_TX_CFG_ENTEST;
  327. rx_cfg |= PLL_RX_CFG_ENTEST;
  328. }
  329. /* Initialize all 4 lanes of the SERDES. */
  330. for (i = 0; i < 4; i++) {
  331. int err = esr2_set_tx_cfg(np, i, tx_cfg);
  332. if (err)
  333. return err;
  334. }
  335. for (i = 0; i < 4; i++) {
  336. int err = esr2_set_rx_cfg(np, i, rx_cfg);
  337. if (err)
  338. return err;
  339. }
  340. return 0;
  341. }
  342. static int serdes_init_niu_1g_serdes(struct niu *np)
  343. {
  344. struct niu_link_config *lp = &np->link_config;
  345. u16 pll_cfg, pll_sts;
  346. int max_retry = 100;
  347. u64 uninitialized_var(sig), mask, val;
  348. u32 tx_cfg, rx_cfg;
  349. unsigned long i;
  350. int err;
  351. tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
  352. PLL_TX_CFG_RATE_HALF);
  353. rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
  354. PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
  355. PLL_RX_CFG_RATE_HALF);
  356. if (np->port == 0)
  357. rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
  358. if (lp->loopback_mode == LOOPBACK_PHY) {
  359. u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
  360. mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  361. ESR2_TI_PLL_TEST_CFG_L, test_cfg);
  362. tx_cfg |= PLL_TX_CFG_ENTEST;
  363. rx_cfg |= PLL_RX_CFG_ENTEST;
  364. }
  365. /* Initialize PLL for 1G */
  366. pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
  367. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  368. ESR2_TI_PLL_CFG_L, pll_cfg);
  369. if (err) {
  370. netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
  371. np->port, __func__);
  372. return err;
  373. }
  374. pll_sts = PLL_CFG_ENPLL;
  375. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  376. ESR2_TI_PLL_STS_L, pll_sts);
  377. if (err) {
  378. netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
  379. np->port, __func__);
  380. return err;
  381. }
  382. udelay(200);
  383. /* Initialize all 4 lanes of the SERDES. */
  384. for (i = 0; i < 4; i++) {
  385. err = esr2_set_tx_cfg(np, i, tx_cfg);
  386. if (err)
  387. return err;
  388. }
  389. for (i = 0; i < 4; i++) {
  390. err = esr2_set_rx_cfg(np, i, rx_cfg);
  391. if (err)
  392. return err;
  393. }
  394. switch (np->port) {
  395. case 0:
  396. val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
  397. mask = val;
  398. break;
  399. case 1:
  400. val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
  401. mask = val;
  402. break;
  403. default:
  404. return -EINVAL;
  405. }
  406. while (max_retry--) {
  407. sig = nr64(ESR_INT_SIGNALS);
  408. if ((sig & mask) == val)
  409. break;
  410. mdelay(500);
  411. }
  412. if ((sig & mask) != val) {
  413. netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
  414. np->port, (int)(sig & mask), (int)val);
  415. return -ENODEV;
  416. }
  417. return 0;
  418. }
  419. static int serdes_init_niu_10g_serdes(struct niu *np)
  420. {
  421. struct niu_link_config *lp = &np->link_config;
  422. u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
  423. int max_retry = 100;
  424. u64 uninitialized_var(sig), mask, val;
  425. unsigned long i;
  426. int err;
  427. tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
  428. rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
  429. PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
  430. PLL_RX_CFG_EQ_LP_ADAPTIVE);
  431. if (lp->loopback_mode == LOOPBACK_PHY) {
  432. u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
  433. mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  434. ESR2_TI_PLL_TEST_CFG_L, test_cfg);
  435. tx_cfg |= PLL_TX_CFG_ENTEST;
  436. rx_cfg |= PLL_RX_CFG_ENTEST;
  437. }
  438. /* Initialize PLL for 10G */
  439. pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
  440. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  441. ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
  442. if (err) {
  443. netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
  444. np->port, __func__);
  445. return err;
  446. }
  447. pll_sts = PLL_CFG_ENPLL;
  448. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  449. ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
  450. if (err) {
  451. netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
  452. np->port, __func__);
  453. return err;
  454. }
  455. udelay(200);
  456. /* Initialize all 4 lanes of the SERDES. */
  457. for (i = 0; i < 4; i++) {
  458. err = esr2_set_tx_cfg(np, i, tx_cfg);
  459. if (err)
  460. return err;
  461. }
  462. for (i = 0; i < 4; i++) {
  463. err = esr2_set_rx_cfg(np, i, rx_cfg);
  464. if (err)
  465. return err;
  466. }
  467. /* check if serdes is ready */
  468. switch (np->port) {
  469. case 0:
  470. mask = ESR_INT_SIGNALS_P0_BITS;
  471. val = (ESR_INT_SRDY0_P0 |
  472. ESR_INT_DET0_P0 |
  473. ESR_INT_XSRDY_P0 |
  474. ESR_INT_XDP_P0_CH3 |
  475. ESR_INT_XDP_P0_CH2 |
  476. ESR_INT_XDP_P0_CH1 |
  477. ESR_INT_XDP_P0_CH0);
  478. break;
  479. case 1:
  480. mask = ESR_INT_SIGNALS_P1_BITS;
  481. val = (ESR_INT_SRDY0_P1 |
  482. ESR_INT_DET0_P1 |
  483. ESR_INT_XSRDY_P1 |
  484. ESR_INT_XDP_P1_CH3 |
  485. ESR_INT_XDP_P1_CH2 |
  486. ESR_INT_XDP_P1_CH1 |
  487. ESR_INT_XDP_P1_CH0);
  488. break;
  489. default:
  490. return -EINVAL;
  491. }
  492. while (max_retry--) {
  493. sig = nr64(ESR_INT_SIGNALS);
  494. if ((sig & mask) == val)
  495. break;
  496. mdelay(500);
  497. }
  498. if ((sig & mask) != val) {
  499. pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
  500. np->port, (int)(sig & mask), (int)val);
  501. /* 10G failed, try initializing at 1G */
  502. err = serdes_init_niu_1g_serdes(np);
  503. if (!err) {
  504. np->flags &= ~NIU_FLAGS_10G;
  505. np->mac_xcvr = MAC_XCVR_PCS;
  506. } else {
  507. netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
  508. np->port);
  509. return -ENODEV;
  510. }
  511. }
  512. return 0;
  513. }
  514. static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
  515. {
  516. int err;
  517. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
  518. if (err >= 0) {
  519. *val = (err & 0xffff);
  520. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  521. ESR_RXTX_CTRL_H(chan));
  522. if (err >= 0)
  523. *val |= ((err & 0xffff) << 16);
  524. err = 0;
  525. }
  526. return err;
  527. }
  528. static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
  529. {
  530. int err;
  531. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  532. ESR_GLUE_CTRL0_L(chan));
  533. if (err >= 0) {
  534. *val = (err & 0xffff);
  535. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  536. ESR_GLUE_CTRL0_H(chan));
  537. if (err >= 0) {
  538. *val |= ((err & 0xffff) << 16);
  539. err = 0;
  540. }
  541. }
  542. return err;
  543. }
  544. static int esr_read_reset(struct niu *np, u32 *val)
  545. {
  546. int err;
  547. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  548. ESR_RXTX_RESET_CTRL_L);
  549. if (err >= 0) {
  550. *val = (err & 0xffff);
  551. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  552. ESR_RXTX_RESET_CTRL_H);
  553. if (err >= 0) {
  554. *val |= ((err & 0xffff) << 16);
  555. err = 0;
  556. }
  557. }
  558. return err;
  559. }
  560. static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
  561. {
  562. int err;
  563. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  564. ESR_RXTX_CTRL_L(chan), val & 0xffff);
  565. if (!err)
  566. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  567. ESR_RXTX_CTRL_H(chan), (val >> 16));
  568. return err;
  569. }
  570. static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
  571. {
  572. int err;
  573. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  574. ESR_GLUE_CTRL0_L(chan), val & 0xffff);
  575. if (!err)
  576. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  577. ESR_GLUE_CTRL0_H(chan), (val >> 16));
  578. return err;
  579. }
  580. static int esr_reset(struct niu *np)
  581. {
  582. u32 uninitialized_var(reset);
  583. int err;
  584. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  585. ESR_RXTX_RESET_CTRL_L, 0x0000);
  586. if (err)
  587. return err;
  588. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  589. ESR_RXTX_RESET_CTRL_H, 0xffff);
  590. if (err)
  591. return err;
  592. udelay(200);
  593. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  594. ESR_RXTX_RESET_CTRL_L, 0xffff);
  595. if (err)
  596. return err;
  597. udelay(200);
  598. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  599. ESR_RXTX_RESET_CTRL_H, 0x0000);
  600. if (err)
  601. return err;
  602. udelay(200);
  603. err = esr_read_reset(np, &reset);
  604. if (err)
  605. return err;
  606. if (reset != 0) {
  607. netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
  608. np->port, reset);
  609. return -ENODEV;
  610. }
  611. return 0;
  612. }
  613. static int serdes_init_10g(struct niu *np)
  614. {
  615. struct niu_link_config *lp = &np->link_config;
  616. unsigned long ctrl_reg, test_cfg_reg, i;
  617. u64 ctrl_val, test_cfg_val, sig, mask, val;
  618. int err;
  619. switch (np->port) {
  620. case 0:
  621. ctrl_reg = ENET_SERDES_0_CTRL_CFG;
  622. test_cfg_reg = ENET_SERDES_0_TEST_CFG;
  623. break;
  624. case 1:
  625. ctrl_reg = ENET_SERDES_1_CTRL_CFG;
  626. test_cfg_reg = ENET_SERDES_1_TEST_CFG;
  627. break;
  628. default:
  629. return -EINVAL;
  630. }
  631. ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
  632. ENET_SERDES_CTRL_SDET_1 |
  633. ENET_SERDES_CTRL_SDET_2 |
  634. ENET_SERDES_CTRL_SDET_3 |
  635. (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
  636. (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
  637. (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
  638. (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
  639. (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
  640. (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
  641. (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
  642. (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
  643. test_cfg_val = 0;
  644. if (lp->loopback_mode == LOOPBACK_PHY) {
  645. test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
  646. ENET_SERDES_TEST_MD_0_SHIFT) |
  647. (ENET_TEST_MD_PAD_LOOPBACK <<
  648. ENET_SERDES_TEST_MD_1_SHIFT) |
  649. (ENET_TEST_MD_PAD_LOOPBACK <<
  650. ENET_SERDES_TEST_MD_2_SHIFT) |
  651. (ENET_TEST_MD_PAD_LOOPBACK <<
  652. ENET_SERDES_TEST_MD_3_SHIFT));
  653. }
  654. nw64(ctrl_reg, ctrl_val);
  655. nw64(test_cfg_reg, test_cfg_val);
  656. /* Initialize all 4 lanes of the SERDES. */
  657. for (i = 0; i < 4; i++) {
  658. u32 rxtx_ctrl, glue0;
  659. err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
  660. if (err)
  661. return err;
  662. err = esr_read_glue0(np, i, &glue0);
  663. if (err)
  664. return err;
  665. rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
  666. rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
  667. (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
  668. glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
  669. ESR_GLUE_CTRL0_THCNT |
  670. ESR_GLUE_CTRL0_BLTIME);
  671. glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
  672. (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
  673. (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
  674. (BLTIME_300_CYCLES <<
  675. ESR_GLUE_CTRL0_BLTIME_SHIFT));
  676. err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
  677. if (err)
  678. return err;
  679. err = esr_write_glue0(np, i, glue0);
  680. if (err)
  681. return err;
  682. }
  683. err = esr_reset(np);
  684. if (err)
  685. return err;
  686. sig = nr64(ESR_INT_SIGNALS);
  687. switch (np->port) {
  688. case 0:
  689. mask = ESR_INT_SIGNALS_P0_BITS;
  690. val = (ESR_INT_SRDY0_P0 |
  691. ESR_INT_DET0_P0 |
  692. ESR_INT_XSRDY_P0 |
  693. ESR_INT_XDP_P0_CH3 |
  694. ESR_INT_XDP_P0_CH2 |
  695. ESR_INT_XDP_P0_CH1 |
  696. ESR_INT_XDP_P0_CH0);
  697. break;
  698. case 1:
  699. mask = ESR_INT_SIGNALS_P1_BITS;
  700. val = (ESR_INT_SRDY0_P1 |
  701. ESR_INT_DET0_P1 |
  702. ESR_INT_XSRDY_P1 |
  703. ESR_INT_XDP_P1_CH3 |
  704. ESR_INT_XDP_P1_CH2 |
  705. ESR_INT_XDP_P1_CH1 |
  706. ESR_INT_XDP_P1_CH0);
  707. break;
  708. default:
  709. return -EINVAL;
  710. }
  711. if ((sig & mask) != val) {
  712. if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
  713. np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  714. return 0;
  715. }
  716. netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
  717. np->port, (int)(sig & mask), (int)val);
  718. return -ENODEV;
  719. }
  720. if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
  721. np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  722. return 0;
  723. }
  724. static int serdes_init_1g(struct niu *np)
  725. {
  726. u64 val;
  727. val = nr64(ENET_SERDES_1_PLL_CFG);
  728. val &= ~ENET_SERDES_PLL_FBDIV2;
  729. switch (np->port) {
  730. case 0:
  731. val |= ENET_SERDES_PLL_HRATE0;
  732. break;
  733. case 1:
  734. val |= ENET_SERDES_PLL_HRATE1;
  735. break;
  736. case 2:
  737. val |= ENET_SERDES_PLL_HRATE2;
  738. break;
  739. case 3:
  740. val |= ENET_SERDES_PLL_HRATE3;
  741. break;
  742. default:
  743. return -EINVAL;
  744. }
  745. nw64(ENET_SERDES_1_PLL_CFG, val);
  746. return 0;
  747. }
  748. static int serdes_init_1g_serdes(struct niu *np)
  749. {
  750. struct niu_link_config *lp = &np->link_config;
  751. unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
  752. u64 ctrl_val, test_cfg_val, sig, mask, val;
  753. int err;
  754. u64 reset_val, val_rd;
  755. val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
  756. ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
  757. ENET_SERDES_PLL_FBDIV0;
  758. switch (np->port) {
  759. case 0:
  760. reset_val = ENET_SERDES_RESET_0;
  761. ctrl_reg = ENET_SERDES_0_CTRL_CFG;
  762. test_cfg_reg = ENET_SERDES_0_TEST_CFG;
  763. pll_cfg = ENET_SERDES_0_PLL_CFG;
  764. break;
  765. case 1:
  766. reset_val = ENET_SERDES_RESET_1;
  767. ctrl_reg = ENET_SERDES_1_CTRL_CFG;
  768. test_cfg_reg = ENET_SERDES_1_TEST_CFG;
  769. pll_cfg = ENET_SERDES_1_PLL_CFG;
  770. break;
  771. default:
  772. return -EINVAL;
  773. }
  774. ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
  775. ENET_SERDES_CTRL_SDET_1 |
  776. ENET_SERDES_CTRL_SDET_2 |
  777. ENET_SERDES_CTRL_SDET_3 |
  778. (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
  779. (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
  780. (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
  781. (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
  782. (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
  783. (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
  784. (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
  785. (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
  786. test_cfg_val = 0;
  787. if (lp->loopback_mode == LOOPBACK_PHY) {
  788. test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
  789. ENET_SERDES_TEST_MD_0_SHIFT) |
  790. (ENET_TEST_MD_PAD_LOOPBACK <<
  791. ENET_SERDES_TEST_MD_1_SHIFT) |
  792. (ENET_TEST_MD_PAD_LOOPBACK <<
  793. ENET_SERDES_TEST_MD_2_SHIFT) |
  794. (ENET_TEST_MD_PAD_LOOPBACK <<
  795. ENET_SERDES_TEST_MD_3_SHIFT));
  796. }
  797. nw64(ENET_SERDES_RESET, reset_val);
  798. mdelay(20);
  799. val_rd = nr64(ENET_SERDES_RESET);
  800. val_rd &= ~reset_val;
  801. nw64(pll_cfg, val);
  802. nw64(ctrl_reg, ctrl_val);
  803. nw64(test_cfg_reg, test_cfg_val);
  804. nw64(ENET_SERDES_RESET, val_rd);
  805. mdelay(2000);
  806. /* Initialize all 4 lanes of the SERDES. */
  807. for (i = 0; i < 4; i++) {
  808. u32 rxtx_ctrl, glue0;
  809. err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
  810. if (err)
  811. return err;
  812. err = esr_read_glue0(np, i, &glue0);
  813. if (err)
  814. return err;
  815. rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
  816. rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
  817. (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
  818. glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
  819. ESR_GLUE_CTRL0_THCNT |
  820. ESR_GLUE_CTRL0_BLTIME);
  821. glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
  822. (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
  823. (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
  824. (BLTIME_300_CYCLES <<
  825. ESR_GLUE_CTRL0_BLTIME_SHIFT));
  826. err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
  827. if (err)
  828. return err;
  829. err = esr_write_glue0(np, i, glue0);
  830. if (err)
  831. return err;
  832. }
  833. sig = nr64(ESR_INT_SIGNALS);
  834. switch (np->port) {
  835. case 0:
  836. val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
  837. mask = val;
  838. break;
  839. case 1:
  840. val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
  841. mask = val;
  842. break;
  843. default:
  844. return -EINVAL;
  845. }
  846. if ((sig & mask) != val) {
  847. netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
  848. np->port, (int)(sig & mask), (int)val);
  849. return -ENODEV;
  850. }
  851. return 0;
  852. }
  853. static int link_status_1g_serdes(struct niu *np, int *link_up_p)
  854. {
  855. struct niu_link_config *lp = &np->link_config;
  856. int link_up;
  857. u64 val;
  858. u16 current_speed;
  859. unsigned long flags;
  860. u8 current_duplex;
  861. link_up = 0;
  862. current_speed = SPEED_INVALID;
  863. current_duplex = DUPLEX_INVALID;
  864. spin_lock_irqsave(&np->lock, flags);
  865. val = nr64_pcs(PCS_MII_STAT);
  866. if (val & PCS_MII_STAT_LINK_STATUS) {
  867. link_up = 1;
  868. current_speed = SPEED_1000;
  869. current_duplex = DUPLEX_FULL;
  870. }
  871. lp->active_speed = current_speed;
  872. lp->active_duplex = current_duplex;
  873. spin_unlock_irqrestore(&np->lock, flags);
  874. *link_up_p = link_up;
  875. return 0;
  876. }
  877. static int link_status_10g_serdes(struct niu *np, int *link_up_p)
  878. {
  879. unsigned long flags;
  880. struct niu_link_config *lp = &np->link_config;
  881. int link_up = 0;
  882. int link_ok = 1;
  883. u64 val, val2;
  884. u16 current_speed;
  885. u8 current_duplex;
  886. if (!(np->flags & NIU_FLAGS_10G))
  887. return link_status_1g_serdes(np, link_up_p);
  888. current_speed = SPEED_INVALID;
  889. current_duplex = DUPLEX_INVALID;
  890. spin_lock_irqsave(&np->lock, flags);
  891. val = nr64_xpcs(XPCS_STATUS(0));
  892. val2 = nr64_mac(XMAC_INTER2);
  893. if (val2 & 0x01000000)
  894. link_ok = 0;
  895. if ((val & 0x1000ULL) && link_ok) {
  896. link_up = 1;
  897. current_speed = SPEED_10000;
  898. current_duplex = DUPLEX_FULL;
  899. }
  900. lp->active_speed = current_speed;
  901. lp->active_duplex = current_duplex;
  902. spin_unlock_irqrestore(&np->lock, flags);
  903. *link_up_p = link_up;
  904. return 0;
  905. }
  906. static int link_status_mii(struct niu *np, int *link_up_p)
  907. {
  908. struct niu_link_config *lp = &np->link_config;
  909. int err;
  910. int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
  911. int supported, advertising, active_speed, active_duplex;
  912. err = mii_read(np, np->phy_addr, MII_BMCR);
  913. if (unlikely(err < 0))
  914. return err;
  915. bmcr = err;
  916. err = mii_read(np, np->phy_addr, MII_BMSR);
  917. if (unlikely(err < 0))
  918. return err;
  919. bmsr = err;
  920. err = mii_read(np, np->phy_addr, MII_ADVERTISE);
  921. if (unlikely(err < 0))
  922. return err;
  923. advert = err;
  924. err = mii_read(np, np->phy_addr, MII_LPA);
  925. if (unlikely(err < 0))
  926. return err;
  927. lpa = err;
  928. if (likely(bmsr & BMSR_ESTATEN)) {
  929. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  930. if (unlikely(err < 0))
  931. return err;
  932. estatus = err;
  933. err = mii_read(np, np->phy_addr, MII_CTRL1000);
  934. if (unlikely(err < 0))
  935. return err;
  936. ctrl1000 = err;
  937. err = mii_read(np, np->phy_addr, MII_STAT1000);
  938. if (unlikely(err < 0))
  939. return err;
  940. stat1000 = err;
  941. } else
  942. estatus = ctrl1000 = stat1000 = 0;
  943. supported = 0;
  944. if (bmsr & BMSR_ANEGCAPABLE)
  945. supported |= SUPPORTED_Autoneg;
  946. if (bmsr & BMSR_10HALF)
  947. supported |= SUPPORTED_10baseT_Half;
  948. if (bmsr & BMSR_10FULL)
  949. supported |= SUPPORTED_10baseT_Full;
  950. if (bmsr & BMSR_100HALF)
  951. supported |= SUPPORTED_100baseT_Half;
  952. if (bmsr & BMSR_100FULL)
  953. supported |= SUPPORTED_100baseT_Full;
  954. if (estatus & ESTATUS_1000_THALF)
  955. supported |= SUPPORTED_1000baseT_Half;
  956. if (estatus & ESTATUS_1000_TFULL)
  957. supported |= SUPPORTED_1000baseT_Full;
  958. lp->supported = supported;
  959. advertising = 0;
  960. if (advert & ADVERTISE_10HALF)
  961. advertising |= ADVERTISED_10baseT_Half;
  962. if (advert & ADVERTISE_10FULL)
  963. advertising |= ADVERTISED_10baseT_Full;
  964. if (advert & ADVERTISE_100HALF)
  965. advertising |= ADVERTISED_100baseT_Half;
  966. if (advert & ADVERTISE_100FULL)
  967. advertising |= ADVERTISED_100baseT_Full;
  968. if (ctrl1000 & ADVERTISE_1000HALF)
  969. advertising |= ADVERTISED_1000baseT_Half;
  970. if (ctrl1000 & ADVERTISE_1000FULL)
  971. advertising |= ADVERTISED_1000baseT_Full;
  972. if (bmcr & BMCR_ANENABLE) {
  973. int neg, neg1000;
  974. lp->active_autoneg = 1;
  975. advertising |= ADVERTISED_Autoneg;
  976. neg = advert & lpa;
  977. neg1000 = (ctrl1000 << 2) & stat1000;
  978. if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
  979. active_speed = SPEED_1000;
  980. else if (neg & LPA_100)
  981. active_speed = SPEED_100;
  982. else if (neg & (LPA_10HALF | LPA_10FULL))
  983. active_speed = SPEED_10;
  984. else
  985. active_speed = SPEED_INVALID;
  986. if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
  987. active_duplex = DUPLEX_FULL;
  988. else if (active_speed != SPEED_INVALID)
  989. active_duplex = DUPLEX_HALF;
  990. else
  991. active_duplex = DUPLEX_INVALID;
  992. } else {
  993. lp->active_autoneg = 0;
  994. if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
  995. active_speed = SPEED_1000;
  996. else if (bmcr & BMCR_SPEED100)
  997. active_speed = SPEED_100;
  998. else
  999. active_speed = SPEED_10;
  1000. if (bmcr & BMCR_FULLDPLX)
  1001. active_duplex = DUPLEX_FULL;
  1002. else
  1003. active_duplex = DUPLEX_HALF;
  1004. }
  1005. lp->active_advertising = advertising;
  1006. lp->active_speed = active_speed;
  1007. lp->active_duplex = active_duplex;
  1008. *link_up_p = !!(bmsr & BMSR_LSTATUS);
  1009. return 0;
  1010. }
  1011. static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
  1012. {
  1013. struct niu_link_config *lp = &np->link_config;
  1014. u16 current_speed, bmsr;
  1015. unsigned long flags;
  1016. u8 current_duplex;
  1017. int err, link_up;
  1018. link_up = 0;
  1019. current_speed = SPEED_INVALID;
  1020. current_duplex = DUPLEX_INVALID;
  1021. spin_lock_irqsave(&np->lock, flags);
  1022. err = -EINVAL;
  1023. err = mii_read(np, np->phy_addr, MII_BMSR);
  1024. if (err < 0)
  1025. goto out;
  1026. bmsr = err;
  1027. if (bmsr & BMSR_LSTATUS) {
  1028. u16 adv, lpa, common, estat;
  1029. err = mii_read(np, np->phy_addr, MII_ADVERTISE);
  1030. if (err < 0)
  1031. goto out;
  1032. adv = err;
  1033. err = mii_read(np, np->phy_addr, MII_LPA);
  1034. if (err < 0)
  1035. goto out;
  1036. lpa = err;
  1037. common = adv & lpa;
  1038. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  1039. if (err < 0)
  1040. goto out;
  1041. estat = err;
  1042. link_up = 1;
  1043. current_speed = SPEED_1000;
  1044. current_duplex = DUPLEX_FULL;
  1045. }
  1046. lp->active_speed = current_speed;
  1047. lp->active_duplex = current_duplex;
  1048. err = 0;
  1049. out:
  1050. spin_unlock_irqrestore(&np->lock, flags);
  1051. *link_up_p = link_up;
  1052. return err;
  1053. }
  1054. static int link_status_1g(struct niu *np, int *link_up_p)
  1055. {
  1056. struct niu_link_config *lp = &np->link_config;
  1057. unsigned long flags;
  1058. int err;
  1059. spin_lock_irqsave(&np->lock, flags);
  1060. err = link_status_mii(np, link_up_p);
  1061. lp->supported |= SUPPORTED_TP;
  1062. lp->active_advertising |= ADVERTISED_TP;
  1063. spin_unlock_irqrestore(&np->lock, flags);
  1064. return err;
  1065. }
  1066. static int bcm8704_reset(struct niu *np)
  1067. {
  1068. int err, limit;
  1069. err = mdio_read(np, np->phy_addr,
  1070. BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
  1071. if (err < 0 || err == 0xffff)
  1072. return err;
  1073. err |= BMCR_RESET;
  1074. err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  1075. MII_BMCR, err);
  1076. if (err)
  1077. return err;
  1078. limit = 1000;
  1079. while (--limit >= 0) {
  1080. err = mdio_read(np, np->phy_addr,
  1081. BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
  1082. if (err < 0)
  1083. return err;
  1084. if (!(err & BMCR_RESET))
  1085. break;
  1086. }
  1087. if (limit < 0) {
  1088. netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
  1089. np->port, (err & 0xffff));
  1090. return -ENODEV;
  1091. }
  1092. return 0;
  1093. }
  1094. /* When written, certain PHY registers need to be read back twice
  1095. * in order for the bits to settle properly.
  1096. */
  1097. static int bcm8704_user_dev3_readback(struct niu *np, int reg)
  1098. {
  1099. int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
  1100. if (err < 0)
  1101. return err;
  1102. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
  1103. if (err < 0)
  1104. return err;
  1105. return 0;
  1106. }
  1107. static int bcm8706_init_user_dev3(struct niu *np)
  1108. {
  1109. int err;
  1110. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1111. BCM8704_USER_OPT_DIGITAL_CTRL);
  1112. if (err < 0)
  1113. return err;
  1114. err &= ~USER_ODIG_CTRL_GPIOS;
  1115. err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
  1116. err |= USER_ODIG_CTRL_RESV2;
  1117. err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1118. BCM8704_USER_OPT_DIGITAL_CTRL, err);
  1119. if (err)
  1120. return err;
  1121. mdelay(1000);
  1122. return 0;
  1123. }
  1124. static int bcm8704_init_user_dev3(struct niu *np)
  1125. {
  1126. int err;
  1127. err = mdio_write(np, np->phy_addr,
  1128. BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
  1129. (USER_CONTROL_OPTXRST_LVL |
  1130. USER_CONTROL_OPBIASFLT_LVL |
  1131. USER_CONTROL_OBTMPFLT_LVL |
  1132. USER_CONTROL_OPPRFLT_LVL |
  1133. USER_CONTROL_OPTXFLT_LVL |
  1134. USER_CONTROL_OPRXLOS_LVL |
  1135. USER_CONTROL_OPRXFLT_LVL |
  1136. USER_CONTROL_OPTXON_LVL |
  1137. (0x3f << USER_CONTROL_RES1_SHIFT)));
  1138. if (err)
  1139. return err;
  1140. err = mdio_write(np, np->phy_addr,
  1141. BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
  1142. (USER_PMD_TX_CTL_XFP_CLKEN |
  1143. (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
  1144. (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
  1145. USER_PMD_TX_CTL_TSCK_LPWREN));
  1146. if (err)
  1147. return err;
  1148. err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
  1149. if (err)
  1150. return err;
  1151. err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
  1152. if (err)
  1153. return err;
  1154. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1155. BCM8704_USER_OPT_DIGITAL_CTRL);
  1156. if (err < 0)
  1157. return err;
  1158. err &= ~USER_ODIG_CTRL_GPIOS;
  1159. err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
  1160. err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1161. BCM8704_USER_OPT_DIGITAL_CTRL, err);
  1162. if (err)
  1163. return err;
  1164. mdelay(1000);
  1165. return 0;
  1166. }
  1167. static int mrvl88x2011_act_led(struct niu *np, int val)
  1168. {
  1169. int err;
  1170. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  1171. MRVL88X2011_LED_8_TO_11_CTL);
  1172. if (err < 0)
  1173. return err;
  1174. err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
  1175. err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
  1176. return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  1177. MRVL88X2011_LED_8_TO_11_CTL, err);
  1178. }
  1179. static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
  1180. {
  1181. int err;
  1182. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  1183. MRVL88X2011_LED_BLINK_CTL);
  1184. if (err >= 0) {
  1185. err &= ~MRVL88X2011_LED_BLKRATE_MASK;
  1186. err |= (rate << 4);
  1187. err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  1188. MRVL88X2011_LED_BLINK_CTL, err);
  1189. }
  1190. return err;
  1191. }
  1192. static int xcvr_init_10g_mrvl88x2011(struct niu *np)
  1193. {
  1194. int err;
  1195. /* Set LED functions */
  1196. err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
  1197. if (err)
  1198. return err;
  1199. /* led activity */
  1200. err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
  1201. if (err)
  1202. return err;
  1203. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  1204. MRVL88X2011_GENERAL_CTL);
  1205. if (err < 0)
  1206. return err;
  1207. err |= MRVL88X2011_ENA_XFPREFCLK;
  1208. err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  1209. MRVL88X2011_GENERAL_CTL, err);
  1210. if (err < 0)
  1211. return err;
  1212. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  1213. MRVL88X2011_PMA_PMD_CTL_1);
  1214. if (err < 0)
  1215. return err;
  1216. if (np->link_config.loopback_mode == LOOPBACK_MAC)
  1217. err |= MRVL88X2011_LOOPBACK;
  1218. else
  1219. err &= ~MRVL88X2011_LOOPBACK;
  1220. err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  1221. MRVL88X2011_PMA_PMD_CTL_1, err);
  1222. if (err < 0)
  1223. return err;
  1224. /* Enable PMD */
  1225. return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  1226. MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
  1227. }
  1228. static int xcvr_diag_bcm870x(struct niu *np)
  1229. {
  1230. u16 analog_stat0, tx_alarm_status;
  1231. int err = 0;
  1232. #if 1
  1233. err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
  1234. MII_STAT1000);
  1235. if (err < 0)
  1236. return err;
  1237. pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
  1238. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
  1239. if (err < 0)
  1240. return err;
  1241. pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
  1242. err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  1243. MII_NWAYTEST);
  1244. if (err < 0)
  1245. return err;
  1246. pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
  1247. #endif
  1248. /* XXX dig this out it might not be so useful XXX */
  1249. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1250. BCM8704_USER_ANALOG_STATUS0);
  1251. if (err < 0)
  1252. return err;
  1253. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1254. BCM8704_USER_ANALOG_STATUS0);
  1255. if (err < 0)
  1256. return err;
  1257. analog_stat0 = err;
  1258. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1259. BCM8704_USER_TX_ALARM_STATUS);
  1260. if (err < 0)
  1261. return err;
  1262. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  1263. BCM8704_USER_TX_ALARM_STATUS);
  1264. if (err < 0)
  1265. return err;
  1266. tx_alarm_status = err;
  1267. if (analog_stat0 != 0x03fc) {
  1268. if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
  1269. pr_info("Port %u cable not connected or bad cable\n",
  1270. np->port);
  1271. } else if (analog_stat0 == 0x639c) {
  1272. pr_info("Port %u optical module is bad or missing\n",
  1273. np->port);
  1274. }
  1275. }
  1276. return 0;
  1277. }
  1278. static int xcvr_10g_set_lb_bcm870x(struct niu *np)
  1279. {
  1280. struct niu_link_config *lp = &np->link_config;
  1281. int err;
  1282. err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1283. MII_BMCR);
  1284. if (err < 0)
  1285. return err;
  1286. err &= ~BMCR_LOOPBACK;
  1287. if (lp->loopback_mode == LOOPBACK_MAC)
  1288. err |= BMCR_LOOPBACK;
  1289. err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1290. MII_BMCR, err);
  1291. if (err)
  1292. return err;
  1293. return 0;
  1294. }
  1295. static int xcvr_init_10g_bcm8706(struct niu *np)
  1296. {
  1297. int err = 0;
  1298. u64 val;
  1299. if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
  1300. (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
  1301. return err;
  1302. val = nr64_mac(XMAC_CONFIG);
  1303. val &= ~XMAC_CONFIG_LED_POLARITY;
  1304. val |= XMAC_CONFIG_FORCE_LED_ON;
  1305. nw64_mac(XMAC_CONFIG, val);
  1306. val = nr64(MIF_CONFIG);
  1307. val |= MIF_CONFIG_INDIRECT_MODE;
  1308. nw64(MIF_CONFIG, val);
  1309. err = bcm8704_reset(np);
  1310. if (err)
  1311. return err;
  1312. err = xcvr_10g_set_lb_bcm870x(np);
  1313. if (err)
  1314. return err;
  1315. err = bcm8706_init_user_dev3(np);
  1316. if (err)
  1317. return err;
  1318. err = xcvr_diag_bcm870x(np);
  1319. if (err)
  1320. return err;
  1321. return 0;
  1322. }
  1323. static int xcvr_init_10g_bcm8704(struct niu *np)
  1324. {
  1325. int err;
  1326. err = bcm8704_reset(np);
  1327. if (err)
  1328. return err;
  1329. err = bcm8704_init_user_dev3(np);
  1330. if (err)
  1331. return err;
  1332. err = xcvr_10g_set_lb_bcm870x(np);
  1333. if (err)
  1334. return err;
  1335. err = xcvr_diag_bcm870x(np);
  1336. if (err)
  1337. return err;
  1338. return 0;
  1339. }
  1340. static int xcvr_init_10g(struct niu *np)
  1341. {
  1342. int phy_id, err;
  1343. u64 val;
  1344. val = nr64_mac(XMAC_CONFIG);
  1345. val &= ~XMAC_CONFIG_LED_POLARITY;
  1346. val |= XMAC_CONFIG_FORCE_LED_ON;
  1347. nw64_mac(XMAC_CONFIG, val);
  1348. /* XXX shared resource, lock parent XXX */
  1349. val = nr64(MIF_CONFIG);
  1350. val |= MIF_CONFIG_INDIRECT_MODE;
  1351. nw64(MIF_CONFIG, val);
  1352. phy_id = phy_decode(np->parent->port_phy, np->port);
  1353. phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
  1354. /* handle different phy types */
  1355. switch (phy_id & NIU_PHY_ID_MASK) {
  1356. case NIU_PHY_ID_MRVL88X2011:
  1357. err = xcvr_init_10g_mrvl88x2011(np);
  1358. break;
  1359. default: /* bcom 8704 */
  1360. err = xcvr_init_10g_bcm8704(np);
  1361. break;
  1362. }
  1363. return 0;
  1364. }
  1365. static int mii_reset(struct niu *np)
  1366. {
  1367. int limit, err;
  1368. err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
  1369. if (err)
  1370. return err;
  1371. limit = 1000;
  1372. while (--limit >= 0) {
  1373. udelay(500);
  1374. err = mii_read(np, np->phy_addr, MII_BMCR);
  1375. if (err < 0)
  1376. return err;
  1377. if (!(err & BMCR_RESET))
  1378. break;
  1379. }
  1380. if (limit < 0) {
  1381. netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
  1382. np->port, err);
  1383. return -ENODEV;
  1384. }
  1385. return 0;
  1386. }
  1387. static int xcvr_init_1g_rgmii(struct niu *np)
  1388. {
  1389. int err;
  1390. u64 val;
  1391. u16 bmcr, bmsr, estat;
  1392. val = nr64(MIF_CONFIG);
  1393. val &= ~MIF_CONFIG_INDIRECT_MODE;
  1394. nw64(MIF_CONFIG, val);
  1395. err = mii_reset(np);
  1396. if (err)
  1397. return err;
  1398. err = mii_read(np, np->phy_addr, MII_BMSR);
  1399. if (err < 0)
  1400. return err;
  1401. bmsr = err;
  1402. estat = 0;
  1403. if (bmsr & BMSR_ESTATEN) {
  1404. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  1405. if (err < 0)
  1406. return err;
  1407. estat = err;
  1408. }
  1409. bmcr = 0;
  1410. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1411. if (err)
  1412. return err;
  1413. if (bmsr & BMSR_ESTATEN) {
  1414. u16 ctrl1000 = 0;
  1415. if (estat & ESTATUS_1000_TFULL)
  1416. ctrl1000 |= ADVERTISE_1000FULL;
  1417. err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
  1418. if (err)
  1419. return err;
  1420. }
  1421. bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
  1422. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1423. if (err)
  1424. return err;
  1425. err = mii_read(np, np->phy_addr, MII_BMCR);
  1426. if (err < 0)
  1427. return err;
  1428. bmcr = mii_read(np, np->phy_addr, MII_BMCR);
  1429. err = mii_read(np, np->phy_addr, MII_BMSR);
  1430. if (err < 0)
  1431. return err;
  1432. return 0;
  1433. }
  1434. static int mii_init_common(struct niu *np)
  1435. {
  1436. struct niu_link_config *lp = &np->link_config;
  1437. u16 bmcr, bmsr, adv, estat;
  1438. int err;
  1439. err = mii_reset(np);
  1440. if (err)
  1441. return err;
  1442. err = mii_read(np, np->phy_addr, MII_BMSR);
  1443. if (err < 0)
  1444. return err;
  1445. bmsr = err;
  1446. estat = 0;
  1447. if (bmsr & BMSR_ESTATEN) {
  1448. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  1449. if (err < 0)
  1450. return err;
  1451. estat = err;
  1452. }
  1453. bmcr = 0;
  1454. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1455. if (err)
  1456. return err;
  1457. if (lp->loopback_mode == LOOPBACK_MAC) {
  1458. bmcr |= BMCR_LOOPBACK;
  1459. if (lp->active_speed == SPEED_1000)
  1460. bmcr |= BMCR_SPEED1000;
  1461. if (lp->active_duplex == DUPLEX_FULL)
  1462. bmcr |= BMCR_FULLDPLX;
  1463. }
  1464. if (lp->loopback_mode == LOOPBACK_PHY) {
  1465. u16 aux;
  1466. aux = (BCM5464R_AUX_CTL_EXT_LB |
  1467. BCM5464R_AUX_CTL_WRITE_1);
  1468. err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
  1469. if (err)
  1470. return err;
  1471. }
  1472. if (lp->autoneg) {
  1473. u16 ctrl1000;
  1474. adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1475. if ((bmsr & BMSR_10HALF) &&
  1476. (lp->advertising & ADVERTISED_10baseT_Half))
  1477. adv |= ADVERTISE_10HALF;
  1478. if ((bmsr & BMSR_10FULL) &&
  1479. (lp->advertising & ADVERTISED_10baseT_Full))
  1480. adv |= ADVERTISE_10FULL;
  1481. if ((bmsr & BMSR_100HALF) &&
  1482. (lp->advertising & ADVERTISED_100baseT_Half))
  1483. adv |= ADVERTISE_100HALF;
  1484. if ((bmsr & BMSR_100FULL) &&
  1485. (lp->advertising & ADVERTISED_100baseT_Full))
  1486. adv |= ADVERTISE_100FULL;
  1487. err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
  1488. if (err)
  1489. return err;
  1490. if (likely(bmsr & BMSR_ESTATEN)) {
  1491. ctrl1000 = 0;
  1492. if ((estat & ESTATUS_1000_THALF) &&
  1493. (lp->advertising & ADVERTISED_1000baseT_Half))
  1494. ctrl1000 |= ADVERTISE_1000HALF;
  1495. if ((estat & ESTATUS_1000_TFULL) &&
  1496. (lp->advertising & ADVERTISED_1000baseT_Full))
  1497. ctrl1000 |= ADVERTISE_1000FULL;
  1498. err = mii_write(np, np->phy_addr,
  1499. MII_CTRL1000, ctrl1000);
  1500. if (err)
  1501. return err;
  1502. }
  1503. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  1504. } else {
  1505. /* !lp->autoneg */
  1506. int fulldpx;
  1507. if (lp->duplex == DUPLEX_FULL) {
  1508. bmcr |= BMCR_FULLDPLX;
  1509. fulldpx = 1;
  1510. } else if (lp->duplex == DUPLEX_HALF)
  1511. fulldpx = 0;
  1512. else
  1513. return -EINVAL;
  1514. if (lp->speed == SPEED_1000) {
  1515. /* if X-full requested while not supported, or
  1516. X-half requested while not supported... */
  1517. if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
  1518. (!fulldpx && !(estat & ESTATUS_1000_THALF)))
  1519. return -EINVAL;
  1520. bmcr |= BMCR_SPEED1000;
  1521. } else if (lp->speed == SPEED_100) {
  1522. if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
  1523. (!fulldpx && !(bmsr & BMSR_100HALF)))
  1524. return -EINVAL;
  1525. bmcr |= BMCR_SPEED100;
  1526. } else if (lp->speed == SPEED_10) {
  1527. if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
  1528. (!fulldpx && !(bmsr & BMSR_10HALF)))
  1529. return -EINVAL;
  1530. } else
  1531. return -EINVAL;
  1532. }
  1533. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1534. if (err)
  1535. return err;
  1536. #if 0
  1537. err = mii_read(np, np->phy_addr, MII_BMCR);
  1538. if (err < 0)
  1539. return err;
  1540. bmcr = err;
  1541. err = mii_read(np, np->phy_addr, MII_BMSR);
  1542. if (err < 0)
  1543. return err;
  1544. bmsr = err;
  1545. pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
  1546. np->port, bmcr, bmsr);
  1547. #endif
  1548. return 0;
  1549. }
  1550. static int xcvr_init_1g(struct niu *np)
  1551. {
  1552. u64 val;
  1553. /* XXX shared resource, lock parent XXX */
  1554. val = nr64(MIF_CONFIG);
  1555. val &= ~MIF_CONFIG_INDIRECT_MODE;
  1556. nw64(MIF_CONFIG, val);
  1557. return mii_init_common(np);
  1558. }
  1559. static int niu_xcvr_init(struct niu *np)
  1560. {
  1561. const struct niu_phy_ops *ops = np->phy_ops;
  1562. int err;
  1563. err = 0;
  1564. if (ops->xcvr_init)
  1565. err = ops->xcvr_init(np);
  1566. return err;
  1567. }
  1568. static int niu_serdes_init(struct niu *np)
  1569. {
  1570. const struct niu_phy_ops *ops = np->phy_ops;
  1571. int err;
  1572. err = 0;
  1573. if (ops->serdes_init)
  1574. err = ops->serdes_init(np);
  1575. return err;
  1576. }
  1577. static void niu_init_xif(struct niu *);
  1578. static void niu_handle_led(struct niu *, int status);
  1579. static int niu_link_status_common(struct niu *np, int link_up)
  1580. {
  1581. struct niu_link_config *lp = &np->link_config;
  1582. struct net_device *dev = np->dev;
  1583. unsigned long flags;
  1584. if (!netif_carrier_ok(dev) && link_up) {
  1585. netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
  1586. lp->active_speed == SPEED_10000 ? "10Gb/sec" :
  1587. lp->active_speed == SPEED_1000 ? "1Gb/sec" :
  1588. lp->active_speed == SPEED_100 ? "100Mbit/sec" :
  1589. "10Mbit/sec",
  1590. lp->active_duplex == DUPLEX_FULL ? "full" : "half");
  1591. spin_lock_irqsave(&np->lock, flags);
  1592. niu_init_xif(np);
  1593. niu_handle_led(np, 1);
  1594. spin_unlock_irqrestore(&np->lock, flags);
  1595. netif_carrier_on(dev);
  1596. } else if (netif_carrier_ok(dev) && !link_up) {
  1597. netif_warn(np, link, dev, "Link is down\n");
  1598. spin_lock_irqsave(&np->lock, flags);
  1599. niu_handle_led(np, 0);
  1600. spin_unlock_irqrestore(&np->lock, flags);
  1601. netif_carrier_off(dev);
  1602. }
  1603. return 0;
  1604. }
  1605. static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
  1606. {
  1607. int err, link_up, pma_status, pcs_status;
  1608. link_up = 0;
  1609. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  1610. MRVL88X2011_10G_PMD_STATUS_2);
  1611. if (err < 0)
  1612. goto out;
  1613. /* Check PMA/PMD Register: 1.0001.2 == 1 */
  1614. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  1615. MRVL88X2011_PMA_PMD_STATUS_1);
  1616. if (err < 0)
  1617. goto out;
  1618. pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
  1619. /* Check PMC Register : 3.0001.2 == 1: read twice */
  1620. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  1621. MRVL88X2011_PMA_PMD_STATUS_1);
  1622. if (err < 0)
  1623. goto out;
  1624. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  1625. MRVL88X2011_PMA_PMD_STATUS_1);
  1626. if (err < 0)
  1627. goto out;
  1628. pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
  1629. /* Check XGXS Register : 4.0018.[0-3,12] */
  1630. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
  1631. MRVL88X2011_10G_XGXS_LANE_STAT);
  1632. if (err < 0)
  1633. goto out;
  1634. if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
  1635. PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
  1636. PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
  1637. 0x800))
  1638. link_up = (pma_status && pcs_status) ? 1 : 0;
  1639. np->link_config.active_speed = SPEED_10000;
  1640. np->link_config.active_duplex = DUPLEX_FULL;
  1641. err = 0;
  1642. out:
  1643. mrvl88x2011_act_led(np, (link_up ?
  1644. MRVL88X2011_LED_CTL_PCS_ACT :
  1645. MRVL88X2011_LED_CTL_OFF));
  1646. *link_up_p = link_up;
  1647. return err;
  1648. }
  1649. static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
  1650. {
  1651. int err, link_up;
  1652. link_up = 0;
  1653. err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
  1654. BCM8704_PMD_RCV_SIGDET);
  1655. if (err < 0 || err == 0xffff)
  1656. goto out;
  1657. if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
  1658. err = 0;
  1659. goto out;
  1660. }
  1661. err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1662. BCM8704_PCS_10G_R_STATUS);
  1663. if (err < 0)
  1664. goto out;
  1665. if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
  1666. err = 0;
  1667. goto out;
  1668. }
  1669. err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  1670. BCM8704_PHYXS_XGXS_LANE_STAT);
  1671. if (err < 0)
  1672. goto out;
  1673. if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
  1674. PHYXS_XGXS_LANE_STAT_MAGIC |
  1675. PHYXS_XGXS_LANE_STAT_PATTEST |
  1676. PHYXS_XGXS_LANE_STAT_LANE3 |
  1677. PHYXS_XGXS_LANE_STAT_LANE2 |
  1678. PHYXS_XGXS_LANE_STAT_LANE1 |
  1679. PHYXS_XGXS_LANE_STAT_LANE0)) {
  1680. err = 0;
  1681. np->link_config.active_speed = SPEED_INVALID;
  1682. np->link_config.active_duplex = DUPLEX_INVALID;
  1683. goto out;
  1684. }
  1685. link_up = 1;
  1686. np->link_config.active_speed = SPEED_10000;
  1687. np->link_config.active_duplex = DUPLEX_FULL;
  1688. err = 0;
  1689. out:
  1690. *link_up_p = link_up;
  1691. return err;
  1692. }
  1693. static int link_status_10g_bcom(struct niu *np, int *link_up_p)
  1694. {
  1695. int err, link_up;
  1696. link_up = 0;
  1697. err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
  1698. BCM8704_PMD_RCV_SIGDET);
  1699. if (err < 0)
  1700. goto out;
  1701. if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
  1702. err = 0;
  1703. goto out;
  1704. }
  1705. err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1706. BCM8704_PCS_10G_R_STATUS);
  1707. if (err < 0)
  1708. goto out;
  1709. if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
  1710. err = 0;
  1711. goto out;
  1712. }
  1713. err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  1714. BCM8704_PHYXS_XGXS_LANE_STAT);
  1715. if (err < 0)
  1716. goto out;
  1717. if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
  1718. PHYXS_XGXS_LANE_STAT_MAGIC |
  1719. PHYXS_XGXS_LANE_STAT_LANE3 |
  1720. PHYXS_XGXS_LANE_STAT_LANE2 |
  1721. PHYXS_XGXS_LANE_STAT_LANE1 |
  1722. PHYXS_XGXS_LANE_STAT_LANE0)) {
  1723. err = 0;
  1724. goto out;
  1725. }
  1726. link_up = 1;
  1727. np->link_config.active_speed = SPEED_10000;
  1728. np->link_config.active_duplex = DUPLEX_FULL;
  1729. err = 0;
  1730. out:
  1731. *link_up_p = link_up;
  1732. return err;
  1733. }
  1734. static int link_status_10g(struct niu *np, int *link_up_p)
  1735. {
  1736. unsigned long flags;
  1737. int err = -EINVAL;
  1738. spin_lock_irqsave(&np->lock, flags);
  1739. if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
  1740. int phy_id;
  1741. phy_id = phy_decode(np->parent->port_phy, np->port);
  1742. phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
  1743. /* handle different phy types */
  1744. switch (phy_id & NIU_PHY_ID_MASK) {
  1745. case NIU_PHY_ID_MRVL88X2011:
  1746. err = link_status_10g_mrvl(np, link_up_p);
  1747. break;
  1748. default: /* bcom 8704 */
  1749. err = link_status_10g_bcom(np, link_up_p);
  1750. break;
  1751. }
  1752. }
  1753. spin_unlock_irqrestore(&np->lock, flags);
  1754. return err;
  1755. }
  1756. static int niu_10g_phy_present(struct niu *np)
  1757. {
  1758. u64 sig, mask, val;
  1759. sig = nr64(ESR_INT_SIGNALS);
  1760. switch (np->port) {
  1761. case 0:
  1762. mask = ESR_INT_SIGNALS_P0_BITS;
  1763. val = (ESR_INT_SRDY0_P0 |
  1764. ESR_INT_DET0_P0 |
  1765. ESR_INT_XSRDY_P0 |
  1766. ESR_INT_XDP_P0_CH3 |
  1767. ESR_INT_XDP_P0_CH2 |
  1768. ESR_INT_XDP_P0_CH1 |
  1769. ESR_INT_XDP_P0_CH0);
  1770. break;
  1771. case 1:
  1772. mask = ESR_INT_SIGNALS_P1_BITS;
  1773. val = (ESR_INT_SRDY0_P1 |
  1774. ESR_INT_DET0_P1 |
  1775. ESR_INT_XSRDY_P1 |
  1776. ESR_INT_XDP_P1_CH3 |
  1777. ESR_INT_XDP_P1_CH2 |
  1778. ESR_INT_XDP_P1_CH1 |
  1779. ESR_INT_XDP_P1_CH0);
  1780. break;
  1781. default:
  1782. return 0;
  1783. }
  1784. if ((sig & mask) != val)
  1785. return 0;
  1786. return 1;
  1787. }
  1788. static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
  1789. {
  1790. unsigned long flags;
  1791. int err = 0;
  1792. int phy_present;
  1793. int phy_present_prev;
  1794. spin_lock_irqsave(&np->lock, flags);
  1795. if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
  1796. phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
  1797. 1 : 0;
  1798. phy_present = niu_10g_phy_present(np);
  1799. if (phy_present != phy_present_prev) {
  1800. /* state change */
  1801. if (phy_present) {
  1802. /* A NEM was just plugged in */
  1803. np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  1804. if (np->phy_ops->xcvr_init)
  1805. err = np->phy_ops->xcvr_init(np);
  1806. if (err) {
  1807. err = mdio_read(np, np->phy_addr,
  1808. BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
  1809. if (err == 0xffff) {
  1810. /* No mdio, back-to-back XAUI */
  1811. goto out;
  1812. }
  1813. /* debounce */
  1814. np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  1815. }
  1816. } else {
  1817. np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  1818. *link_up_p = 0;
  1819. netif_warn(np, link, np->dev,
  1820. "Hotplug PHY Removed\n");
  1821. }
  1822. }
  1823. out:
  1824. if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
  1825. err = link_status_10g_bcm8706(np, link_up_p);
  1826. if (err == 0xffff) {
  1827. /* No mdio, back-to-back XAUI: it is C10NEM */
  1828. *link_up_p = 1;
  1829. np->link_config.active_speed = SPEED_10000;
  1830. np->link_config.active_duplex = DUPLEX_FULL;
  1831. }
  1832. }
  1833. }
  1834. spin_unlock_irqrestore(&np->lock, flags);
  1835. return 0;
  1836. }
  1837. static int niu_link_status(struct niu *np, int *link_up_p)
  1838. {
  1839. const struct niu_phy_ops *ops = np->phy_ops;
  1840. int err;
  1841. err = 0;
  1842. if (ops->link_status)
  1843. err = ops->link_status(np, link_up_p);
  1844. return err;
  1845. }
  1846. static void niu_timer(unsigned long __opaque)
  1847. {
  1848. struct niu *np = (struct niu *) __opaque;
  1849. unsigned long off;
  1850. int err, link_up;
  1851. err = niu_link_status(np, &link_up);
  1852. if (!err)
  1853. niu_link_status_common(np, link_up);
  1854. if (netif_carrier_ok(np->dev))
  1855. off = 5 * HZ;
  1856. else
  1857. off = 1 * HZ;
  1858. np->timer.expires = jiffies + off;
  1859. add_timer(&np->timer);
  1860. }
  1861. static const struct niu_phy_ops phy_ops_10g_serdes = {
  1862. .serdes_init = serdes_init_10g_serdes,
  1863. .link_status = link_status_10g_serdes,
  1864. };
  1865. static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
  1866. .serdes_init = serdes_init_niu_10g_serdes,
  1867. .link_status = link_status_10g_serdes,
  1868. };
  1869. static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
  1870. .serdes_init = serdes_init_niu_1g_serdes,
  1871. .link_status = link_status_1g_serdes,
  1872. };
  1873. static const struct niu_phy_ops phy_ops_1g_rgmii = {
  1874. .xcvr_init = xcvr_init_1g_rgmii,
  1875. .link_status = link_status_1g_rgmii,
  1876. };
  1877. static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
  1878. .serdes_init = serdes_init_niu_10g_fiber,
  1879. .xcvr_init = xcvr_init_10g,
  1880. .link_status = link_status_10g,
  1881. };
  1882. static const struct niu_phy_ops phy_ops_10g_fiber = {
  1883. .serdes_init = serdes_init_10g,
  1884. .xcvr_init = xcvr_init_10g,
  1885. .link_status = link_status_10g,
  1886. };
  1887. static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
  1888. .serdes_init = serdes_init_10g,
  1889. .xcvr_init = xcvr_init_10g_bcm8706,
  1890. .link_status = link_status_10g_hotplug,
  1891. };
  1892. static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
  1893. .serdes_init = serdes_init_niu_10g_fiber,
  1894. .xcvr_init = xcvr_init_10g_bcm8706,
  1895. .link_status = link_status_10g_hotplug,
  1896. };
  1897. static const struct niu_phy_ops phy_ops_10g_copper = {
  1898. .serdes_init = serdes_init_10g,
  1899. .link_status = link_status_10g, /* XXX */
  1900. };
  1901. static const struct niu_phy_ops phy_ops_1g_fiber = {
  1902. .serdes_init = serdes_init_1g,
  1903. .xcvr_init = xcvr_init_1g,
  1904. .link_status = link_status_1g,
  1905. };
  1906. static const struct niu_phy_ops phy_ops_1g_copper = {
  1907. .xcvr_init = xcvr_init_1g,
  1908. .link_status = link_status_1g,
  1909. };
  1910. struct niu_phy_template {
  1911. const struct niu_phy_ops *ops;
  1912. u32 phy_addr_base;
  1913. };
  1914. static const struct niu_phy_template phy_template_niu_10g_fiber = {
  1915. .ops = &phy_ops_10g_fiber_niu,
  1916. .phy_addr_base = 16,
  1917. };
  1918. static const struct niu_phy_template phy_template_niu_10g_serdes = {
  1919. .ops = &phy_ops_10g_serdes_niu,
  1920. .phy_addr_base = 0,
  1921. };
  1922. static const struct niu_phy_template phy_template_niu_1g_serdes = {
  1923. .ops = &phy_ops_1g_serdes_niu,
  1924. .phy_addr_base = 0,
  1925. };
  1926. static const struct niu_phy_template phy_template_10g_fiber = {
  1927. .ops = &phy_ops_10g_fiber,
  1928. .phy_addr_base = 8,
  1929. };
  1930. static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
  1931. .ops = &phy_ops_10g_fiber_hotplug,
  1932. .phy_addr_base = 8,
  1933. };
  1934. static const struct niu_phy_template phy_template_niu_10g_hotplug = {
  1935. .ops = &phy_ops_niu_10g_hotplug,
  1936. .phy_addr_base = 8,
  1937. };
  1938. static const struct niu_phy_template phy_template_10g_copper = {
  1939. .ops = &phy_ops_10g_copper,
  1940. .phy_addr_base = 10,
  1941. };
  1942. static const struct niu_phy_template phy_template_1g_fiber = {
  1943. .ops = &phy_ops_1g_fiber,
  1944. .phy_addr_base = 0,
  1945. };
  1946. static const struct niu_phy_template phy_template_1g_copper = {
  1947. .ops = &phy_ops_1g_copper,
  1948. .phy_addr_base = 0,
  1949. };
  1950. static const struct niu_phy_template phy_template_1g_rgmii = {
  1951. .ops = &phy_ops_1g_rgmii,
  1952. .phy_addr_base = 0,
  1953. };
  1954. static const struct niu_phy_template phy_template_10g_serdes = {
  1955. .ops = &phy_ops_10g_serdes,
  1956. .phy_addr_base = 0,
  1957. };
  1958. static int niu_atca_port_num[4] = {
  1959. 0, 0, 11, 10
  1960. };
  1961. static int serdes_init_10g_serdes(struct niu *np)
  1962. {
  1963. struct niu_link_config *lp = &np->link_config;
  1964. unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
  1965. u64 ctrl_val, test_cfg_val, sig, mask, val;
  1966. u64 reset_val;
  1967. switch (np->port) {
  1968. case 0:
  1969. reset_val = ENET_SERDES_RESET_0;
  1970. ctrl_reg = ENET_SERDES_0_CTRL_CFG;
  1971. test_cfg_reg = ENET_SERDES_0_TEST_CFG;
  1972. pll_cfg = ENET_SERDES_0_PLL_CFG;
  1973. break;
  1974. case 1:
  1975. reset_val = ENET_SERDES_RESET_1;
  1976. ctrl_reg = ENET_SERDES_1_CTRL_CFG;
  1977. test_cfg_reg = ENET_SERDES_1_TEST_CFG;
  1978. pll_cfg = ENET_SERDES_1_PLL_CFG;
  1979. break;
  1980. default:
  1981. return -EINVAL;
  1982. }
  1983. ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
  1984. ENET_SERDES_CTRL_SDET_1 |
  1985. ENET_SERDES_CTRL_SDET_2 |
  1986. ENET_SERDES_CTRL_SDET_3 |
  1987. (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
  1988. (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
  1989. (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
  1990. (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
  1991. (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
  1992. (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
  1993. (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
  1994. (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
  1995. test_cfg_val = 0;
  1996. if (lp->loopback_mode == LOOPBACK_PHY) {
  1997. test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
  1998. ENET_SERDES_TEST_MD_0_SHIFT) |
  1999. (ENET_TEST_MD_PAD_LOOPBACK <<
  2000. ENET_SERDES_TEST_MD_1_SHIFT) |
  2001. (ENET_TEST_MD_PAD_LOOPBACK <<
  2002. ENET_SERDES_TEST_MD_2_SHIFT) |
  2003. (ENET_TEST_MD_PAD_LOOPBACK <<
  2004. ENET_SERDES_TEST_MD_3_SHIFT));
  2005. }
  2006. esr_reset(np);
  2007. nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
  2008. nw64(ctrl_reg, ctrl_val);
  2009. nw64(test_cfg_reg, test_cfg_val);
  2010. /* Initialize all 4 lanes of the SERDES. */
  2011. for (i = 0; i < 4; i++) {
  2012. u32 rxtx_ctrl, glue0;
  2013. int err;
  2014. err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
  2015. if (err)
  2016. return err;
  2017. err = esr_read_glue0(np, i, &glue0);
  2018. if (err)
  2019. return err;
  2020. rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
  2021. rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
  2022. (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
  2023. glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
  2024. ESR_GLUE_CTRL0_THCNT |
  2025. ESR_GLUE_CTRL0_BLTIME);
  2026. glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
  2027. (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
  2028. (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
  2029. (BLTIME_300_CYCLES <<
  2030. ESR_GLUE_CTRL0_BLTIME_SHIFT));
  2031. err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
  2032. if (err)
  2033. return err;
  2034. err = esr_write_glue0(np, i, glue0);
  2035. if (err)
  2036. return err;
  2037. }
  2038. sig = nr64(ESR_INT_SIGNALS);
  2039. switch (np->port) {
  2040. case 0:
  2041. mask = ESR_INT_SIGNALS_P0_BITS;
  2042. val = (ESR_INT_SRDY0_P0 |
  2043. ESR_INT_DET0_P0 |
  2044. ESR_INT_XSRDY_P0 |
  2045. ESR_INT_XDP_P0_CH3 |
  2046. ESR_INT_XDP_P0_CH2 |
  2047. ESR_INT_XDP_P0_CH1 |
  2048. ESR_INT_XDP_P0_CH0);
  2049. break;
  2050. case 1:
  2051. mask = ESR_INT_SIGNALS_P1_BITS;
  2052. val = (ESR_INT_SRDY0_P1 |
  2053. ESR_INT_DET0_P1 |
  2054. ESR_INT_XSRDY_P1 |
  2055. ESR_INT_XDP_P1_CH3 |
  2056. ESR_INT_XDP_P1_CH2 |
  2057. ESR_INT_XDP_P1_CH1 |
  2058. ESR_INT_XDP_P1_CH0);
  2059. break;
  2060. default:
  2061. return -EINVAL;
  2062. }
  2063. if ((sig & mask) != val) {
  2064. int err;
  2065. err = serdes_init_1g_serdes(np);
  2066. if (!err) {
  2067. np->flags &= ~NIU_FLAGS_10G;
  2068. np->mac_xcvr = MAC_XCVR_PCS;
  2069. } else {
  2070. netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
  2071. np->port);
  2072. return -ENODEV;
  2073. }
  2074. }
  2075. return 0;
  2076. }
  2077. static int niu_determine_phy_disposition(struct niu *np)
  2078. {
  2079. struct niu_parent *parent = np->parent;
  2080. u8 plat_type = parent->plat_type;
  2081. const struct niu_phy_template *tp;
  2082. u32 phy_addr_off = 0;
  2083. if (plat_type == PLAT_TYPE_NIU) {
  2084. switch (np->flags &
  2085. (NIU_FLAGS_10G |
  2086. NIU_FLAGS_FIBER |
  2087. NIU_FLAGS_XCVR_SERDES)) {
  2088. case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
  2089. /* 10G Serdes */
  2090. tp = &phy_template_niu_10g_serdes;
  2091. break;
  2092. case NIU_FLAGS_XCVR_SERDES:
  2093. /* 1G Serdes */
  2094. tp = &phy_template_niu_1g_serdes;
  2095. break;
  2096. case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
  2097. /* 10G Fiber */
  2098. default:
  2099. if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
  2100. tp = &phy_template_niu_10g_hotplug;
  2101. if (np->port == 0)
  2102. phy_addr_off = 8;
  2103. if (np->port == 1)
  2104. phy_addr_off = 12;
  2105. } else {
  2106. tp = &phy_template_niu_10g_fiber;
  2107. phy_addr_off += np->port;
  2108. }
  2109. break;
  2110. }
  2111. } else {
  2112. switch (np->flags &
  2113. (NIU_FLAGS_10G |
  2114. NIU_FLAGS_FIBER |
  2115. NIU_FLAGS_XCVR_SERDES)) {
  2116. case 0:
  2117. /* 1G copper */
  2118. tp = &phy_template_1g_copper;
  2119. if (plat_type == PLAT_TYPE_VF_P0)
  2120. phy_addr_off = 10;
  2121. else if (plat_type == PLAT_TYPE_VF_P1)
  2122. phy_addr_off = 26;
  2123. phy_addr_off += (np->port ^ 0x3);
  2124. break;
  2125. case NIU_FLAGS_10G:
  2126. /* 10G copper */
  2127. tp = &phy_template_10g_copper;
  2128. break;
  2129. case NIU_FLAGS_FIBER:
  2130. /* 1G fiber */
  2131. tp = &phy_template_1g_fiber;
  2132. break;
  2133. case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
  2134. /* 10G fiber */
  2135. tp = &phy_template_10g_fiber;
  2136. if (plat_type == PLAT_TYPE_VF_P0 ||
  2137. plat_type == PLAT_TYPE_VF_P1)
  2138. phy_addr_off = 8;
  2139. phy_addr_off += np->port;
  2140. if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
  2141. tp = &phy_template_10g_fiber_hotplug;
  2142. if (np->port == 0)
  2143. phy_addr_off = 8;
  2144. if (np->port == 1)
  2145. phy_addr_off = 12;
  2146. }
  2147. break;
  2148. case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
  2149. case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
  2150. case NIU_FLAGS_XCVR_SERDES:
  2151. switch(np->port) {
  2152. case 0:
  2153. case 1:
  2154. tp = &phy_template_10g_serdes;
  2155. break;
  2156. case 2:
  2157. case 3:
  2158. tp = &phy_template_1g_rgmii;
  2159. break;
  2160. default:
  2161. return -EINVAL;
  2162. break;
  2163. }
  2164. phy_addr_off = niu_atca_port_num[np->port];
  2165. break;
  2166. default:
  2167. return -EINVAL;
  2168. }
  2169. }
  2170. np->phy_ops = tp->ops;
  2171. np->phy_addr = tp->phy_addr_base + phy_addr_off;
  2172. return 0;
  2173. }
  2174. static int niu_init_link(struct niu *np)
  2175. {
  2176. struct niu_parent *parent = np->parent;
  2177. int err, ignore;
  2178. if (parent->plat_type == PLAT_TYPE_NIU) {
  2179. err = niu_xcvr_init(np);
  2180. if (err)
  2181. return err;
  2182. msleep(200);
  2183. }
  2184. err = niu_serdes_init(np);
  2185. if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
  2186. return err;
  2187. msleep(200);
  2188. err = niu_xcvr_init(np);
  2189. if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
  2190. niu_link_status(np, &ignore);
  2191. return 0;
  2192. }
  2193. static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
  2194. {
  2195. u16 reg0 = addr[4] << 8 | addr[5];
  2196. u16 reg1 = addr[2] << 8 | addr[3];
  2197. u16 reg2 = addr[0] << 8 | addr[1];
  2198. if (np->flags & NIU_FLAGS_XMAC) {
  2199. nw64_mac(XMAC_ADDR0, reg0);
  2200. nw64_mac(XMAC_ADDR1, reg1);
  2201. nw64_mac(XMAC_ADDR2, reg2);
  2202. } else {
  2203. nw64_mac(BMAC_ADDR0, reg0);
  2204. nw64_mac(BMAC_ADDR1, reg1);
  2205. nw64_mac(BMAC_ADDR2, reg2);
  2206. }
  2207. }
  2208. static int niu_num_alt_addr(struct niu *np)
  2209. {
  2210. if (np->flags & NIU_FLAGS_XMAC)
  2211. return XMAC_NUM_ALT_ADDR;
  2212. else
  2213. return BMAC_NUM_ALT_ADDR;
  2214. }
  2215. static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
  2216. {
  2217. u16 reg0 = addr[4] << 8 | addr[5];
  2218. u16 reg1 = addr[2] << 8 | addr[3];
  2219. u16 reg2 = addr[0] << 8 | addr[1];
  2220. if (index >= niu_num_alt_addr(np))
  2221. return -EINVAL;
  2222. if (np->flags & NIU_FLAGS_XMAC) {
  2223. nw64_mac(XMAC_ALT_ADDR0(index), reg0);
  2224. nw64_mac(XMAC_ALT_ADDR1(index), reg1);
  2225. nw64_mac(XMAC_ALT_ADDR2(index), reg2);
  2226. } else {
  2227. nw64_mac(BMAC_ALT_ADDR0(index), reg0);
  2228. nw64_mac(BMAC_ALT_ADDR1(index), reg1);
  2229. nw64_mac(BMAC_ALT_ADDR2(index), reg2);
  2230. }
  2231. return 0;
  2232. }
  2233. static int niu_enable_alt_mac(struct niu *np, int index, int on)
  2234. {
  2235. unsigned long reg;
  2236. u64 val, mask;
  2237. if (index >= niu_num_alt_addr(np))
  2238. return -EINVAL;
  2239. if (np->flags & NIU_FLAGS_XMAC) {
  2240. reg = XMAC_ADDR_CMPEN;
  2241. mask = 1 << index;
  2242. } else {
  2243. reg = BMAC_ADDR_CMPEN;
  2244. mask = 1 << (index + 1);
  2245. }
  2246. val = nr64_mac(reg);
  2247. if (on)
  2248. val |= mask;
  2249. else
  2250. val &= ~mask;
  2251. nw64_mac(reg, val);
  2252. return 0;
  2253. }
  2254. static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
  2255. int num, int mac_pref)
  2256. {
  2257. u64 val = nr64_mac(reg);
  2258. val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
  2259. val |= num;
  2260. if (mac_pref)
  2261. val |= HOST_INFO_MPR;
  2262. nw64_mac(reg, val);
  2263. }
  2264. static int __set_rdc_table_num(struct niu *np,
  2265. int xmac_index, int bmac_index,
  2266. int rdc_table_num, int mac_pref)
  2267. {
  2268. unsigned long reg;
  2269. if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
  2270. return -EINVAL;
  2271. if (np->flags & NIU_FLAGS_XMAC)
  2272. reg = XMAC_HOST_INFO(xmac_index);
  2273. else
  2274. reg = BMAC_HOST_INFO(bmac_index);
  2275. __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
  2276. return 0;
  2277. }
  2278. static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
  2279. int mac_pref)
  2280. {
  2281. return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
  2282. }
  2283. static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
  2284. int mac_pref)
  2285. {
  2286. return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
  2287. }
  2288. static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
  2289. int table_num, int mac_pref)
  2290. {
  2291. if (idx >= niu_num_alt_addr(np))
  2292. return -EINVAL;
  2293. return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
  2294. }
  2295. static u64 vlan_entry_set_parity(u64 reg_val)
  2296. {
  2297. u64 port01_mask;
  2298. u64 port23_mask;
  2299. port01_mask = 0x00ff;
  2300. port23_mask = 0xff00;
  2301. if (hweight64(reg_val & port01_mask) & 1)
  2302. reg_val |= ENET_VLAN_TBL_PARITY0;
  2303. else
  2304. reg_val &= ~ENET_VLAN_TBL_PARITY0;
  2305. if (hweight64(reg_val & port23_mask) & 1)
  2306. reg_val |= ENET_VLAN_TBL_PARITY1;
  2307. else
  2308. reg_val &= ~ENET_VLAN_TBL_PARITY1;
  2309. return reg_val;
  2310. }
  2311. static void vlan_tbl_write(struct niu *np, unsigned long index,
  2312. int port, int vpr, int rdc_table)
  2313. {
  2314. u64 reg_val = nr64(ENET_VLAN_TBL(index));
  2315. reg_val &= ~((ENET_VLAN_TBL_VPR |
  2316. ENET_VLAN_TBL_VLANRDCTBLN) <<
  2317. ENET_VLAN_TBL_SHIFT(port));
  2318. if (vpr)
  2319. reg_val |= (ENET_VLAN_TBL_VPR <<
  2320. ENET_VLAN_TBL_SHIFT(port));
  2321. reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
  2322. reg_val = vlan_entry_set_parity(reg_val);
  2323. nw64(ENET_VLAN_TBL(index), reg_val);
  2324. }
  2325. static void vlan_tbl_clear(struct niu *np)
  2326. {
  2327. int i;
  2328. for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
  2329. nw64(ENET_VLAN_TBL(i), 0);
  2330. }
  2331. static int tcam_wait_bit(struct niu *np, u64 bit)
  2332. {
  2333. int limit = 1000;
  2334. while (--limit > 0) {
  2335. if (nr64(TCAM_CTL) & bit)
  2336. break;
  2337. udelay(1);
  2338. }
  2339. if (limit <= 0)
  2340. return -ENODEV;
  2341. return 0;
  2342. }
  2343. static int tcam_flush(struct niu *np, int index)
  2344. {
  2345. nw64(TCAM_KEY_0, 0x00);
  2346. nw64(TCAM_KEY_MASK_0, 0xff);
  2347. nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
  2348. return tcam_wait_bit(np, TCAM_CTL_STAT);
  2349. }
  2350. #if 0
  2351. static int tcam_read(struct niu *np, int index,
  2352. u64 *key, u64 *mask)
  2353. {
  2354. int err;
  2355. nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
  2356. err = tcam_wait_bit(np, TCAM_CTL_STAT);
  2357. if (!err) {
  2358. key[0] = nr64(TCAM_KEY_0);
  2359. key[1] = nr64(TCAM_KEY_1);
  2360. key[2] = nr64(TCAM_KEY_2);
  2361. key[3] = nr64(TCAM_KEY_3);
  2362. mask[0] = nr64(TCAM_KEY_MASK_0);
  2363. mask[1] = nr64(TCAM_KEY_MASK_1);
  2364. mask[2] = nr64(TCAM_KEY_MASK_2);
  2365. mask[3] = nr64(TCAM_KEY_MASK_3);
  2366. }
  2367. return err;
  2368. }
  2369. #endif
  2370. static int tcam_write(struct niu *np, int index,
  2371. u64 *key, u64 *mask)
  2372. {
  2373. nw64(TCAM_KEY_0, key[0]);
  2374. nw64(TCAM_KEY_1, key[1]);
  2375. nw64(TCAM_KEY_2, key[2]);
  2376. nw64(TCAM_KEY_3, key[3]);
  2377. nw64(TCAM_KEY_MASK_0, mask[0]);
  2378. nw64(TCAM_KEY_MASK_1, mask[1]);
  2379. nw64(TCAM_KEY_MASK_2, mask[2]);
  2380. nw64(TCAM_KEY_MASK_3, mask[3]);
  2381. nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
  2382. return tcam_wait_bit(np, TCAM_CTL_STAT);
  2383. }
  2384. #if 0
  2385. static int tcam_assoc_read(struct niu *np, int index, u64 *data)
  2386. {
  2387. int err;
  2388. nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
  2389. err = tcam_wait_bit(np, TCAM_CTL_STAT);
  2390. if (!err)
  2391. *data = nr64(TCAM_KEY_1);
  2392. return err;
  2393. }
  2394. #endif
  2395. static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
  2396. {
  2397. nw64(TCAM_KEY_1, assoc_data);
  2398. nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
  2399. return tcam_wait_bit(np, TCAM_CTL_STAT);
  2400. }
  2401. static void tcam_enable(struct niu *np, int on)
  2402. {
  2403. u64 val = nr64(FFLP_CFG_1);
  2404. if (on)
  2405. val &= ~FFLP_CFG_1_TCAM_DIS;
  2406. else
  2407. val |= FFLP_CFG_1_TCAM_DIS;
  2408. nw64(FFLP_CFG_1, val);
  2409. }
  2410. static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
  2411. {
  2412. u64 val = nr64(FFLP_CFG_1);
  2413. val &= ~(FFLP_CFG_1_FFLPINITDONE |
  2414. FFLP_CFG_1_CAMLAT |
  2415. FFLP_CFG_1_CAMRATIO);
  2416. val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
  2417. val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
  2418. nw64(FFLP_CFG_1, val);
  2419. val = nr64(FFLP_CFG_1);
  2420. val |= FFLP_CFG_1_FFLPINITDONE;
  2421. nw64(FFLP_CFG_1, val);
  2422. }
  2423. static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
  2424. int on)
  2425. {
  2426. unsigned long reg;
  2427. u64 val;
  2428. if (class < CLASS_CODE_ETHERTYPE1 ||
  2429. class > CLASS_CODE_ETHERTYPE2)
  2430. return -EINVAL;
  2431. reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
  2432. val = nr64(reg);
  2433. if (on)
  2434. val |= L2_CLS_VLD;
  2435. else
  2436. val &= ~L2_CLS_VLD;
  2437. nw64(reg, val);
  2438. return 0;
  2439. }
  2440. #if 0
  2441. static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
  2442. u64 ether_type)
  2443. {
  2444. unsigned long reg;
  2445. u64 val;
  2446. if (class < CLASS_CODE_ETHERTYPE1 ||
  2447. class > CLASS_CODE_ETHERTYPE2 ||
  2448. (ether_type & ~(u64)0xffff) != 0)
  2449. return -EINVAL;
  2450. reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
  2451. val = nr64(reg);
  2452. val &= ~L2_CLS_ETYPE;
  2453. val |= (ether_type << L2_CLS_ETYPE_SHIFT);
  2454. nw64(reg, val);
  2455. return 0;
  2456. }
  2457. #endif
  2458. static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
  2459. int on)
  2460. {
  2461. unsigned long reg;
  2462. u64 val;
  2463. if (class < CLASS_CODE_USER_PROG1 ||
  2464. class > CLASS_CODE_USER_PROG4)
  2465. return -EINVAL;
  2466. reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
  2467. val = nr64(reg);
  2468. if (on)
  2469. val |= L3_CLS_VALID;
  2470. else
  2471. val &= ~L3_CLS_VALID;
  2472. nw64(reg, val);
  2473. return 0;
  2474. }
  2475. static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
  2476. int ipv6, u64 protocol_id,
  2477. u64 tos_mask, u64 tos_val)
  2478. {
  2479. unsigned long reg;
  2480. u64 val;
  2481. if (class < CLASS_CODE_USER_PROG1 ||
  2482. class > CLASS_CODE_USER_PROG4 ||
  2483. (protocol_id & ~(u64)0xff) != 0 ||
  2484. (tos_mask & ~(u64)0xff) != 0 ||
  2485. (tos_val & ~(u64)0xff) != 0)
  2486. return -EINVAL;
  2487. reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
  2488. val = nr64(reg);
  2489. val &= ~(L3_CLS_IPVER | L3_CLS_PID |
  2490. L3_CLS_TOSMASK | L3_CLS_TOS);
  2491. if (ipv6)
  2492. val |= L3_CLS_IPVER;
  2493. val |= (protocol_id << L3_CLS_PID_SHIFT);
  2494. val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
  2495. val |= (tos_val << L3_CLS_TOS_SHIFT);
  2496. nw64(reg, val);
  2497. return 0;
  2498. }
  2499. static int tcam_early_init(struct niu *np)
  2500. {
  2501. unsigned long i;
  2502. int err;
  2503. tcam_enable(np, 0);
  2504. tcam_set_lat_and_ratio(np,
  2505. DEFAULT_TCAM_LATENCY,
  2506. DEFAULT_TCAM_ACCESS_RATIO);
  2507. for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
  2508. err = tcam_user_eth_class_enable(np, i, 0);
  2509. if (err)
  2510. return err;
  2511. }
  2512. for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
  2513. err = tcam_user_ip_class_enable(np, i, 0);
  2514. if (err)
  2515. return err;
  2516. }
  2517. return 0;
  2518. }
  2519. static int tcam_flush_all(struct niu *np)
  2520. {
  2521. unsigned long i;
  2522. for (i = 0; i < np->parent->tcam_num_entries; i++) {
  2523. int err = tcam_flush(np, i);
  2524. if (err)
  2525. return err;
  2526. }
  2527. return 0;
  2528. }
  2529. static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
  2530. {
  2531. return ((u64)index | (num_entries == 1 ?
  2532. HASH_TBL_ADDR_AUTOINC : 0));
  2533. }
  2534. #if 0
  2535. static int hash_read(struct niu *np, unsigned long partition,
  2536. unsigned long index, unsigned long num_entries,
  2537. u64 *data)
  2538. {
  2539. u64 val = hash_addr_regval(index, num_entries);
  2540. unsigned long i;
  2541. if (partition >= FCRAM_NUM_PARTITIONS ||
  2542. index + num_entries > FCRAM_SIZE)
  2543. return -EINVAL;
  2544. nw64(HASH_TBL_ADDR(partition), val);
  2545. for (i = 0; i < num_entries; i++)
  2546. data[i] = nr64(HASH_TBL_DATA(partition));
  2547. return 0;
  2548. }
  2549. #endif
  2550. static int hash_write(struct niu *np, unsigned long partition,
  2551. unsigned long index, unsigned long num_entries,
  2552. u64 *data)
  2553. {
  2554. u64 val = hash_addr_regval(index, num_entries);
  2555. unsigned long i;
  2556. if (partition >= FCRAM_NUM_PARTITIONS ||
  2557. index + (num_entries * 8) > FCRAM_SIZE)
  2558. return -EINVAL;
  2559. nw64(HASH_TBL_ADDR(partition), val);
  2560. for (i = 0; i < num_entries; i++)
  2561. nw64(HASH_TBL_DATA(partition), data[i]);
  2562. return 0;
  2563. }
  2564. static void fflp_reset(struct niu *np)
  2565. {
  2566. u64 val;
  2567. nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
  2568. udelay(10);
  2569. nw64(FFLP_CFG_1, 0);
  2570. val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
  2571. nw64(FFLP_CFG_1, val);
  2572. }
  2573. static void fflp_set_timings(struct niu *np)
  2574. {
  2575. u64 val = nr64(FFLP_CFG_1);
  2576. val &= ~FFLP_CFG_1_FFLPINITDONE;
  2577. val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
  2578. nw64(FFLP_CFG_1, val);
  2579. val = nr64(FFLP_CFG_1);
  2580. val |= FFLP_CFG_1_FFLPINITDONE;
  2581. nw64(FFLP_CFG_1, val);
  2582. val = nr64(FCRAM_REF_TMR);
  2583. val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
  2584. val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
  2585. val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
  2586. nw64(FCRAM_REF_TMR, val);
  2587. }
  2588. static int fflp_set_partition(struct niu *np, u64 partition,
  2589. u64 mask, u64 base, int enable)
  2590. {
  2591. unsigned long reg;
  2592. u64 val;
  2593. if (partition >= FCRAM_NUM_PARTITIONS ||
  2594. (mask & ~(u64)0x1f) != 0 ||
  2595. (base & ~(u64)0x1f) != 0)
  2596. return -EINVAL;
  2597. reg = FLW_PRT_SEL(partition);
  2598. val = nr64(reg);
  2599. val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
  2600. val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
  2601. val |= (base << FLW_PRT_SEL_BASE_SHIFT);
  2602. if (enable)
  2603. val |= FLW_PRT_SEL_EXT;
  2604. nw64(reg, val);
  2605. return 0;
  2606. }
  2607. static int fflp_disable_all_partitions(struct niu *np)
  2608. {
  2609. unsigned long i;
  2610. for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
  2611. int err = fflp_set_partition(np, 0, 0, 0, 0);
  2612. if (err)
  2613. return err;
  2614. }
  2615. return 0;
  2616. }
  2617. static void fflp_llcsnap_enable(struct niu *np, int on)
  2618. {
  2619. u64 val = nr64(FFLP_CFG_1);
  2620. if (on)
  2621. val |= FFLP_CFG_1_LLCSNAP;
  2622. else
  2623. val &= ~FFLP_CFG_1_LLCSNAP;
  2624. nw64(FFLP_CFG_1, val);
  2625. }
  2626. static void fflp_errors_enable(struct niu *np, int on)
  2627. {
  2628. u64 val = nr64(FFLP_CFG_1);
  2629. if (on)
  2630. val &= ~FFLP_CFG_1_ERRORDIS;
  2631. else
  2632. val |= FFLP_CFG_1_ERRORDIS;
  2633. nw64(FFLP_CFG_1, val);
  2634. }
  2635. static int fflp_hash_clear(struct niu *np)
  2636. {
  2637. struct fcram_hash_ipv4 ent;
  2638. unsigned long i;
  2639. /* IPV4 hash entry with valid bit clear, rest is don't care. */
  2640. memset(&ent, 0, sizeof(ent));
  2641. ent.header = HASH_HEADER_EXT;
  2642. for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
  2643. int err = hash_write(np, 0, i, 1, (u64 *) &ent);
  2644. if (err)
  2645. return err;
  2646. }
  2647. return 0;
  2648. }
  2649. static int fflp_early_init(struct niu *np)
  2650. {
  2651. struct niu_parent *parent;
  2652. unsigned long flags;
  2653. int err;
  2654. niu_lock_parent(np, flags);
  2655. parent = np->parent;
  2656. err = 0;
  2657. if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
  2658. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  2659. fflp_reset(np);
  2660. fflp_set_timings(np);
  2661. err = fflp_disable_all_partitions(np);
  2662. if (err) {
  2663. netif_printk(np, probe, KERN_DEBUG, np->dev,
  2664. "fflp_disable_all_partitions failed, err=%d\n",
  2665. err);
  2666. goto out;
  2667. }
  2668. }
  2669. err = tcam_early_init(np);
  2670. if (err) {
  2671. netif_printk(np, probe, KERN_DEBUG, np->dev,
  2672. "tcam_early_init failed, err=%d\n", err);
  2673. goto out;
  2674. }
  2675. fflp_llcsnap_enable(np, 1);
  2676. fflp_errors_enable(np, 0);
  2677. nw64(H1POLY, 0);
  2678. nw64(H2POLY, 0);
  2679. err = tcam_flush_all(np);
  2680. if (err) {
  2681. netif_printk(np, probe, KERN_DEBUG, np->dev,
  2682. "tcam_flush_all failed, err=%d\n", err);
  2683. goto out;
  2684. }
  2685. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  2686. err = fflp_hash_clear(np);
  2687. if (err) {
  2688. netif_printk(np, probe, KERN_DEBUG, np->dev,
  2689. "fflp_hash_clear failed, err=%d\n",
  2690. err);
  2691. goto out;
  2692. }
  2693. }
  2694. vlan_tbl_clear(np);
  2695. parent->flags |= PARENT_FLGS_CLS_HWINIT;
  2696. }
  2697. out:
  2698. niu_unlock_parent(np, flags);
  2699. return err;
  2700. }
  2701. static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
  2702. {
  2703. if (class_code < CLASS_CODE_USER_PROG1 ||
  2704. class_code > CLASS_CODE_SCTP_IPV6)
  2705. return -EINVAL;
  2706. nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
  2707. return 0;
  2708. }
  2709. static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
  2710. {
  2711. if (class_code < CLASS_CODE_USER_PROG1 ||
  2712. class_code > CLASS_CODE_SCTP_IPV6)
  2713. return -EINVAL;
  2714. nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
  2715. return 0;
  2716. }
  2717. /* Entries for the ports are interleaved in the TCAM */
  2718. static u16 tcam_get_index(struct niu *np, u16 idx)
  2719. {
  2720. /* One entry reserved for IP fragment rule */
  2721. if (idx >= (np->clas.tcam_sz - 1))
  2722. idx = 0;
  2723. return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
  2724. }
  2725. static u16 tcam_get_size(struct niu *np)
  2726. {
  2727. /* One entry reserved for IP fragment rule */
  2728. return np->clas.tcam_sz - 1;
  2729. }
  2730. static u16 tcam_get_valid_entry_cnt(struct niu *np)
  2731. {
  2732. /* One entry reserved for IP fragment rule */
  2733. return np->clas.tcam_valid_entries - 1;
  2734. }
  2735. static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
  2736. u32 offset, u32 size)
  2737. {
  2738. int i = skb_shinfo(skb)->nr_frags;
  2739. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2740. frag->page = page;
  2741. frag->page_offset = offset;
  2742. frag->size = size;
  2743. skb->len += size;
  2744. skb->data_len += size;
  2745. skb->truesize += size;
  2746. skb_shinfo(skb)->nr_frags = i + 1;
  2747. }
  2748. static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
  2749. {
  2750. a >>= PAGE_SHIFT;
  2751. a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
  2752. return (a & (MAX_RBR_RING_SIZE - 1));
  2753. }
  2754. static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
  2755. struct page ***link)
  2756. {
  2757. unsigned int h = niu_hash_rxaddr(rp, addr);
  2758. struct page *p, **pp;
  2759. addr &= PAGE_MASK;
  2760. pp = &rp->rxhash[h];
  2761. for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
  2762. if (p->index == addr) {
  2763. *link = pp;
  2764. break;
  2765. }
  2766. }
  2767. return p;
  2768. }
  2769. static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
  2770. {
  2771. unsigned int h = niu_hash_rxaddr(rp, base);
  2772. page->index = base;
  2773. page->mapping = (struct address_space *) rp->rxhash[h];
  2774. rp->rxhash[h] = page;
  2775. }
  2776. static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
  2777. gfp_t mask, int start_index)
  2778. {
  2779. struct page *page;
  2780. u64 addr;
  2781. int i;
  2782. page = alloc_page(mask);
  2783. if (!page)
  2784. return -ENOMEM;
  2785. addr = np->ops->map_page(np->device, page, 0,
  2786. PAGE_SIZE, DMA_FROM_DEVICE);
  2787. niu_hash_page(rp, page, addr);
  2788. if (rp->rbr_blocks_per_page > 1)
  2789. atomic_add(rp->rbr_blocks_per_page - 1,
  2790. &compound_head(page)->_count);
  2791. for (i = 0; i < rp->rbr_blocks_per_page; i++) {
  2792. __le32 *rbr = &rp->rbr[start_index + i];
  2793. *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
  2794. addr += rp->rbr_block_size;
  2795. }
  2796. return 0;
  2797. }
  2798. static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
  2799. {
  2800. int index = rp->rbr_index;
  2801. rp->rbr_pending++;
  2802. if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
  2803. int err = niu_rbr_add_page(np, rp, mask, index);
  2804. if (unlikely(err)) {
  2805. rp->rbr_pending--;
  2806. return;
  2807. }
  2808. rp->rbr_index += rp->rbr_blocks_per_page;
  2809. BUG_ON(rp->rbr_index > rp->rbr_table_size);
  2810. if (rp->rbr_index == rp->rbr_table_size)
  2811. rp->rbr_index = 0;
  2812. if (rp->rbr_pending >= rp->rbr_kick_thresh) {
  2813. nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
  2814. rp->rbr_pending = 0;
  2815. }
  2816. }
  2817. }
  2818. static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
  2819. {
  2820. unsigned int index = rp->rcr_index;
  2821. int num_rcr = 0;
  2822. rp->rx_dropped++;
  2823. while (1) {
  2824. struct page *page, **link;
  2825. u64 addr, val;
  2826. u32 rcr_size;
  2827. num_rcr++;
  2828. val = le64_to_cpup(&rp->rcr[index]);
  2829. addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
  2830. RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
  2831. page = niu_find_rxpage(rp, addr, &link);
  2832. rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
  2833. RCR_ENTRY_PKTBUFSZ_SHIFT];
  2834. if ((page->index + PAGE_SIZE) - rcr_size == addr) {
  2835. *link = (struct page *) page->mapping;
  2836. np->ops->unmap_page(np->device, page->index,
  2837. PAGE_SIZE, DMA_FROM_DEVICE);
  2838. page->index = 0;
  2839. page->mapping = NULL;
  2840. __free_page(page);
  2841. rp->rbr_refill_pending++;
  2842. }
  2843. index = NEXT_RCR(rp, index);
  2844. if (!(val & RCR_ENTRY_MULTI))
  2845. break;
  2846. }
  2847. rp->rcr_index = index;
  2848. return num_rcr;
  2849. }
  2850. static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
  2851. struct rx_ring_info *rp)
  2852. {
  2853. unsigned int index = rp->rcr_index;
  2854. struct rx_pkt_hdr1 *rh;
  2855. struct sk_buff *skb;
  2856. int len, num_rcr;
  2857. skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
  2858. if (unlikely(!skb))
  2859. return niu_rx_pkt_ignore(np, rp);
  2860. num_rcr = 0;
  2861. while (1) {
  2862. struct page *page, **link;
  2863. u32 rcr_size, append_size;
  2864. u64 addr, val, off;
  2865. num_rcr++;
  2866. val = le64_to_cpup(&rp->rcr[index]);
  2867. len = (val & RCR_ENTRY_L2_LEN) >>
  2868. RCR_ENTRY_L2_LEN_SHIFT;
  2869. len -= ETH_FCS_LEN;
  2870. addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
  2871. RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
  2872. page = niu_find_rxpage(rp, addr, &link);
  2873. rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
  2874. RCR_ENTRY_PKTBUFSZ_SHIFT];
  2875. off = addr & ~PAGE_MASK;
  2876. append_size = rcr_size;
  2877. if (num_rcr == 1) {
  2878. int ptype;
  2879. ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
  2880. if ((ptype == RCR_PKT_TYPE_TCP ||
  2881. ptype == RCR_PKT_TYPE_UDP) &&
  2882. !(val & (RCR_ENTRY_NOPORT |
  2883. RCR_ENTRY_ERROR)))
  2884. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2885. else
  2886. skb->ip_summed = CHECKSUM_NONE;
  2887. } else if (!(val & RCR_ENTRY_MULTI))
  2888. append_size = len - skb->len;
  2889. niu_rx_skb_append(skb, page, off, append_size);
  2890. if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
  2891. *link = (struct page *) page->mapping;
  2892. np->ops->unmap_page(np->device, page->index,
  2893. PAGE_SIZE, DMA_FROM_DEVICE);
  2894. page->index = 0;
  2895. page->mapping = NULL;
  2896. rp->rbr_refill_pending++;
  2897. } else
  2898. get_page(page);
  2899. index = NEXT_RCR(rp, index);
  2900. if (!(val & RCR_ENTRY_MULTI))
  2901. break;
  2902. }
  2903. rp->rcr_index = index;
  2904. len += sizeof(*rh);
  2905. len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
  2906. __pskb_pull_tail(skb, len);
  2907. rh = (struct rx_pkt_hdr1 *) skb->data;
  2908. if (np->dev->features & NETIF_F_RXHASH)
  2909. skb->rxhash = ((u32)rh->hashval2_0 << 24 |
  2910. (u32)rh->hashval2_1 << 16 |
  2911. (u32)rh->hashval1_1 << 8 |
  2912. (u32)rh->hashval1_2 << 0);
  2913. skb_pull(skb, sizeof(*rh));
  2914. rp->rx_packets++;
  2915. rp->rx_bytes += skb->len;
  2916. skb->protocol = eth_type_trans(skb, np->dev);
  2917. skb_record_rx_queue(skb, rp->rx_channel);
  2918. napi_gro_receive(napi, skb);
  2919. return num_rcr;
  2920. }
  2921. static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
  2922. {
  2923. int blocks_per_page = rp->rbr_blocks_per_page;
  2924. int err, index = rp->rbr_index;
  2925. err = 0;
  2926. while (index < (rp->rbr_table_size - blocks_per_page)) {
  2927. err = niu_rbr_add_page(np, rp, mask, index);
  2928. if (err)
  2929. break;
  2930. index += blocks_per_page;
  2931. }
  2932. rp->rbr_index = index;
  2933. return err;
  2934. }
  2935. static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
  2936. {
  2937. int i;
  2938. for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
  2939. struct page *page;
  2940. page = rp->rxhash[i];
  2941. while (page) {
  2942. struct page *next = (struct page *) page->mapping;
  2943. u64 base = page->index;
  2944. np->ops->unmap_page(np->device, base, PAGE_SIZE,
  2945. DMA_FROM_DEVICE);
  2946. page->index = 0;
  2947. page->mapping = NULL;
  2948. __free_page(page);
  2949. page = next;
  2950. }
  2951. }
  2952. for (i = 0; i < rp->rbr_table_size; i++)
  2953. rp->rbr[i] = cpu_to_le32(0);
  2954. rp->rbr_index = 0;
  2955. }
  2956. static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
  2957. {
  2958. struct tx_buff_info *tb = &rp->tx_buffs[idx];
  2959. struct sk_buff *skb = tb->skb;
  2960. struct tx_pkt_hdr *tp;
  2961. u64 tx_flags;
  2962. int i, len;
  2963. tp = (struct tx_pkt_hdr *) skb->data;
  2964. tx_flags = le64_to_cpup(&tp->flags);
  2965. rp->tx_packets++;
  2966. rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
  2967. ((tx_flags & TXHDR_PAD) / 2));
  2968. len = skb_headlen(skb);
  2969. np->ops->unmap_single(np->device, tb->mapping,
  2970. len, DMA_TO_DEVICE);
  2971. if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
  2972. rp->mark_pending--;
  2973. tb->skb = NULL;
  2974. do {
  2975. idx = NEXT_TX(rp, idx);
  2976. len -= MAX_TX_DESC_LEN;
  2977. } while (len > 0);
  2978. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2979. tb = &rp->tx_buffs[idx];
  2980. BUG_ON(tb->skb != NULL);
  2981. np->ops->unmap_page(np->device, tb->mapping,
  2982. skb_shinfo(skb)->frags[i].size,
  2983. DMA_TO_DEVICE);
  2984. idx = NEXT_TX(rp, idx);
  2985. }
  2986. dev_kfree_skb(skb);
  2987. return idx;
  2988. }
  2989. #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
  2990. static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
  2991. {
  2992. struct netdev_queue *txq;
  2993. u16 pkt_cnt, tmp;
  2994. int cons, index;
  2995. u64 cs;
  2996. index = (rp - np->tx_rings);
  2997. txq = netdev_get_tx_queue(np->dev, index);
  2998. cs = rp->tx_cs;
  2999. if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
  3000. goto out;
  3001. tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
  3002. pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
  3003. (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
  3004. rp->last_pkt_cnt = tmp;
  3005. cons = rp->cons;
  3006. netif_printk(np, tx_done, KERN_DEBUG, np->dev,
  3007. "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
  3008. while (pkt_cnt--)
  3009. cons = release_tx_packet(np, rp, cons);
  3010. rp->cons = cons;
  3011. smp_mb();
  3012. out:
  3013. if (unlikely(netif_tx_queue_stopped(txq) &&
  3014. (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
  3015. __netif_tx_lock(txq, smp_processor_id());
  3016. if (netif_tx_queue_stopped(txq) &&
  3017. (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
  3018. netif_tx_wake_queue(txq);
  3019. __netif_tx_unlock(txq);
  3020. }
  3021. }
  3022. static inline void niu_sync_rx_discard_stats(struct niu *np,
  3023. struct rx_ring_info *rp,
  3024. const int limit)
  3025. {
  3026. /* This elaborate scheme is needed for reading the RX discard
  3027. * counters, as they are only 16-bit and can overflow quickly,
  3028. * and because the overflow indication bit is not usable as
  3029. * the counter value does not wrap, but remains at max value
  3030. * 0xFFFF.
  3031. *
  3032. * In theory and in practice counters can be lost in between
  3033. * reading nr64() and clearing the counter nw64(). For this
  3034. * reason, the number of counter clearings nw64() is
  3035. * limited/reduced though the limit parameter.
  3036. */
  3037. int rx_channel = rp->rx_channel;
  3038. u32 misc, wred;
  3039. /* RXMISC (Receive Miscellaneous Discard Count), covers the
  3040. * following discard events: IPP (Input Port Process),
  3041. * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
  3042. * Block Ring) prefetch buffer is empty.
  3043. */
  3044. misc = nr64(RXMISC(rx_channel));
  3045. if (unlikely((misc & RXMISC_COUNT) > limit)) {
  3046. nw64(RXMISC(rx_channel), 0);
  3047. rp->rx_errors += misc & RXMISC_COUNT;
  3048. if (unlikely(misc & RXMISC_OFLOW))
  3049. dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
  3050. rx_channel);
  3051. netif_printk(np, rx_err, KERN_DEBUG, np->dev,
  3052. "rx-%d: MISC drop=%u over=%u\n",
  3053. rx_channel, misc, misc-limit);
  3054. }
  3055. /* WRED (Weighted Random Early Discard) by hardware */
  3056. wred = nr64(RED_DIS_CNT(rx_channel));
  3057. if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
  3058. nw64(RED_DIS_CNT(rx_channel), 0);
  3059. rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
  3060. if (unlikely(wred & RED_DIS_CNT_OFLOW))
  3061. dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
  3062. netif_printk(np, rx_err, KERN_DEBUG, np->dev,
  3063. "rx-%d: WRED drop=%u over=%u\n",
  3064. rx_channel, wred, wred-limit);
  3065. }
  3066. }
  3067. static int niu_rx_work(struct napi_struct *napi, struct niu *np,
  3068. struct rx_ring_info *rp, int budget)
  3069. {
  3070. int qlen, rcr_done = 0, work_done = 0;
  3071. struct rxdma_mailbox *mbox = rp->mbox;
  3072. u64 stat;
  3073. #if 1
  3074. stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
  3075. qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
  3076. #else
  3077. stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
  3078. qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
  3079. #endif
  3080. mbox->rx_dma_ctl_stat = 0;
  3081. mbox->rcrstat_a = 0;
  3082. netif_printk(np, rx_status, KERN_DEBUG, np->dev,
  3083. "%s(chan[%d]), stat[%llx] qlen=%d\n",
  3084. __func__, rp->rx_channel, (unsigned long long)stat, qlen);
  3085. rcr_done = work_done = 0;
  3086. qlen = min(qlen, budget);
  3087. while (work_done < qlen) {
  3088. rcr_done += niu_process_rx_pkt(napi, np, rp);
  3089. work_done++;
  3090. }
  3091. if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
  3092. unsigned int i;
  3093. for (i = 0; i < rp->rbr_refill_pending; i++)
  3094. niu_rbr_refill(np, rp, GFP_ATOMIC);
  3095. rp->rbr_refill_pending = 0;
  3096. }
  3097. stat = (RX_DMA_CTL_STAT_MEX |
  3098. ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
  3099. ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
  3100. nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
  3101. /* Only sync discards stats when qlen indicate potential for drops */
  3102. if (qlen > 10)
  3103. niu_sync_rx_discard_stats(np, rp, 0x7FFF);
  3104. return work_done;
  3105. }
  3106. static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
  3107. {
  3108. u64 v0 = lp->v0;
  3109. u32 tx_vec = (v0 >> 32);
  3110. u32 rx_vec = (v0 & 0xffffffff);
  3111. int i, work_done = 0;
  3112. netif_printk(np, intr, KERN_DEBUG, np->dev,
  3113. "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
  3114. for (i = 0; i < np->num_tx_rings; i++) {
  3115. struct tx_ring_info *rp = &np->tx_rings[i];
  3116. if (tx_vec & (1 << rp->tx_channel))
  3117. niu_tx_work(np, rp);
  3118. nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
  3119. }
  3120. for (i = 0; i < np->num_rx_rings; i++) {
  3121. struct rx_ring_info *rp = &np->rx_rings[i];
  3122. if (rx_vec & (1 << rp->rx_channel)) {
  3123. int this_work_done;
  3124. this_work_done = niu_rx_work(&lp->napi, np, rp,
  3125. budget);
  3126. budget -= this_work_done;
  3127. work_done += this_work_done;
  3128. }
  3129. nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
  3130. }
  3131. return work_done;
  3132. }
  3133. static int niu_poll(struct napi_struct *napi, int budget)
  3134. {
  3135. struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
  3136. struct niu *np = lp->np;
  3137. int work_done;
  3138. work_done = niu_poll_core(np, lp, budget);
  3139. if (work_done < budget) {
  3140. napi_complete(napi);
  3141. niu_ldg_rearm(np, lp, 1);
  3142. }
  3143. return work_done;
  3144. }
  3145. static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
  3146. u64 stat)
  3147. {
  3148. netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
  3149. if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
  3150. pr_cont("RBR_TMOUT ");
  3151. if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
  3152. pr_cont("RSP_CNT ");
  3153. if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
  3154. pr_cont("BYTE_EN_BUS ");
  3155. if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
  3156. pr_cont("RSP_DAT ");
  3157. if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
  3158. pr_cont("RCR_ACK ");
  3159. if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
  3160. pr_cont("RCR_SHA_PAR ");
  3161. if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
  3162. pr_cont("RBR_PRE_PAR ");
  3163. if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
  3164. pr_cont("CONFIG ");
  3165. if (stat & RX_DMA_CTL_STAT_RCRINCON)
  3166. pr_cont("RCRINCON ");
  3167. if (stat & RX_DMA_CTL_STAT_RCRFULL)
  3168. pr_cont("RCRFULL ");
  3169. if (stat & RX_DMA_CTL_STAT_RBRFULL)
  3170. pr_cont("RBRFULL ");
  3171. if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
  3172. pr_cont("RBRLOGPAGE ");
  3173. if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
  3174. pr_cont("CFIGLOGPAGE ");
  3175. if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
  3176. pr_cont("DC_FIDO ");
  3177. pr_cont(")\n");
  3178. }
  3179. static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
  3180. {
  3181. u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
  3182. int err = 0;
  3183. if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
  3184. RX_DMA_CTL_STAT_PORT_FATAL))
  3185. err = -EINVAL;
  3186. if (err) {
  3187. netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
  3188. rp->rx_channel,
  3189. (unsigned long long) stat);
  3190. niu_log_rxchan_errors(np, rp, stat);
  3191. }
  3192. nw64(RX_DMA_CTL_STAT(rp->rx_channel),
  3193. stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
  3194. return err;
  3195. }
  3196. static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
  3197. u64 cs)
  3198. {
  3199. netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
  3200. if (cs & TX_CS_MBOX_ERR)
  3201. pr_cont("MBOX ");
  3202. if (cs & TX_CS_PKT_SIZE_ERR)
  3203. pr_cont("PKT_SIZE ");
  3204. if (cs & TX_CS_TX_RING_OFLOW)
  3205. pr_cont("TX_RING_OFLOW ");
  3206. if (cs & TX_CS_PREF_BUF_PAR_ERR)
  3207. pr_cont("PREF_BUF_PAR ");
  3208. if (cs & TX_CS_NACK_PREF)
  3209. pr_cont("NACK_PREF ");
  3210. if (cs & TX_CS_NACK_PKT_RD)
  3211. pr_cont("NACK_PKT_RD ");
  3212. if (cs & TX_CS_CONF_PART_ERR)
  3213. pr_cont("CONF_PART ");
  3214. if (cs & TX_CS_PKT_PRT_ERR)
  3215. pr_cont("PKT_PTR ");
  3216. pr_cont(")\n");
  3217. }
  3218. static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
  3219. {
  3220. u64 cs, logh, logl;
  3221. cs = nr64(TX_CS(rp->tx_channel));
  3222. logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
  3223. logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
  3224. netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
  3225. rp->tx_channel,
  3226. (unsigned long long)cs,
  3227. (unsigned long long)logh,
  3228. (unsigned long long)logl);
  3229. niu_log_txchan_errors(np, rp, cs);
  3230. return -ENODEV;
  3231. }
  3232. static int niu_mif_interrupt(struct niu *np)
  3233. {
  3234. u64 mif_status = nr64(MIF_STATUS);
  3235. int phy_mdint = 0;
  3236. if (np->flags & NIU_FLAGS_XMAC) {
  3237. u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
  3238. if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
  3239. phy_mdint = 1;
  3240. }
  3241. netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
  3242. (unsigned long long)mif_status, phy_mdint);
  3243. return -ENODEV;
  3244. }
  3245. static void niu_xmac_interrupt(struct niu *np)
  3246. {
  3247. struct niu_xmac_stats *mp = &np->mac_stats.xmac;
  3248. u64 val;
  3249. val = nr64_mac(XTXMAC_STATUS);
  3250. if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
  3251. mp->tx_frames += TXMAC_FRM_CNT_COUNT;
  3252. if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
  3253. mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
  3254. if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
  3255. mp->tx_fifo_errors++;
  3256. if (val & XTXMAC_STATUS_TXMAC_OFLOW)
  3257. mp->tx_overflow_errors++;
  3258. if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
  3259. mp->tx_max_pkt_size_errors++;
  3260. if (val & XTXMAC_STATUS_TXMAC_UFLOW)
  3261. mp->tx_underflow_errors++;
  3262. val = nr64_mac(XRXMAC_STATUS);
  3263. if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
  3264. mp->rx_local_faults++;
  3265. if (val & XRXMAC_STATUS_RFLT_DET)
  3266. mp->rx_remote_faults++;
  3267. if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
  3268. mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
  3269. if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
  3270. mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
  3271. if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
  3272. mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
  3273. if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
  3274. mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
  3275. if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
  3276. mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
  3277. if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
  3278. mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
  3279. if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
  3280. mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
  3281. if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
  3282. mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
  3283. if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
  3284. mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
  3285. if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
  3286. mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
  3287. if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
  3288. mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
  3289. if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
  3290. mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
  3291. if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
  3292. mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
  3293. if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
  3294. mp->rx_octets += RXMAC_BT_CNT_COUNT;
  3295. if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
  3296. mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
  3297. if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
  3298. mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
  3299. if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
  3300. mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
  3301. if (val & XRXMAC_STATUS_RXUFLOW)
  3302. mp->rx_underflows++;
  3303. if (val & XRXMAC_STATUS_RXOFLOW)
  3304. mp->rx_overflows++;
  3305. val = nr64_mac(XMAC_FC_STAT);
  3306. if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
  3307. mp->pause_off_state++;
  3308. if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
  3309. mp->pause_on_state++;
  3310. if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
  3311. mp->pause_received++;
  3312. }
  3313. static void niu_bmac_interrupt(struct niu *np)
  3314. {
  3315. struct niu_bmac_stats *mp = &np->mac_stats.bmac;
  3316. u64 val;
  3317. val = nr64_mac(BTXMAC_STATUS);
  3318. if (val & BTXMAC_STATUS_UNDERRUN)
  3319. mp->tx_underflow_errors++;
  3320. if (val & BTXMAC_STATUS_MAX_PKT_ERR)
  3321. mp->tx_max_pkt_size_errors++;
  3322. if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
  3323. mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
  3324. if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
  3325. mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
  3326. val = nr64_mac(BRXMAC_STATUS);
  3327. if (val & BRXMAC_STATUS_OVERFLOW)
  3328. mp->rx_overflows++;
  3329. if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
  3330. mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
  3331. if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
  3332. mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
  3333. if (val & BRXMAC_STATUS_CRC_ERR_EXP)
  3334. mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
  3335. if (val & BRXMAC_STATUS_LEN_ERR_EXP)
  3336. mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
  3337. val = nr64_mac(BMAC_CTRL_STATUS);
  3338. if (val & BMAC_CTRL_STATUS_NOPAUSE)
  3339. mp->pause_off_state++;
  3340. if (val & BMAC_CTRL_STATUS_PAUSE)
  3341. mp->pause_on_state++;
  3342. if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
  3343. mp->pause_received++;
  3344. }
  3345. static int niu_mac_interrupt(struct niu *np)
  3346. {
  3347. if (np->flags & NIU_FLAGS_XMAC)
  3348. niu_xmac_interrupt(np);
  3349. else
  3350. niu_bmac_interrupt(np);
  3351. return 0;
  3352. }
  3353. static void niu_log_device_error(struct niu *np, u64 stat)
  3354. {
  3355. netdev_err(np->dev, "Core device errors ( ");
  3356. if (stat & SYS_ERR_MASK_META2)
  3357. pr_cont("META2 ");
  3358. if (stat & SYS_ERR_MASK_META1)
  3359. pr_cont("META1 ");
  3360. if (stat & SYS_ERR_MASK_PEU)
  3361. pr_cont("PEU ");
  3362. if (stat & SYS_ERR_MASK_TXC)
  3363. pr_cont("TXC ");
  3364. if (stat & SYS_ERR_MASK_RDMC)
  3365. pr_cont("RDMC ");
  3366. if (stat & SYS_ERR_MASK_TDMC)
  3367. pr_cont("TDMC ");
  3368. if (stat & SYS_ERR_MASK_ZCP)
  3369. pr_cont("ZCP ");
  3370. if (stat & SYS_ERR_MASK_FFLP)
  3371. pr_cont("FFLP ");
  3372. if (stat & SYS_ERR_MASK_IPP)
  3373. pr_cont("IPP ");
  3374. if (stat & SYS_ERR_MASK_MAC)
  3375. pr_cont("MAC ");
  3376. if (stat & SYS_ERR_MASK_SMX)
  3377. pr_cont("SMX ");
  3378. pr_cont(")\n");
  3379. }
  3380. static int niu_device_error(struct niu *np)
  3381. {
  3382. u64 stat = nr64(SYS_ERR_STAT);
  3383. netdev_err(np->dev, "Core device error, stat[%llx]\n",
  3384. (unsigned long long)stat);
  3385. niu_log_device_error(np, stat);
  3386. return -ENODEV;
  3387. }
  3388. static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
  3389. u64 v0, u64 v1, u64 v2)
  3390. {
  3391. int i, err = 0;
  3392. lp->v0 = v0;
  3393. lp->v1 = v1;
  3394. lp->v2 = v2;
  3395. if (v1 & 0x00000000ffffffffULL) {
  3396. u32 rx_vec = (v1 & 0xffffffff);
  3397. for (i = 0; i < np->num_rx_rings; i++) {
  3398. struct rx_ring_info *rp = &np->rx_rings[i];
  3399. if (rx_vec & (1 << rp->rx_channel)) {
  3400. int r = niu_rx_error(np, rp);
  3401. if (r) {
  3402. err = r;
  3403. } else {
  3404. if (!v0)
  3405. nw64(RX_DMA_CTL_STAT(rp->rx_channel),
  3406. RX_DMA_CTL_STAT_MEX);
  3407. }
  3408. }
  3409. }
  3410. }
  3411. if (v1 & 0x7fffffff00000000ULL) {
  3412. u32 tx_vec = (v1 >> 32) & 0x7fffffff;
  3413. for (i = 0; i < np->num_tx_rings; i++) {
  3414. struct tx_ring_info *rp = &np->tx_rings[i];
  3415. if (tx_vec & (1 << rp->tx_channel)) {
  3416. int r = niu_tx_error(np, rp);
  3417. if (r)
  3418. err = r;
  3419. }
  3420. }
  3421. }
  3422. if ((v0 | v1) & 0x8000000000000000ULL) {
  3423. int r = niu_mif_interrupt(np);
  3424. if (r)
  3425. err = r;
  3426. }
  3427. if (v2) {
  3428. if (v2 & 0x01ef) {
  3429. int r = niu_mac_interrupt(np);
  3430. if (r)
  3431. err = r;
  3432. }
  3433. if (v2 & 0x0210) {
  3434. int r = niu_device_error(np);
  3435. if (r)
  3436. err = r;
  3437. }
  3438. }
  3439. if (err)
  3440. niu_enable_interrupts(np, 0);
  3441. return err;
  3442. }
  3443. static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
  3444. int ldn)
  3445. {
  3446. struct rxdma_mailbox *mbox = rp->mbox;
  3447. u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
  3448. stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
  3449. RX_DMA_CTL_STAT_RCRTO);
  3450. nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
  3451. netif_printk(np, intr, KERN_DEBUG, np->dev,
  3452. "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
  3453. }
  3454. static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
  3455. int ldn)
  3456. {
  3457. rp->tx_cs = nr64(TX_CS(rp->tx_channel));
  3458. netif_printk(np, intr, KERN_DEBUG, np->dev,
  3459. "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
  3460. }
  3461. static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
  3462. {
  3463. struct niu_parent *parent = np->parent;
  3464. u32 rx_vec, tx_vec;
  3465. int i;
  3466. tx_vec = (v0 >> 32);
  3467. rx_vec = (v0 & 0xffffffff);
  3468. for (i = 0; i < np->num_rx_rings; i++) {
  3469. struct rx_ring_info *rp = &np->rx_rings[i];
  3470. int ldn = LDN_RXDMA(rp->rx_channel);
  3471. if (parent->ldg_map[ldn] != ldg)
  3472. continue;
  3473. nw64(LD_IM0(ldn), LD_IM0_MASK);
  3474. if (rx_vec & (1 << rp->rx_channel))
  3475. niu_rxchan_intr(np, rp, ldn);
  3476. }
  3477. for (i = 0; i < np->num_tx_rings; i++) {
  3478. struct tx_ring_info *rp = &np->tx_rings[i];
  3479. int ldn = LDN_TXDMA(rp->tx_channel);
  3480. if (parent->ldg_map[ldn] != ldg)
  3481. continue;
  3482. nw64(LD_IM0(ldn), LD_IM0_MASK);
  3483. if (tx_vec & (1 << rp->tx_channel))
  3484. niu_txchan_intr(np, rp, ldn);
  3485. }
  3486. }
  3487. static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
  3488. u64 v0, u64 v1, u64 v2)
  3489. {
  3490. if (likely(napi_schedule_prep(&lp->napi))) {
  3491. lp->v0 = v0;
  3492. lp->v1 = v1;
  3493. lp->v2 = v2;
  3494. __niu_fastpath_interrupt(np, lp->ldg_num, v0);
  3495. __napi_schedule(&lp->napi);
  3496. }
  3497. }
  3498. static irqreturn_t niu_interrupt(int irq, void *dev_id)
  3499. {
  3500. struct niu_ldg *lp = dev_id;
  3501. struct niu *np = lp->np;
  3502. int ldg = lp->ldg_num;
  3503. unsigned long flags;
  3504. u64 v0, v1, v2;
  3505. if (netif_msg_intr(np))
  3506. printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
  3507. __func__, lp, ldg);
  3508. spin_lock_irqsave(&np->lock, flags);
  3509. v0 = nr64(LDSV0(ldg));
  3510. v1 = nr64(LDSV1(ldg));
  3511. v2 = nr64(LDSV2(ldg));
  3512. if (netif_msg_intr(np))
  3513. pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
  3514. (unsigned long long) v0,
  3515. (unsigned long long) v1,
  3516. (unsigned long long) v2);
  3517. if (unlikely(!v0 && !v1 && !v2)) {
  3518. spin_unlock_irqrestore(&np->lock, flags);
  3519. return IRQ_NONE;
  3520. }
  3521. if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
  3522. int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
  3523. if (err)
  3524. goto out;
  3525. }
  3526. if (likely(v0 & ~((u64)1 << LDN_MIF)))
  3527. niu_schedule_napi(np, lp, v0, v1, v2);
  3528. else
  3529. niu_ldg_rearm(np, lp, 1);
  3530. out:
  3531. spin_unlock_irqrestore(&np->lock, flags);
  3532. return IRQ_HANDLED;
  3533. }
  3534. static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
  3535. {
  3536. if (rp->mbox) {
  3537. np->ops->free_coherent(np->device,
  3538. sizeof(struct rxdma_mailbox),
  3539. rp->mbox, rp->mbox_dma);
  3540. rp->mbox = NULL;
  3541. }
  3542. if (rp->rcr) {
  3543. np->ops->free_coherent(np->device,
  3544. MAX_RCR_RING_SIZE * sizeof(__le64),
  3545. rp->rcr, rp->rcr_dma);
  3546. rp->rcr = NULL;
  3547. rp->rcr_table_size = 0;
  3548. rp->rcr_index = 0;
  3549. }
  3550. if (rp->rbr) {
  3551. niu_rbr_free(np, rp);
  3552. np->ops->free_coherent(np->device,
  3553. MAX_RBR_RING_SIZE * sizeof(__le32),
  3554. rp->rbr, rp->rbr_dma);
  3555. rp->rbr = NULL;
  3556. rp->rbr_table_size = 0;
  3557. rp->rbr_index = 0;
  3558. }
  3559. kfree(rp->rxhash);
  3560. rp->rxhash = NULL;
  3561. }
  3562. static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
  3563. {
  3564. if (rp->mbox) {
  3565. np->ops->free_coherent(np->device,
  3566. sizeof(struct txdma_mailbox),
  3567. rp->mbox, rp->mbox_dma);
  3568. rp->mbox = NULL;
  3569. }
  3570. if (rp->descr) {
  3571. int i;
  3572. for (i = 0; i < MAX_TX_RING_SIZE; i++) {
  3573. if (rp->tx_buffs[i].skb)
  3574. (void) release_tx_packet(np, rp, i);
  3575. }
  3576. np->ops->free_coherent(np->device,
  3577. MAX_TX_RING_SIZE * sizeof(__le64),
  3578. rp->descr, rp->descr_dma);
  3579. rp->descr = NULL;
  3580. rp->pending = 0;
  3581. rp->prod = 0;
  3582. rp->cons = 0;
  3583. rp->wrap_bit = 0;
  3584. }
  3585. }
  3586. static void niu_free_channels(struct niu *np)
  3587. {
  3588. int i;
  3589. if (np->rx_rings) {
  3590. for (i = 0; i < np->num_rx_rings; i++) {
  3591. struct rx_ring_info *rp = &np->rx_rings[i];
  3592. niu_free_rx_ring_info(np, rp);
  3593. }
  3594. kfree(np->rx_rings);
  3595. np->rx_rings = NULL;
  3596. np->num_rx_rings = 0;
  3597. }
  3598. if (np->tx_rings) {
  3599. for (i = 0; i < np->num_tx_rings; i++) {
  3600. struct tx_ring_info *rp = &np->tx_rings[i];
  3601. niu_free_tx_ring_info(np, rp);
  3602. }
  3603. kfree(np->tx_rings);
  3604. np->tx_rings = NULL;
  3605. np->num_tx_rings = 0;
  3606. }
  3607. }
  3608. static int niu_alloc_rx_ring_info(struct niu *np,
  3609. struct rx_ring_info *rp)
  3610. {
  3611. BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
  3612. rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
  3613. GFP_KERNEL);
  3614. if (!rp->rxhash)
  3615. return -ENOMEM;
  3616. rp->mbox = np->ops->alloc_coherent(np->device,
  3617. sizeof(struct rxdma_mailbox),
  3618. &rp->mbox_dma, GFP_KERNEL);
  3619. if (!rp->mbox)
  3620. return -ENOMEM;
  3621. if ((unsigned long)rp->mbox & (64UL - 1)) {
  3622. netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
  3623. rp->mbox);
  3624. return -EINVAL;
  3625. }
  3626. rp->rcr = np->ops->alloc_coherent(np->device,
  3627. MAX_RCR_RING_SIZE * sizeof(__le64),
  3628. &rp->rcr_dma, GFP_KERNEL);
  3629. if (!rp->rcr)
  3630. return -ENOMEM;
  3631. if ((unsigned long)rp->rcr & (64UL - 1)) {
  3632. netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
  3633. rp->rcr);
  3634. return -EINVAL;
  3635. }
  3636. rp->rcr_table_size = MAX_RCR_RING_SIZE;
  3637. rp->rcr_index = 0;
  3638. rp->rbr = np->ops->alloc_coherent(np->device,
  3639. MAX_RBR_RING_SIZE * sizeof(__le32),
  3640. &rp->rbr_dma, GFP_KERNEL);
  3641. if (!rp->rbr)
  3642. return -ENOMEM;
  3643. if ((unsigned long)rp->rbr & (64UL - 1)) {
  3644. netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
  3645. rp->rbr);
  3646. return -EINVAL;
  3647. }
  3648. rp->rbr_table_size = MAX_RBR_RING_SIZE;
  3649. rp->rbr_index = 0;
  3650. rp->rbr_pending = 0;
  3651. return 0;
  3652. }
  3653. static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
  3654. {
  3655. int mtu = np->dev->mtu;
  3656. /* These values are recommended by the HW designers for fair
  3657. * utilization of DRR amongst the rings.
  3658. */
  3659. rp->max_burst = mtu + 32;
  3660. if (rp->max_burst > 4096)
  3661. rp->max_burst = 4096;
  3662. }
  3663. static int niu_alloc_tx_ring_info(struct niu *np,
  3664. struct tx_ring_info *rp)
  3665. {
  3666. BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
  3667. rp->mbox = np->ops->alloc_coherent(np->device,
  3668. sizeof(struct txdma_mailbox),
  3669. &rp->mbox_dma, GFP_KERNEL);
  3670. if (!rp->mbox)
  3671. return -ENOMEM;
  3672. if ((unsigned long)rp->mbox & (64UL - 1)) {
  3673. netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
  3674. rp->mbox);
  3675. return -EINVAL;
  3676. }
  3677. rp->descr = np->ops->alloc_coherent(np->device,
  3678. MAX_TX_RING_SIZE * sizeof(__le64),
  3679. &rp->descr_dma, GFP_KERNEL);
  3680. if (!rp->descr)
  3681. return -ENOMEM;
  3682. if ((unsigned long)rp->descr & (64UL - 1)) {
  3683. netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
  3684. rp->descr);
  3685. return -EINVAL;
  3686. }
  3687. rp->pending = MAX_TX_RING_SIZE;
  3688. rp->prod = 0;
  3689. rp->cons = 0;
  3690. rp->wrap_bit = 0;
  3691. /* XXX make these configurable... XXX */
  3692. rp->mark_freq = rp->pending / 4;
  3693. niu_set_max_burst(np, rp);
  3694. return 0;
  3695. }
  3696. static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
  3697. {
  3698. u16 bss;
  3699. bss = min(PAGE_SHIFT, 15);
  3700. rp->rbr_block_size = 1 << bss;
  3701. rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
  3702. rp->rbr_sizes[0] = 256;
  3703. rp->rbr_sizes[1] = 1024;
  3704. if (np->dev->mtu > ETH_DATA_LEN) {
  3705. switch (PAGE_SIZE) {
  3706. case 4 * 1024:
  3707. rp->rbr_sizes[2] = 4096;
  3708. break;
  3709. default:
  3710. rp->rbr_sizes[2] = 8192;
  3711. break;
  3712. }
  3713. } else {
  3714. rp->rbr_sizes[2] = 2048;
  3715. }
  3716. rp->rbr_sizes[3] = rp->rbr_block_size;
  3717. }
  3718. static int niu_alloc_channels(struct niu *np)
  3719. {
  3720. struct niu_parent *parent = np->parent;
  3721. int first_rx_channel, first_tx_channel;
  3722. int i, port, err;
  3723. port = np->port;
  3724. first_rx_channel = first_tx_channel = 0;
  3725. for (i = 0; i < port; i++) {
  3726. first_rx_channel += parent->rxchan_per_port[i];
  3727. first_tx_channel += parent->txchan_per_port[i];
  3728. }
  3729. np->num_rx_rings = parent->rxchan_per_port[port];
  3730. np->num_tx_rings = parent->txchan_per_port[port];
  3731. np->dev->real_num_tx_queues = np->num_tx_rings;
  3732. np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
  3733. GFP_KERNEL);
  3734. err = -ENOMEM;
  3735. if (!np->rx_rings)
  3736. goto out_err;
  3737. for (i = 0; i < np->num_rx_rings; i++) {
  3738. struct rx_ring_info *rp = &np->rx_rings[i];
  3739. rp->np = np;
  3740. rp->rx_channel = first_rx_channel + i;
  3741. err = niu_alloc_rx_ring_info(np, rp);
  3742. if (err)
  3743. goto out_err;
  3744. niu_size_rbr(np, rp);
  3745. /* XXX better defaults, configurable, etc... XXX */
  3746. rp->nonsyn_window = 64;
  3747. rp->nonsyn_threshold = rp->rcr_table_size - 64;
  3748. rp->syn_window = 64;
  3749. rp->syn_threshold = rp->rcr_table_size - 64;
  3750. rp->rcr_pkt_threshold = 16;
  3751. rp->rcr_timeout = 8;
  3752. rp->rbr_kick_thresh = RBR_REFILL_MIN;
  3753. if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
  3754. rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
  3755. err = niu_rbr_fill(np, rp, GFP_KERNEL);
  3756. if (err)
  3757. return err;
  3758. }
  3759. np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
  3760. GFP_KERNEL);
  3761. err = -ENOMEM;
  3762. if (!np->tx_rings)
  3763. goto out_err;
  3764. for (i = 0; i < np->num_tx_rings; i++) {
  3765. struct tx_ring_info *rp = &np->tx_rings[i];
  3766. rp->np = np;
  3767. rp->tx_channel = first_tx_channel + i;
  3768. err = niu_alloc_tx_ring_info(np, rp);
  3769. if (err)
  3770. goto out_err;
  3771. }
  3772. return 0;
  3773. out_err:
  3774. niu_free_channels(np);
  3775. return err;
  3776. }
  3777. static int niu_tx_cs_sng_poll(struct niu *np, int channel)
  3778. {
  3779. int limit = 1000;
  3780. while (--limit > 0) {
  3781. u64 val = nr64(TX_CS(channel));
  3782. if (val & TX_CS_SNG_STATE)
  3783. return 0;
  3784. }
  3785. return -ENODEV;
  3786. }
  3787. static int niu_tx_channel_stop(struct niu *np, int channel)
  3788. {
  3789. u64 val = nr64(TX_CS(channel));
  3790. val |= TX_CS_STOP_N_GO;
  3791. nw64(TX_CS(channel), val);
  3792. return niu_tx_cs_sng_poll(np, channel);
  3793. }
  3794. static int niu_tx_cs_reset_poll(struct niu *np, int channel)
  3795. {
  3796. int limit = 1000;
  3797. while (--limit > 0) {
  3798. u64 val = nr64(TX_CS(channel));
  3799. if (!(val & TX_CS_RST))
  3800. return 0;
  3801. }
  3802. return -ENODEV;
  3803. }
  3804. static int niu_tx_channel_reset(struct niu *np, int channel)
  3805. {
  3806. u64 val = nr64(TX_CS(channel));
  3807. int err;
  3808. val |= TX_CS_RST;
  3809. nw64(TX_CS(channel), val);
  3810. err = niu_tx_cs_reset_poll(np, channel);
  3811. if (!err)
  3812. nw64(TX_RING_KICK(channel), 0);
  3813. return err;
  3814. }
  3815. static int niu_tx_channel_lpage_init(struct niu *np, int channel)
  3816. {
  3817. u64 val;
  3818. nw64(TX_LOG_MASK1(channel), 0);
  3819. nw64(TX_LOG_VAL1(channel), 0);
  3820. nw64(TX_LOG_MASK2(channel), 0);
  3821. nw64(TX_LOG_VAL2(channel), 0);
  3822. nw64(TX_LOG_PAGE_RELO1(channel), 0);
  3823. nw64(TX_LOG_PAGE_RELO2(channel), 0);
  3824. nw64(TX_LOG_PAGE_HDL(channel), 0);
  3825. val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
  3826. val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
  3827. nw64(TX_LOG_PAGE_VLD(channel), val);
  3828. /* XXX TXDMA 32bit mode? XXX */
  3829. return 0;
  3830. }
  3831. static void niu_txc_enable_port(struct niu *np, int on)
  3832. {
  3833. unsigned long flags;
  3834. u64 val, mask;
  3835. niu_lock_parent(np, flags);
  3836. val = nr64(TXC_CONTROL);
  3837. mask = (u64)1 << np->port;
  3838. if (on) {
  3839. val |= TXC_CONTROL_ENABLE | mask;
  3840. } else {
  3841. val &= ~mask;
  3842. if ((val & ~TXC_CONTROL_ENABLE) == 0)
  3843. val &= ~TXC_CONTROL_ENABLE;
  3844. }
  3845. nw64(TXC_CONTROL, val);
  3846. niu_unlock_parent(np, flags);
  3847. }
  3848. static void niu_txc_set_imask(struct niu *np, u64 imask)
  3849. {
  3850. unsigned long flags;
  3851. u64 val;
  3852. niu_lock_parent(np, flags);
  3853. val = nr64(TXC_INT_MASK);
  3854. val &= ~TXC_INT_MASK_VAL(np->port);
  3855. val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
  3856. niu_unlock_parent(np, flags);
  3857. }
  3858. static void niu_txc_port_dma_enable(struct niu *np, int on)
  3859. {
  3860. u64 val = 0;
  3861. if (on) {
  3862. int i;
  3863. for (i = 0; i < np->num_tx_rings; i++)
  3864. val |= (1 << np->tx_rings[i].tx_channel);
  3865. }
  3866. nw64(TXC_PORT_DMA(np->port), val);
  3867. }
  3868. static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
  3869. {
  3870. int err, channel = rp->tx_channel;
  3871. u64 val, ring_len;
  3872. err = niu_tx_channel_stop(np, channel);
  3873. if (err)
  3874. return err;
  3875. err = niu_tx_channel_reset(np, channel);
  3876. if (err)
  3877. return err;
  3878. err = niu_tx_channel_lpage_init(np, channel);
  3879. if (err)
  3880. return err;
  3881. nw64(TXC_DMA_MAX(channel), rp->max_burst);
  3882. nw64(TX_ENT_MSK(channel), 0);
  3883. if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
  3884. TX_RNG_CFIG_STADDR)) {
  3885. netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
  3886. channel, (unsigned long long)rp->descr_dma);
  3887. return -EINVAL;
  3888. }
  3889. /* The length field in TX_RNG_CFIG is measured in 64-byte
  3890. * blocks. rp->pending is the number of TX descriptors in
  3891. * our ring, 8 bytes each, thus we divide by 8 bytes more
  3892. * to get the proper value the chip wants.
  3893. */
  3894. ring_len = (rp->pending / 8);
  3895. val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
  3896. rp->descr_dma);
  3897. nw64(TX_RNG_CFIG(channel), val);
  3898. if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
  3899. ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
  3900. netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
  3901. channel, (unsigned long long)rp->mbox_dma);
  3902. return -EINVAL;
  3903. }
  3904. nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
  3905. nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
  3906. nw64(TX_CS(channel), 0);
  3907. rp->last_pkt_cnt = 0;
  3908. return 0;
  3909. }
  3910. static void niu_init_rdc_groups(struct niu *np)
  3911. {
  3912. struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
  3913. int i, first_table_num = tp->first_table_num;
  3914. for (i = 0; i < tp->num_tables; i++) {
  3915. struct rdc_table *tbl = &tp->tables[i];
  3916. int this_table = first_table_num + i;
  3917. int slot;
  3918. for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
  3919. nw64(RDC_TBL(this_table, slot),
  3920. tbl->rxdma_channel[slot]);
  3921. }
  3922. nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
  3923. }
  3924. static void niu_init_drr_weight(struct niu *np)
  3925. {
  3926. int type = phy_decode(np->parent->port_phy, np->port);
  3927. u64 val;
  3928. switch (type) {
  3929. case PORT_TYPE_10G:
  3930. val = PT_DRR_WEIGHT_DEFAULT_10G;
  3931. break;
  3932. case PORT_TYPE_1G:
  3933. default:
  3934. val = PT_DRR_WEIGHT_DEFAULT_1G;
  3935. break;
  3936. }
  3937. nw64(PT_DRR_WT(np->port), val);
  3938. }
  3939. static int niu_init_hostinfo(struct niu *np)
  3940. {
  3941. struct niu_parent *parent = np->parent;
  3942. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
  3943. int i, err, num_alt = niu_num_alt_addr(np);
  3944. int first_rdc_table = tp->first_table_num;
  3945. err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
  3946. if (err)
  3947. return err;
  3948. err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
  3949. if (err)
  3950. return err;
  3951. for (i = 0; i < num_alt; i++) {
  3952. err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
  3953. if (err)
  3954. return err;
  3955. }
  3956. return 0;
  3957. }
  3958. static int niu_rx_channel_reset(struct niu *np, int channel)
  3959. {
  3960. return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
  3961. RXDMA_CFIG1_RST, 1000, 10,
  3962. "RXDMA_CFIG1");
  3963. }
  3964. static int niu_rx_channel_lpage_init(struct niu *np, int channel)
  3965. {
  3966. u64 val;
  3967. nw64(RX_LOG_MASK1(channel), 0);
  3968. nw64(RX_LOG_VAL1(channel), 0);
  3969. nw64(RX_LOG_MASK2(channel), 0);
  3970. nw64(RX_LOG_VAL2(channel), 0);
  3971. nw64(RX_LOG_PAGE_RELO1(channel), 0);
  3972. nw64(RX_LOG_PAGE_RELO2(channel), 0);
  3973. nw64(RX_LOG_PAGE_HDL(channel), 0);
  3974. val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
  3975. val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
  3976. nw64(RX_LOG_PAGE_VLD(channel), val);
  3977. return 0;
  3978. }
  3979. static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
  3980. {
  3981. u64 val;
  3982. val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
  3983. ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
  3984. ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
  3985. ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
  3986. nw64(RDC_RED_PARA(rp->rx_channel), val);
  3987. }
  3988. static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
  3989. {
  3990. u64 val = 0;
  3991. *ret = 0;
  3992. switch (rp->rbr_block_size) {
  3993. case 4 * 1024:
  3994. val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
  3995. break;
  3996. case 8 * 1024:
  3997. val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
  3998. break;
  3999. case 16 * 1024:
  4000. val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
  4001. break;
  4002. case 32 * 1024:
  4003. val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
  4004. break;
  4005. default:
  4006. return -EINVAL;
  4007. }
  4008. val |= RBR_CFIG_B_VLD2;
  4009. switch (rp->rbr_sizes[2]) {
  4010. case 2 * 1024:
  4011. val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
  4012. break;
  4013. case 4 * 1024:
  4014. val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
  4015. break;
  4016. case 8 * 1024:
  4017. val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
  4018. break;
  4019. case 16 * 1024:
  4020. val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
  4021. break;
  4022. default:
  4023. return -EINVAL;
  4024. }
  4025. val |= RBR_CFIG_B_VLD1;
  4026. switch (rp->rbr_sizes[1]) {
  4027. case 1 * 1024:
  4028. val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
  4029. break;
  4030. case 2 * 1024:
  4031. val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
  4032. break;
  4033. case 4 * 1024:
  4034. val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
  4035. break;
  4036. case 8 * 1024:
  4037. val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
  4038. break;
  4039. default:
  4040. return -EINVAL;
  4041. }
  4042. val |= RBR_CFIG_B_VLD0;
  4043. switch (rp->rbr_sizes[0]) {
  4044. case 256:
  4045. val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
  4046. break;
  4047. case 512:
  4048. val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
  4049. break;
  4050. case 1 * 1024:
  4051. val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
  4052. break;
  4053. case 2 * 1024:
  4054. val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
  4055. break;
  4056. default:
  4057. return -EINVAL;
  4058. }
  4059. *ret = val;
  4060. return 0;
  4061. }
  4062. static int niu_enable_rx_channel(struct niu *np, int channel, int on)
  4063. {
  4064. u64 val = nr64(RXDMA_CFIG1(channel));
  4065. int limit;
  4066. if (on)
  4067. val |= RXDMA_CFIG1_EN;
  4068. else
  4069. val &= ~RXDMA_CFIG1_EN;
  4070. nw64(RXDMA_CFIG1(channel), val);
  4071. limit = 1000;
  4072. while (--limit > 0) {
  4073. if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
  4074. break;
  4075. udelay(10);
  4076. }
  4077. if (limit <= 0)
  4078. return -ENODEV;
  4079. return 0;
  4080. }
  4081. static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
  4082. {
  4083. int err, channel = rp->rx_channel;
  4084. u64 val;
  4085. err = niu_rx_channel_reset(np, channel);
  4086. if (err)
  4087. return err;
  4088. err = niu_rx_channel_lpage_init(np, channel);
  4089. if (err)
  4090. return err;
  4091. niu_rx_channel_wred_init(np, rp);
  4092. nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
  4093. nw64(RX_DMA_CTL_STAT(channel),
  4094. (RX_DMA_CTL_STAT_MEX |
  4095. RX_DMA_CTL_STAT_RCRTHRES |
  4096. RX_DMA_CTL_STAT_RCRTO |
  4097. RX_DMA_CTL_STAT_RBR_EMPTY));
  4098. nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
  4099. nw64(RXDMA_CFIG2(channel),
  4100. ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
  4101. RXDMA_CFIG2_FULL_HDR));
  4102. nw64(RBR_CFIG_A(channel),
  4103. ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
  4104. (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
  4105. err = niu_compute_rbr_cfig_b(rp, &val);
  4106. if (err)
  4107. return err;
  4108. nw64(RBR_CFIG_B(channel), val);
  4109. nw64(RCRCFIG_A(channel),
  4110. ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
  4111. (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
  4112. nw64(RCRCFIG_B(channel),
  4113. ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
  4114. RCRCFIG_B_ENTOUT |
  4115. ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
  4116. err = niu_enable_rx_channel(np, channel, 1);
  4117. if (err)
  4118. return err;
  4119. nw64(RBR_KICK(channel), rp->rbr_index);
  4120. val = nr64(RX_DMA_CTL_STAT(channel));
  4121. val |= RX_DMA_CTL_STAT_RBR_EMPTY;
  4122. nw64(RX_DMA_CTL_STAT(channel), val);
  4123. return 0;
  4124. }
  4125. static int niu_init_rx_channels(struct niu *np)
  4126. {
  4127. unsigned long flags;
  4128. u64 seed = jiffies_64;
  4129. int err, i;
  4130. niu_lock_parent(np, flags);
  4131. nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
  4132. nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
  4133. niu_unlock_parent(np, flags);
  4134. /* XXX RXDMA 32bit mode? XXX */
  4135. niu_init_rdc_groups(np);
  4136. niu_init_drr_weight(np);
  4137. err = niu_init_hostinfo(np);
  4138. if (err)
  4139. return err;
  4140. for (i = 0; i < np->num_rx_rings; i++) {
  4141. struct rx_ring_info *rp = &np->rx_rings[i];
  4142. err = niu_init_one_rx_channel(np, rp);
  4143. if (err)
  4144. return err;
  4145. }
  4146. return 0;
  4147. }
  4148. static int niu_set_ip_frag_rule(struct niu *np)
  4149. {
  4150. struct niu_parent *parent = np->parent;
  4151. struct niu_classifier *cp = &np->clas;
  4152. struct niu_tcam_entry *tp;
  4153. int index, err;
  4154. index = cp->tcam_top;
  4155. tp = &parent->tcam[index];
  4156. /* Note that the noport bit is the same in both ipv4 and
  4157. * ipv6 format TCAM entries.
  4158. */
  4159. memset(tp, 0, sizeof(*tp));
  4160. tp->key[1] = TCAM_V4KEY1_NOPORT;
  4161. tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
  4162. tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
  4163. ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
  4164. err = tcam_write(np, index, tp->key, tp->key_mask);
  4165. if (err)
  4166. return err;
  4167. err = tcam_assoc_write(np, index, tp->assoc_data);
  4168. if (err)
  4169. return err;
  4170. tp->valid = 1;
  4171. cp->tcam_valid_entries++;
  4172. return 0;
  4173. }
  4174. static int niu_init_classifier_hw(struct niu *np)
  4175. {
  4176. struct niu_parent *parent = np->parent;
  4177. struct niu_classifier *cp = &np->clas;
  4178. int i, err;
  4179. nw64(H1POLY, cp->h1_init);
  4180. nw64(H2POLY, cp->h2_init);
  4181. err = niu_init_hostinfo(np);
  4182. if (err)
  4183. return err;
  4184. for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
  4185. struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
  4186. vlan_tbl_write(np, i, np->port,
  4187. vp->vlan_pref, vp->rdc_num);
  4188. }
  4189. for (i = 0; i < cp->num_alt_mac_mappings; i++) {
  4190. struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
  4191. err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
  4192. ap->rdc_num, ap->mac_pref);
  4193. if (err)
  4194. return err;
  4195. }
  4196. for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
  4197. int index = i - CLASS_CODE_USER_PROG1;
  4198. err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
  4199. if (err)
  4200. return err;
  4201. err = niu_set_flow_key(np, i, parent->flow_key[index]);
  4202. if (err)
  4203. return err;
  4204. }
  4205. err = niu_set_ip_frag_rule(np);
  4206. if (err)
  4207. return err;
  4208. tcam_enable(np, 1);
  4209. return 0;
  4210. }
  4211. static int niu_zcp_write(struct niu *np, int index, u64 *data)
  4212. {
  4213. nw64(ZCP_RAM_DATA0, data[0]);
  4214. nw64(ZCP_RAM_DATA1, data[1]);
  4215. nw64(ZCP_RAM_DATA2, data[2]);
  4216. nw64(ZCP_RAM_DATA3, data[3]);
  4217. nw64(ZCP_RAM_DATA4, data[4]);
  4218. nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
  4219. nw64(ZCP_RAM_ACC,
  4220. (ZCP_RAM_ACC_WRITE |
  4221. (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
  4222. (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
  4223. return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
  4224. 1000, 100);
  4225. }
  4226. static int niu_zcp_read(struct niu *np, int index, u64 *data)
  4227. {
  4228. int err;
  4229. err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
  4230. 1000, 100);
  4231. if (err) {
  4232. netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
  4233. (unsigned long long)nr64(ZCP_RAM_ACC));
  4234. return err;
  4235. }
  4236. nw64(ZCP_RAM_ACC,
  4237. (ZCP_RAM_ACC_READ |
  4238. (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
  4239. (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
  4240. err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
  4241. 1000, 100);
  4242. if (err) {
  4243. netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
  4244. (unsigned long long)nr64(ZCP_RAM_ACC));
  4245. return err;
  4246. }
  4247. data[0] = nr64(ZCP_RAM_DATA0);
  4248. data[1] = nr64(ZCP_RAM_DATA1);
  4249. data[2] = nr64(ZCP_RAM_DATA2);
  4250. data[3] = nr64(ZCP_RAM_DATA3);
  4251. data[4] = nr64(ZCP_RAM_DATA4);
  4252. return 0;
  4253. }
  4254. static void niu_zcp_cfifo_reset(struct niu *np)
  4255. {
  4256. u64 val = nr64(RESET_CFIFO);
  4257. val |= RESET_CFIFO_RST(np->port);
  4258. nw64(RESET_CFIFO, val);
  4259. udelay(10);
  4260. val &= ~RESET_CFIFO_RST(np->port);
  4261. nw64(RESET_CFIFO, val);
  4262. }
  4263. static int niu_init_zcp(struct niu *np)
  4264. {
  4265. u64 data[5], rbuf[5];
  4266. int i, max, err;
  4267. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  4268. if (np->port == 0 || np->port == 1)
  4269. max = ATLAS_P0_P1_CFIFO_ENTRIES;
  4270. else
  4271. max = ATLAS_P2_P3_CFIFO_ENTRIES;
  4272. } else
  4273. max = NIU_CFIFO_ENTRIES;
  4274. data[0] = 0;
  4275. data[1] = 0;
  4276. data[2] = 0;
  4277. data[3] = 0;
  4278. data[4] = 0;
  4279. for (i = 0; i < max; i++) {
  4280. err = niu_zcp_write(np, i, data);
  4281. if (err)
  4282. return err;
  4283. err = niu_zcp_read(np, i, rbuf);
  4284. if (err)
  4285. return err;
  4286. }
  4287. niu_zcp_cfifo_reset(np);
  4288. nw64(CFIFO_ECC(np->port), 0);
  4289. nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
  4290. (void) nr64(ZCP_INT_STAT);
  4291. nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
  4292. return 0;
  4293. }
  4294. static void niu_ipp_write(struct niu *np, int index, u64 *data)
  4295. {
  4296. u64 val = nr64_ipp(IPP_CFIG);
  4297. nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
  4298. nw64_ipp(IPP_DFIFO_WR_PTR, index);
  4299. nw64_ipp(IPP_DFIFO_WR0, data[0]);
  4300. nw64_ipp(IPP_DFIFO_WR1, data[1]);
  4301. nw64_ipp(IPP_DFIFO_WR2, data[2]);
  4302. nw64_ipp(IPP_DFIFO_WR3, data[3]);
  4303. nw64_ipp(IPP_DFIFO_WR4, data[4]);
  4304. nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
  4305. }
  4306. static void niu_ipp_read(struct niu *np, int index, u64 *data)
  4307. {
  4308. nw64_ipp(IPP_DFIFO_RD_PTR, index);
  4309. data[0] = nr64_ipp(IPP_DFIFO_RD0);
  4310. data[1] = nr64_ipp(IPP_DFIFO_RD1);
  4311. data[2] = nr64_ipp(IPP_DFIFO_RD2);
  4312. data[3] = nr64_ipp(IPP_DFIFO_RD3);
  4313. data[4] = nr64_ipp(IPP_DFIFO_RD4);
  4314. }
  4315. static int niu_ipp_reset(struct niu *np)
  4316. {
  4317. return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
  4318. 1000, 100, "IPP_CFIG");
  4319. }
  4320. static int niu_init_ipp(struct niu *np)
  4321. {
  4322. u64 data[5], rbuf[5], val;
  4323. int i, max, err;
  4324. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  4325. if (np->port == 0 || np->port == 1)
  4326. max = ATLAS_P0_P1_DFIFO_ENTRIES;
  4327. else
  4328. max = ATLAS_P2_P3_DFIFO_ENTRIES;
  4329. } else
  4330. max = NIU_DFIFO_ENTRIES;
  4331. data[0] = 0;
  4332. data[1] = 0;
  4333. data[2] = 0;
  4334. data[3] = 0;
  4335. data[4] = 0;
  4336. for (i = 0; i < max; i++) {
  4337. niu_ipp_write(np, i, data);
  4338. niu_ipp_read(np, i, rbuf);
  4339. }
  4340. (void) nr64_ipp(IPP_INT_STAT);
  4341. (void) nr64_ipp(IPP_INT_STAT);
  4342. err = niu_ipp_reset(np);
  4343. if (err)
  4344. return err;
  4345. (void) nr64_ipp(IPP_PKT_DIS);
  4346. (void) nr64_ipp(IPP_BAD_CS_CNT);
  4347. (void) nr64_ipp(IPP_ECC);
  4348. (void) nr64_ipp(IPP_INT_STAT);
  4349. nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
  4350. val = nr64_ipp(IPP_CFIG);
  4351. val &= ~IPP_CFIG_IP_MAX_PKT;
  4352. val |= (IPP_CFIG_IPP_ENABLE |
  4353. IPP_CFIG_DFIFO_ECC_EN |
  4354. IPP_CFIG_DROP_BAD_CRC |
  4355. IPP_CFIG_CKSUM_EN |
  4356. (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
  4357. nw64_ipp(IPP_CFIG, val);
  4358. return 0;
  4359. }
  4360. static void niu_handle_led(struct niu *np, int status)
  4361. {
  4362. u64 val;
  4363. val = nr64_mac(XMAC_CONFIG);
  4364. if ((np->flags & NIU_FLAGS_10G) != 0 &&
  4365. (np->flags & NIU_FLAGS_FIBER) != 0) {
  4366. if (status) {
  4367. val |= XMAC_CONFIG_LED_POLARITY;
  4368. val &= ~XMAC_CONFIG_FORCE_LED_ON;
  4369. } else {
  4370. val |= XMAC_CONFIG_FORCE_LED_ON;
  4371. val &= ~XMAC_CONFIG_LED_POLARITY;
  4372. }
  4373. }
  4374. nw64_mac(XMAC_CONFIG, val);
  4375. }
  4376. static void niu_init_xif_xmac(struct niu *np)
  4377. {
  4378. struct niu_link_config *lp = &np->link_config;
  4379. u64 val;
  4380. if (np->flags & NIU_FLAGS_XCVR_SERDES) {
  4381. val = nr64(MIF_CONFIG);
  4382. val |= MIF_CONFIG_ATCA_GE;
  4383. nw64(MIF_CONFIG, val);
  4384. }
  4385. val = nr64_mac(XMAC_CONFIG);
  4386. val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
  4387. val |= XMAC_CONFIG_TX_OUTPUT_EN;
  4388. if (lp->loopback_mode == LOOPBACK_MAC) {
  4389. val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
  4390. val |= XMAC_CONFIG_LOOPBACK;
  4391. } else {
  4392. val &= ~XMAC_CONFIG_LOOPBACK;
  4393. }
  4394. if (np->flags & NIU_FLAGS_10G) {
  4395. val &= ~XMAC_CONFIG_LFS_DISABLE;
  4396. } else {
  4397. val |= XMAC_CONFIG_LFS_DISABLE;
  4398. if (!(np->flags & NIU_FLAGS_FIBER) &&
  4399. !(np->flags & NIU_FLAGS_XCVR_SERDES))
  4400. val |= XMAC_CONFIG_1G_PCS_BYPASS;
  4401. else
  4402. val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
  4403. }
  4404. val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
  4405. if (lp->active_speed == SPEED_100)
  4406. val |= XMAC_CONFIG_SEL_CLK_25MHZ;
  4407. else
  4408. val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
  4409. nw64_mac(XMAC_CONFIG, val);
  4410. val = nr64_mac(XMAC_CONFIG);
  4411. val &= ~XMAC_CONFIG_MODE_MASK;
  4412. if (np->flags & NIU_FLAGS_10G) {
  4413. val |= XMAC_CONFIG_MODE_XGMII;
  4414. } else {
  4415. if (lp->active_speed == SPEED_1000)
  4416. val |= XMAC_CONFIG_MODE_GMII;
  4417. else
  4418. val |= XMAC_CONFIG_MODE_MII;
  4419. }
  4420. nw64_mac(XMAC_CONFIG, val);
  4421. }
  4422. static void niu_init_xif_bmac(struct niu *np)
  4423. {
  4424. struct niu_link_config *lp = &np->link_config;
  4425. u64 val;
  4426. val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
  4427. if (lp->loopback_mode == LOOPBACK_MAC)
  4428. val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
  4429. else
  4430. val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
  4431. if (lp->active_speed == SPEED_1000)
  4432. val |= BMAC_XIF_CONFIG_GMII_MODE;
  4433. else
  4434. val &= ~BMAC_XIF_CONFIG_GMII_MODE;
  4435. val &= ~(BMAC_XIF_CONFIG_LINK_LED |
  4436. BMAC_XIF_CONFIG_LED_POLARITY);
  4437. if (!(np->flags & NIU_FLAGS_10G) &&
  4438. !(np->flags & NIU_FLAGS_FIBER) &&
  4439. lp->active_speed == SPEED_100)
  4440. val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
  4441. else
  4442. val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
  4443. nw64_mac(BMAC_XIF_CONFIG, val);
  4444. }
  4445. static void niu_init_xif(struct niu *np)
  4446. {
  4447. if (np->flags & NIU_FLAGS_XMAC)
  4448. niu_init_xif_xmac(np);
  4449. else
  4450. niu_init_xif_bmac(np);
  4451. }
  4452. static void niu_pcs_mii_reset(struct niu *np)
  4453. {
  4454. int limit = 1000;
  4455. u64 val = nr64_pcs(PCS_MII_CTL);
  4456. val |= PCS_MII_CTL_RST;
  4457. nw64_pcs(PCS_MII_CTL, val);
  4458. while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
  4459. udelay(100);
  4460. val = nr64_pcs(PCS_MII_CTL);
  4461. }
  4462. }
  4463. static void niu_xpcs_reset(struct niu *np)
  4464. {
  4465. int limit = 1000;
  4466. u64 val = nr64_xpcs(XPCS_CONTROL1);
  4467. val |= XPCS_CONTROL1_RESET;
  4468. nw64_xpcs(XPCS_CONTROL1, val);
  4469. while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
  4470. udelay(100);
  4471. val = nr64_xpcs(XPCS_CONTROL1);
  4472. }
  4473. }
  4474. static int niu_init_pcs(struct niu *np)
  4475. {
  4476. struct niu_link_config *lp = &np->link_config;
  4477. u64 val;
  4478. switch (np->flags & (NIU_FLAGS_10G |
  4479. NIU_FLAGS_FIBER |
  4480. NIU_FLAGS_XCVR_SERDES)) {
  4481. case NIU_FLAGS_FIBER:
  4482. /* 1G fiber */
  4483. nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
  4484. nw64_pcs(PCS_DPATH_MODE, 0);
  4485. niu_pcs_mii_reset(np);
  4486. break;
  4487. case NIU_FLAGS_10G:
  4488. case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
  4489. case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
  4490. /* 10G SERDES */
  4491. if (!(np->flags & NIU_FLAGS_XMAC))
  4492. return -EINVAL;
  4493. /* 10G copper or fiber */
  4494. val = nr64_mac(XMAC_CONFIG);
  4495. val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
  4496. nw64_mac(XMAC_CONFIG, val);
  4497. niu_xpcs_reset(np);
  4498. val = nr64_xpcs(XPCS_CONTROL1);
  4499. if (lp->loopback_mode == LOOPBACK_PHY)
  4500. val |= XPCS_CONTROL1_LOOPBACK;
  4501. else
  4502. val &= ~XPCS_CONTROL1_LOOPBACK;
  4503. nw64_xpcs(XPCS_CONTROL1, val);
  4504. nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
  4505. (void) nr64_xpcs(XPCS_SYMERR_CNT01);
  4506. (void) nr64_xpcs(XPCS_SYMERR_CNT23);
  4507. break;
  4508. case NIU_FLAGS_XCVR_SERDES:
  4509. /* 1G SERDES */
  4510. niu_pcs_mii_reset(np);
  4511. nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
  4512. nw64_pcs(PCS_DPATH_MODE, 0);
  4513. break;
  4514. case 0:
  4515. /* 1G copper */
  4516. case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
  4517. /* 1G RGMII FIBER */
  4518. nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
  4519. niu_pcs_mii_reset(np);
  4520. break;
  4521. default:
  4522. return -EINVAL;
  4523. }
  4524. return 0;
  4525. }
  4526. static int niu_reset_tx_xmac(struct niu *np)
  4527. {
  4528. return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
  4529. (XTXMAC_SW_RST_REG_RS |
  4530. XTXMAC_SW_RST_SOFT_RST),
  4531. 1000, 100, "XTXMAC_SW_RST");
  4532. }
  4533. static int niu_reset_tx_bmac(struct niu *np)
  4534. {
  4535. int limit;
  4536. nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
  4537. limit = 1000;
  4538. while (--limit >= 0) {
  4539. if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
  4540. break;
  4541. udelay(100);
  4542. }
  4543. if (limit < 0) {
  4544. dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
  4545. np->port,
  4546. (unsigned long long) nr64_mac(BTXMAC_SW_RST));
  4547. return -ENODEV;
  4548. }
  4549. return 0;
  4550. }
  4551. static int niu_reset_tx_mac(struct niu *np)
  4552. {
  4553. if (np->flags & NIU_FLAGS_XMAC)
  4554. return niu_reset_tx_xmac(np);
  4555. else
  4556. return niu_reset_tx_bmac(np);
  4557. }
  4558. static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
  4559. {
  4560. u64 val;
  4561. val = nr64_mac(XMAC_MIN);
  4562. val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
  4563. XMAC_MIN_RX_MIN_PKT_SIZE);
  4564. val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
  4565. val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
  4566. nw64_mac(XMAC_MIN, val);
  4567. nw64_mac(XMAC_MAX, max);
  4568. nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
  4569. val = nr64_mac(XMAC_IPG);
  4570. if (np->flags & NIU_FLAGS_10G) {
  4571. val &= ~XMAC_IPG_IPG_XGMII;
  4572. val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
  4573. } else {
  4574. val &= ~XMAC_IPG_IPG_MII_GMII;
  4575. val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
  4576. }
  4577. nw64_mac(XMAC_IPG, val);
  4578. val = nr64_mac(XMAC_CONFIG);
  4579. val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
  4580. XMAC_CONFIG_STRETCH_MODE |
  4581. XMAC_CONFIG_VAR_MIN_IPG_EN |
  4582. XMAC_CONFIG_TX_ENABLE);
  4583. nw64_mac(XMAC_CONFIG, val);
  4584. nw64_mac(TXMAC_FRM_CNT, 0);
  4585. nw64_mac(TXMAC_BYTE_CNT, 0);
  4586. }
  4587. static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
  4588. {
  4589. u64 val;
  4590. nw64_mac(BMAC_MIN_FRAME, min);
  4591. nw64_mac(BMAC_MAX_FRAME, max);
  4592. nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
  4593. nw64_mac(BMAC_CTRL_TYPE, 0x8808);
  4594. nw64_mac(BMAC_PREAMBLE_SIZE, 7);
  4595. val = nr64_mac(BTXMAC_CONFIG);
  4596. val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
  4597. BTXMAC_CONFIG_ENABLE);
  4598. nw64_mac(BTXMAC_CONFIG, val);
  4599. }
  4600. static void niu_init_tx_mac(struct niu *np)
  4601. {
  4602. u64 min, max;
  4603. min = 64;
  4604. if (np->dev->mtu > ETH_DATA_LEN)
  4605. max = 9216;
  4606. else
  4607. max = 1522;
  4608. /* The XMAC_MIN register only accepts values for TX min which
  4609. * have the low 3 bits cleared.
  4610. */
  4611. BUG_ON(min & 0x7);
  4612. if (np->flags & NIU_FLAGS_XMAC)
  4613. niu_init_tx_xmac(np, min, max);
  4614. else
  4615. niu_init_tx_bmac(np, min, max);
  4616. }
  4617. static int niu_reset_rx_xmac(struct niu *np)
  4618. {
  4619. int limit;
  4620. nw64_mac(XRXMAC_SW_RST,
  4621. XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
  4622. limit = 1000;
  4623. while (--limit >= 0) {
  4624. if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
  4625. XRXMAC_SW_RST_SOFT_RST)))
  4626. break;
  4627. udelay(100);
  4628. }
  4629. if (limit < 0) {
  4630. dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
  4631. np->port,
  4632. (unsigned long long) nr64_mac(XRXMAC_SW_RST));
  4633. return -ENODEV;
  4634. }
  4635. return 0;
  4636. }
  4637. static int niu_reset_rx_bmac(struct niu *np)
  4638. {
  4639. int limit;
  4640. nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
  4641. limit = 1000;
  4642. while (--limit >= 0) {
  4643. if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
  4644. break;
  4645. udelay(100);
  4646. }
  4647. if (limit < 0) {
  4648. dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
  4649. np->port,
  4650. (unsigned long long) nr64_mac(BRXMAC_SW_RST));
  4651. return -ENODEV;
  4652. }
  4653. return 0;
  4654. }
  4655. static int niu_reset_rx_mac(struct niu *np)
  4656. {
  4657. if (np->flags & NIU_FLAGS_XMAC)
  4658. return niu_reset_rx_xmac(np);
  4659. else
  4660. return niu_reset_rx_bmac(np);
  4661. }
  4662. static void niu_init_rx_xmac(struct niu *np)
  4663. {
  4664. struct niu_parent *parent = np->parent;
  4665. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
  4666. int first_rdc_table = tp->first_table_num;
  4667. unsigned long i;
  4668. u64 val;
  4669. nw64_mac(XMAC_ADD_FILT0, 0);
  4670. nw64_mac(XMAC_ADD_FILT1, 0);
  4671. nw64_mac(XMAC_ADD_FILT2, 0);
  4672. nw64_mac(XMAC_ADD_FILT12_MASK, 0);
  4673. nw64_mac(XMAC_ADD_FILT00_MASK, 0);
  4674. for (i = 0; i < MAC_NUM_HASH; i++)
  4675. nw64_mac(XMAC_HASH_TBL(i), 0);
  4676. nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
  4677. niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
  4678. niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
  4679. val = nr64_mac(XMAC_CONFIG);
  4680. val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
  4681. XMAC_CONFIG_PROMISCUOUS |
  4682. XMAC_CONFIG_PROMISC_GROUP |
  4683. XMAC_CONFIG_ERR_CHK_DIS |
  4684. XMAC_CONFIG_RX_CRC_CHK_DIS |
  4685. XMAC_CONFIG_RESERVED_MULTICAST |
  4686. XMAC_CONFIG_RX_CODEV_CHK_DIS |
  4687. XMAC_CONFIG_ADDR_FILTER_EN |
  4688. XMAC_CONFIG_RCV_PAUSE_ENABLE |
  4689. XMAC_CONFIG_STRIP_CRC |
  4690. XMAC_CONFIG_PASS_FLOW_CTRL |
  4691. XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
  4692. val |= (XMAC_CONFIG_HASH_FILTER_EN);
  4693. nw64_mac(XMAC_CONFIG, val);
  4694. nw64_mac(RXMAC_BT_CNT, 0);
  4695. nw64_mac(RXMAC_BC_FRM_CNT, 0);
  4696. nw64_mac(RXMAC_MC_FRM_CNT, 0);
  4697. nw64_mac(RXMAC_FRAG_CNT, 0);
  4698. nw64_mac(RXMAC_HIST_CNT1, 0);
  4699. nw64_mac(RXMAC_HIST_CNT2, 0);
  4700. nw64_mac(RXMAC_HIST_CNT3, 0);
  4701. nw64_mac(RXMAC_HIST_CNT4, 0);
  4702. nw64_mac(RXMAC_HIST_CNT5, 0);
  4703. nw64_mac(RXMAC_HIST_CNT6, 0);
  4704. nw64_mac(RXMAC_HIST_CNT7, 0);
  4705. nw64_mac(RXMAC_MPSZER_CNT, 0);
  4706. nw64_mac(RXMAC_CRC_ER_CNT, 0);
  4707. nw64_mac(RXMAC_CD_VIO_CNT, 0);
  4708. nw64_mac(LINK_FAULT_CNT, 0);
  4709. }
  4710. static void niu_init_rx_bmac(struct niu *np)
  4711. {
  4712. struct niu_parent *parent = np->parent;
  4713. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
  4714. int first_rdc_table = tp->first_table_num;
  4715. unsigned long i;
  4716. u64 val;
  4717. nw64_mac(BMAC_ADD_FILT0, 0);
  4718. nw64_mac(BMAC_ADD_FILT1, 0);
  4719. nw64_mac(BMAC_ADD_FILT2, 0);
  4720. nw64_mac(BMAC_ADD_FILT12_MASK, 0);
  4721. nw64_mac(BMAC_ADD_FILT00_MASK, 0);
  4722. for (i = 0; i < MAC_NUM_HASH; i++)
  4723. nw64_mac(BMAC_HASH_TBL(i), 0);
  4724. niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
  4725. niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
  4726. nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
  4727. val = nr64_mac(BRXMAC_CONFIG);
  4728. val &= ~(BRXMAC_CONFIG_ENABLE |
  4729. BRXMAC_CONFIG_STRIP_PAD |
  4730. BRXMAC_CONFIG_STRIP_FCS |
  4731. BRXMAC_CONFIG_PROMISC |
  4732. BRXMAC_CONFIG_PROMISC_GRP |
  4733. BRXMAC_CONFIG_ADDR_FILT_EN |
  4734. BRXMAC_CONFIG_DISCARD_DIS);
  4735. val |= (BRXMAC_CONFIG_HASH_FILT_EN);
  4736. nw64_mac(BRXMAC_CONFIG, val);
  4737. val = nr64_mac(BMAC_ADDR_CMPEN);
  4738. val |= BMAC_ADDR_CMPEN_EN0;
  4739. nw64_mac(BMAC_ADDR_CMPEN, val);
  4740. }
  4741. static void niu_init_rx_mac(struct niu *np)
  4742. {
  4743. niu_set_primary_mac(np, np->dev->dev_addr);
  4744. if (np->flags & NIU_FLAGS_XMAC)
  4745. niu_init_rx_xmac(np);
  4746. else
  4747. niu_init_rx_bmac(np);
  4748. }
  4749. static void niu_enable_tx_xmac(struct niu *np, int on)
  4750. {
  4751. u64 val = nr64_mac(XMAC_CONFIG);
  4752. if (on)
  4753. val |= XMAC_CONFIG_TX_ENABLE;
  4754. else
  4755. val &= ~XMAC_CONFIG_TX_ENABLE;
  4756. nw64_mac(XMAC_CONFIG, val);
  4757. }
  4758. static void niu_enable_tx_bmac(struct niu *np, int on)
  4759. {
  4760. u64 val = nr64_mac(BTXMAC_CONFIG);
  4761. if (on)
  4762. val |= BTXMAC_CONFIG_ENABLE;
  4763. else
  4764. val &= ~BTXMAC_CONFIG_ENABLE;
  4765. nw64_mac(BTXMAC_CONFIG, val);
  4766. }
  4767. static void niu_enable_tx_mac(struct niu *np, int on)
  4768. {
  4769. if (np->flags & NIU_FLAGS_XMAC)
  4770. niu_enable_tx_xmac(np, on);
  4771. else
  4772. niu_enable_tx_bmac(np, on);
  4773. }
  4774. static void niu_enable_rx_xmac(struct niu *np, int on)
  4775. {
  4776. u64 val = nr64_mac(XMAC_CONFIG);
  4777. val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
  4778. XMAC_CONFIG_PROMISCUOUS);
  4779. if (np->flags & NIU_FLAGS_MCAST)
  4780. val |= XMAC_CONFIG_HASH_FILTER_EN;
  4781. if (np->flags & NIU_FLAGS_PROMISC)
  4782. val |= XMAC_CONFIG_PROMISCUOUS;
  4783. if (on)
  4784. val |= XMAC_CONFIG_RX_MAC_ENABLE;
  4785. else
  4786. val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
  4787. nw64_mac(XMAC_CONFIG, val);
  4788. }
  4789. static void niu_enable_rx_bmac(struct niu *np, int on)
  4790. {
  4791. u64 val = nr64_mac(BRXMAC_CONFIG);
  4792. val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
  4793. BRXMAC_CONFIG_PROMISC);
  4794. if (np->flags & NIU_FLAGS_MCAST)
  4795. val |= BRXMAC_CONFIG_HASH_FILT_EN;
  4796. if (np->flags & NIU_FLAGS_PROMISC)
  4797. val |= BRXMAC_CONFIG_PROMISC;
  4798. if (on)
  4799. val |= BRXMAC_CONFIG_ENABLE;
  4800. else
  4801. val &= ~BRXMAC_CONFIG_ENABLE;
  4802. nw64_mac(BRXMAC_CONFIG, val);
  4803. }
  4804. static void niu_enable_rx_mac(struct niu *np, int on)
  4805. {
  4806. if (np->flags & NIU_FLAGS_XMAC)
  4807. niu_enable_rx_xmac(np, on);
  4808. else
  4809. niu_enable_rx_bmac(np, on);
  4810. }
  4811. static int niu_init_mac(struct niu *np)
  4812. {
  4813. int err;
  4814. niu_init_xif(np);
  4815. err = niu_init_pcs(np);
  4816. if (err)
  4817. return err;
  4818. err = niu_reset_tx_mac(np);
  4819. if (err)
  4820. return err;
  4821. niu_init_tx_mac(np);
  4822. err = niu_reset_rx_mac(np);
  4823. if (err)
  4824. return err;
  4825. niu_init_rx_mac(np);
  4826. /* This looks hookey but the RX MAC reset we just did will
  4827. * undo some of the state we setup in niu_init_tx_mac() so we
  4828. * have to call it again. In particular, the RX MAC reset will
  4829. * set the XMAC_MAX register back to it's default value.
  4830. */
  4831. niu_init_tx_mac(np);
  4832. niu_enable_tx_mac(np, 1);
  4833. niu_enable_rx_mac(np, 1);
  4834. return 0;
  4835. }
  4836. static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
  4837. {
  4838. (void) niu_tx_channel_stop(np, rp->tx_channel);
  4839. }
  4840. static void niu_stop_tx_channels(struct niu *np)
  4841. {
  4842. int i;
  4843. for (i = 0; i < np->num_tx_rings; i++) {
  4844. struct tx_ring_info *rp = &np->tx_rings[i];
  4845. niu_stop_one_tx_channel(np, rp);
  4846. }
  4847. }
  4848. static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
  4849. {
  4850. (void) niu_tx_channel_reset(np, rp->tx_channel);
  4851. }
  4852. static void niu_reset_tx_channels(struct niu *np)
  4853. {
  4854. int i;
  4855. for (i = 0; i < np->num_tx_rings; i++) {
  4856. struct tx_ring_info *rp = &np->tx_rings[i];
  4857. niu_reset_one_tx_channel(np, rp);
  4858. }
  4859. }
  4860. static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
  4861. {
  4862. (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
  4863. }
  4864. static void niu_stop_rx_channels(struct niu *np)
  4865. {
  4866. int i;
  4867. for (i = 0; i < np->num_rx_rings; i++) {
  4868. struct rx_ring_info *rp = &np->rx_rings[i];
  4869. niu_stop_one_rx_channel(np, rp);
  4870. }
  4871. }
  4872. static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
  4873. {
  4874. int channel = rp->rx_channel;
  4875. (void) niu_rx_channel_reset(np, channel);
  4876. nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
  4877. nw64(RX_DMA_CTL_STAT(channel), 0);
  4878. (void) niu_enable_rx_channel(np, channel, 0);
  4879. }
  4880. static void niu_reset_rx_channels(struct niu *np)
  4881. {
  4882. int i;
  4883. for (i = 0; i < np->num_rx_rings; i++) {
  4884. struct rx_ring_info *rp = &np->rx_rings[i];
  4885. niu_reset_one_rx_channel(np, rp);
  4886. }
  4887. }
  4888. static void niu_disable_ipp(struct niu *np)
  4889. {
  4890. u64 rd, wr, val;
  4891. int limit;
  4892. rd = nr64_ipp(IPP_DFIFO_RD_PTR);
  4893. wr = nr64_ipp(IPP_DFIFO_WR_PTR);
  4894. limit = 100;
  4895. while (--limit >= 0 && (rd != wr)) {
  4896. rd = nr64_ipp(IPP_DFIFO_RD_PTR);
  4897. wr = nr64_ipp(IPP_DFIFO_WR_PTR);
  4898. }
  4899. if (limit < 0 &&
  4900. (rd != 0 && wr != 1)) {
  4901. netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
  4902. (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
  4903. (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
  4904. }
  4905. val = nr64_ipp(IPP_CFIG);
  4906. val &= ~(IPP_CFIG_IPP_ENABLE |
  4907. IPP_CFIG_DFIFO_ECC_EN |
  4908. IPP_CFIG_DROP_BAD_CRC |
  4909. IPP_CFIG_CKSUM_EN);
  4910. nw64_ipp(IPP_CFIG, val);
  4911. (void) niu_ipp_reset(np);
  4912. }
  4913. static int niu_init_hw(struct niu *np)
  4914. {
  4915. int i, err;
  4916. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
  4917. niu_txc_enable_port(np, 1);
  4918. niu_txc_port_dma_enable(np, 1);
  4919. niu_txc_set_imask(np, 0);
  4920. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
  4921. for (i = 0; i < np->num_tx_rings; i++) {
  4922. struct tx_ring_info *rp = &np->tx_rings[i];
  4923. err = niu_init_one_tx_channel(np, rp);
  4924. if (err)
  4925. return err;
  4926. }
  4927. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
  4928. err = niu_init_rx_channels(np);
  4929. if (err)
  4930. goto out_uninit_tx_channels;
  4931. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
  4932. err = niu_init_classifier_hw(np);
  4933. if (err)
  4934. goto out_uninit_rx_channels;
  4935. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
  4936. err = niu_init_zcp(np);
  4937. if (err)
  4938. goto out_uninit_rx_channels;
  4939. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
  4940. err = niu_init_ipp(np);
  4941. if (err)
  4942. goto out_uninit_rx_channels;
  4943. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
  4944. err = niu_init_mac(np);
  4945. if (err)
  4946. goto out_uninit_ipp;
  4947. return 0;
  4948. out_uninit_ipp:
  4949. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
  4950. niu_disable_ipp(np);
  4951. out_uninit_rx_channels:
  4952. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
  4953. niu_stop_rx_channels(np);
  4954. niu_reset_rx_channels(np);
  4955. out_uninit_tx_channels:
  4956. netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
  4957. niu_stop_tx_channels(np);
  4958. niu_reset_tx_channels(np);
  4959. return err;
  4960. }
  4961. static void niu_stop_hw(struct niu *np)
  4962. {
  4963. netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
  4964. niu_enable_interrupts(np, 0);
  4965. netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
  4966. niu_enable_rx_mac(np, 0);
  4967. netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
  4968. niu_disable_ipp(np);
  4969. netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
  4970. niu_stop_tx_channels(np);
  4971. netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
  4972. niu_stop_rx_channels(np);
  4973. netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
  4974. niu_reset_tx_channels(np);
  4975. netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
  4976. niu_reset_rx_channels(np);
  4977. }
  4978. static void niu_set_irq_name(struct niu *np)
  4979. {
  4980. int port = np->port;
  4981. int i, j = 1;
  4982. sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
  4983. if (port == 0) {
  4984. sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
  4985. sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
  4986. j = 3;
  4987. }
  4988. for (i = 0; i < np->num_ldg - j; i++) {
  4989. if (i < np->num_rx_rings)
  4990. sprintf(np->irq_name[i+j], "%s-rx-%d",
  4991. np->dev->name, i);
  4992. else if (i < np->num_tx_rings + np->num_rx_rings)
  4993. sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
  4994. i - np->num_rx_rings);
  4995. }
  4996. }
  4997. static int niu_request_irq(struct niu *np)
  4998. {
  4999. int i, j, err;
  5000. niu_set_irq_name(np);
  5001. err = 0;
  5002. for (i = 0; i < np->num_ldg; i++) {
  5003. struct niu_ldg *lp = &np->ldg[i];
  5004. err = request_irq(lp->irq, niu_interrupt,
  5005. IRQF_SHARED | IRQF_SAMPLE_RANDOM,
  5006. np->irq_name[i], lp);
  5007. if (err)
  5008. goto out_free_irqs;
  5009. }
  5010. return 0;
  5011. out_free_irqs:
  5012. for (j = 0; j < i; j++) {
  5013. struct niu_ldg *lp = &np->ldg[j];
  5014. free_irq(lp->irq, lp);
  5015. }
  5016. return err;
  5017. }
  5018. static void niu_free_irq(struct niu *np)
  5019. {
  5020. int i;
  5021. for (i = 0; i < np->num_ldg; i++) {
  5022. struct niu_ldg *lp = &np->ldg[i];
  5023. free_irq(lp->irq, lp);
  5024. }
  5025. }
  5026. static void niu_enable_napi(struct niu *np)
  5027. {
  5028. int i;
  5029. for (i = 0; i < np->num_ldg; i++)
  5030. napi_enable(&np->ldg[i].napi);
  5031. }
  5032. static void niu_disable_napi(struct niu *np)
  5033. {
  5034. int i;
  5035. for (i = 0; i < np->num_ldg; i++)
  5036. napi_disable(&np->ldg[i].napi);
  5037. }
  5038. static int niu_open(struct net_device *dev)
  5039. {
  5040. struct niu *np = netdev_priv(dev);
  5041. int err;
  5042. netif_carrier_off(dev);
  5043. err = niu_alloc_channels(np);
  5044. if (err)
  5045. goto out_err;
  5046. err = niu_enable_interrupts(np, 0);
  5047. if (err)
  5048. goto out_free_channels;
  5049. err = niu_request_irq(np);
  5050. if (err)
  5051. goto out_free_channels;
  5052. niu_enable_napi(np);
  5053. spin_lock_irq(&np->lock);
  5054. err = niu_init_hw(np);
  5055. if (!err) {
  5056. init_timer(&np->timer);
  5057. np->timer.expires = jiffies + HZ;
  5058. np->timer.data = (unsigned long) np;
  5059. np->timer.function = niu_timer;
  5060. err = niu_enable_interrupts(np, 1);
  5061. if (err)
  5062. niu_stop_hw(np);
  5063. }
  5064. spin_unlock_irq(&np->lock);
  5065. if (err) {
  5066. niu_disable_napi(np);
  5067. goto out_free_irq;
  5068. }
  5069. netif_tx_start_all_queues(dev);
  5070. if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
  5071. netif_carrier_on(dev);
  5072. add_timer(&np->timer);
  5073. return 0;
  5074. out_free_irq:
  5075. niu_free_irq(np);
  5076. out_free_channels:
  5077. niu_free_channels(np);
  5078. out_err:
  5079. return err;
  5080. }
  5081. static void niu_full_shutdown(struct niu *np, struct net_device *dev)
  5082. {
  5083. cancel_work_sync(&np->reset_task);
  5084. niu_disable_napi(np);
  5085. netif_tx_stop_all_queues(dev);
  5086. del_timer_sync(&np->timer);
  5087. spin_lock_irq(&np->lock);
  5088. niu_stop_hw(np);
  5089. spin_unlock_irq(&np->lock);
  5090. }
  5091. static int niu_close(struct net_device *dev)
  5092. {
  5093. struct niu *np = netdev_priv(dev);
  5094. niu_full_shutdown(np, dev);
  5095. niu_free_irq(np);
  5096. niu_free_channels(np);
  5097. niu_handle_led(np, 0);
  5098. return 0;
  5099. }
  5100. static void niu_sync_xmac_stats(struct niu *np)
  5101. {
  5102. struct niu_xmac_stats *mp = &np->mac_stats.xmac;
  5103. mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
  5104. mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
  5105. mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
  5106. mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
  5107. mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
  5108. mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
  5109. mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
  5110. mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
  5111. mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
  5112. mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
  5113. mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
  5114. mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
  5115. mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
  5116. mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
  5117. mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
  5118. mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
  5119. mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
  5120. mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
  5121. }
  5122. static void niu_sync_bmac_stats(struct niu *np)
  5123. {
  5124. struct niu_bmac_stats *mp = &np->mac_stats.bmac;
  5125. mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
  5126. mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
  5127. mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
  5128. mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
  5129. mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
  5130. mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
  5131. }
  5132. static void niu_sync_mac_stats(struct niu *np)
  5133. {
  5134. if (np->flags & NIU_FLAGS_XMAC)
  5135. niu_sync_xmac_stats(np);
  5136. else
  5137. niu_sync_bmac_stats(np);
  5138. }
  5139. static void niu_get_rx_stats(struct niu *np)
  5140. {
  5141. unsigned long pkts, dropped, errors, bytes;
  5142. int i;
  5143. pkts = dropped = errors = bytes = 0;
  5144. for (i = 0; i < np->num_rx_rings; i++) {
  5145. struct rx_ring_info *rp = &np->rx_rings[i];
  5146. niu_sync_rx_discard_stats(np, rp, 0);
  5147. pkts += rp->rx_packets;
  5148. bytes += rp->rx_bytes;
  5149. dropped += rp->rx_dropped;
  5150. errors += rp->rx_errors;
  5151. }
  5152. np->dev->stats.rx_packets = pkts;
  5153. np->dev->stats.rx_bytes = bytes;
  5154. np->dev->stats.rx_dropped = dropped;
  5155. np->dev->stats.rx_errors = errors;
  5156. }
  5157. static void niu_get_tx_stats(struct niu *np)
  5158. {
  5159. unsigned long pkts, errors, bytes;
  5160. int i;
  5161. pkts = errors = bytes = 0;
  5162. for (i = 0; i < np->num_tx_rings; i++) {
  5163. struct tx_ring_info *rp = &np->tx_rings[i];
  5164. pkts += rp->tx_packets;
  5165. bytes += rp->tx_bytes;
  5166. errors += rp->tx_errors;
  5167. }
  5168. np->dev->stats.tx_packets = pkts;
  5169. np->dev->stats.tx_bytes = bytes;
  5170. np->dev->stats.tx_errors = errors;
  5171. }
  5172. static struct net_device_stats *niu_get_stats(struct net_device *dev)
  5173. {
  5174. struct niu *np = netdev_priv(dev);
  5175. niu_get_rx_stats(np);
  5176. niu_get_tx_stats(np);
  5177. return &dev->stats;
  5178. }
  5179. static void niu_load_hash_xmac(struct niu *np, u16 *hash)
  5180. {
  5181. int i;
  5182. for (i = 0; i < 16; i++)
  5183. nw64_mac(XMAC_HASH_TBL(i), hash[i]);
  5184. }
  5185. static void niu_load_hash_bmac(struct niu *np, u16 *hash)
  5186. {
  5187. int i;
  5188. for (i = 0; i < 16; i++)
  5189. nw64_mac(BMAC_HASH_TBL(i), hash[i]);
  5190. }
  5191. static void niu_load_hash(struct niu *np, u16 *hash)
  5192. {
  5193. if (np->flags & NIU_FLAGS_XMAC)
  5194. niu_load_hash_xmac(np, hash);
  5195. else
  5196. niu_load_hash_bmac(np, hash);
  5197. }
  5198. static void niu_set_rx_mode(struct net_device *dev)
  5199. {
  5200. struct niu *np = netdev_priv(dev);
  5201. int i, alt_cnt, err;
  5202. struct netdev_hw_addr *ha;
  5203. unsigned long flags;
  5204. u16 hash[16] = { 0, };
  5205. spin_lock_irqsave(&np->lock, flags);
  5206. niu_enable_rx_mac(np, 0);
  5207. np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
  5208. if (dev->flags & IFF_PROMISC)
  5209. np->flags |= NIU_FLAGS_PROMISC;
  5210. if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
  5211. np->flags |= NIU_FLAGS_MCAST;
  5212. alt_cnt = netdev_uc_count(dev);
  5213. if (alt_cnt > niu_num_alt_addr(np)) {
  5214. alt_cnt = 0;
  5215. np->flags |= NIU_FLAGS_PROMISC;
  5216. }
  5217. if (alt_cnt) {
  5218. int index = 0;
  5219. netdev_for_each_uc_addr(ha, dev) {
  5220. err = niu_set_alt_mac(np, index, ha->addr);
  5221. if (err)
  5222. netdev_warn(dev, "Error %d adding alt mac %d\n",
  5223. err, index);
  5224. err = niu_enable_alt_mac(np, index, 1);
  5225. if (err)
  5226. netdev_warn(dev, "Error %d enabling alt mac %d\n",
  5227. err, index);
  5228. index++;
  5229. }
  5230. } else {
  5231. int alt_start;
  5232. if (np->flags & NIU_FLAGS_XMAC)
  5233. alt_start = 0;
  5234. else
  5235. alt_start = 1;
  5236. for (i = alt_start; i < niu_num_alt_addr(np); i++) {
  5237. err = niu_enable_alt_mac(np, i, 0);
  5238. if (err)
  5239. netdev_warn(dev, "Error %d disabling alt mac %d\n",
  5240. err, i);
  5241. }
  5242. }
  5243. if (dev->flags & IFF_ALLMULTI) {
  5244. for (i = 0; i < 16; i++)
  5245. hash[i] = 0xffff;
  5246. } else if (!netdev_mc_empty(dev)) {
  5247. netdev_for_each_mc_addr(ha, dev) {
  5248. u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
  5249. crc >>= 24;
  5250. hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
  5251. }
  5252. }
  5253. if (np->flags & NIU_FLAGS_MCAST)
  5254. niu_load_hash(np, hash);
  5255. niu_enable_rx_mac(np, 1);
  5256. spin_unlock_irqrestore(&np->lock, flags);
  5257. }
  5258. static int niu_set_mac_addr(struct net_device *dev, void *p)
  5259. {
  5260. struct niu *np = netdev_priv(dev);
  5261. struct sockaddr *addr = p;
  5262. unsigned long flags;
  5263. if (!is_valid_ether_addr(addr->sa_data))
  5264. return -EINVAL;
  5265. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  5266. if (!netif_running(dev))
  5267. return 0;
  5268. spin_lock_irqsave(&np->lock, flags);
  5269. niu_enable_rx_mac(np, 0);
  5270. niu_set_primary_mac(np, dev->dev_addr);
  5271. niu_enable_rx_mac(np, 1);
  5272. spin_unlock_irqrestore(&np->lock, flags);
  5273. return 0;
  5274. }
  5275. static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  5276. {
  5277. return -EOPNOTSUPP;
  5278. }
  5279. static void niu_netif_stop(struct niu *np)
  5280. {
  5281. np->dev->trans_start = jiffies; /* prevent tx timeout */
  5282. niu_disable_napi(np);
  5283. netif_tx_disable(np->dev);
  5284. }
  5285. static void niu_netif_start(struct niu *np)
  5286. {
  5287. /* NOTE: unconditional netif_wake_queue is only appropriate
  5288. * so long as all callers are assured to have free tx slots
  5289. * (such as after niu_init_hw).
  5290. */
  5291. netif_tx_wake_all_queues(np->dev);
  5292. niu_enable_napi(np);
  5293. niu_enable_interrupts(np, 1);
  5294. }
  5295. static void niu_reset_buffers(struct niu *np)
  5296. {
  5297. int i, j, k, err;
  5298. if (np->rx_rings) {
  5299. for (i = 0; i < np->num_rx_rings; i++) {
  5300. struct rx_ring_info *rp = &np->rx_rings[i];
  5301. for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
  5302. struct page *page;
  5303. page = rp->rxhash[j];
  5304. while (page) {
  5305. struct page *next =
  5306. (struct page *) page->mapping;
  5307. u64 base = page->index;
  5308. base = base >> RBR_DESCR_ADDR_SHIFT;
  5309. rp->rbr[k++] = cpu_to_le32(base);
  5310. page = next;
  5311. }
  5312. }
  5313. for (; k < MAX_RBR_RING_SIZE; k++) {
  5314. err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
  5315. if (unlikely(err))
  5316. break;
  5317. }
  5318. rp->rbr_index = rp->rbr_table_size - 1;
  5319. rp->rcr_index = 0;
  5320. rp->rbr_pending = 0;
  5321. rp->rbr_refill_pending = 0;
  5322. }
  5323. }
  5324. if (np->tx_rings) {
  5325. for (i = 0; i < np->num_tx_rings; i++) {
  5326. struct tx_ring_info *rp = &np->tx_rings[i];
  5327. for (j = 0; j < MAX_TX_RING_SIZE; j++) {
  5328. if (rp->tx_buffs[j].skb)
  5329. (void) release_tx_packet(np, rp, j);
  5330. }
  5331. rp->pending = MAX_TX_RING_SIZE;
  5332. rp->prod = 0;
  5333. rp->cons = 0;
  5334. rp->wrap_bit = 0;
  5335. }
  5336. }
  5337. }
  5338. static void niu_reset_task(struct work_struct *work)
  5339. {
  5340. struct niu *np = container_of(work, struct niu, reset_task);
  5341. unsigned long flags;
  5342. int err;
  5343. spin_lock_irqsave(&np->lock, flags);
  5344. if (!netif_running(np->dev)) {
  5345. spin_unlock_irqrestore(&np->lock, flags);
  5346. return;
  5347. }
  5348. spin_unlock_irqrestore(&np->lock, flags);
  5349. del_timer_sync(&np->timer);
  5350. niu_netif_stop(np);
  5351. spin_lock_irqsave(&np->lock, flags);
  5352. niu_stop_hw(np);
  5353. spin_unlock_irqrestore(&np->lock, flags);
  5354. niu_reset_buffers(np);
  5355. spin_lock_irqsave(&np->lock, flags);
  5356. err = niu_init_hw(np);
  5357. if (!err) {
  5358. np->timer.expires = jiffies + HZ;
  5359. add_timer(&np->timer);
  5360. niu_netif_start(np);
  5361. }
  5362. spin_unlock_irqrestore(&np->lock, flags);
  5363. }
  5364. static void niu_tx_timeout(struct net_device *dev)
  5365. {
  5366. struct niu *np = netdev_priv(dev);
  5367. dev_err(np->device, "%s: Transmit timed out, resetting\n",
  5368. dev->name);
  5369. schedule_work(&np->reset_task);
  5370. }
  5371. static void niu_set_txd(struct tx_ring_info *rp, int index,
  5372. u64 mapping, u64 len, u64 mark,
  5373. u64 n_frags)
  5374. {
  5375. __le64 *desc = &rp->descr[index];
  5376. *desc = cpu_to_le64(mark |
  5377. (n_frags << TX_DESC_NUM_PTR_SHIFT) |
  5378. (len << TX_DESC_TR_LEN_SHIFT) |
  5379. (mapping & TX_DESC_SAD));
  5380. }
  5381. static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
  5382. u64 pad_bytes, u64 len)
  5383. {
  5384. u16 eth_proto, eth_proto_inner;
  5385. u64 csum_bits, l3off, ihl, ret;
  5386. u8 ip_proto;
  5387. int ipv6;
  5388. eth_proto = be16_to_cpu(ehdr->h_proto);
  5389. eth_proto_inner = eth_proto;
  5390. if (eth_proto == ETH_P_8021Q) {
  5391. struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
  5392. __be16 val = vp->h_vlan_encapsulated_proto;
  5393. eth_proto_inner = be16_to_cpu(val);
  5394. }
  5395. ipv6 = ihl = 0;
  5396. switch (skb->protocol) {
  5397. case cpu_to_be16(ETH_P_IP):
  5398. ip_proto = ip_hdr(skb)->protocol;
  5399. ihl = ip_hdr(skb)->ihl;
  5400. break;
  5401. case cpu_to_be16(ETH_P_IPV6):
  5402. ip_proto = ipv6_hdr(skb)->nexthdr;
  5403. ihl = (40 >> 2);
  5404. ipv6 = 1;
  5405. break;
  5406. default:
  5407. ip_proto = ihl = 0;
  5408. break;
  5409. }
  5410. csum_bits = TXHDR_CSUM_NONE;
  5411. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  5412. u64 start, stuff;
  5413. csum_bits = (ip_proto == IPPROTO_TCP ?
  5414. TXHDR_CSUM_TCP :
  5415. (ip_proto == IPPROTO_UDP ?
  5416. TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
  5417. start = skb_transport_offset(skb) -
  5418. (pad_bytes + sizeof(struct tx_pkt_hdr));
  5419. stuff = start + skb->csum_offset;
  5420. csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
  5421. csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
  5422. }
  5423. l3off = skb_network_offset(skb) -
  5424. (pad_bytes + sizeof(struct tx_pkt_hdr));
  5425. ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
  5426. (len << TXHDR_LEN_SHIFT) |
  5427. ((l3off / 2) << TXHDR_L3START_SHIFT) |
  5428. (ihl << TXHDR_IHL_SHIFT) |
  5429. ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
  5430. ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
  5431. (ipv6 ? TXHDR_IP_VER : 0) |
  5432. csum_bits);
  5433. return ret;
  5434. }
  5435. static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
  5436. struct net_device *dev)
  5437. {
  5438. struct niu *np = netdev_priv(dev);
  5439. unsigned long align, headroom;
  5440. struct netdev_queue *txq;
  5441. struct tx_ring_info *rp;
  5442. struct tx_pkt_hdr *tp;
  5443. unsigned int len, nfg;
  5444. struct ethhdr *ehdr;
  5445. int prod, i, tlen;
  5446. u64 mapping, mrk;
  5447. i = skb_get_queue_mapping(skb);
  5448. rp = &np->tx_rings[i];
  5449. txq = netdev_get_tx_queue(dev, i);
  5450. if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
  5451. netif_tx_stop_queue(txq);
  5452. dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
  5453. rp->tx_errors++;
  5454. return NETDEV_TX_BUSY;
  5455. }
  5456. if (skb->len < ETH_ZLEN) {
  5457. unsigned int pad_bytes = ETH_ZLEN - skb->len;
  5458. if (skb_pad(skb, pad_bytes))
  5459. goto out;
  5460. skb_put(skb, pad_bytes);
  5461. }
  5462. len = sizeof(struct tx_pkt_hdr) + 15;
  5463. if (skb_headroom(skb) < len) {
  5464. struct sk_buff *skb_new;
  5465. skb_new = skb_realloc_headroom(skb, len);
  5466. if (!skb_new) {
  5467. rp->tx_errors++;
  5468. goto out_drop;
  5469. }
  5470. kfree_skb(skb);
  5471. skb = skb_new;
  5472. } else
  5473. skb_orphan(skb);
  5474. align = ((unsigned long) skb->data & (16 - 1));
  5475. headroom = align + sizeof(struct tx_pkt_hdr);
  5476. ehdr = (struct ethhdr *) skb->data;
  5477. tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
  5478. len = skb->len - sizeof(struct tx_pkt_hdr);
  5479. tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
  5480. tp->resv = 0;
  5481. len = skb_headlen(skb);
  5482. mapping = np->ops->map_single(np->device, skb->data,
  5483. len, DMA_TO_DEVICE);
  5484. prod = rp->prod;
  5485. rp->tx_buffs[prod].skb = skb;
  5486. rp->tx_buffs[prod].mapping = mapping;
  5487. mrk = TX_DESC_SOP;
  5488. if (++rp->mark_counter == rp->mark_freq) {
  5489. rp->mark_counter = 0;
  5490. mrk |= TX_DESC_MARK;
  5491. rp->mark_pending++;
  5492. }
  5493. tlen = len;
  5494. nfg = skb_shinfo(skb)->nr_frags;
  5495. while (tlen > 0) {
  5496. tlen -= MAX_TX_DESC_LEN;
  5497. nfg++;
  5498. }
  5499. while (len > 0) {
  5500. unsigned int this_len = len;
  5501. if (this_len > MAX_TX_DESC_LEN)
  5502. this_len = MAX_TX_DESC_LEN;
  5503. niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
  5504. mrk = nfg = 0;
  5505. prod = NEXT_TX(rp, prod);
  5506. mapping += this_len;
  5507. len -= this_len;
  5508. }
  5509. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  5510. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  5511. len = frag->size;
  5512. mapping = np->ops->map_page(np->device, frag->page,
  5513. frag->page_offset, len,
  5514. DMA_TO_DEVICE);
  5515. rp->tx_buffs[prod].skb = NULL;
  5516. rp->tx_buffs[prod].mapping = mapping;
  5517. niu_set_txd(rp, prod, mapping, len, 0, 0);
  5518. prod = NEXT_TX(rp, prod);
  5519. }
  5520. if (prod < rp->prod)
  5521. rp->wrap_bit ^= TX_RING_KICK_WRAP;
  5522. rp->prod = prod;
  5523. nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
  5524. if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
  5525. netif_tx_stop_queue(txq);
  5526. if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
  5527. netif_tx_wake_queue(txq);
  5528. }
  5529. out:
  5530. return NETDEV_TX_OK;
  5531. out_drop:
  5532. rp->tx_errors++;
  5533. kfree_skb(skb);
  5534. goto out;
  5535. }
  5536. static int niu_change_mtu(struct net_device *dev, int new_mtu)
  5537. {
  5538. struct niu *np = netdev_priv(dev);
  5539. int err, orig_jumbo, new_jumbo;
  5540. if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
  5541. return -EINVAL;
  5542. orig_jumbo = (dev->mtu > ETH_DATA_LEN);
  5543. new_jumbo = (new_mtu > ETH_DATA_LEN);
  5544. dev->mtu = new_mtu;
  5545. if (!netif_running(dev) ||
  5546. (orig_jumbo == new_jumbo))
  5547. return 0;
  5548. niu_full_shutdown(np, dev);
  5549. niu_free_channels(np);
  5550. niu_enable_napi(np);
  5551. err = niu_alloc_channels(np);
  5552. if (err)
  5553. return err;
  5554. spin_lock_irq(&np->lock);
  5555. err = niu_init_hw(np);
  5556. if (!err) {
  5557. init_timer(&np->timer);
  5558. np->timer.expires = jiffies + HZ;
  5559. np->timer.data = (unsigned long) np;
  5560. np->timer.function = niu_timer;
  5561. err = niu_enable_interrupts(np, 1);
  5562. if (err)
  5563. niu_stop_hw(np);
  5564. }
  5565. spin_unlock_irq(&np->lock);
  5566. if (!err) {
  5567. netif_tx_start_all_queues(dev);
  5568. if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
  5569. netif_carrier_on(dev);
  5570. add_timer(&np->timer);
  5571. }
  5572. return err;
  5573. }
  5574. static void niu_get_drvinfo(struct net_device *dev,
  5575. struct ethtool_drvinfo *info)
  5576. {
  5577. struct niu *np = netdev_priv(dev);
  5578. struct niu_vpd *vpd = &np->vpd;
  5579. strcpy(info->driver, DRV_MODULE_NAME);
  5580. strcpy(info->version, DRV_MODULE_VERSION);
  5581. sprintf(info->fw_version, "%d.%d",
  5582. vpd->fcode_major, vpd->fcode_minor);
  5583. if (np->parent->plat_type != PLAT_TYPE_NIU)
  5584. strcpy(info->bus_info, pci_name(np->pdev));
  5585. }
  5586. static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5587. {
  5588. struct niu *np = netdev_priv(dev);
  5589. struct niu_link_config *lp;
  5590. lp = &np->link_config;
  5591. memset(cmd, 0, sizeof(*cmd));
  5592. cmd->phy_address = np->phy_addr;
  5593. cmd->supported = lp->supported;
  5594. cmd->advertising = lp->active_advertising;
  5595. cmd->autoneg = lp->active_autoneg;
  5596. cmd->speed = lp->active_speed;
  5597. cmd->duplex = lp->active_duplex;
  5598. cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
  5599. cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
  5600. XCVR_EXTERNAL : XCVR_INTERNAL;
  5601. return 0;
  5602. }
  5603. static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5604. {
  5605. struct niu *np = netdev_priv(dev);
  5606. struct niu_link_config *lp = &np->link_config;
  5607. lp->advertising = cmd->advertising;
  5608. lp->speed = cmd->speed;
  5609. lp->duplex = cmd->duplex;
  5610. lp->autoneg = cmd->autoneg;
  5611. return niu_init_link(np);
  5612. }
  5613. static u32 niu_get_msglevel(struct net_device *dev)
  5614. {
  5615. struct niu *np = netdev_priv(dev);
  5616. return np->msg_enable;
  5617. }
  5618. static void niu_set_msglevel(struct net_device *dev, u32 value)
  5619. {
  5620. struct niu *np = netdev_priv(dev);
  5621. np->msg_enable = value;
  5622. }
  5623. static int niu_nway_reset(struct net_device *dev)
  5624. {
  5625. struct niu *np = netdev_priv(dev);
  5626. if (np->link_config.autoneg)
  5627. return niu_init_link(np);
  5628. return 0;
  5629. }
  5630. static int niu_get_eeprom_len(struct net_device *dev)
  5631. {
  5632. struct niu *np = netdev_priv(dev);
  5633. return np->eeprom_len;
  5634. }
  5635. static int niu_get_eeprom(struct net_device *dev,
  5636. struct ethtool_eeprom *eeprom, u8 *data)
  5637. {
  5638. struct niu *np = netdev_priv(dev);
  5639. u32 offset, len, val;
  5640. offset = eeprom->offset;
  5641. len = eeprom->len;
  5642. if (offset + len < offset)
  5643. return -EINVAL;
  5644. if (offset >= np->eeprom_len)
  5645. return -EINVAL;
  5646. if (offset + len > np->eeprom_len)
  5647. len = eeprom->len = np->eeprom_len - offset;
  5648. if (offset & 3) {
  5649. u32 b_offset, b_count;
  5650. b_offset = offset & 3;
  5651. b_count = 4 - b_offset;
  5652. if (b_count > len)
  5653. b_count = len;
  5654. val = nr64(ESPC_NCR((offset - b_offset) / 4));
  5655. memcpy(data, ((char *)&val) + b_offset, b_count);
  5656. data += b_count;
  5657. len -= b_count;
  5658. offset += b_count;
  5659. }
  5660. while (len >= 4) {
  5661. val = nr64(ESPC_NCR(offset / 4));
  5662. memcpy(data, &val, 4);
  5663. data += 4;
  5664. len -= 4;
  5665. offset += 4;
  5666. }
  5667. if (len) {
  5668. val = nr64(ESPC_NCR(offset / 4));
  5669. memcpy(data, &val, len);
  5670. }
  5671. return 0;
  5672. }
  5673. static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
  5674. {
  5675. switch (flow_type) {
  5676. case TCP_V4_FLOW:
  5677. case TCP_V6_FLOW:
  5678. *pid = IPPROTO_TCP;
  5679. break;
  5680. case UDP_V4_FLOW:
  5681. case UDP_V6_FLOW:
  5682. *pid = IPPROTO_UDP;
  5683. break;
  5684. case SCTP_V4_FLOW:
  5685. case SCTP_V6_FLOW:
  5686. *pid = IPPROTO_SCTP;
  5687. break;
  5688. case AH_V4_FLOW:
  5689. case AH_V6_FLOW:
  5690. *pid = IPPROTO_AH;
  5691. break;
  5692. case ESP_V4_FLOW:
  5693. case ESP_V6_FLOW:
  5694. *pid = IPPROTO_ESP;
  5695. break;
  5696. default:
  5697. *pid = 0;
  5698. break;
  5699. }
  5700. }
  5701. static int niu_class_to_ethflow(u64 class, int *flow_type)
  5702. {
  5703. switch (class) {
  5704. case CLASS_CODE_TCP_IPV4:
  5705. *flow_type = TCP_V4_FLOW;
  5706. break;
  5707. case CLASS_CODE_UDP_IPV4:
  5708. *flow_type = UDP_V4_FLOW;
  5709. break;
  5710. case CLASS_CODE_AH_ESP_IPV4:
  5711. *flow_type = AH_V4_FLOW;
  5712. break;
  5713. case CLASS_CODE_SCTP_IPV4:
  5714. *flow_type = SCTP_V4_FLOW;
  5715. break;
  5716. case CLASS_CODE_TCP_IPV6:
  5717. *flow_type = TCP_V6_FLOW;
  5718. break;
  5719. case CLASS_CODE_UDP_IPV6:
  5720. *flow_type = UDP_V6_FLOW;
  5721. break;
  5722. case CLASS_CODE_AH_ESP_IPV6:
  5723. *flow_type = AH_V6_FLOW;
  5724. break;
  5725. case CLASS_CODE_SCTP_IPV6:
  5726. *flow_type = SCTP_V6_FLOW;
  5727. break;
  5728. case CLASS_CODE_USER_PROG1:
  5729. case CLASS_CODE_USER_PROG2:
  5730. case CLASS_CODE_USER_PROG3:
  5731. case CLASS_CODE_USER_PROG4:
  5732. *flow_type = IP_USER_FLOW;
  5733. break;
  5734. default:
  5735. return 0;
  5736. }
  5737. return 1;
  5738. }
  5739. static int niu_ethflow_to_class(int flow_type, u64 *class)
  5740. {
  5741. switch (flow_type) {
  5742. case TCP_V4_FLOW:
  5743. *class = CLASS_CODE_TCP_IPV4;
  5744. break;
  5745. case UDP_V4_FLOW:
  5746. *class = CLASS_CODE_UDP_IPV4;
  5747. break;
  5748. case AH_V4_FLOW:
  5749. case ESP_V4_FLOW:
  5750. *class = CLASS_CODE_AH_ESP_IPV4;
  5751. break;
  5752. case SCTP_V4_FLOW:
  5753. *class = CLASS_CODE_SCTP_IPV4;
  5754. break;
  5755. case TCP_V6_FLOW:
  5756. *class = CLASS_CODE_TCP_IPV6;
  5757. break;
  5758. case UDP_V6_FLOW:
  5759. *class = CLASS_CODE_UDP_IPV6;
  5760. break;
  5761. case AH_V6_FLOW:
  5762. case ESP_V6_FLOW:
  5763. *class = CLASS_CODE_AH_ESP_IPV6;
  5764. break;
  5765. case SCTP_V6_FLOW:
  5766. *class = CLASS_CODE_SCTP_IPV6;
  5767. break;
  5768. default:
  5769. return 0;
  5770. }
  5771. return 1;
  5772. }
  5773. static u64 niu_flowkey_to_ethflow(u64 flow_key)
  5774. {
  5775. u64 ethflow = 0;
  5776. if (flow_key & FLOW_KEY_L2DA)
  5777. ethflow |= RXH_L2DA;
  5778. if (flow_key & FLOW_KEY_VLAN)
  5779. ethflow |= RXH_VLAN;
  5780. if (flow_key & FLOW_KEY_IPSA)
  5781. ethflow |= RXH_IP_SRC;
  5782. if (flow_key & FLOW_KEY_IPDA)
  5783. ethflow |= RXH_IP_DST;
  5784. if (flow_key & FLOW_KEY_PROTO)
  5785. ethflow |= RXH_L3_PROTO;
  5786. if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
  5787. ethflow |= RXH_L4_B_0_1;
  5788. if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
  5789. ethflow |= RXH_L4_B_2_3;
  5790. return ethflow;
  5791. }
  5792. static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
  5793. {
  5794. u64 key = 0;
  5795. if (ethflow & RXH_L2DA)
  5796. key |= FLOW_KEY_L2DA;
  5797. if (ethflow & RXH_VLAN)
  5798. key |= FLOW_KEY_VLAN;
  5799. if (ethflow & RXH_IP_SRC)
  5800. key |= FLOW_KEY_IPSA;
  5801. if (ethflow & RXH_IP_DST)
  5802. key |= FLOW_KEY_IPDA;
  5803. if (ethflow & RXH_L3_PROTO)
  5804. key |= FLOW_KEY_PROTO;
  5805. if (ethflow & RXH_L4_B_0_1)
  5806. key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
  5807. if (ethflow & RXH_L4_B_2_3)
  5808. key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
  5809. *flow_key = key;
  5810. return 1;
  5811. }
  5812. static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
  5813. {
  5814. u64 class;
  5815. nfc->data = 0;
  5816. if (!niu_ethflow_to_class(nfc->flow_type, &class))
  5817. return -EINVAL;
  5818. if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
  5819. TCAM_KEY_DISC)
  5820. nfc->data = RXH_DISCARD;
  5821. else
  5822. nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
  5823. CLASS_CODE_USER_PROG1]);
  5824. return 0;
  5825. }
  5826. static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
  5827. struct ethtool_rx_flow_spec *fsp)
  5828. {
  5829. fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
  5830. TCAM_V4KEY3_SADDR_SHIFT;
  5831. fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
  5832. TCAM_V4KEY3_DADDR_SHIFT;
  5833. fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
  5834. TCAM_V4KEY3_SADDR_SHIFT;
  5835. fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
  5836. TCAM_V4KEY3_DADDR_SHIFT;
  5837. fsp->h_u.tcp_ip4_spec.ip4src =
  5838. cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
  5839. fsp->m_u.tcp_ip4_spec.ip4src =
  5840. cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
  5841. fsp->h_u.tcp_ip4_spec.ip4dst =
  5842. cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
  5843. fsp->m_u.tcp_ip4_spec.ip4dst =
  5844. cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
  5845. fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
  5846. TCAM_V4KEY2_TOS_SHIFT;
  5847. fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
  5848. TCAM_V4KEY2_TOS_SHIFT;
  5849. switch (fsp->flow_type) {
  5850. case TCP_V4_FLOW:
  5851. case UDP_V4_FLOW:
  5852. case SCTP_V4_FLOW:
  5853. fsp->h_u.tcp_ip4_spec.psrc =
  5854. ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
  5855. TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
  5856. fsp->h_u.tcp_ip4_spec.pdst =
  5857. ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
  5858. TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
  5859. fsp->m_u.tcp_ip4_spec.psrc =
  5860. ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
  5861. TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
  5862. fsp->m_u.tcp_ip4_spec.pdst =
  5863. ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
  5864. TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
  5865. fsp->h_u.tcp_ip4_spec.psrc =
  5866. cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
  5867. fsp->h_u.tcp_ip4_spec.pdst =
  5868. cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
  5869. fsp->m_u.tcp_ip4_spec.psrc =
  5870. cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
  5871. fsp->m_u.tcp_ip4_spec.pdst =
  5872. cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
  5873. break;
  5874. case AH_V4_FLOW:
  5875. case ESP_V4_FLOW:
  5876. fsp->h_u.ah_ip4_spec.spi =
  5877. (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
  5878. TCAM_V4KEY2_PORT_SPI_SHIFT;
  5879. fsp->m_u.ah_ip4_spec.spi =
  5880. (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
  5881. TCAM_V4KEY2_PORT_SPI_SHIFT;
  5882. fsp->h_u.ah_ip4_spec.spi =
  5883. cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
  5884. fsp->m_u.ah_ip4_spec.spi =
  5885. cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
  5886. break;
  5887. case IP_USER_FLOW:
  5888. fsp->h_u.usr_ip4_spec.l4_4_bytes =
  5889. (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
  5890. TCAM_V4KEY2_PORT_SPI_SHIFT;
  5891. fsp->m_u.usr_ip4_spec.l4_4_bytes =
  5892. (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
  5893. TCAM_V4KEY2_PORT_SPI_SHIFT;
  5894. fsp->h_u.usr_ip4_spec.l4_4_bytes =
  5895. cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
  5896. fsp->m_u.usr_ip4_spec.l4_4_bytes =
  5897. cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
  5898. fsp->h_u.usr_ip4_spec.proto =
  5899. (tp->key[2] & TCAM_V4KEY2_PROTO) >>
  5900. TCAM_V4KEY2_PROTO_SHIFT;
  5901. fsp->m_u.usr_ip4_spec.proto =
  5902. (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
  5903. TCAM_V4KEY2_PROTO_SHIFT;
  5904. fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
  5905. break;
  5906. default:
  5907. break;
  5908. }
  5909. }
  5910. static int niu_get_ethtool_tcam_entry(struct niu *np,
  5911. struct ethtool_rxnfc *nfc)
  5912. {
  5913. struct niu_parent *parent = np->parent;
  5914. struct niu_tcam_entry *tp;
  5915. struct ethtool_rx_flow_spec *fsp = &nfc->fs;
  5916. u16 idx;
  5917. u64 class;
  5918. int ret = 0;
  5919. idx = tcam_get_index(np, (u16)nfc->fs.location);
  5920. tp = &parent->tcam[idx];
  5921. if (!tp->valid) {
  5922. netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
  5923. parent->index, (u16)nfc->fs.location, idx);
  5924. return -EINVAL;
  5925. }
  5926. /* fill the flow spec entry */
  5927. class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
  5928. TCAM_V4KEY0_CLASS_CODE_SHIFT;
  5929. ret = niu_class_to_ethflow(class, &fsp->flow_type);
  5930. if (ret < 0) {
  5931. netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
  5932. parent->index);
  5933. ret = -EINVAL;
  5934. goto out;
  5935. }
  5936. if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
  5937. u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
  5938. TCAM_V4KEY2_PROTO_SHIFT;
  5939. if (proto == IPPROTO_ESP) {
  5940. if (fsp->flow_type == AH_V4_FLOW)
  5941. fsp->flow_type = ESP_V4_FLOW;
  5942. else
  5943. fsp->flow_type = ESP_V6_FLOW;
  5944. }
  5945. }
  5946. switch (fsp->flow_type) {
  5947. case TCP_V4_FLOW:
  5948. case UDP_V4_FLOW:
  5949. case SCTP_V4_FLOW:
  5950. case AH_V4_FLOW:
  5951. case ESP_V4_FLOW:
  5952. niu_get_ip4fs_from_tcam_key(tp, fsp);
  5953. break;
  5954. case TCP_V6_FLOW:
  5955. case UDP_V6_FLOW:
  5956. case SCTP_V6_FLOW:
  5957. case AH_V6_FLOW:
  5958. case ESP_V6_FLOW:
  5959. /* Not yet implemented */
  5960. ret = -EINVAL;
  5961. break;
  5962. case IP_USER_FLOW:
  5963. niu_get_ip4fs_from_tcam_key(tp, fsp);
  5964. break;
  5965. default:
  5966. ret = -EINVAL;
  5967. break;
  5968. }
  5969. if (ret < 0)
  5970. goto out;
  5971. if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
  5972. fsp->ring_cookie = RX_CLS_FLOW_DISC;
  5973. else
  5974. fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
  5975. TCAM_ASSOCDATA_OFFSET_SHIFT;
  5976. /* put the tcam size here */
  5977. nfc->data = tcam_get_size(np);
  5978. out:
  5979. return ret;
  5980. }
  5981. static int niu_get_ethtool_tcam_all(struct niu *np,
  5982. struct ethtool_rxnfc *nfc,
  5983. u32 *rule_locs)
  5984. {
  5985. struct niu_parent *parent = np->parent;
  5986. struct niu_tcam_entry *tp;
  5987. int i, idx, cnt;
  5988. u16 n_entries;
  5989. unsigned long flags;
  5990. /* put the tcam size here */
  5991. nfc->data = tcam_get_size(np);
  5992. niu_lock_parent(np, flags);
  5993. n_entries = nfc->rule_cnt;
  5994. for (cnt = 0, i = 0; i < nfc->data; i++) {
  5995. idx = tcam_get_index(np, i);
  5996. tp = &parent->tcam[idx];
  5997. if (!tp->valid)
  5998. continue;
  5999. rule_locs[cnt] = i;
  6000. cnt++;
  6001. }
  6002. niu_unlock_parent(np, flags);
  6003. if (n_entries != cnt) {
  6004. /* print warning, this should not happen */
  6005. netdev_info(np->dev, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
  6006. np->parent->index, __func__, n_entries, cnt);
  6007. }
  6008. return 0;
  6009. }
  6010. static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
  6011. void *rule_locs)
  6012. {
  6013. struct niu *np = netdev_priv(dev);
  6014. int ret = 0;
  6015. switch (cmd->cmd) {
  6016. case ETHTOOL_GRXFH:
  6017. ret = niu_get_hash_opts(np, cmd);
  6018. break;
  6019. case ETHTOOL_GRXRINGS:
  6020. cmd->data = np->num_rx_rings;
  6021. break;
  6022. case ETHTOOL_GRXCLSRLCNT:
  6023. cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
  6024. break;
  6025. case ETHTOOL_GRXCLSRULE:
  6026. ret = niu_get_ethtool_tcam_entry(np, cmd);
  6027. break;
  6028. case ETHTOOL_GRXCLSRLALL:
  6029. ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
  6030. break;
  6031. default:
  6032. ret = -EINVAL;
  6033. break;
  6034. }
  6035. return ret;
  6036. }
  6037. static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
  6038. {
  6039. u64 class;
  6040. u64 flow_key = 0;
  6041. unsigned long flags;
  6042. if (!niu_ethflow_to_class(nfc->flow_type, &class))
  6043. return -EINVAL;
  6044. if (class < CLASS_CODE_USER_PROG1 ||
  6045. class > CLASS_CODE_SCTP_IPV6)
  6046. return -EINVAL;
  6047. if (nfc->data & RXH_DISCARD) {
  6048. niu_lock_parent(np, flags);
  6049. flow_key = np->parent->tcam_key[class -
  6050. CLASS_CODE_USER_PROG1];
  6051. flow_key |= TCAM_KEY_DISC;
  6052. nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
  6053. np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
  6054. niu_unlock_parent(np, flags);
  6055. return 0;
  6056. } else {
  6057. /* Discard was set before, but is not set now */
  6058. if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
  6059. TCAM_KEY_DISC) {
  6060. niu_lock_parent(np, flags);
  6061. flow_key = np->parent->tcam_key[class -
  6062. CLASS_CODE_USER_PROG1];
  6063. flow_key &= ~TCAM_KEY_DISC;
  6064. nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
  6065. flow_key);
  6066. np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
  6067. flow_key;
  6068. niu_unlock_parent(np, flags);
  6069. }
  6070. }
  6071. if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
  6072. return -EINVAL;
  6073. niu_lock_parent(np, flags);
  6074. nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
  6075. np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
  6076. niu_unlock_parent(np, flags);
  6077. return 0;
  6078. }
  6079. static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
  6080. struct niu_tcam_entry *tp,
  6081. int l2_rdc_tab, u64 class)
  6082. {
  6083. u8 pid = 0;
  6084. u32 sip, dip, sipm, dipm, spi, spim;
  6085. u16 sport, dport, spm, dpm;
  6086. sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
  6087. sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
  6088. dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
  6089. dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
  6090. tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
  6091. tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
  6092. tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
  6093. tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
  6094. tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
  6095. tp->key[3] |= dip;
  6096. tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
  6097. tp->key_mask[3] |= dipm;
  6098. tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
  6099. TCAM_V4KEY2_TOS_SHIFT);
  6100. tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
  6101. TCAM_V4KEY2_TOS_SHIFT);
  6102. switch (fsp->flow_type) {
  6103. case TCP_V4_FLOW:
  6104. case UDP_V4_FLOW:
  6105. case SCTP_V4_FLOW:
  6106. sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
  6107. spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
  6108. dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
  6109. dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
  6110. tp->key[2] |= (((u64)sport << 16) | dport);
  6111. tp->key_mask[2] |= (((u64)spm << 16) | dpm);
  6112. niu_ethflow_to_l3proto(fsp->flow_type, &pid);
  6113. break;
  6114. case AH_V4_FLOW:
  6115. case ESP_V4_FLOW:
  6116. spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
  6117. spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
  6118. tp->key[2] |= spi;
  6119. tp->key_mask[2] |= spim;
  6120. niu_ethflow_to_l3proto(fsp->flow_type, &pid);
  6121. break;
  6122. case IP_USER_FLOW:
  6123. spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
  6124. spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
  6125. tp->key[2] |= spi;
  6126. tp->key_mask[2] |= spim;
  6127. pid = fsp->h_u.usr_ip4_spec.proto;
  6128. break;
  6129. default:
  6130. break;
  6131. }
  6132. tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
  6133. if (pid) {
  6134. tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
  6135. }
  6136. }
  6137. static int niu_add_ethtool_tcam_entry(struct niu *np,
  6138. struct ethtool_rxnfc *nfc)
  6139. {
  6140. struct niu_parent *parent = np->parent;
  6141. struct niu_tcam_entry *tp;
  6142. struct ethtool_rx_flow_spec *fsp = &nfc->fs;
  6143. struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
  6144. int l2_rdc_table = rdc_table->first_table_num;
  6145. u16 idx;
  6146. u64 class;
  6147. unsigned long flags;
  6148. int err, ret;
  6149. ret = 0;
  6150. idx = nfc->fs.location;
  6151. if (idx >= tcam_get_size(np))
  6152. return -EINVAL;
  6153. if (fsp->flow_type == IP_USER_FLOW) {
  6154. int i;
  6155. int add_usr_cls = 0;
  6156. int ipv6 = 0;
  6157. struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
  6158. struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
  6159. niu_lock_parent(np, flags);
  6160. for (i = 0; i < NIU_L3_PROG_CLS; i++) {
  6161. if (parent->l3_cls[i]) {
  6162. if (uspec->proto == parent->l3_cls_pid[i]) {
  6163. class = parent->l3_cls[i];
  6164. parent->l3_cls_refcnt[i]++;
  6165. add_usr_cls = 1;
  6166. break;
  6167. }
  6168. } else {
  6169. /* Program new user IP class */
  6170. switch (i) {
  6171. case 0:
  6172. class = CLASS_CODE_USER_PROG1;
  6173. break;
  6174. case 1:
  6175. class = CLASS_CODE_USER_PROG2;
  6176. break;
  6177. case 2:
  6178. class = CLASS_CODE_USER_PROG3;
  6179. break;
  6180. case 3:
  6181. class = CLASS_CODE_USER_PROG4;
  6182. break;
  6183. default:
  6184. break;
  6185. }
  6186. if (uspec->ip_ver == ETH_RX_NFC_IP6)
  6187. ipv6 = 1;
  6188. ret = tcam_user_ip_class_set(np, class, ipv6,
  6189. uspec->proto,
  6190. uspec->tos,
  6191. umask->tos);
  6192. if (ret)
  6193. goto out;
  6194. ret = tcam_user_ip_class_enable(np, class, 1);
  6195. if (ret)
  6196. goto out;
  6197. parent->l3_cls[i] = class;
  6198. parent->l3_cls_pid[i] = uspec->proto;
  6199. parent->l3_cls_refcnt[i]++;
  6200. add_usr_cls = 1;
  6201. break;
  6202. }
  6203. }
  6204. if (!add_usr_cls) {
  6205. netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
  6206. parent->index, __func__, uspec->proto);
  6207. ret = -EINVAL;
  6208. goto out;
  6209. }
  6210. niu_unlock_parent(np, flags);
  6211. } else {
  6212. if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
  6213. return -EINVAL;
  6214. }
  6215. }
  6216. niu_lock_parent(np, flags);
  6217. idx = tcam_get_index(np, idx);
  6218. tp = &parent->tcam[idx];
  6219. memset(tp, 0, sizeof(*tp));
  6220. /* fill in the tcam key and mask */
  6221. switch (fsp->flow_type) {
  6222. case TCP_V4_FLOW:
  6223. case UDP_V4_FLOW:
  6224. case SCTP_V4_FLOW:
  6225. case AH_V4_FLOW:
  6226. case ESP_V4_FLOW:
  6227. niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
  6228. break;
  6229. case TCP_V6_FLOW:
  6230. case UDP_V6_FLOW:
  6231. case SCTP_V6_FLOW:
  6232. case AH_V6_FLOW:
  6233. case ESP_V6_FLOW:
  6234. /* Not yet implemented */
  6235. netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
  6236. parent->index, __func__, fsp->flow_type);
  6237. ret = -EINVAL;
  6238. goto out;
  6239. case IP_USER_FLOW:
  6240. if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
  6241. niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
  6242. class);
  6243. } else {
  6244. /* Not yet implemented */
  6245. netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
  6246. parent->index, __func__);
  6247. ret = -EINVAL;
  6248. goto out;
  6249. }
  6250. break;
  6251. default:
  6252. netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
  6253. parent->index, __func__, fsp->flow_type);
  6254. ret = -EINVAL;
  6255. goto out;
  6256. }
  6257. /* fill in the assoc data */
  6258. if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
  6259. tp->assoc_data = TCAM_ASSOCDATA_DISC;
  6260. } else {
  6261. if (fsp->ring_cookie >= np->num_rx_rings) {
  6262. netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
  6263. parent->index, __func__,
  6264. (long long)fsp->ring_cookie);
  6265. ret = -EINVAL;
  6266. goto out;
  6267. }
  6268. tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
  6269. (fsp->ring_cookie <<
  6270. TCAM_ASSOCDATA_OFFSET_SHIFT));
  6271. }
  6272. err = tcam_write(np, idx, tp->key, tp->key_mask);
  6273. if (err) {
  6274. ret = -EINVAL;
  6275. goto out;
  6276. }
  6277. err = tcam_assoc_write(np, idx, tp->assoc_data);
  6278. if (err) {
  6279. ret = -EINVAL;
  6280. goto out;
  6281. }
  6282. /* validate the entry */
  6283. tp->valid = 1;
  6284. np->clas.tcam_valid_entries++;
  6285. out:
  6286. niu_unlock_parent(np, flags);
  6287. return ret;
  6288. }
  6289. static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
  6290. {
  6291. struct niu_parent *parent = np->parent;
  6292. struct niu_tcam_entry *tp;
  6293. u16 idx;
  6294. unsigned long flags;
  6295. u64 class;
  6296. int ret = 0;
  6297. if (loc >= tcam_get_size(np))
  6298. return -EINVAL;
  6299. niu_lock_parent(np, flags);
  6300. idx = tcam_get_index(np, loc);
  6301. tp = &parent->tcam[idx];
  6302. /* if the entry is of a user defined class, then update*/
  6303. class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
  6304. TCAM_V4KEY0_CLASS_CODE_SHIFT;
  6305. if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
  6306. int i;
  6307. for (i = 0; i < NIU_L3_PROG_CLS; i++) {
  6308. if (parent->l3_cls[i] == class) {
  6309. parent->l3_cls_refcnt[i]--;
  6310. if (!parent->l3_cls_refcnt[i]) {
  6311. /* disable class */
  6312. ret = tcam_user_ip_class_enable(np,
  6313. class,
  6314. 0);
  6315. if (ret)
  6316. goto out;
  6317. parent->l3_cls[i] = 0;
  6318. parent->l3_cls_pid[i] = 0;
  6319. }
  6320. break;
  6321. }
  6322. }
  6323. if (i == NIU_L3_PROG_CLS) {
  6324. netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
  6325. parent->index, __func__,
  6326. (unsigned long long)class);
  6327. ret = -EINVAL;
  6328. goto out;
  6329. }
  6330. }
  6331. ret = tcam_flush(np, idx);
  6332. if (ret)
  6333. goto out;
  6334. /* invalidate the entry */
  6335. tp->valid = 0;
  6336. np->clas.tcam_valid_entries--;
  6337. out:
  6338. niu_unlock_parent(np, flags);
  6339. return ret;
  6340. }
  6341. static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
  6342. {
  6343. struct niu *np = netdev_priv(dev);
  6344. int ret = 0;
  6345. switch (cmd->cmd) {
  6346. case ETHTOOL_SRXFH:
  6347. ret = niu_set_hash_opts(np, cmd);
  6348. break;
  6349. case ETHTOOL_SRXCLSRLINS:
  6350. ret = niu_add_ethtool_tcam_entry(np, cmd);
  6351. break;
  6352. case ETHTOOL_SRXCLSRLDEL:
  6353. ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
  6354. break;
  6355. default:
  6356. ret = -EINVAL;
  6357. break;
  6358. }
  6359. return ret;
  6360. }
  6361. static const struct {
  6362. const char string[ETH_GSTRING_LEN];
  6363. } niu_xmac_stat_keys[] = {
  6364. { "tx_frames" },
  6365. { "tx_bytes" },
  6366. { "tx_fifo_errors" },
  6367. { "tx_overflow_errors" },
  6368. { "tx_max_pkt_size_errors" },
  6369. { "tx_underflow_errors" },
  6370. { "rx_local_faults" },
  6371. { "rx_remote_faults" },
  6372. { "rx_link_faults" },
  6373. { "rx_align_errors" },
  6374. { "rx_frags" },
  6375. { "rx_mcasts" },
  6376. { "rx_bcasts" },
  6377. { "rx_hist_cnt1" },
  6378. { "rx_hist_cnt2" },
  6379. { "rx_hist_cnt3" },
  6380. { "rx_hist_cnt4" },
  6381. { "rx_hist_cnt5" },
  6382. { "rx_hist_cnt6" },
  6383. { "rx_hist_cnt7" },
  6384. { "rx_octets" },
  6385. { "rx_code_violations" },
  6386. { "rx_len_errors" },
  6387. { "rx_crc_errors" },
  6388. { "rx_underflows" },
  6389. { "rx_overflows" },
  6390. { "pause_off_state" },
  6391. { "pause_on_state" },
  6392. { "pause_received" },
  6393. };
  6394. #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
  6395. static const struct {
  6396. const char string[ETH_GSTRING_LEN];
  6397. } niu_bmac_stat_keys[] = {
  6398. { "tx_underflow_errors" },
  6399. { "tx_max_pkt_size_errors" },
  6400. { "tx_bytes" },
  6401. { "tx_frames" },
  6402. { "rx_overflows" },
  6403. { "rx_frames" },
  6404. { "rx_align_errors" },
  6405. { "rx_crc_errors" },
  6406. { "rx_len_errors" },
  6407. { "pause_off_state" },
  6408. { "pause_on_state" },
  6409. { "pause_received" },
  6410. };
  6411. #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
  6412. static const struct {
  6413. const char string[ETH_GSTRING_LEN];
  6414. } niu_rxchan_stat_keys[] = {
  6415. { "rx_channel" },
  6416. { "rx_packets" },
  6417. { "rx_bytes" },
  6418. { "rx_dropped" },
  6419. { "rx_errors" },
  6420. };
  6421. #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
  6422. static const struct {
  6423. const char string[ETH_GSTRING_LEN];
  6424. } niu_txchan_stat_keys[] = {
  6425. { "tx_channel" },
  6426. { "tx_packets" },
  6427. { "tx_bytes" },
  6428. { "tx_errors" },
  6429. };
  6430. #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
  6431. static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  6432. {
  6433. struct niu *np = netdev_priv(dev);
  6434. int i;
  6435. if (stringset != ETH_SS_STATS)
  6436. return;
  6437. if (np->flags & NIU_FLAGS_XMAC) {
  6438. memcpy(data, niu_xmac_stat_keys,
  6439. sizeof(niu_xmac_stat_keys));
  6440. data += sizeof(niu_xmac_stat_keys);
  6441. } else {
  6442. memcpy(data, niu_bmac_stat_keys,
  6443. sizeof(niu_bmac_stat_keys));
  6444. data += sizeof(niu_bmac_stat_keys);
  6445. }
  6446. for (i = 0; i < np->num_rx_rings; i++) {
  6447. memcpy(data, niu_rxchan_stat_keys,
  6448. sizeof(niu_rxchan_stat_keys));
  6449. data += sizeof(niu_rxchan_stat_keys);
  6450. }
  6451. for (i = 0; i < np->num_tx_rings; i++) {
  6452. memcpy(data, niu_txchan_stat_keys,
  6453. sizeof(niu_txchan_stat_keys));
  6454. data += sizeof(niu_txchan_stat_keys);
  6455. }
  6456. }
  6457. static int niu_get_sset_count(struct net_device *dev, int stringset)
  6458. {
  6459. struct niu *np = netdev_priv(dev);
  6460. if (stringset != ETH_SS_STATS)
  6461. return -EINVAL;
  6462. return ((np->flags & NIU_FLAGS_XMAC ?
  6463. NUM_XMAC_STAT_KEYS :
  6464. NUM_BMAC_STAT_KEYS) +
  6465. (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
  6466. (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
  6467. }
  6468. static void niu_get_ethtool_stats(struct net_device *dev,
  6469. struct ethtool_stats *stats, u64 *data)
  6470. {
  6471. struct niu *np = netdev_priv(dev);
  6472. int i;
  6473. niu_sync_mac_stats(np);
  6474. if (np->flags & NIU_FLAGS_XMAC) {
  6475. memcpy(data, &np->mac_stats.xmac,
  6476. sizeof(struct niu_xmac_stats));
  6477. data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
  6478. } else {
  6479. memcpy(data, &np->mac_stats.bmac,
  6480. sizeof(struct niu_bmac_stats));
  6481. data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
  6482. }
  6483. for (i = 0; i < np->num_rx_rings; i++) {
  6484. struct rx_ring_info *rp = &np->rx_rings[i];
  6485. niu_sync_rx_discard_stats(np, rp, 0);
  6486. data[0] = rp->rx_channel;
  6487. data[1] = rp->rx_packets;
  6488. data[2] = rp->rx_bytes;
  6489. data[3] = rp->rx_dropped;
  6490. data[4] = rp->rx_errors;
  6491. data += 5;
  6492. }
  6493. for (i = 0; i < np->num_tx_rings; i++) {
  6494. struct tx_ring_info *rp = &np->tx_rings[i];
  6495. data[0] = rp->tx_channel;
  6496. data[1] = rp->tx_packets;
  6497. data[2] = rp->tx_bytes;
  6498. data[3] = rp->tx_errors;
  6499. data += 4;
  6500. }
  6501. }
  6502. static u64 niu_led_state_save(struct niu *np)
  6503. {
  6504. if (np->flags & NIU_FLAGS_XMAC)
  6505. return nr64_mac(XMAC_CONFIG);
  6506. else
  6507. return nr64_mac(BMAC_XIF_CONFIG);
  6508. }
  6509. static void niu_led_state_restore(struct niu *np, u64 val)
  6510. {
  6511. if (np->flags & NIU_FLAGS_XMAC)
  6512. nw64_mac(XMAC_CONFIG, val);
  6513. else
  6514. nw64_mac(BMAC_XIF_CONFIG, val);
  6515. }
  6516. static void niu_force_led(struct niu *np, int on)
  6517. {
  6518. u64 val, reg, bit;
  6519. if (np->flags & NIU_FLAGS_XMAC) {
  6520. reg = XMAC_CONFIG;
  6521. bit = XMAC_CONFIG_FORCE_LED_ON;
  6522. } else {
  6523. reg = BMAC_XIF_CONFIG;
  6524. bit = BMAC_XIF_CONFIG_LINK_LED;
  6525. }
  6526. val = nr64_mac(reg);
  6527. if (on)
  6528. val |= bit;
  6529. else
  6530. val &= ~bit;
  6531. nw64_mac(reg, val);
  6532. }
  6533. static int niu_phys_id(struct net_device *dev, u32 data)
  6534. {
  6535. struct niu *np = netdev_priv(dev);
  6536. u64 orig_led_state;
  6537. int i;
  6538. if (!netif_running(dev))
  6539. return -EAGAIN;
  6540. if (data == 0)
  6541. data = 2;
  6542. orig_led_state = niu_led_state_save(np);
  6543. for (i = 0; i < (data * 2); i++) {
  6544. int on = ((i % 2) == 0);
  6545. niu_force_led(np, on);
  6546. if (msleep_interruptible(500))
  6547. break;
  6548. }
  6549. niu_led_state_restore(np, orig_led_state);
  6550. return 0;
  6551. }
  6552. static int niu_set_flags(struct net_device *dev, u32 data)
  6553. {
  6554. if (data & (ETH_FLAG_LRO | ETH_FLAG_NTUPLE))
  6555. return -EOPNOTSUPP;
  6556. if (data & ETH_FLAG_RXHASH)
  6557. dev->features |= NETIF_F_RXHASH;
  6558. else
  6559. dev->features &= ~NETIF_F_RXHASH;
  6560. return 0;
  6561. }
  6562. static const struct ethtool_ops niu_ethtool_ops = {
  6563. .get_drvinfo = niu_get_drvinfo,
  6564. .get_link = ethtool_op_get_link,
  6565. .get_msglevel = niu_get_msglevel,
  6566. .set_msglevel = niu_set_msglevel,
  6567. .nway_reset = niu_nway_reset,
  6568. .get_eeprom_len = niu_get_eeprom_len,
  6569. .get_eeprom = niu_get_eeprom,
  6570. .get_settings = niu_get_settings,
  6571. .set_settings = niu_set_settings,
  6572. .get_strings = niu_get_strings,
  6573. .get_sset_count = niu_get_sset_count,
  6574. .get_ethtool_stats = niu_get_ethtool_stats,
  6575. .phys_id = niu_phys_id,
  6576. .get_rxnfc = niu_get_nfc,
  6577. .set_rxnfc = niu_set_nfc,
  6578. .set_flags = niu_set_flags,
  6579. .get_flags = ethtool_op_get_flags,
  6580. };
  6581. static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
  6582. int ldg, int ldn)
  6583. {
  6584. if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
  6585. return -EINVAL;
  6586. if (ldn < 0 || ldn > LDN_MAX)
  6587. return -EINVAL;
  6588. parent->ldg_map[ldn] = ldg;
  6589. if (np->parent->plat_type == PLAT_TYPE_NIU) {
  6590. /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
  6591. * the firmware, and we're not supposed to change them.
  6592. * Validate the mapping, because if it's wrong we probably
  6593. * won't get any interrupts and that's painful to debug.
  6594. */
  6595. if (nr64(LDG_NUM(ldn)) != ldg) {
  6596. dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
  6597. np->port, ldn, ldg,
  6598. (unsigned long long) nr64(LDG_NUM(ldn)));
  6599. return -EINVAL;
  6600. }
  6601. } else
  6602. nw64(LDG_NUM(ldn), ldg);
  6603. return 0;
  6604. }
  6605. static int niu_set_ldg_timer_res(struct niu *np, int res)
  6606. {
  6607. if (res < 0 || res > LDG_TIMER_RES_VAL)
  6608. return -EINVAL;
  6609. nw64(LDG_TIMER_RES, res);
  6610. return 0;
  6611. }
  6612. static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
  6613. {
  6614. if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
  6615. (func < 0 || func > 3) ||
  6616. (vector < 0 || vector > 0x1f))
  6617. return -EINVAL;
  6618. nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
  6619. return 0;
  6620. }
  6621. static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
  6622. {
  6623. u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
  6624. (addr << ESPC_PIO_STAT_ADDR_SHIFT));
  6625. int limit;
  6626. if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
  6627. return -EINVAL;
  6628. frame = frame_base;
  6629. nw64(ESPC_PIO_STAT, frame);
  6630. limit = 64;
  6631. do {
  6632. udelay(5);
  6633. frame = nr64(ESPC_PIO_STAT);
  6634. if (frame & ESPC_PIO_STAT_READ_END)
  6635. break;
  6636. } while (limit--);
  6637. if (!(frame & ESPC_PIO_STAT_READ_END)) {
  6638. dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
  6639. (unsigned long long) frame);
  6640. return -ENODEV;
  6641. }
  6642. frame = frame_base;
  6643. nw64(ESPC_PIO_STAT, frame);
  6644. limit = 64;
  6645. do {
  6646. udelay(5);
  6647. frame = nr64(ESPC_PIO_STAT);
  6648. if (frame & ESPC_PIO_STAT_READ_END)
  6649. break;
  6650. } while (limit--);
  6651. if (!(frame & ESPC_PIO_STAT_READ_END)) {
  6652. dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
  6653. (unsigned long long) frame);
  6654. return -ENODEV;
  6655. }
  6656. frame = nr64(ESPC_PIO_STAT);
  6657. return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
  6658. }
  6659. static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
  6660. {
  6661. int err = niu_pci_eeprom_read(np, off);
  6662. u16 val;
  6663. if (err < 0)
  6664. return err;
  6665. val = (err << 8);
  6666. err = niu_pci_eeprom_read(np, off + 1);
  6667. if (err < 0)
  6668. return err;
  6669. val |= (err & 0xff);
  6670. return val;
  6671. }
  6672. static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
  6673. {
  6674. int err = niu_pci_eeprom_read(np, off);
  6675. u16 val;
  6676. if (err < 0)
  6677. return err;
  6678. val = (err & 0xff);
  6679. err = niu_pci_eeprom_read(np, off + 1);
  6680. if (err < 0)
  6681. return err;
  6682. val |= (err & 0xff) << 8;
  6683. return val;
  6684. }
  6685. static int __devinit niu_pci_vpd_get_propname(struct niu *np,
  6686. u32 off,
  6687. char *namebuf,
  6688. int namebuf_len)
  6689. {
  6690. int i;
  6691. for (i = 0; i < namebuf_len; i++) {
  6692. int err = niu_pci_eeprom_read(np, off + i);
  6693. if (err < 0)
  6694. return err;
  6695. *namebuf++ = err;
  6696. if (!err)
  6697. break;
  6698. }
  6699. if (i >= namebuf_len)
  6700. return -EINVAL;
  6701. return i + 1;
  6702. }
  6703. static void __devinit niu_vpd_parse_version(struct niu *np)
  6704. {
  6705. struct niu_vpd *vpd = &np->vpd;
  6706. int len = strlen(vpd->version) + 1;
  6707. const char *s = vpd->version;
  6708. int i;
  6709. for (i = 0; i < len - 5; i++) {
  6710. if (!strncmp(s + i, "FCode ", 6))
  6711. break;
  6712. }
  6713. if (i >= len - 5)
  6714. return;
  6715. s += i + 5;
  6716. sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
  6717. netif_printk(np, probe, KERN_DEBUG, np->dev,
  6718. "VPD_SCAN: FCODE major(%d) minor(%d)\n",
  6719. vpd->fcode_major, vpd->fcode_minor);
  6720. if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
  6721. (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
  6722. vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
  6723. np->flags |= NIU_FLAGS_VPD_VALID;
  6724. }
  6725. /* ESPC_PIO_EN_ENABLE must be set */
  6726. static int __devinit niu_pci_vpd_scan_props(struct niu *np,
  6727. u32 start, u32 end)
  6728. {
  6729. unsigned int found_mask = 0;
  6730. #define FOUND_MASK_MODEL 0x00000001
  6731. #define FOUND_MASK_BMODEL 0x00000002
  6732. #define FOUND_MASK_VERS 0x00000004
  6733. #define FOUND_MASK_MAC 0x00000008
  6734. #define FOUND_MASK_NMAC 0x00000010
  6735. #define FOUND_MASK_PHY 0x00000020
  6736. #define FOUND_MASK_ALL 0x0000003f
  6737. netif_printk(np, probe, KERN_DEBUG, np->dev,
  6738. "VPD_SCAN: start[%x] end[%x]\n", start, end);
  6739. while (start < end) {
  6740. int len, err, instance, type, prop_len;
  6741. char namebuf[64];
  6742. u8 *prop_buf;
  6743. int max_len;
  6744. if (found_mask == FOUND_MASK_ALL) {
  6745. niu_vpd_parse_version(np);
  6746. return 1;
  6747. }
  6748. err = niu_pci_eeprom_read(np, start + 2);
  6749. if (err < 0)
  6750. return err;
  6751. len = err;
  6752. start += 3;
  6753. instance = niu_pci_eeprom_read(np, start);
  6754. type = niu_pci_eeprom_read(np, start + 3);
  6755. prop_len = niu_pci_eeprom_read(np, start + 4);
  6756. err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
  6757. if (err < 0)
  6758. return err;
  6759. prop_buf = NULL;
  6760. max_len = 0;
  6761. if (!strcmp(namebuf, "model")) {
  6762. prop_buf = np->vpd.model;
  6763. max_len = NIU_VPD_MODEL_MAX;
  6764. found_mask |= FOUND_MASK_MODEL;
  6765. } else if (!strcmp(namebuf, "board-model")) {
  6766. prop_buf = np->vpd.board_model;
  6767. max_len = NIU_VPD_BD_MODEL_MAX;
  6768. found_mask |= FOUND_MASK_BMODEL;
  6769. } else if (!strcmp(namebuf, "version")) {
  6770. prop_buf = np->vpd.version;
  6771. max_len = NIU_VPD_VERSION_MAX;
  6772. found_mask |= FOUND_MASK_VERS;
  6773. } else if (!strcmp(namebuf, "local-mac-address")) {
  6774. prop_buf = np->vpd.local_mac;
  6775. max_len = ETH_ALEN;
  6776. found_mask |= FOUND_MASK_MAC;
  6777. } else if (!strcmp(namebuf, "num-mac-addresses")) {
  6778. prop_buf = &np->vpd.mac_num;
  6779. max_len = 1;
  6780. found_mask |= FOUND_MASK_NMAC;
  6781. } else if (!strcmp(namebuf, "phy-type")) {
  6782. prop_buf = np->vpd.phy_type;
  6783. max_len = NIU_VPD_PHY_TYPE_MAX;
  6784. found_mask |= FOUND_MASK_PHY;
  6785. }
  6786. if (max_len && prop_len > max_len) {
  6787. dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
  6788. return -EINVAL;
  6789. }
  6790. if (prop_buf) {
  6791. u32 off = start + 5 + err;
  6792. int i;
  6793. netif_printk(np, probe, KERN_DEBUG, np->dev,
  6794. "VPD_SCAN: Reading in property [%s] len[%d]\n",
  6795. namebuf, prop_len);
  6796. for (i = 0; i < prop_len; i++)
  6797. *prop_buf++ = niu_pci_eeprom_read(np, off + i);
  6798. }
  6799. start += len;
  6800. }
  6801. return 0;
  6802. }
  6803. /* ESPC_PIO_EN_ENABLE must be set */
  6804. static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
  6805. {
  6806. u32 offset;
  6807. int err;
  6808. err = niu_pci_eeprom_read16_swp(np, start + 1);
  6809. if (err < 0)
  6810. return;
  6811. offset = err + 3;
  6812. while (start + offset < ESPC_EEPROM_SIZE) {
  6813. u32 here = start + offset;
  6814. u32 end;
  6815. err = niu_pci_eeprom_read(np, here);
  6816. if (err != 0x90)
  6817. return;
  6818. err = niu_pci_eeprom_read16_swp(np, here + 1);
  6819. if (err < 0)
  6820. return;
  6821. here = start + offset + 3;
  6822. end = start + offset + err;
  6823. offset += err;
  6824. err = niu_pci_vpd_scan_props(np, here, end);
  6825. if (err < 0 || err == 1)
  6826. return;
  6827. }
  6828. }
  6829. /* ESPC_PIO_EN_ENABLE must be set */
  6830. static u32 __devinit niu_pci_vpd_offset(struct niu *np)
  6831. {
  6832. u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
  6833. int err;
  6834. while (start < end) {
  6835. ret = start;
  6836. /* ROM header signature? */
  6837. err = niu_pci_eeprom_read16(np, start + 0);
  6838. if (err != 0x55aa)
  6839. return 0;
  6840. /* Apply offset to PCI data structure. */
  6841. err = niu_pci_eeprom_read16(np, start + 23);
  6842. if (err < 0)
  6843. return 0;
  6844. start += err;
  6845. /* Check for "PCIR" signature. */
  6846. err = niu_pci_eeprom_read16(np, start + 0);
  6847. if (err != 0x5043)
  6848. return 0;
  6849. err = niu_pci_eeprom_read16(np, start + 2);
  6850. if (err != 0x4952)
  6851. return 0;
  6852. /* Check for OBP image type. */
  6853. err = niu_pci_eeprom_read(np, start + 20);
  6854. if (err < 0)
  6855. return 0;
  6856. if (err != 0x01) {
  6857. err = niu_pci_eeprom_read(np, ret + 2);
  6858. if (err < 0)
  6859. return 0;
  6860. start = ret + (err * 512);
  6861. continue;
  6862. }
  6863. err = niu_pci_eeprom_read16_swp(np, start + 8);
  6864. if (err < 0)
  6865. return err;
  6866. ret += err;
  6867. err = niu_pci_eeprom_read(np, ret + 0);
  6868. if (err != 0x82)
  6869. return 0;
  6870. return ret;
  6871. }
  6872. return 0;
  6873. }
  6874. static int __devinit niu_phy_type_prop_decode(struct niu *np,
  6875. const char *phy_prop)
  6876. {
  6877. if (!strcmp(phy_prop, "mif")) {
  6878. /* 1G copper, MII */
  6879. np->flags &= ~(NIU_FLAGS_FIBER |
  6880. NIU_FLAGS_10G);
  6881. np->mac_xcvr = MAC_XCVR_MII;
  6882. } else if (!strcmp(phy_prop, "xgf")) {
  6883. /* 10G fiber, XPCS */
  6884. np->flags |= (NIU_FLAGS_10G |
  6885. NIU_FLAGS_FIBER);
  6886. np->mac_xcvr = MAC_XCVR_XPCS;
  6887. } else if (!strcmp(phy_prop, "pcs")) {
  6888. /* 1G fiber, PCS */
  6889. np->flags &= ~NIU_FLAGS_10G;
  6890. np->flags |= NIU_FLAGS_FIBER;
  6891. np->mac_xcvr = MAC_XCVR_PCS;
  6892. } else if (!strcmp(phy_prop, "xgc")) {
  6893. /* 10G copper, XPCS */
  6894. np->flags |= NIU_FLAGS_10G;
  6895. np->flags &= ~NIU_FLAGS_FIBER;
  6896. np->mac_xcvr = MAC_XCVR_XPCS;
  6897. } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
  6898. /* 10G Serdes or 1G Serdes, default to 10G */
  6899. np->flags |= NIU_FLAGS_10G;
  6900. np->flags &= ~NIU_FLAGS_FIBER;
  6901. np->flags |= NIU_FLAGS_XCVR_SERDES;
  6902. np->mac_xcvr = MAC_XCVR_XPCS;
  6903. } else {
  6904. return -EINVAL;
  6905. }
  6906. return 0;
  6907. }
  6908. static int niu_pci_vpd_get_nports(struct niu *np)
  6909. {
  6910. int ports = 0;
  6911. if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
  6912. (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
  6913. (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
  6914. (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
  6915. (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
  6916. ports = 4;
  6917. } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
  6918. (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
  6919. (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
  6920. (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
  6921. ports = 2;
  6922. }
  6923. return ports;
  6924. }
  6925. static void __devinit niu_pci_vpd_validate(struct niu *np)
  6926. {
  6927. struct net_device *dev = np->dev;
  6928. struct niu_vpd *vpd = &np->vpd;
  6929. u8 val8;
  6930. if (!is_valid_ether_addr(&vpd->local_mac[0])) {
  6931. dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
  6932. np->flags &= ~NIU_FLAGS_VPD_VALID;
  6933. return;
  6934. }
  6935. if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
  6936. !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
  6937. np->flags |= NIU_FLAGS_10G;
  6938. np->flags &= ~NIU_FLAGS_FIBER;
  6939. np->flags |= NIU_FLAGS_XCVR_SERDES;
  6940. np->mac_xcvr = MAC_XCVR_PCS;
  6941. if (np->port > 1) {
  6942. np->flags |= NIU_FLAGS_FIBER;
  6943. np->flags &= ~NIU_FLAGS_10G;
  6944. }
  6945. if (np->flags & NIU_FLAGS_10G)
  6946. np->mac_xcvr = MAC_XCVR_XPCS;
  6947. } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
  6948. np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
  6949. NIU_FLAGS_HOTPLUG_PHY);
  6950. } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
  6951. dev_err(np->device, "Illegal phy string [%s]\n",
  6952. np->vpd.phy_type);
  6953. dev_err(np->device, "Falling back to SPROM\n");
  6954. np->flags &= ~NIU_FLAGS_VPD_VALID;
  6955. return;
  6956. }
  6957. memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
  6958. val8 = dev->perm_addr[5];
  6959. dev->perm_addr[5] += np->port;
  6960. if (dev->perm_addr[5] < val8)
  6961. dev->perm_addr[4]++;
  6962. memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
  6963. }
  6964. static int __devinit niu_pci_probe_sprom(struct niu *np)
  6965. {
  6966. struct net_device *dev = np->dev;
  6967. int len, i;
  6968. u64 val, sum;
  6969. u8 val8;
  6970. val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
  6971. val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
  6972. len = val / 4;
  6973. np->eeprom_len = len;
  6974. netif_printk(np, probe, KERN_DEBUG, np->dev,
  6975. "SPROM: Image size %llu\n", (unsigned long long)val);
  6976. sum = 0;
  6977. for (i = 0; i < len; i++) {
  6978. val = nr64(ESPC_NCR(i));
  6979. sum += (val >> 0) & 0xff;
  6980. sum += (val >> 8) & 0xff;
  6981. sum += (val >> 16) & 0xff;
  6982. sum += (val >> 24) & 0xff;
  6983. }
  6984. netif_printk(np, probe, KERN_DEBUG, np->dev,
  6985. "SPROM: Checksum %x\n", (int)(sum & 0xff));
  6986. if ((sum & 0xff) != 0xab) {
  6987. dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
  6988. return -EINVAL;
  6989. }
  6990. val = nr64(ESPC_PHY_TYPE);
  6991. switch (np->port) {
  6992. case 0:
  6993. val8 = (val & ESPC_PHY_TYPE_PORT0) >>
  6994. ESPC_PHY_TYPE_PORT0_SHIFT;
  6995. break;
  6996. case 1:
  6997. val8 = (val & ESPC_PHY_TYPE_PORT1) >>
  6998. ESPC_PHY_TYPE_PORT1_SHIFT;
  6999. break;
  7000. case 2:
  7001. val8 = (val & ESPC_PHY_TYPE_PORT2) >>
  7002. ESPC_PHY_TYPE_PORT2_SHIFT;
  7003. break;
  7004. case 3:
  7005. val8 = (val & ESPC_PHY_TYPE_PORT3) >>
  7006. ESPC_PHY_TYPE_PORT3_SHIFT;
  7007. break;
  7008. default:
  7009. dev_err(np->device, "Bogus port number %u\n",
  7010. np->port);
  7011. return -EINVAL;
  7012. }
  7013. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7014. "SPROM: PHY type %x\n", val8);
  7015. switch (val8) {
  7016. case ESPC_PHY_TYPE_1G_COPPER:
  7017. /* 1G copper, MII */
  7018. np->flags &= ~(NIU_FLAGS_FIBER |
  7019. NIU_FLAGS_10G);
  7020. np->mac_xcvr = MAC_XCVR_MII;
  7021. break;
  7022. case ESPC_PHY_TYPE_1G_FIBER:
  7023. /* 1G fiber, PCS */
  7024. np->flags &= ~NIU_FLAGS_10G;
  7025. np->flags |= NIU_FLAGS_FIBER;
  7026. np->mac_xcvr = MAC_XCVR_PCS;
  7027. break;
  7028. case ESPC_PHY_TYPE_10G_COPPER:
  7029. /* 10G copper, XPCS */
  7030. np->flags |= NIU_FLAGS_10G;
  7031. np->flags &= ~NIU_FLAGS_FIBER;
  7032. np->mac_xcvr = MAC_XCVR_XPCS;
  7033. break;
  7034. case ESPC_PHY_TYPE_10G_FIBER:
  7035. /* 10G fiber, XPCS */
  7036. np->flags |= (NIU_FLAGS_10G |
  7037. NIU_FLAGS_FIBER);
  7038. np->mac_xcvr = MAC_XCVR_XPCS;
  7039. break;
  7040. default:
  7041. dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
  7042. return -EINVAL;
  7043. }
  7044. val = nr64(ESPC_MAC_ADDR0);
  7045. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7046. "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
  7047. dev->perm_addr[0] = (val >> 0) & 0xff;
  7048. dev->perm_addr[1] = (val >> 8) & 0xff;
  7049. dev->perm_addr[2] = (val >> 16) & 0xff;
  7050. dev->perm_addr[3] = (val >> 24) & 0xff;
  7051. val = nr64(ESPC_MAC_ADDR1);
  7052. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7053. "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
  7054. dev->perm_addr[4] = (val >> 0) & 0xff;
  7055. dev->perm_addr[5] = (val >> 8) & 0xff;
  7056. if (!is_valid_ether_addr(&dev->perm_addr[0])) {
  7057. dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
  7058. dev->perm_addr);
  7059. return -EINVAL;
  7060. }
  7061. val8 = dev->perm_addr[5];
  7062. dev->perm_addr[5] += np->port;
  7063. if (dev->perm_addr[5] < val8)
  7064. dev->perm_addr[4]++;
  7065. memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
  7066. val = nr64(ESPC_MOD_STR_LEN);
  7067. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7068. "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
  7069. if (val >= 8 * 4)
  7070. return -EINVAL;
  7071. for (i = 0; i < val; i += 4) {
  7072. u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
  7073. np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
  7074. np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
  7075. np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
  7076. np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
  7077. }
  7078. np->vpd.model[val] = '\0';
  7079. val = nr64(ESPC_BD_MOD_STR_LEN);
  7080. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7081. "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
  7082. if (val >= 4 * 4)
  7083. return -EINVAL;
  7084. for (i = 0; i < val; i += 4) {
  7085. u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
  7086. np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
  7087. np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
  7088. np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
  7089. np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
  7090. }
  7091. np->vpd.board_model[val] = '\0';
  7092. np->vpd.mac_num =
  7093. nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
  7094. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7095. "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
  7096. return 0;
  7097. }
  7098. static int __devinit niu_get_and_validate_port(struct niu *np)
  7099. {
  7100. struct niu_parent *parent = np->parent;
  7101. if (np->port <= 1)
  7102. np->flags |= NIU_FLAGS_XMAC;
  7103. if (!parent->num_ports) {
  7104. if (parent->plat_type == PLAT_TYPE_NIU) {
  7105. parent->num_ports = 2;
  7106. } else {
  7107. parent->num_ports = niu_pci_vpd_get_nports(np);
  7108. if (!parent->num_ports) {
  7109. /* Fall back to SPROM as last resort.
  7110. * This will fail on most cards.
  7111. */
  7112. parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
  7113. ESPC_NUM_PORTS_MACS_VAL;
  7114. /* All of the current probing methods fail on
  7115. * Maramba on-board parts.
  7116. */
  7117. if (!parent->num_ports)
  7118. parent->num_ports = 4;
  7119. }
  7120. }
  7121. }
  7122. if (np->port >= parent->num_ports)
  7123. return -ENODEV;
  7124. return 0;
  7125. }
  7126. static int __devinit phy_record(struct niu_parent *parent,
  7127. struct phy_probe_info *p,
  7128. int dev_id_1, int dev_id_2, u8 phy_port,
  7129. int type)
  7130. {
  7131. u32 id = (dev_id_1 << 16) | dev_id_2;
  7132. u8 idx;
  7133. if (dev_id_1 < 0 || dev_id_2 < 0)
  7134. return 0;
  7135. if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
  7136. if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
  7137. ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
  7138. ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
  7139. return 0;
  7140. } else {
  7141. if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
  7142. return 0;
  7143. }
  7144. pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
  7145. parent->index, id,
  7146. type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
  7147. type == PHY_TYPE_PCS ? "PCS" : "MII",
  7148. phy_port);
  7149. if (p->cur[type] >= NIU_MAX_PORTS) {
  7150. pr_err("Too many PHY ports\n");
  7151. return -EINVAL;
  7152. }
  7153. idx = p->cur[type];
  7154. p->phy_id[type][idx] = id;
  7155. p->phy_port[type][idx] = phy_port;
  7156. p->cur[type] = idx + 1;
  7157. return 0;
  7158. }
  7159. static int __devinit port_has_10g(struct phy_probe_info *p, int port)
  7160. {
  7161. int i;
  7162. for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
  7163. if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
  7164. return 1;
  7165. }
  7166. for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
  7167. if (p->phy_port[PHY_TYPE_PCS][i] == port)
  7168. return 1;
  7169. }
  7170. return 0;
  7171. }
  7172. static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
  7173. {
  7174. int port, cnt;
  7175. cnt = 0;
  7176. *lowest = 32;
  7177. for (port = 8; port < 32; port++) {
  7178. if (port_has_10g(p, port)) {
  7179. if (!cnt)
  7180. *lowest = port;
  7181. cnt++;
  7182. }
  7183. }
  7184. return cnt;
  7185. }
  7186. static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
  7187. {
  7188. *lowest = 32;
  7189. if (p->cur[PHY_TYPE_MII])
  7190. *lowest = p->phy_port[PHY_TYPE_MII][0];
  7191. return p->cur[PHY_TYPE_MII];
  7192. }
  7193. static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
  7194. {
  7195. int num_ports = parent->num_ports;
  7196. int i;
  7197. for (i = 0; i < num_ports; i++) {
  7198. parent->rxchan_per_port[i] = (16 / num_ports);
  7199. parent->txchan_per_port[i] = (16 / num_ports);
  7200. pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
  7201. parent->index, i,
  7202. parent->rxchan_per_port[i],
  7203. parent->txchan_per_port[i]);
  7204. }
  7205. }
  7206. static void __devinit niu_divide_channels(struct niu_parent *parent,
  7207. int num_10g, int num_1g)
  7208. {
  7209. int num_ports = parent->num_ports;
  7210. int rx_chans_per_10g, rx_chans_per_1g;
  7211. int tx_chans_per_10g, tx_chans_per_1g;
  7212. int i, tot_rx, tot_tx;
  7213. if (!num_10g || !num_1g) {
  7214. rx_chans_per_10g = rx_chans_per_1g =
  7215. (NIU_NUM_RXCHAN / num_ports);
  7216. tx_chans_per_10g = tx_chans_per_1g =
  7217. (NIU_NUM_TXCHAN / num_ports);
  7218. } else {
  7219. rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
  7220. rx_chans_per_10g = (NIU_NUM_RXCHAN -
  7221. (rx_chans_per_1g * num_1g)) /
  7222. num_10g;
  7223. tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
  7224. tx_chans_per_10g = (NIU_NUM_TXCHAN -
  7225. (tx_chans_per_1g * num_1g)) /
  7226. num_10g;
  7227. }
  7228. tot_rx = tot_tx = 0;
  7229. for (i = 0; i < num_ports; i++) {
  7230. int type = phy_decode(parent->port_phy, i);
  7231. if (type == PORT_TYPE_10G) {
  7232. parent->rxchan_per_port[i] = rx_chans_per_10g;
  7233. parent->txchan_per_port[i] = tx_chans_per_10g;
  7234. } else {
  7235. parent->rxchan_per_port[i] = rx_chans_per_1g;
  7236. parent->txchan_per_port[i] = tx_chans_per_1g;
  7237. }
  7238. pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
  7239. parent->index, i,
  7240. parent->rxchan_per_port[i],
  7241. parent->txchan_per_port[i]);
  7242. tot_rx += parent->rxchan_per_port[i];
  7243. tot_tx += parent->txchan_per_port[i];
  7244. }
  7245. if (tot_rx > NIU_NUM_RXCHAN) {
  7246. pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
  7247. parent->index, tot_rx);
  7248. for (i = 0; i < num_ports; i++)
  7249. parent->rxchan_per_port[i] = 1;
  7250. }
  7251. if (tot_tx > NIU_NUM_TXCHAN) {
  7252. pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
  7253. parent->index, tot_tx);
  7254. for (i = 0; i < num_ports; i++)
  7255. parent->txchan_per_port[i] = 1;
  7256. }
  7257. if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
  7258. pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
  7259. parent->index, tot_rx, tot_tx);
  7260. }
  7261. }
  7262. static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
  7263. int num_10g, int num_1g)
  7264. {
  7265. int i, num_ports = parent->num_ports;
  7266. int rdc_group, rdc_groups_per_port;
  7267. int rdc_channel_base;
  7268. rdc_group = 0;
  7269. rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
  7270. rdc_channel_base = 0;
  7271. for (i = 0; i < num_ports; i++) {
  7272. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
  7273. int grp, num_channels = parent->rxchan_per_port[i];
  7274. int this_channel_offset;
  7275. tp->first_table_num = rdc_group;
  7276. tp->num_tables = rdc_groups_per_port;
  7277. this_channel_offset = 0;
  7278. for (grp = 0; grp < tp->num_tables; grp++) {
  7279. struct rdc_table *rt = &tp->tables[grp];
  7280. int slot;
  7281. pr_info("niu%d: Port %d RDC tbl(%d) [ ",
  7282. parent->index, i, tp->first_table_num + grp);
  7283. for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
  7284. rt->rxdma_channel[slot] =
  7285. rdc_channel_base + this_channel_offset;
  7286. pr_cont("%d ", rt->rxdma_channel[slot]);
  7287. if (++this_channel_offset == num_channels)
  7288. this_channel_offset = 0;
  7289. }
  7290. pr_cont("]\n");
  7291. }
  7292. parent->rdc_default[i] = rdc_channel_base;
  7293. rdc_channel_base += num_channels;
  7294. rdc_group += rdc_groups_per_port;
  7295. }
  7296. }
  7297. static int __devinit fill_phy_probe_info(struct niu *np,
  7298. struct niu_parent *parent,
  7299. struct phy_probe_info *info)
  7300. {
  7301. unsigned long flags;
  7302. int port, err;
  7303. memset(info, 0, sizeof(*info));
  7304. /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
  7305. niu_lock_parent(np, flags);
  7306. err = 0;
  7307. for (port = 8; port < 32; port++) {
  7308. int dev_id_1, dev_id_2;
  7309. dev_id_1 = mdio_read(np, port,
  7310. NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
  7311. dev_id_2 = mdio_read(np, port,
  7312. NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
  7313. err = phy_record(parent, info, dev_id_1, dev_id_2, port,
  7314. PHY_TYPE_PMA_PMD);
  7315. if (err)
  7316. break;
  7317. dev_id_1 = mdio_read(np, port,
  7318. NIU_PCS_DEV_ADDR, MII_PHYSID1);
  7319. dev_id_2 = mdio_read(np, port,
  7320. NIU_PCS_DEV_ADDR, MII_PHYSID2);
  7321. err = phy_record(parent, info, dev_id_1, dev_id_2, port,
  7322. PHY_TYPE_PCS);
  7323. if (err)
  7324. break;
  7325. dev_id_1 = mii_read(np, port, MII_PHYSID1);
  7326. dev_id_2 = mii_read(np, port, MII_PHYSID2);
  7327. err = phy_record(parent, info, dev_id_1, dev_id_2, port,
  7328. PHY_TYPE_MII);
  7329. if (err)
  7330. break;
  7331. }
  7332. niu_unlock_parent(np, flags);
  7333. return err;
  7334. }
  7335. static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
  7336. {
  7337. struct phy_probe_info *info = &parent->phy_probe_info;
  7338. int lowest_10g, lowest_1g;
  7339. int num_10g, num_1g;
  7340. u32 val;
  7341. int err;
  7342. num_10g = num_1g = 0;
  7343. if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
  7344. !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
  7345. num_10g = 0;
  7346. num_1g = 2;
  7347. parent->plat_type = PLAT_TYPE_ATCA_CP3220;
  7348. parent->num_ports = 4;
  7349. val = (phy_encode(PORT_TYPE_1G, 0) |
  7350. phy_encode(PORT_TYPE_1G, 1) |
  7351. phy_encode(PORT_TYPE_1G, 2) |
  7352. phy_encode(PORT_TYPE_1G, 3));
  7353. } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
  7354. num_10g = 2;
  7355. num_1g = 0;
  7356. parent->num_ports = 2;
  7357. val = (phy_encode(PORT_TYPE_10G, 0) |
  7358. phy_encode(PORT_TYPE_10G, 1));
  7359. } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
  7360. (parent->plat_type == PLAT_TYPE_NIU)) {
  7361. /* this is the Monza case */
  7362. if (np->flags & NIU_FLAGS_10G) {
  7363. val = (phy_encode(PORT_TYPE_10G, 0) |
  7364. phy_encode(PORT_TYPE_10G, 1));
  7365. } else {
  7366. val = (phy_encode(PORT_TYPE_1G, 0) |
  7367. phy_encode(PORT_TYPE_1G, 1));
  7368. }
  7369. } else {
  7370. err = fill_phy_probe_info(np, parent, info);
  7371. if (err)
  7372. return err;
  7373. num_10g = count_10g_ports(info, &lowest_10g);
  7374. num_1g = count_1g_ports(info, &lowest_1g);
  7375. switch ((num_10g << 4) | num_1g) {
  7376. case 0x24:
  7377. if (lowest_1g == 10)
  7378. parent->plat_type = PLAT_TYPE_VF_P0;
  7379. else if (lowest_1g == 26)
  7380. parent->plat_type = PLAT_TYPE_VF_P1;
  7381. else
  7382. goto unknown_vg_1g_port;
  7383. /* fallthru */
  7384. case 0x22:
  7385. val = (phy_encode(PORT_TYPE_10G, 0) |
  7386. phy_encode(PORT_TYPE_10G, 1) |
  7387. phy_encode(PORT_TYPE_1G, 2) |
  7388. phy_encode(PORT_TYPE_1G, 3));
  7389. break;
  7390. case 0x20:
  7391. val = (phy_encode(PORT_TYPE_10G, 0) |
  7392. phy_encode(PORT_TYPE_10G, 1));
  7393. break;
  7394. case 0x10:
  7395. val = phy_encode(PORT_TYPE_10G, np->port);
  7396. break;
  7397. case 0x14:
  7398. if (lowest_1g == 10)
  7399. parent->plat_type = PLAT_TYPE_VF_P0;
  7400. else if (lowest_1g == 26)
  7401. parent->plat_type = PLAT_TYPE_VF_P1;
  7402. else
  7403. goto unknown_vg_1g_port;
  7404. /* fallthru */
  7405. case 0x13:
  7406. if ((lowest_10g & 0x7) == 0)
  7407. val = (phy_encode(PORT_TYPE_10G, 0) |
  7408. phy_encode(PORT_TYPE_1G, 1) |
  7409. phy_encode(PORT_TYPE_1G, 2) |
  7410. phy_encode(PORT_TYPE_1G, 3));
  7411. else
  7412. val = (phy_encode(PORT_TYPE_1G, 0) |
  7413. phy_encode(PORT_TYPE_10G, 1) |
  7414. phy_encode(PORT_TYPE_1G, 2) |
  7415. phy_encode(PORT_TYPE_1G, 3));
  7416. break;
  7417. case 0x04:
  7418. if (lowest_1g == 10)
  7419. parent->plat_type = PLAT_TYPE_VF_P0;
  7420. else if (lowest_1g == 26)
  7421. parent->plat_type = PLAT_TYPE_VF_P1;
  7422. else
  7423. goto unknown_vg_1g_port;
  7424. val = (phy_encode(PORT_TYPE_1G, 0) |
  7425. phy_encode(PORT_TYPE_1G, 1) |
  7426. phy_encode(PORT_TYPE_1G, 2) |
  7427. phy_encode(PORT_TYPE_1G, 3));
  7428. break;
  7429. default:
  7430. pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
  7431. num_10g, num_1g);
  7432. return -EINVAL;
  7433. }
  7434. }
  7435. parent->port_phy = val;
  7436. if (parent->plat_type == PLAT_TYPE_NIU)
  7437. niu_n2_divide_channels(parent);
  7438. else
  7439. niu_divide_channels(parent, num_10g, num_1g);
  7440. niu_divide_rdc_groups(parent, num_10g, num_1g);
  7441. return 0;
  7442. unknown_vg_1g_port:
  7443. pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
  7444. return -EINVAL;
  7445. }
  7446. static int __devinit niu_probe_ports(struct niu *np)
  7447. {
  7448. struct niu_parent *parent = np->parent;
  7449. int err, i;
  7450. if (parent->port_phy == PORT_PHY_UNKNOWN) {
  7451. err = walk_phys(np, parent);
  7452. if (err)
  7453. return err;
  7454. niu_set_ldg_timer_res(np, 2);
  7455. for (i = 0; i <= LDN_MAX; i++)
  7456. niu_ldn_irq_enable(np, i, 0);
  7457. }
  7458. if (parent->port_phy == PORT_PHY_INVALID)
  7459. return -EINVAL;
  7460. return 0;
  7461. }
  7462. static int __devinit niu_classifier_swstate_init(struct niu *np)
  7463. {
  7464. struct niu_classifier *cp = &np->clas;
  7465. cp->tcam_top = (u16) np->port;
  7466. cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
  7467. cp->h1_init = 0xffffffff;
  7468. cp->h2_init = 0xffff;
  7469. return fflp_early_init(np);
  7470. }
  7471. static void __devinit niu_link_config_init(struct niu *np)
  7472. {
  7473. struct niu_link_config *lp = &np->link_config;
  7474. lp->advertising = (ADVERTISED_10baseT_Half |
  7475. ADVERTISED_10baseT_Full |
  7476. ADVERTISED_100baseT_Half |
  7477. ADVERTISED_100baseT_Full |
  7478. ADVERTISED_1000baseT_Half |
  7479. ADVERTISED_1000baseT_Full |
  7480. ADVERTISED_10000baseT_Full |
  7481. ADVERTISED_Autoneg);
  7482. lp->speed = lp->active_speed = SPEED_INVALID;
  7483. lp->duplex = DUPLEX_FULL;
  7484. lp->active_duplex = DUPLEX_INVALID;
  7485. lp->autoneg = 1;
  7486. #if 0
  7487. lp->loopback_mode = LOOPBACK_MAC;
  7488. lp->active_speed = SPEED_10000;
  7489. lp->active_duplex = DUPLEX_FULL;
  7490. #else
  7491. lp->loopback_mode = LOOPBACK_DISABLED;
  7492. #endif
  7493. }
  7494. static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
  7495. {
  7496. switch (np->port) {
  7497. case 0:
  7498. np->mac_regs = np->regs + XMAC_PORT0_OFF;
  7499. np->ipp_off = 0x00000;
  7500. np->pcs_off = 0x04000;
  7501. np->xpcs_off = 0x02000;
  7502. break;
  7503. case 1:
  7504. np->mac_regs = np->regs + XMAC_PORT1_OFF;
  7505. np->ipp_off = 0x08000;
  7506. np->pcs_off = 0x0a000;
  7507. np->xpcs_off = 0x08000;
  7508. break;
  7509. case 2:
  7510. np->mac_regs = np->regs + BMAC_PORT2_OFF;
  7511. np->ipp_off = 0x04000;
  7512. np->pcs_off = 0x0e000;
  7513. np->xpcs_off = ~0UL;
  7514. break;
  7515. case 3:
  7516. np->mac_regs = np->regs + BMAC_PORT3_OFF;
  7517. np->ipp_off = 0x0c000;
  7518. np->pcs_off = 0x12000;
  7519. np->xpcs_off = ~0UL;
  7520. break;
  7521. default:
  7522. dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
  7523. return -EINVAL;
  7524. }
  7525. return 0;
  7526. }
  7527. static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
  7528. {
  7529. struct msix_entry msi_vec[NIU_NUM_LDG];
  7530. struct niu_parent *parent = np->parent;
  7531. struct pci_dev *pdev = np->pdev;
  7532. int i, num_irqs, err;
  7533. u8 first_ldg;
  7534. first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
  7535. for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
  7536. ldg_num_map[i] = first_ldg + i;
  7537. num_irqs = (parent->rxchan_per_port[np->port] +
  7538. parent->txchan_per_port[np->port] +
  7539. (np->port == 0 ? 3 : 1));
  7540. BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
  7541. retry:
  7542. for (i = 0; i < num_irqs; i++) {
  7543. msi_vec[i].vector = 0;
  7544. msi_vec[i].entry = i;
  7545. }
  7546. err = pci_enable_msix(pdev, msi_vec, num_irqs);
  7547. if (err < 0) {
  7548. np->flags &= ~NIU_FLAGS_MSIX;
  7549. return;
  7550. }
  7551. if (err > 0) {
  7552. num_irqs = err;
  7553. goto retry;
  7554. }
  7555. np->flags |= NIU_FLAGS_MSIX;
  7556. for (i = 0; i < num_irqs; i++)
  7557. np->ldg[i].irq = msi_vec[i].vector;
  7558. np->num_ldg = num_irqs;
  7559. }
  7560. static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
  7561. {
  7562. #ifdef CONFIG_SPARC64
  7563. struct of_device *op = np->op;
  7564. const u32 *int_prop;
  7565. int i;
  7566. int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
  7567. if (!int_prop)
  7568. return -ENODEV;
  7569. for (i = 0; i < op->num_irqs; i++) {
  7570. ldg_num_map[i] = int_prop[i];
  7571. np->ldg[i].irq = op->irqs[i];
  7572. }
  7573. np->num_ldg = op->num_irqs;
  7574. return 0;
  7575. #else
  7576. return -EINVAL;
  7577. #endif
  7578. }
  7579. static int __devinit niu_ldg_init(struct niu *np)
  7580. {
  7581. struct niu_parent *parent = np->parent;
  7582. u8 ldg_num_map[NIU_NUM_LDG];
  7583. int first_chan, num_chan;
  7584. int i, err, ldg_rotor;
  7585. u8 port;
  7586. np->num_ldg = 1;
  7587. np->ldg[0].irq = np->dev->irq;
  7588. if (parent->plat_type == PLAT_TYPE_NIU) {
  7589. err = niu_n2_irq_init(np, ldg_num_map);
  7590. if (err)
  7591. return err;
  7592. } else
  7593. niu_try_msix(np, ldg_num_map);
  7594. port = np->port;
  7595. for (i = 0; i < np->num_ldg; i++) {
  7596. struct niu_ldg *lp = &np->ldg[i];
  7597. netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
  7598. lp->np = np;
  7599. lp->ldg_num = ldg_num_map[i];
  7600. lp->timer = 2; /* XXX */
  7601. /* On N2 NIU the firmware has setup the SID mappings so they go
  7602. * to the correct values that will route the LDG to the proper
  7603. * interrupt in the NCU interrupt table.
  7604. */
  7605. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  7606. err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
  7607. if (err)
  7608. return err;
  7609. }
  7610. }
  7611. /* We adopt the LDG assignment ordering used by the N2 NIU
  7612. * 'interrupt' properties because that simplifies a lot of
  7613. * things. This ordering is:
  7614. *
  7615. * MAC
  7616. * MIF (if port zero)
  7617. * SYSERR (if port zero)
  7618. * RX channels
  7619. * TX channels
  7620. */
  7621. ldg_rotor = 0;
  7622. err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
  7623. LDN_MAC(port));
  7624. if (err)
  7625. return err;
  7626. ldg_rotor++;
  7627. if (ldg_rotor == np->num_ldg)
  7628. ldg_rotor = 0;
  7629. if (port == 0) {
  7630. err = niu_ldg_assign_ldn(np, parent,
  7631. ldg_num_map[ldg_rotor],
  7632. LDN_MIF);
  7633. if (err)
  7634. return err;
  7635. ldg_rotor++;
  7636. if (ldg_rotor == np->num_ldg)
  7637. ldg_rotor = 0;
  7638. err = niu_ldg_assign_ldn(np, parent,
  7639. ldg_num_map[ldg_rotor],
  7640. LDN_DEVICE_ERROR);
  7641. if (err)
  7642. return err;
  7643. ldg_rotor++;
  7644. if (ldg_rotor == np->num_ldg)
  7645. ldg_rotor = 0;
  7646. }
  7647. first_chan = 0;
  7648. for (i = 0; i < port; i++)
  7649. first_chan += parent->rxchan_per_port[port];
  7650. num_chan = parent->rxchan_per_port[port];
  7651. for (i = first_chan; i < (first_chan + num_chan); i++) {
  7652. err = niu_ldg_assign_ldn(np, parent,
  7653. ldg_num_map[ldg_rotor],
  7654. LDN_RXDMA(i));
  7655. if (err)
  7656. return err;
  7657. ldg_rotor++;
  7658. if (ldg_rotor == np->num_ldg)
  7659. ldg_rotor = 0;
  7660. }
  7661. first_chan = 0;
  7662. for (i = 0; i < port; i++)
  7663. first_chan += parent->txchan_per_port[port];
  7664. num_chan = parent->txchan_per_port[port];
  7665. for (i = first_chan; i < (first_chan + num_chan); i++) {
  7666. err = niu_ldg_assign_ldn(np, parent,
  7667. ldg_num_map[ldg_rotor],
  7668. LDN_TXDMA(i));
  7669. if (err)
  7670. return err;
  7671. ldg_rotor++;
  7672. if (ldg_rotor == np->num_ldg)
  7673. ldg_rotor = 0;
  7674. }
  7675. return 0;
  7676. }
  7677. static void __devexit niu_ldg_free(struct niu *np)
  7678. {
  7679. if (np->flags & NIU_FLAGS_MSIX)
  7680. pci_disable_msix(np->pdev);
  7681. }
  7682. static int __devinit niu_get_of_props(struct niu *np)
  7683. {
  7684. #ifdef CONFIG_SPARC64
  7685. struct net_device *dev = np->dev;
  7686. struct device_node *dp;
  7687. const char *phy_type;
  7688. const u8 *mac_addr;
  7689. const char *model;
  7690. int prop_len;
  7691. if (np->parent->plat_type == PLAT_TYPE_NIU)
  7692. dp = np->op->dev.of_node;
  7693. else
  7694. dp = pci_device_to_OF_node(np->pdev);
  7695. phy_type = of_get_property(dp, "phy-type", &prop_len);
  7696. if (!phy_type) {
  7697. netdev_err(dev, "%s: OF node lacks phy-type property\n",
  7698. dp->full_name);
  7699. return -EINVAL;
  7700. }
  7701. if (!strcmp(phy_type, "none"))
  7702. return -ENODEV;
  7703. strcpy(np->vpd.phy_type, phy_type);
  7704. if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
  7705. netdev_err(dev, "%s: Illegal phy string [%s]\n",
  7706. dp->full_name, np->vpd.phy_type);
  7707. return -EINVAL;
  7708. }
  7709. mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
  7710. if (!mac_addr) {
  7711. netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
  7712. dp->full_name);
  7713. return -EINVAL;
  7714. }
  7715. if (prop_len != dev->addr_len) {
  7716. netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
  7717. dp->full_name, prop_len);
  7718. }
  7719. memcpy(dev->perm_addr, mac_addr, dev->addr_len);
  7720. if (!is_valid_ether_addr(&dev->perm_addr[0])) {
  7721. netdev_err(dev, "%s: OF MAC address is invalid\n",
  7722. dp->full_name);
  7723. netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
  7724. return -EINVAL;
  7725. }
  7726. memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
  7727. model = of_get_property(dp, "model", &prop_len);
  7728. if (model)
  7729. strcpy(np->vpd.model, model);
  7730. if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
  7731. np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
  7732. NIU_FLAGS_HOTPLUG_PHY);
  7733. }
  7734. return 0;
  7735. #else
  7736. return -EINVAL;
  7737. #endif
  7738. }
  7739. static int __devinit niu_get_invariants(struct niu *np)
  7740. {
  7741. int err, have_props;
  7742. u32 offset;
  7743. err = niu_get_of_props(np);
  7744. if (err == -ENODEV)
  7745. return err;
  7746. have_props = !err;
  7747. err = niu_init_mac_ipp_pcs_base(np);
  7748. if (err)
  7749. return err;
  7750. if (have_props) {
  7751. err = niu_get_and_validate_port(np);
  7752. if (err)
  7753. return err;
  7754. } else {
  7755. if (np->parent->plat_type == PLAT_TYPE_NIU)
  7756. return -EINVAL;
  7757. nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
  7758. offset = niu_pci_vpd_offset(np);
  7759. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7760. "%s() VPD offset [%08x]\n", __func__, offset);
  7761. if (offset)
  7762. niu_pci_vpd_fetch(np, offset);
  7763. nw64(ESPC_PIO_EN, 0);
  7764. if (np->flags & NIU_FLAGS_VPD_VALID) {
  7765. niu_pci_vpd_validate(np);
  7766. err = niu_get_and_validate_port(np);
  7767. if (err)
  7768. return err;
  7769. }
  7770. if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
  7771. err = niu_get_and_validate_port(np);
  7772. if (err)
  7773. return err;
  7774. err = niu_pci_probe_sprom(np);
  7775. if (err)
  7776. return err;
  7777. }
  7778. }
  7779. err = niu_probe_ports(np);
  7780. if (err)
  7781. return err;
  7782. niu_ldg_init(np);
  7783. niu_classifier_swstate_init(np);
  7784. niu_link_config_init(np);
  7785. err = niu_determine_phy_disposition(np);
  7786. if (!err)
  7787. err = niu_init_link(np);
  7788. return err;
  7789. }
  7790. static LIST_HEAD(niu_parent_list);
  7791. static DEFINE_MUTEX(niu_parent_lock);
  7792. static int niu_parent_index;
  7793. static ssize_t show_port_phy(struct device *dev,
  7794. struct device_attribute *attr, char *buf)
  7795. {
  7796. struct platform_device *plat_dev = to_platform_device(dev);
  7797. struct niu_parent *p = plat_dev->dev.platform_data;
  7798. u32 port_phy = p->port_phy;
  7799. char *orig_buf = buf;
  7800. int i;
  7801. if (port_phy == PORT_PHY_UNKNOWN ||
  7802. port_phy == PORT_PHY_INVALID)
  7803. return 0;
  7804. for (i = 0; i < p->num_ports; i++) {
  7805. const char *type_str;
  7806. int type;
  7807. type = phy_decode(port_phy, i);
  7808. if (type == PORT_TYPE_10G)
  7809. type_str = "10G";
  7810. else
  7811. type_str = "1G";
  7812. buf += sprintf(buf,
  7813. (i == 0) ? "%s" : " %s",
  7814. type_str);
  7815. }
  7816. buf += sprintf(buf, "\n");
  7817. return buf - orig_buf;
  7818. }
  7819. static ssize_t show_plat_type(struct device *dev,
  7820. struct device_attribute *attr, char *buf)
  7821. {
  7822. struct platform_device *plat_dev = to_platform_device(dev);
  7823. struct niu_parent *p = plat_dev->dev.platform_data;
  7824. const char *type_str;
  7825. switch (p->plat_type) {
  7826. case PLAT_TYPE_ATLAS:
  7827. type_str = "atlas";
  7828. break;
  7829. case PLAT_TYPE_NIU:
  7830. type_str = "niu";
  7831. break;
  7832. case PLAT_TYPE_VF_P0:
  7833. type_str = "vf_p0";
  7834. break;
  7835. case PLAT_TYPE_VF_P1:
  7836. type_str = "vf_p1";
  7837. break;
  7838. default:
  7839. type_str = "unknown";
  7840. break;
  7841. }
  7842. return sprintf(buf, "%s\n", type_str);
  7843. }
  7844. static ssize_t __show_chan_per_port(struct device *dev,
  7845. struct device_attribute *attr, char *buf,
  7846. int rx)
  7847. {
  7848. struct platform_device *plat_dev = to_platform_device(dev);
  7849. struct niu_parent *p = plat_dev->dev.platform_data;
  7850. char *orig_buf = buf;
  7851. u8 *arr;
  7852. int i;
  7853. arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
  7854. for (i = 0; i < p->num_ports; i++) {
  7855. buf += sprintf(buf,
  7856. (i == 0) ? "%d" : " %d",
  7857. arr[i]);
  7858. }
  7859. buf += sprintf(buf, "\n");
  7860. return buf - orig_buf;
  7861. }
  7862. static ssize_t show_rxchan_per_port(struct device *dev,
  7863. struct device_attribute *attr, char *buf)
  7864. {
  7865. return __show_chan_per_port(dev, attr, buf, 1);
  7866. }
  7867. static ssize_t show_txchan_per_port(struct device *dev,
  7868. struct device_attribute *attr, char *buf)
  7869. {
  7870. return __show_chan_per_port(dev, attr, buf, 1);
  7871. }
  7872. static ssize_t show_num_ports(struct device *dev,
  7873. struct device_attribute *attr, char *buf)
  7874. {
  7875. struct platform_device *plat_dev = to_platform_device(dev);
  7876. struct niu_parent *p = plat_dev->dev.platform_data;
  7877. return sprintf(buf, "%d\n", p->num_ports);
  7878. }
  7879. static struct device_attribute niu_parent_attributes[] = {
  7880. __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
  7881. __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
  7882. __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
  7883. __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
  7884. __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
  7885. {}
  7886. };
  7887. static struct niu_parent * __devinit niu_new_parent(struct niu *np,
  7888. union niu_parent_id *id,
  7889. u8 ptype)
  7890. {
  7891. struct platform_device *plat_dev;
  7892. struct niu_parent *p;
  7893. int i;
  7894. plat_dev = platform_device_register_simple("niu", niu_parent_index,
  7895. NULL, 0);
  7896. if (IS_ERR(plat_dev))
  7897. return NULL;
  7898. for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
  7899. int err = device_create_file(&plat_dev->dev,
  7900. &niu_parent_attributes[i]);
  7901. if (err)
  7902. goto fail_unregister;
  7903. }
  7904. p = kzalloc(sizeof(*p), GFP_KERNEL);
  7905. if (!p)
  7906. goto fail_unregister;
  7907. p->index = niu_parent_index++;
  7908. plat_dev->dev.platform_data = p;
  7909. p->plat_dev = plat_dev;
  7910. memcpy(&p->id, id, sizeof(*id));
  7911. p->plat_type = ptype;
  7912. INIT_LIST_HEAD(&p->list);
  7913. atomic_set(&p->refcnt, 0);
  7914. list_add(&p->list, &niu_parent_list);
  7915. spin_lock_init(&p->lock);
  7916. p->rxdma_clock_divider = 7500;
  7917. p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
  7918. if (p->plat_type == PLAT_TYPE_NIU)
  7919. p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
  7920. for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
  7921. int index = i - CLASS_CODE_USER_PROG1;
  7922. p->tcam_key[index] = TCAM_KEY_TSEL;
  7923. p->flow_key[index] = (FLOW_KEY_IPSA |
  7924. FLOW_KEY_IPDA |
  7925. FLOW_KEY_PROTO |
  7926. (FLOW_KEY_L4_BYTE12 <<
  7927. FLOW_KEY_L4_0_SHIFT) |
  7928. (FLOW_KEY_L4_BYTE12 <<
  7929. FLOW_KEY_L4_1_SHIFT));
  7930. }
  7931. for (i = 0; i < LDN_MAX + 1; i++)
  7932. p->ldg_map[i] = LDG_INVALID;
  7933. return p;
  7934. fail_unregister:
  7935. platform_device_unregister(plat_dev);
  7936. return NULL;
  7937. }
  7938. static struct niu_parent * __devinit niu_get_parent(struct niu *np,
  7939. union niu_parent_id *id,
  7940. u8 ptype)
  7941. {
  7942. struct niu_parent *p, *tmp;
  7943. int port = np->port;
  7944. mutex_lock(&niu_parent_lock);
  7945. p = NULL;
  7946. list_for_each_entry(tmp, &niu_parent_list, list) {
  7947. if (!memcmp(id, &tmp->id, sizeof(*id))) {
  7948. p = tmp;
  7949. break;
  7950. }
  7951. }
  7952. if (!p)
  7953. p = niu_new_parent(np, id, ptype);
  7954. if (p) {
  7955. char port_name[6];
  7956. int err;
  7957. sprintf(port_name, "port%d", port);
  7958. err = sysfs_create_link(&p->plat_dev->dev.kobj,
  7959. &np->device->kobj,
  7960. port_name);
  7961. if (!err) {
  7962. p->ports[port] = np;
  7963. atomic_inc(&p->refcnt);
  7964. }
  7965. }
  7966. mutex_unlock(&niu_parent_lock);
  7967. return p;
  7968. }
  7969. static void niu_put_parent(struct niu *np)
  7970. {
  7971. struct niu_parent *p = np->parent;
  7972. u8 port = np->port;
  7973. char port_name[6];
  7974. BUG_ON(!p || p->ports[port] != np);
  7975. netif_printk(np, probe, KERN_DEBUG, np->dev,
  7976. "%s() port[%u]\n", __func__, port);
  7977. sprintf(port_name, "port%d", port);
  7978. mutex_lock(&niu_parent_lock);
  7979. sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
  7980. p->ports[port] = NULL;
  7981. np->parent = NULL;
  7982. if (atomic_dec_and_test(&p->refcnt)) {
  7983. list_del(&p->list);
  7984. platform_device_unregister(p->plat_dev);
  7985. }
  7986. mutex_unlock(&niu_parent_lock);
  7987. }
  7988. static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
  7989. u64 *handle, gfp_t flag)
  7990. {
  7991. dma_addr_t dh;
  7992. void *ret;
  7993. ret = dma_alloc_coherent(dev, size, &dh, flag);
  7994. if (ret)
  7995. *handle = dh;
  7996. return ret;
  7997. }
  7998. static void niu_pci_free_coherent(struct device *dev, size_t size,
  7999. void *cpu_addr, u64 handle)
  8000. {
  8001. dma_free_coherent(dev, size, cpu_addr, handle);
  8002. }
  8003. static u64 niu_pci_map_page(struct device *dev, struct page *page,
  8004. unsigned long offset, size_t size,
  8005. enum dma_data_direction direction)
  8006. {
  8007. return dma_map_page(dev, page, offset, size, direction);
  8008. }
  8009. static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
  8010. size_t size, enum dma_data_direction direction)
  8011. {
  8012. dma_unmap_page(dev, dma_address, size, direction);
  8013. }
  8014. static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
  8015. size_t size,
  8016. enum dma_data_direction direction)
  8017. {
  8018. return dma_map_single(dev, cpu_addr, size, direction);
  8019. }
  8020. static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
  8021. size_t size,
  8022. enum dma_data_direction direction)
  8023. {
  8024. dma_unmap_single(dev, dma_address, size, direction);
  8025. }
  8026. static const struct niu_ops niu_pci_ops = {
  8027. .alloc_coherent = niu_pci_alloc_coherent,
  8028. .free_coherent = niu_pci_free_coherent,
  8029. .map_page = niu_pci_map_page,
  8030. .unmap_page = niu_pci_unmap_page,
  8031. .map_single = niu_pci_map_single,
  8032. .unmap_single = niu_pci_unmap_single,
  8033. };
  8034. static void __devinit niu_driver_version(void)
  8035. {
  8036. static int niu_version_printed;
  8037. if (niu_version_printed++ == 0)
  8038. pr_info("%s", version);
  8039. }
  8040. static struct net_device * __devinit niu_alloc_and_init(
  8041. struct device *gen_dev, struct pci_dev *pdev,
  8042. struct of_device *op, const struct niu_ops *ops,
  8043. u8 port)
  8044. {
  8045. struct net_device *dev;
  8046. struct niu *np;
  8047. dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
  8048. if (!dev) {
  8049. dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
  8050. return NULL;
  8051. }
  8052. SET_NETDEV_DEV(dev, gen_dev);
  8053. np = netdev_priv(dev);
  8054. np->dev = dev;
  8055. np->pdev = pdev;
  8056. np->op = op;
  8057. np->device = gen_dev;
  8058. np->ops = ops;
  8059. np->msg_enable = niu_debug;
  8060. spin_lock_init(&np->lock);
  8061. INIT_WORK(&np->reset_task, niu_reset_task);
  8062. np->port = port;
  8063. return dev;
  8064. }
  8065. static const struct net_device_ops niu_netdev_ops = {
  8066. .ndo_open = niu_open,
  8067. .ndo_stop = niu_close,
  8068. .ndo_start_xmit = niu_start_xmit,
  8069. .ndo_get_stats = niu_get_stats,
  8070. .ndo_set_multicast_list = niu_set_rx_mode,
  8071. .ndo_validate_addr = eth_validate_addr,
  8072. .ndo_set_mac_address = niu_set_mac_addr,
  8073. .ndo_do_ioctl = niu_ioctl,
  8074. .ndo_tx_timeout = niu_tx_timeout,
  8075. .ndo_change_mtu = niu_change_mtu,
  8076. };
  8077. static void __devinit niu_assign_netdev_ops(struct net_device *dev)
  8078. {
  8079. dev->netdev_ops = &niu_netdev_ops;
  8080. dev->ethtool_ops = &niu_ethtool_ops;
  8081. dev->watchdog_timeo = NIU_TX_TIMEOUT;
  8082. }
  8083. static void __devinit niu_device_announce(struct niu *np)
  8084. {
  8085. struct net_device *dev = np->dev;
  8086. pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
  8087. if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
  8088. pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
  8089. dev->name,
  8090. (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
  8091. (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
  8092. (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
  8093. (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
  8094. (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
  8095. np->vpd.phy_type);
  8096. } else {
  8097. pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
  8098. dev->name,
  8099. (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
  8100. (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
  8101. (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
  8102. (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
  8103. "COPPER")),
  8104. (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
  8105. (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
  8106. np->vpd.phy_type);
  8107. }
  8108. }
  8109. static void __devinit niu_set_basic_features(struct net_device *dev)
  8110. {
  8111. dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM |
  8112. NETIF_F_GRO | NETIF_F_RXHASH);
  8113. }
  8114. static int __devinit niu_pci_init_one(struct pci_dev *pdev,
  8115. const struct pci_device_id *ent)
  8116. {
  8117. union niu_parent_id parent_id;
  8118. struct net_device *dev;
  8119. struct niu *np;
  8120. int err, pos;
  8121. u64 dma_mask;
  8122. u16 val16;
  8123. niu_driver_version();
  8124. err = pci_enable_device(pdev);
  8125. if (err) {
  8126. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  8127. return err;
  8128. }
  8129. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  8130. !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  8131. dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
  8132. err = -ENODEV;
  8133. goto err_out_disable_pdev;
  8134. }
  8135. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  8136. if (err) {
  8137. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  8138. goto err_out_disable_pdev;
  8139. }
  8140. pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
  8141. if (pos <= 0) {
  8142. dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
  8143. goto err_out_free_res;
  8144. }
  8145. dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
  8146. &niu_pci_ops, PCI_FUNC(pdev->devfn));
  8147. if (!dev) {
  8148. err = -ENOMEM;
  8149. goto err_out_free_res;
  8150. }
  8151. np = netdev_priv(dev);
  8152. memset(&parent_id, 0, sizeof(parent_id));
  8153. parent_id.pci.domain = pci_domain_nr(pdev->bus);
  8154. parent_id.pci.bus = pdev->bus->number;
  8155. parent_id.pci.device = PCI_SLOT(pdev->devfn);
  8156. np->parent = niu_get_parent(np, &parent_id,
  8157. PLAT_TYPE_ATLAS);
  8158. if (!np->parent) {
  8159. err = -ENOMEM;
  8160. goto err_out_free_dev;
  8161. }
  8162. pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
  8163. val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
  8164. val16 |= (PCI_EXP_DEVCTL_CERE |
  8165. PCI_EXP_DEVCTL_NFERE |
  8166. PCI_EXP_DEVCTL_FERE |
  8167. PCI_EXP_DEVCTL_URRE |
  8168. PCI_EXP_DEVCTL_RELAX_EN);
  8169. pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
  8170. dma_mask = DMA_BIT_MASK(44);
  8171. err = pci_set_dma_mask(pdev, dma_mask);
  8172. if (!err) {
  8173. dev->features |= NETIF_F_HIGHDMA;
  8174. err = pci_set_consistent_dma_mask(pdev, dma_mask);
  8175. if (err) {
  8176. dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
  8177. goto err_out_release_parent;
  8178. }
  8179. }
  8180. if (err || dma_mask == DMA_BIT_MASK(32)) {
  8181. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  8182. if (err) {
  8183. dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
  8184. goto err_out_release_parent;
  8185. }
  8186. }
  8187. niu_set_basic_features(dev);
  8188. np->regs = pci_ioremap_bar(pdev, 0);
  8189. if (!np->regs) {
  8190. dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
  8191. err = -ENOMEM;
  8192. goto err_out_release_parent;
  8193. }
  8194. pci_set_master(pdev);
  8195. pci_save_state(pdev);
  8196. dev->irq = pdev->irq;
  8197. niu_assign_netdev_ops(dev);
  8198. err = niu_get_invariants(np);
  8199. if (err) {
  8200. if (err != -ENODEV)
  8201. dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
  8202. goto err_out_iounmap;
  8203. }
  8204. err = register_netdev(dev);
  8205. if (err) {
  8206. dev_err(&pdev->dev, "Cannot register net device, aborting\n");
  8207. goto err_out_iounmap;
  8208. }
  8209. pci_set_drvdata(pdev, dev);
  8210. niu_device_announce(np);
  8211. return 0;
  8212. err_out_iounmap:
  8213. if (np->regs) {
  8214. iounmap(np->regs);
  8215. np->regs = NULL;
  8216. }
  8217. err_out_release_parent:
  8218. niu_put_parent(np);
  8219. err_out_free_dev:
  8220. free_netdev(dev);
  8221. err_out_free_res:
  8222. pci_release_regions(pdev);
  8223. err_out_disable_pdev:
  8224. pci_disable_device(pdev);
  8225. pci_set_drvdata(pdev, NULL);
  8226. return err;
  8227. }
  8228. static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
  8229. {
  8230. struct net_device *dev = pci_get_drvdata(pdev);
  8231. if (dev) {
  8232. struct niu *np = netdev_priv(dev);
  8233. unregister_netdev(dev);
  8234. if (np->regs) {
  8235. iounmap(np->regs);
  8236. np->regs = NULL;
  8237. }
  8238. niu_ldg_free(np);
  8239. niu_put_parent(np);
  8240. free_netdev(dev);
  8241. pci_release_regions(pdev);
  8242. pci_disable_device(pdev);
  8243. pci_set_drvdata(pdev, NULL);
  8244. }
  8245. }
  8246. static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
  8247. {
  8248. struct net_device *dev = pci_get_drvdata(pdev);
  8249. struct niu *np = netdev_priv(dev);
  8250. unsigned long flags;
  8251. if (!netif_running(dev))
  8252. return 0;
  8253. flush_scheduled_work();
  8254. niu_netif_stop(np);
  8255. del_timer_sync(&np->timer);
  8256. spin_lock_irqsave(&np->lock, flags);
  8257. niu_enable_interrupts(np, 0);
  8258. spin_unlock_irqrestore(&np->lock, flags);
  8259. netif_device_detach(dev);
  8260. spin_lock_irqsave(&np->lock, flags);
  8261. niu_stop_hw(np);
  8262. spin_unlock_irqrestore(&np->lock, flags);
  8263. pci_save_state(pdev);
  8264. return 0;
  8265. }
  8266. static int niu_resume(struct pci_dev *pdev)
  8267. {
  8268. struct net_device *dev = pci_get_drvdata(pdev);
  8269. struct niu *np = netdev_priv(dev);
  8270. unsigned long flags;
  8271. int err;
  8272. if (!netif_running(dev))
  8273. return 0;
  8274. pci_restore_state(pdev);
  8275. netif_device_attach(dev);
  8276. spin_lock_irqsave(&np->lock, flags);
  8277. err = niu_init_hw(np);
  8278. if (!err) {
  8279. np->timer.expires = jiffies + HZ;
  8280. add_timer(&np->timer);
  8281. niu_netif_start(np);
  8282. }
  8283. spin_unlock_irqrestore(&np->lock, flags);
  8284. return err;
  8285. }
  8286. static struct pci_driver niu_pci_driver = {
  8287. .name = DRV_MODULE_NAME,
  8288. .id_table = niu_pci_tbl,
  8289. .probe = niu_pci_init_one,
  8290. .remove = __devexit_p(niu_pci_remove_one),
  8291. .suspend = niu_suspend,
  8292. .resume = niu_resume,
  8293. };
  8294. #ifdef CONFIG_SPARC64
  8295. static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
  8296. u64 *dma_addr, gfp_t flag)
  8297. {
  8298. unsigned long order = get_order(size);
  8299. unsigned long page = __get_free_pages(flag, order);
  8300. if (page == 0UL)
  8301. return NULL;
  8302. memset((char *)page, 0, PAGE_SIZE << order);
  8303. *dma_addr = __pa(page);
  8304. return (void *) page;
  8305. }
  8306. static void niu_phys_free_coherent(struct device *dev, size_t size,
  8307. void *cpu_addr, u64 handle)
  8308. {
  8309. unsigned long order = get_order(size);
  8310. free_pages((unsigned long) cpu_addr, order);
  8311. }
  8312. static u64 niu_phys_map_page(struct device *dev, struct page *page,
  8313. unsigned long offset, size_t size,
  8314. enum dma_data_direction direction)
  8315. {
  8316. return page_to_phys(page) + offset;
  8317. }
  8318. static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
  8319. size_t size, enum dma_data_direction direction)
  8320. {
  8321. /* Nothing to do. */
  8322. }
  8323. static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
  8324. size_t size,
  8325. enum dma_data_direction direction)
  8326. {
  8327. return __pa(cpu_addr);
  8328. }
  8329. static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
  8330. size_t size,
  8331. enum dma_data_direction direction)
  8332. {
  8333. /* Nothing to do. */
  8334. }
  8335. static const struct niu_ops niu_phys_ops = {
  8336. .alloc_coherent = niu_phys_alloc_coherent,
  8337. .free_coherent = niu_phys_free_coherent,
  8338. .map_page = niu_phys_map_page,
  8339. .unmap_page = niu_phys_unmap_page,
  8340. .map_single = niu_phys_map_single,
  8341. .unmap_single = niu_phys_unmap_single,
  8342. };
  8343. static int __devinit niu_of_probe(struct of_device *op,
  8344. const struct of_device_id *match)
  8345. {
  8346. union niu_parent_id parent_id;
  8347. struct net_device *dev;
  8348. struct niu *np;
  8349. const u32 *reg;
  8350. int err;
  8351. niu_driver_version();
  8352. reg = of_get_property(op->dev.of_node, "reg", NULL);
  8353. if (!reg) {
  8354. dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
  8355. op->dev.of_node->full_name);
  8356. return -ENODEV;
  8357. }
  8358. dev = niu_alloc_and_init(&op->dev, NULL, op,
  8359. &niu_phys_ops, reg[0] & 0x1);
  8360. if (!dev) {
  8361. err = -ENOMEM;
  8362. goto err_out;
  8363. }
  8364. np = netdev_priv(dev);
  8365. memset(&parent_id, 0, sizeof(parent_id));
  8366. parent_id.of = of_get_parent(op->dev.of_node);
  8367. np->parent = niu_get_parent(np, &parent_id,
  8368. PLAT_TYPE_NIU);
  8369. if (!np->parent) {
  8370. err = -ENOMEM;
  8371. goto err_out_free_dev;
  8372. }
  8373. niu_set_basic_features(dev);
  8374. np->regs = of_ioremap(&op->resource[1], 0,
  8375. resource_size(&op->resource[1]),
  8376. "niu regs");
  8377. if (!np->regs) {
  8378. dev_err(&op->dev, "Cannot map device registers, aborting\n");
  8379. err = -ENOMEM;
  8380. goto err_out_release_parent;
  8381. }
  8382. np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
  8383. resource_size(&op->resource[2]),
  8384. "niu vregs-1");
  8385. if (!np->vir_regs_1) {
  8386. dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
  8387. err = -ENOMEM;
  8388. goto err_out_iounmap;
  8389. }
  8390. np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
  8391. resource_size(&op->resource[3]),
  8392. "niu vregs-2");
  8393. if (!np->vir_regs_2) {
  8394. dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
  8395. err = -ENOMEM;
  8396. goto err_out_iounmap;
  8397. }
  8398. niu_assign_netdev_ops(dev);
  8399. err = niu_get_invariants(np);
  8400. if (err) {
  8401. if (err != -ENODEV)
  8402. dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
  8403. goto err_out_iounmap;
  8404. }
  8405. err = register_netdev(dev);
  8406. if (err) {
  8407. dev_err(&op->dev, "Cannot register net device, aborting\n");
  8408. goto err_out_iounmap;
  8409. }
  8410. dev_set_drvdata(&op->dev, dev);
  8411. niu_device_announce(np);
  8412. return 0;
  8413. err_out_iounmap:
  8414. if (np->vir_regs_1) {
  8415. of_iounmap(&op->resource[2], np->vir_regs_1,
  8416. resource_size(&op->resource[2]));
  8417. np->vir_regs_1 = NULL;
  8418. }
  8419. if (np->vir_regs_2) {
  8420. of_iounmap(&op->resource[3], np->vir_regs_2,
  8421. resource_size(&op->resource[3]));
  8422. np->vir_regs_2 = NULL;
  8423. }
  8424. if (np->regs) {
  8425. of_iounmap(&op->resource[1], np->regs,
  8426. resource_size(&op->resource[1]));
  8427. np->regs = NULL;
  8428. }
  8429. err_out_release_parent:
  8430. niu_put_parent(np);
  8431. err_out_free_dev:
  8432. free_netdev(dev);
  8433. err_out:
  8434. return err;
  8435. }
  8436. static int __devexit niu_of_remove(struct of_device *op)
  8437. {
  8438. struct net_device *dev = dev_get_drvdata(&op->dev);
  8439. if (dev) {
  8440. struct niu *np = netdev_priv(dev);
  8441. unregister_netdev(dev);
  8442. if (np->vir_regs_1) {
  8443. of_iounmap(&op->resource[2], np->vir_regs_1,
  8444. resource_size(&op->resource[2]));
  8445. np->vir_regs_1 = NULL;
  8446. }
  8447. if (np->vir_regs_2) {
  8448. of_iounmap(&op->resource[3], np->vir_regs_2,
  8449. resource_size(&op->resource[3]));
  8450. np->vir_regs_2 = NULL;
  8451. }
  8452. if (np->regs) {
  8453. of_iounmap(&op->resource[1], np->regs,
  8454. resource_size(&op->resource[1]));
  8455. np->regs = NULL;
  8456. }
  8457. niu_ldg_free(np);
  8458. niu_put_parent(np);
  8459. free_netdev(dev);
  8460. dev_set_drvdata(&op->dev, NULL);
  8461. }
  8462. return 0;
  8463. }
  8464. static const struct of_device_id niu_match[] = {
  8465. {
  8466. .name = "network",
  8467. .compatible = "SUNW,niusl",
  8468. },
  8469. {},
  8470. };
  8471. MODULE_DEVICE_TABLE(of, niu_match);
  8472. static struct of_platform_driver niu_of_driver = {
  8473. .driver = {
  8474. .name = "niu",
  8475. .owner = THIS_MODULE,
  8476. .of_match_table = niu_match,
  8477. },
  8478. .probe = niu_of_probe,
  8479. .remove = __devexit_p(niu_of_remove),
  8480. };
  8481. #endif /* CONFIG_SPARC64 */
  8482. static int __init niu_init(void)
  8483. {
  8484. int err = 0;
  8485. BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
  8486. niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
  8487. #ifdef CONFIG_SPARC64
  8488. err = of_register_driver(&niu_of_driver, &of_bus_type);
  8489. #endif
  8490. if (!err) {
  8491. err = pci_register_driver(&niu_pci_driver);
  8492. #ifdef CONFIG_SPARC64
  8493. if (err)
  8494. of_unregister_driver(&niu_of_driver);
  8495. #endif
  8496. }
  8497. return err;
  8498. }
  8499. static void __exit niu_exit(void)
  8500. {
  8501. pci_unregister_driver(&niu_pci_driver);
  8502. #ifdef CONFIG_SPARC64
  8503. of_unregister_driver(&niu_of_driver);
  8504. #endif
  8505. }
  8506. module_init(niu_init);
  8507. module_exit(niu_exit);