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/drivers/gpu/drm/radeon/evergreen_cs.c

https://gitlab.com/tbwtiot/kernel_source
C | 3514 lines | 3157 code | 168 blank | 189 comment | 421 complexity | 0ccf203e8bc0538e0da0bcd10c886abd MD5 | raw file
Possible License(s): GPL-2.0
  1. /*
  2. * Copyright 2010 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <drm/drmP.h>
  29. #include "radeon.h"
  30. #include "evergreend.h"
  31. #include "evergreen_reg_safe.h"
  32. #include "cayman_reg_safe.h"
  33. #define MAX(a,b) (((a)>(b))?(a):(b))
  34. #define MIN(a,b) (((a)<(b))?(a):(b))
  35. int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
  36. struct radeon_cs_reloc **cs_reloc);
  37. struct evergreen_cs_track {
  38. u32 group_size;
  39. u32 nbanks;
  40. u32 npipes;
  41. u32 row_size;
  42. /* value we track */
  43. u32 nsamples; /* unused */
  44. struct radeon_bo *cb_color_bo[12];
  45. u32 cb_color_bo_offset[12];
  46. struct radeon_bo *cb_color_fmask_bo[8]; /* unused */
  47. struct radeon_bo *cb_color_cmask_bo[8]; /* unused */
  48. u32 cb_color_info[12];
  49. u32 cb_color_view[12];
  50. u32 cb_color_pitch[12];
  51. u32 cb_color_slice[12];
  52. u32 cb_color_slice_idx[12];
  53. u32 cb_color_attrib[12];
  54. u32 cb_color_cmask_slice[8];/* unused */
  55. u32 cb_color_fmask_slice[8];/* unused */
  56. u32 cb_target_mask;
  57. u32 cb_shader_mask; /* unused */
  58. u32 vgt_strmout_config;
  59. u32 vgt_strmout_buffer_config;
  60. struct radeon_bo *vgt_strmout_bo[4];
  61. u32 vgt_strmout_bo_offset[4];
  62. u32 vgt_strmout_size[4];
  63. u32 db_depth_control;
  64. u32 db_depth_view;
  65. u32 db_depth_slice;
  66. u32 db_depth_size;
  67. u32 db_z_info;
  68. u32 db_z_read_offset;
  69. u32 db_z_write_offset;
  70. struct radeon_bo *db_z_read_bo;
  71. struct radeon_bo *db_z_write_bo;
  72. u32 db_s_info;
  73. u32 db_s_read_offset;
  74. u32 db_s_write_offset;
  75. struct radeon_bo *db_s_read_bo;
  76. struct radeon_bo *db_s_write_bo;
  77. bool sx_misc_kill_all_prims;
  78. bool cb_dirty;
  79. bool db_dirty;
  80. bool streamout_dirty;
  81. u32 htile_offset;
  82. u32 htile_surface;
  83. struct radeon_bo *htile_bo;
  84. };
  85. static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
  86. {
  87. if (tiling_flags & RADEON_TILING_MACRO)
  88. return ARRAY_2D_TILED_THIN1;
  89. else if (tiling_flags & RADEON_TILING_MICRO)
  90. return ARRAY_1D_TILED_THIN1;
  91. else
  92. return ARRAY_LINEAR_GENERAL;
  93. }
  94. static u32 evergreen_cs_get_num_banks(u32 nbanks)
  95. {
  96. switch (nbanks) {
  97. case 2:
  98. return ADDR_SURF_2_BANK;
  99. case 4:
  100. return ADDR_SURF_4_BANK;
  101. case 8:
  102. default:
  103. return ADDR_SURF_8_BANK;
  104. case 16:
  105. return ADDR_SURF_16_BANK;
  106. }
  107. }
  108. static void evergreen_cs_track_init(struct evergreen_cs_track *track)
  109. {
  110. int i;
  111. for (i = 0; i < 8; i++) {
  112. track->cb_color_fmask_bo[i] = NULL;
  113. track->cb_color_cmask_bo[i] = NULL;
  114. track->cb_color_cmask_slice[i] = 0;
  115. track->cb_color_fmask_slice[i] = 0;
  116. }
  117. for (i = 0; i < 12; i++) {
  118. track->cb_color_bo[i] = NULL;
  119. track->cb_color_bo_offset[i] = 0xFFFFFFFF;
  120. track->cb_color_info[i] = 0;
  121. track->cb_color_view[i] = 0xFFFFFFFF;
  122. track->cb_color_pitch[i] = 0;
  123. track->cb_color_slice[i] = 0xfffffff;
  124. track->cb_color_slice_idx[i] = 0;
  125. }
  126. track->cb_target_mask = 0xFFFFFFFF;
  127. track->cb_shader_mask = 0xFFFFFFFF;
  128. track->cb_dirty = true;
  129. track->db_depth_slice = 0xffffffff;
  130. track->db_depth_view = 0xFFFFC000;
  131. track->db_depth_size = 0xFFFFFFFF;
  132. track->db_depth_control = 0xFFFFFFFF;
  133. track->db_z_info = 0xFFFFFFFF;
  134. track->db_z_read_offset = 0xFFFFFFFF;
  135. track->db_z_write_offset = 0xFFFFFFFF;
  136. track->db_z_read_bo = NULL;
  137. track->db_z_write_bo = NULL;
  138. track->db_s_info = 0xFFFFFFFF;
  139. track->db_s_read_offset = 0xFFFFFFFF;
  140. track->db_s_write_offset = 0xFFFFFFFF;
  141. track->db_s_read_bo = NULL;
  142. track->db_s_write_bo = NULL;
  143. track->db_dirty = true;
  144. track->htile_bo = NULL;
  145. track->htile_offset = 0xFFFFFFFF;
  146. track->htile_surface = 0;
  147. for (i = 0; i < 4; i++) {
  148. track->vgt_strmout_size[i] = 0;
  149. track->vgt_strmout_bo[i] = NULL;
  150. track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
  151. }
  152. track->streamout_dirty = true;
  153. track->sx_misc_kill_all_prims = false;
  154. }
  155. struct eg_surface {
  156. /* value gathered from cs */
  157. unsigned nbx;
  158. unsigned nby;
  159. unsigned format;
  160. unsigned mode;
  161. unsigned nbanks;
  162. unsigned bankw;
  163. unsigned bankh;
  164. unsigned tsplit;
  165. unsigned mtilea;
  166. unsigned nsamples;
  167. /* output value */
  168. unsigned bpe;
  169. unsigned layer_size;
  170. unsigned palign;
  171. unsigned halign;
  172. unsigned long base_align;
  173. };
  174. static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
  175. struct eg_surface *surf,
  176. const char *prefix)
  177. {
  178. surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
  179. surf->base_align = surf->bpe;
  180. surf->palign = 1;
  181. surf->halign = 1;
  182. return 0;
  183. }
  184. static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
  185. struct eg_surface *surf,
  186. const char *prefix)
  187. {
  188. struct evergreen_cs_track *track = p->track;
  189. unsigned palign;
  190. palign = MAX(64, track->group_size / surf->bpe);
  191. surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
  192. surf->base_align = track->group_size;
  193. surf->palign = palign;
  194. surf->halign = 1;
  195. if (surf->nbx & (palign - 1)) {
  196. if (prefix) {
  197. dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
  198. __func__, __LINE__, prefix, surf->nbx, palign);
  199. }
  200. return -EINVAL;
  201. }
  202. return 0;
  203. }
  204. static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
  205. struct eg_surface *surf,
  206. const char *prefix)
  207. {
  208. struct evergreen_cs_track *track = p->track;
  209. unsigned palign;
  210. palign = track->group_size / (8 * surf->bpe * surf->nsamples);
  211. palign = MAX(8, palign);
  212. surf->layer_size = surf->nbx * surf->nby * surf->bpe;
  213. surf->base_align = track->group_size;
  214. surf->palign = palign;
  215. surf->halign = 8;
  216. if ((surf->nbx & (palign - 1))) {
  217. if (prefix) {
  218. dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
  219. __func__, __LINE__, prefix, surf->nbx, palign,
  220. track->group_size, surf->bpe, surf->nsamples);
  221. }
  222. return -EINVAL;
  223. }
  224. if ((surf->nby & (8 - 1))) {
  225. if (prefix) {
  226. dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
  227. __func__, __LINE__, prefix, surf->nby);
  228. }
  229. return -EINVAL;
  230. }
  231. return 0;
  232. }
  233. static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
  234. struct eg_surface *surf,
  235. const char *prefix)
  236. {
  237. struct evergreen_cs_track *track = p->track;
  238. unsigned palign, halign, tileb, slice_pt;
  239. unsigned mtile_pr, mtile_ps, mtileb;
  240. tileb = 64 * surf->bpe * surf->nsamples;
  241. slice_pt = 1;
  242. if (tileb > surf->tsplit) {
  243. slice_pt = tileb / surf->tsplit;
  244. }
  245. tileb = tileb / slice_pt;
  246. /* macro tile width & height */
  247. palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
  248. halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
  249. mtileb = (palign / 8) * (halign / 8) * tileb;
  250. mtile_pr = surf->nbx / palign;
  251. mtile_ps = (mtile_pr * surf->nby) / halign;
  252. surf->layer_size = mtile_ps * mtileb * slice_pt;
  253. surf->base_align = (palign / 8) * (halign / 8) * tileb;
  254. surf->palign = palign;
  255. surf->halign = halign;
  256. if ((surf->nbx & (palign - 1))) {
  257. if (prefix) {
  258. dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
  259. __func__, __LINE__, prefix, surf->nbx, palign);
  260. }
  261. return -EINVAL;
  262. }
  263. if ((surf->nby & (halign - 1))) {
  264. if (prefix) {
  265. dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
  266. __func__, __LINE__, prefix, surf->nby, halign);
  267. }
  268. return -EINVAL;
  269. }
  270. return 0;
  271. }
  272. static int evergreen_surface_check(struct radeon_cs_parser *p,
  273. struct eg_surface *surf,
  274. const char *prefix)
  275. {
  276. /* some common value computed here */
  277. surf->bpe = r600_fmt_get_blocksize(surf->format);
  278. switch (surf->mode) {
  279. case ARRAY_LINEAR_GENERAL:
  280. return evergreen_surface_check_linear(p, surf, prefix);
  281. case ARRAY_LINEAR_ALIGNED:
  282. return evergreen_surface_check_linear_aligned(p, surf, prefix);
  283. case ARRAY_1D_TILED_THIN1:
  284. return evergreen_surface_check_1d(p, surf, prefix);
  285. case ARRAY_2D_TILED_THIN1:
  286. return evergreen_surface_check_2d(p, surf, prefix);
  287. default:
  288. dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
  289. __func__, __LINE__, prefix, surf->mode);
  290. return -EINVAL;
  291. }
  292. return -EINVAL;
  293. }
  294. static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
  295. struct eg_surface *surf,
  296. const char *prefix)
  297. {
  298. switch (surf->mode) {
  299. case ARRAY_2D_TILED_THIN1:
  300. break;
  301. case ARRAY_LINEAR_GENERAL:
  302. case ARRAY_LINEAR_ALIGNED:
  303. case ARRAY_1D_TILED_THIN1:
  304. return 0;
  305. default:
  306. dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
  307. __func__, __LINE__, prefix, surf->mode);
  308. return -EINVAL;
  309. }
  310. switch (surf->nbanks) {
  311. case 0: surf->nbanks = 2; break;
  312. case 1: surf->nbanks = 4; break;
  313. case 2: surf->nbanks = 8; break;
  314. case 3: surf->nbanks = 16; break;
  315. default:
  316. dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
  317. __func__, __LINE__, prefix, surf->nbanks);
  318. return -EINVAL;
  319. }
  320. switch (surf->bankw) {
  321. case 0: surf->bankw = 1; break;
  322. case 1: surf->bankw = 2; break;
  323. case 2: surf->bankw = 4; break;
  324. case 3: surf->bankw = 8; break;
  325. default:
  326. dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
  327. __func__, __LINE__, prefix, surf->bankw);
  328. return -EINVAL;
  329. }
  330. switch (surf->bankh) {
  331. case 0: surf->bankh = 1; break;
  332. case 1: surf->bankh = 2; break;
  333. case 2: surf->bankh = 4; break;
  334. case 3: surf->bankh = 8; break;
  335. default:
  336. dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
  337. __func__, __LINE__, prefix, surf->bankh);
  338. return -EINVAL;
  339. }
  340. switch (surf->mtilea) {
  341. case 0: surf->mtilea = 1; break;
  342. case 1: surf->mtilea = 2; break;
  343. case 2: surf->mtilea = 4; break;
  344. case 3: surf->mtilea = 8; break;
  345. default:
  346. dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
  347. __func__, __LINE__, prefix, surf->mtilea);
  348. return -EINVAL;
  349. }
  350. switch (surf->tsplit) {
  351. case 0: surf->tsplit = 64; break;
  352. case 1: surf->tsplit = 128; break;
  353. case 2: surf->tsplit = 256; break;
  354. case 3: surf->tsplit = 512; break;
  355. case 4: surf->tsplit = 1024; break;
  356. case 5: surf->tsplit = 2048; break;
  357. case 6: surf->tsplit = 4096; break;
  358. default:
  359. dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
  360. __func__, __LINE__, prefix, surf->tsplit);
  361. return -EINVAL;
  362. }
  363. return 0;
  364. }
  365. static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
  366. {
  367. struct evergreen_cs_track *track = p->track;
  368. struct eg_surface surf;
  369. unsigned pitch, slice, mslice;
  370. unsigned long offset;
  371. int r;
  372. mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
  373. pitch = track->cb_color_pitch[id];
  374. slice = track->cb_color_slice[id];
  375. surf.nbx = (pitch + 1) * 8;
  376. surf.nby = ((slice + 1) * 64) / surf.nbx;
  377. surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
  378. surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
  379. surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
  380. surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
  381. surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
  382. surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
  383. surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
  384. surf.nsamples = 1;
  385. if (!r600_fmt_is_valid_color(surf.format)) {
  386. dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
  387. __func__, __LINE__, surf.format,
  388. id, track->cb_color_info[id]);
  389. return -EINVAL;
  390. }
  391. r = evergreen_surface_value_conv_check(p, &surf, "cb");
  392. if (r) {
  393. return r;
  394. }
  395. r = evergreen_surface_check(p, &surf, "cb");
  396. if (r) {
  397. dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
  398. __func__, __LINE__, id, track->cb_color_pitch[id],
  399. track->cb_color_slice[id], track->cb_color_attrib[id],
  400. track->cb_color_info[id]);
  401. return r;
  402. }
  403. offset = track->cb_color_bo_offset[id] << 8;
  404. if (offset & (surf.base_align - 1)) {
  405. dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
  406. __func__, __LINE__, id, offset, surf.base_align);
  407. return -EINVAL;
  408. }
  409. offset += surf.layer_size * mslice;
  410. if (offset > radeon_bo_size(track->cb_color_bo[id])) {
  411. /* old ddx are broken they allocate bo with w*h*bpp but
  412. * program slice with ALIGN(h, 8), catch this and patch
  413. * command stream.
  414. */
  415. if (!surf.mode) {
  416. volatile u32 *ib = p->ib.ptr;
  417. unsigned long tmp, nby, bsize, size, min = 0;
  418. /* find the height the ddx wants */
  419. if (surf.nby > 8) {
  420. min = surf.nby - 8;
  421. }
  422. bsize = radeon_bo_size(track->cb_color_bo[id]);
  423. tmp = track->cb_color_bo_offset[id] << 8;
  424. for (nby = surf.nby; nby > min; nby--) {
  425. size = nby * surf.nbx * surf.bpe * surf.nsamples;
  426. if ((tmp + size * mslice) <= bsize) {
  427. break;
  428. }
  429. }
  430. if (nby > min) {
  431. surf.nby = nby;
  432. slice = ((nby * surf.nbx) / 64) - 1;
  433. if (!evergreen_surface_check(p, &surf, "cb")) {
  434. /* check if this one works */
  435. tmp += surf.layer_size * mslice;
  436. if (tmp <= bsize) {
  437. ib[track->cb_color_slice_idx[id]] = slice;
  438. goto old_ddx_ok;
  439. }
  440. }
  441. }
  442. }
  443. dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
  444. "offset %d, max layer %d, bo size %ld, slice %d)\n",
  445. __func__, __LINE__, id, surf.layer_size,
  446. track->cb_color_bo_offset[id] << 8, mslice,
  447. radeon_bo_size(track->cb_color_bo[id]), slice);
  448. dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
  449. __func__, __LINE__, surf.nbx, surf.nby,
  450. surf.mode, surf.bpe, surf.nsamples,
  451. surf.bankw, surf.bankh,
  452. surf.tsplit, surf.mtilea);
  453. return -EINVAL;
  454. }
  455. old_ddx_ok:
  456. return 0;
  457. }
  458. static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
  459. unsigned nbx, unsigned nby)
  460. {
  461. struct evergreen_cs_track *track = p->track;
  462. unsigned long size;
  463. if (track->htile_bo == NULL) {
  464. dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
  465. __func__, __LINE__, track->db_z_info);
  466. return -EINVAL;
  467. }
  468. if (G_028ABC_LINEAR(track->htile_surface)) {
  469. /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
  470. nbx = round_up(nbx, 16 * 8);
  471. /* height is npipes htiles aligned == npipes * 8 pixel aligned */
  472. nby = round_up(nby, track->npipes * 8);
  473. } else {
  474. /* always assume 8x8 htile */
  475. /* align is htile align * 8, htile align vary according to
  476. * number of pipe and tile width and nby
  477. */
  478. switch (track->npipes) {
  479. case 8:
  480. /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
  481. nbx = round_up(nbx, 64 * 8);
  482. nby = round_up(nby, 64 * 8);
  483. break;
  484. case 4:
  485. /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
  486. nbx = round_up(nbx, 64 * 8);
  487. nby = round_up(nby, 32 * 8);
  488. break;
  489. case 2:
  490. /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
  491. nbx = round_up(nbx, 32 * 8);
  492. nby = round_up(nby, 32 * 8);
  493. break;
  494. case 1:
  495. /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
  496. nbx = round_up(nbx, 32 * 8);
  497. nby = round_up(nby, 16 * 8);
  498. break;
  499. default:
  500. dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
  501. __func__, __LINE__, track->npipes);
  502. return -EINVAL;
  503. }
  504. }
  505. /* compute number of htile */
  506. nbx = nbx >> 3;
  507. nby = nby >> 3;
  508. /* size must be aligned on npipes * 2K boundary */
  509. size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
  510. size += track->htile_offset;
  511. if (size > radeon_bo_size(track->htile_bo)) {
  512. dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
  513. __func__, __LINE__, radeon_bo_size(track->htile_bo),
  514. size, nbx, nby);
  515. return -EINVAL;
  516. }
  517. return 0;
  518. }
  519. static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
  520. {
  521. struct evergreen_cs_track *track = p->track;
  522. struct eg_surface surf;
  523. unsigned pitch, slice, mslice;
  524. unsigned long offset;
  525. int r;
  526. mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
  527. pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
  528. slice = track->db_depth_slice;
  529. surf.nbx = (pitch + 1) * 8;
  530. surf.nby = ((slice + 1) * 64) / surf.nbx;
  531. surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
  532. surf.format = G_028044_FORMAT(track->db_s_info);
  533. surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
  534. surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
  535. surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
  536. surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
  537. surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
  538. surf.nsamples = 1;
  539. if (surf.format != 1) {
  540. dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
  541. __func__, __LINE__, surf.format);
  542. return -EINVAL;
  543. }
  544. /* replace by color format so we can use same code */
  545. surf.format = V_028C70_COLOR_8;
  546. r = evergreen_surface_value_conv_check(p, &surf, "stencil");
  547. if (r) {
  548. return r;
  549. }
  550. r = evergreen_surface_check(p, &surf, NULL);
  551. if (r) {
  552. /* old userspace doesn't compute proper depth/stencil alignment
  553. * check that alignment against a bigger byte per elements and
  554. * only report if that alignment is wrong too.
  555. */
  556. surf.format = V_028C70_COLOR_8_8_8_8;
  557. r = evergreen_surface_check(p, &surf, "stencil");
  558. if (r) {
  559. dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
  560. __func__, __LINE__, track->db_depth_size,
  561. track->db_depth_slice, track->db_s_info, track->db_z_info);
  562. }
  563. return r;
  564. }
  565. offset = track->db_s_read_offset << 8;
  566. if (offset & (surf.base_align - 1)) {
  567. dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
  568. __func__, __LINE__, offset, surf.base_align);
  569. return -EINVAL;
  570. }
  571. offset += surf.layer_size * mslice;
  572. if (offset > radeon_bo_size(track->db_s_read_bo)) {
  573. dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
  574. "offset %ld, max layer %d, bo size %ld)\n",
  575. __func__, __LINE__, surf.layer_size,
  576. (unsigned long)track->db_s_read_offset << 8, mslice,
  577. radeon_bo_size(track->db_s_read_bo));
  578. dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
  579. __func__, __LINE__, track->db_depth_size,
  580. track->db_depth_slice, track->db_s_info, track->db_z_info);
  581. return -EINVAL;
  582. }
  583. offset = track->db_s_write_offset << 8;
  584. if (offset & (surf.base_align - 1)) {
  585. dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
  586. __func__, __LINE__, offset, surf.base_align);
  587. return -EINVAL;
  588. }
  589. offset += surf.layer_size * mslice;
  590. if (offset > radeon_bo_size(track->db_s_write_bo)) {
  591. dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
  592. "offset %ld, max layer %d, bo size %ld)\n",
  593. __func__, __LINE__, surf.layer_size,
  594. (unsigned long)track->db_s_write_offset << 8, mslice,
  595. radeon_bo_size(track->db_s_write_bo));
  596. return -EINVAL;
  597. }
  598. /* hyperz */
  599. if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
  600. r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
  601. if (r) {
  602. return r;
  603. }
  604. }
  605. return 0;
  606. }
  607. static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
  608. {
  609. struct evergreen_cs_track *track = p->track;
  610. struct eg_surface surf;
  611. unsigned pitch, slice, mslice;
  612. unsigned long offset;
  613. int r;
  614. mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
  615. pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
  616. slice = track->db_depth_slice;
  617. surf.nbx = (pitch + 1) * 8;
  618. surf.nby = ((slice + 1) * 64) / surf.nbx;
  619. surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
  620. surf.format = G_028040_FORMAT(track->db_z_info);
  621. surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
  622. surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
  623. surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
  624. surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
  625. surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
  626. surf.nsamples = 1;
  627. switch (surf.format) {
  628. case V_028040_Z_16:
  629. surf.format = V_028C70_COLOR_16;
  630. break;
  631. case V_028040_Z_24:
  632. case V_028040_Z_32_FLOAT:
  633. surf.format = V_028C70_COLOR_8_8_8_8;
  634. break;
  635. default:
  636. dev_warn(p->dev, "%s:%d depth invalid format %d\n",
  637. __func__, __LINE__, surf.format);
  638. return -EINVAL;
  639. }
  640. r = evergreen_surface_value_conv_check(p, &surf, "depth");
  641. if (r) {
  642. dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
  643. __func__, __LINE__, track->db_depth_size,
  644. track->db_depth_slice, track->db_z_info);
  645. return r;
  646. }
  647. r = evergreen_surface_check(p, &surf, "depth");
  648. if (r) {
  649. dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
  650. __func__, __LINE__, track->db_depth_size,
  651. track->db_depth_slice, track->db_z_info);
  652. return r;
  653. }
  654. offset = track->db_z_read_offset << 8;
  655. if (offset & (surf.base_align - 1)) {
  656. dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
  657. __func__, __LINE__, offset, surf.base_align);
  658. return -EINVAL;
  659. }
  660. offset += surf.layer_size * mslice;
  661. if (offset > radeon_bo_size(track->db_z_read_bo)) {
  662. dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
  663. "offset %ld, max layer %d, bo size %ld)\n",
  664. __func__, __LINE__, surf.layer_size,
  665. (unsigned long)track->db_z_read_offset << 8, mslice,
  666. radeon_bo_size(track->db_z_read_bo));
  667. return -EINVAL;
  668. }
  669. offset = track->db_z_write_offset << 8;
  670. if (offset & (surf.base_align - 1)) {
  671. dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
  672. __func__, __LINE__, offset, surf.base_align);
  673. return -EINVAL;
  674. }
  675. offset += surf.layer_size * mslice;
  676. if (offset > radeon_bo_size(track->db_z_write_bo)) {
  677. dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
  678. "offset %ld, max layer %d, bo size %ld)\n",
  679. __func__, __LINE__, surf.layer_size,
  680. (unsigned long)track->db_z_write_offset << 8, mslice,
  681. radeon_bo_size(track->db_z_write_bo));
  682. return -EINVAL;
  683. }
  684. /* hyperz */
  685. if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
  686. r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
  687. if (r) {
  688. return r;
  689. }
  690. }
  691. return 0;
  692. }
  693. static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
  694. struct radeon_bo *texture,
  695. struct radeon_bo *mipmap,
  696. unsigned idx)
  697. {
  698. struct eg_surface surf;
  699. unsigned long toffset, moffset;
  700. unsigned dim, llevel, mslice, width, height, depth, i;
  701. u32 texdw[8];
  702. int r;
  703. texdw[0] = radeon_get_ib_value(p, idx + 0);
  704. texdw[1] = radeon_get_ib_value(p, idx + 1);
  705. texdw[2] = radeon_get_ib_value(p, idx + 2);
  706. texdw[3] = radeon_get_ib_value(p, idx + 3);
  707. texdw[4] = radeon_get_ib_value(p, idx + 4);
  708. texdw[5] = radeon_get_ib_value(p, idx + 5);
  709. texdw[6] = radeon_get_ib_value(p, idx + 6);
  710. texdw[7] = radeon_get_ib_value(p, idx + 7);
  711. dim = G_030000_DIM(texdw[0]);
  712. llevel = G_030014_LAST_LEVEL(texdw[5]);
  713. mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
  714. width = G_030000_TEX_WIDTH(texdw[0]) + 1;
  715. height = G_030004_TEX_HEIGHT(texdw[1]) + 1;
  716. depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
  717. surf.format = G_03001C_DATA_FORMAT(texdw[7]);
  718. surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
  719. surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
  720. surf.nby = r600_fmt_get_nblocksy(surf.format, height);
  721. surf.mode = G_030004_ARRAY_MODE(texdw[1]);
  722. surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
  723. surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
  724. surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
  725. surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
  726. surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
  727. surf.nsamples = 1;
  728. toffset = texdw[2] << 8;
  729. moffset = texdw[3] << 8;
  730. if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
  731. dev_warn(p->dev, "%s:%d texture invalid format %d\n",
  732. __func__, __LINE__, surf.format);
  733. return -EINVAL;
  734. }
  735. switch (dim) {
  736. case V_030000_SQ_TEX_DIM_1D:
  737. case V_030000_SQ_TEX_DIM_2D:
  738. case V_030000_SQ_TEX_DIM_CUBEMAP:
  739. case V_030000_SQ_TEX_DIM_1D_ARRAY:
  740. case V_030000_SQ_TEX_DIM_2D_ARRAY:
  741. depth = 1;
  742. break;
  743. case V_030000_SQ_TEX_DIM_2D_MSAA:
  744. case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
  745. surf.nsamples = 1 << llevel;
  746. llevel = 0;
  747. depth = 1;
  748. break;
  749. case V_030000_SQ_TEX_DIM_3D:
  750. break;
  751. default:
  752. dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
  753. __func__, __LINE__, dim);
  754. return -EINVAL;
  755. }
  756. r = evergreen_surface_value_conv_check(p, &surf, "texture");
  757. if (r) {
  758. return r;
  759. }
  760. /* align height */
  761. evergreen_surface_check(p, &surf, NULL);
  762. surf.nby = ALIGN(surf.nby, surf.halign);
  763. r = evergreen_surface_check(p, &surf, "texture");
  764. if (r) {
  765. dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
  766. __func__, __LINE__, texdw[0], texdw[1], texdw[4],
  767. texdw[5], texdw[6], texdw[7]);
  768. return r;
  769. }
  770. /* check texture size */
  771. if (toffset & (surf.base_align - 1)) {
  772. dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
  773. __func__, __LINE__, toffset, surf.base_align);
  774. return -EINVAL;
  775. }
  776. if (surf.nsamples <= 1 && moffset & (surf.base_align - 1)) {
  777. dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
  778. __func__, __LINE__, moffset, surf.base_align);
  779. return -EINVAL;
  780. }
  781. if (dim == SQ_TEX_DIM_3D) {
  782. toffset += surf.layer_size * depth;
  783. } else {
  784. toffset += surf.layer_size * mslice;
  785. }
  786. if (toffset > radeon_bo_size(texture)) {
  787. dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
  788. "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
  789. __func__, __LINE__, surf.layer_size,
  790. (unsigned long)texdw[2] << 8, mslice,
  791. depth, radeon_bo_size(texture),
  792. surf.nbx, surf.nby);
  793. return -EINVAL;
  794. }
  795. if (!mipmap) {
  796. if (llevel) {
  797. dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n",
  798. __func__, __LINE__);
  799. return -EINVAL;
  800. } else {
  801. return 0; /* everything's ok */
  802. }
  803. }
  804. /* check mipmap size */
  805. for (i = 1; i <= llevel; i++) {
  806. unsigned w, h, d;
  807. w = r600_mip_minify(width, i);
  808. h = r600_mip_minify(height, i);
  809. d = r600_mip_minify(depth, i);
  810. surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
  811. surf.nby = r600_fmt_get_nblocksy(surf.format, h);
  812. switch (surf.mode) {
  813. case ARRAY_2D_TILED_THIN1:
  814. if (surf.nbx < surf.palign || surf.nby < surf.halign) {
  815. surf.mode = ARRAY_1D_TILED_THIN1;
  816. }
  817. /* recompute alignment */
  818. evergreen_surface_check(p, &surf, NULL);
  819. break;
  820. case ARRAY_LINEAR_GENERAL:
  821. case ARRAY_LINEAR_ALIGNED:
  822. case ARRAY_1D_TILED_THIN1:
  823. break;
  824. default:
  825. dev_warn(p->dev, "%s:%d invalid array mode %d\n",
  826. __func__, __LINE__, surf.mode);
  827. return -EINVAL;
  828. }
  829. surf.nbx = ALIGN(surf.nbx, surf.palign);
  830. surf.nby = ALIGN(surf.nby, surf.halign);
  831. r = evergreen_surface_check(p, &surf, "mipmap");
  832. if (r) {
  833. return r;
  834. }
  835. if (dim == SQ_TEX_DIM_3D) {
  836. moffset += surf.layer_size * d;
  837. } else {
  838. moffset += surf.layer_size * mslice;
  839. }
  840. if (moffset > radeon_bo_size(mipmap)) {
  841. dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
  842. "offset %ld, coffset %ld, max layer %d, depth %d, "
  843. "bo size %ld) level0 (%d %d %d)\n",
  844. __func__, __LINE__, i, surf.layer_size,
  845. (unsigned long)texdw[3] << 8, moffset, mslice,
  846. d, radeon_bo_size(mipmap),
  847. width, height, depth);
  848. dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
  849. __func__, __LINE__, surf.nbx, surf.nby,
  850. surf.mode, surf.bpe, surf.nsamples,
  851. surf.bankw, surf.bankh,
  852. surf.tsplit, surf.mtilea);
  853. return -EINVAL;
  854. }
  855. }
  856. return 0;
  857. }
  858. static int evergreen_cs_track_check(struct radeon_cs_parser *p)
  859. {
  860. struct evergreen_cs_track *track = p->track;
  861. unsigned tmp, i;
  862. int r;
  863. unsigned buffer_mask = 0;
  864. /* check streamout */
  865. if (track->streamout_dirty && track->vgt_strmout_config) {
  866. for (i = 0; i < 4; i++) {
  867. if (track->vgt_strmout_config & (1 << i)) {
  868. buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
  869. }
  870. }
  871. for (i = 0; i < 4; i++) {
  872. if (buffer_mask & (1 << i)) {
  873. if (track->vgt_strmout_bo[i]) {
  874. u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
  875. (u64)track->vgt_strmout_size[i];
  876. if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
  877. DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
  878. i, offset,
  879. radeon_bo_size(track->vgt_strmout_bo[i]));
  880. return -EINVAL;
  881. }
  882. } else {
  883. dev_warn(p->dev, "No buffer for streamout %d\n", i);
  884. return -EINVAL;
  885. }
  886. }
  887. }
  888. track->streamout_dirty = false;
  889. }
  890. if (track->sx_misc_kill_all_prims)
  891. return 0;
  892. /* check that we have a cb for each enabled target
  893. */
  894. if (track->cb_dirty) {
  895. tmp = track->cb_target_mask;
  896. for (i = 0; i < 8; i++) {
  897. if ((tmp >> (i * 4)) & 0xF) {
  898. /* at least one component is enabled */
  899. if (track->cb_color_bo[i] == NULL) {
  900. dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
  901. __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
  902. return -EINVAL;
  903. }
  904. /* check cb */
  905. r = evergreen_cs_track_validate_cb(p, i);
  906. if (r) {
  907. return r;
  908. }
  909. }
  910. }
  911. track->cb_dirty = false;
  912. }
  913. if (track->db_dirty) {
  914. /* Check stencil buffer */
  915. if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
  916. G_028800_STENCIL_ENABLE(track->db_depth_control)) {
  917. r = evergreen_cs_track_validate_stencil(p);
  918. if (r)
  919. return r;
  920. }
  921. /* Check depth buffer */
  922. if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
  923. G_028800_Z_ENABLE(track->db_depth_control)) {
  924. r = evergreen_cs_track_validate_depth(p);
  925. if (r)
  926. return r;
  927. }
  928. track->db_dirty = false;
  929. }
  930. return 0;
  931. }
  932. /**
  933. * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet
  934. * @parser: parser structure holding parsing context.
  935. *
  936. * This is an Evergreen(+)-specific function for parsing VLINE packets.
  937. * Real work is done by r600_cs_common_vline_parse function.
  938. * Here we just set up ASIC-specific register table and call
  939. * the common implementation function.
  940. */
  941. static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
  942. {
  943. static uint32_t vline_start_end[6] = {
  944. EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,
  945. EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET,
  946. EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET,
  947. EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET,
  948. EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,
  949. EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET
  950. };
  951. static uint32_t vline_status[6] = {
  952. EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
  953. EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
  954. EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
  955. EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
  956. EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
  957. EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET
  958. };
  959. return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
  960. }
  961. static int evergreen_packet0_check(struct radeon_cs_parser *p,
  962. struct radeon_cs_packet *pkt,
  963. unsigned idx, unsigned reg)
  964. {
  965. int r;
  966. switch (reg) {
  967. case EVERGREEN_VLINE_START_END:
  968. r = evergreen_cs_packet_parse_vline(p);
  969. if (r) {
  970. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  971. idx, reg);
  972. return r;
  973. }
  974. break;
  975. default:
  976. printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
  977. reg, idx);
  978. return -EINVAL;
  979. }
  980. return 0;
  981. }
  982. static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
  983. struct radeon_cs_packet *pkt)
  984. {
  985. unsigned reg, i;
  986. unsigned idx;
  987. int r;
  988. idx = pkt->idx + 1;
  989. reg = pkt->reg;
  990. for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
  991. r = evergreen_packet0_check(p, pkt, idx, reg);
  992. if (r) {
  993. return r;
  994. }
  995. }
  996. return 0;
  997. }
  998. /**
  999. * evergreen_cs_check_reg() - check if register is authorized or not
  1000. * @parser: parser structure holding parsing context
  1001. * @reg: register we are testing
  1002. * @idx: index into the cs buffer
  1003. *
  1004. * This function will test against evergreen_reg_safe_bm and return 0
  1005. * if register is safe. If register is not flag as safe this function
  1006. * will test it against a list of register needind special handling.
  1007. */
  1008. static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
  1009. {
  1010. struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
  1011. struct radeon_cs_reloc *reloc;
  1012. u32 last_reg;
  1013. u32 m, i, tmp, *ib;
  1014. int r;
  1015. if (p->rdev->family >= CHIP_CAYMAN)
  1016. last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
  1017. else
  1018. last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
  1019. i = (reg >> 7);
  1020. if (i >= last_reg) {
  1021. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  1022. return -EINVAL;
  1023. }
  1024. m = 1 << ((reg >> 2) & 31);
  1025. if (p->rdev->family >= CHIP_CAYMAN) {
  1026. if (!(cayman_reg_safe_bm[i] & m))
  1027. return 0;
  1028. } else {
  1029. if (!(evergreen_reg_safe_bm[i] & m))
  1030. return 0;
  1031. }
  1032. ib = p->ib.ptr;
  1033. switch (reg) {
  1034. /* force following reg to 0 in an attempt to disable out buffer
  1035. * which will need us to better understand how it works to perform
  1036. * security check on it (Jerome)
  1037. */
  1038. case SQ_ESGS_RING_SIZE:
  1039. case SQ_GSVS_RING_SIZE:
  1040. case SQ_ESTMP_RING_SIZE:
  1041. case SQ_GSTMP_RING_SIZE:
  1042. case SQ_HSTMP_RING_SIZE:
  1043. case SQ_LSTMP_RING_SIZE:
  1044. case SQ_PSTMP_RING_SIZE:
  1045. case SQ_VSTMP_RING_SIZE:
  1046. case SQ_ESGS_RING_ITEMSIZE:
  1047. case SQ_ESTMP_RING_ITEMSIZE:
  1048. case SQ_GSTMP_RING_ITEMSIZE:
  1049. case SQ_GSVS_RING_ITEMSIZE:
  1050. case SQ_GS_VERT_ITEMSIZE:
  1051. case SQ_GS_VERT_ITEMSIZE_1:
  1052. case SQ_GS_VERT_ITEMSIZE_2:
  1053. case SQ_GS_VERT_ITEMSIZE_3:
  1054. case SQ_GSVS_RING_OFFSET_1:
  1055. case SQ_GSVS_RING_OFFSET_2:
  1056. case SQ_GSVS_RING_OFFSET_3:
  1057. case SQ_HSTMP_RING_ITEMSIZE:
  1058. case SQ_LSTMP_RING_ITEMSIZE:
  1059. case SQ_PSTMP_RING_ITEMSIZE:
  1060. case SQ_VSTMP_RING_ITEMSIZE:
  1061. case VGT_TF_RING_SIZE:
  1062. /* get value to populate the IB don't remove */
  1063. /*tmp =radeon_get_ib_value(p, idx);
  1064. ib[idx] = 0;*/
  1065. break;
  1066. case SQ_ESGS_RING_BASE:
  1067. case SQ_GSVS_RING_BASE:
  1068. case SQ_ESTMP_RING_BASE:
  1069. case SQ_GSTMP_RING_BASE:
  1070. case SQ_HSTMP_RING_BASE:
  1071. case SQ_LSTMP_RING_BASE:
  1072. case SQ_PSTMP_RING_BASE:
  1073. case SQ_VSTMP_RING_BASE:
  1074. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1075. if (r) {
  1076. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1077. "0x%04X\n", reg);
  1078. return -EINVAL;
  1079. }
  1080. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1081. break;
  1082. case DB_DEPTH_CONTROL:
  1083. track->db_depth_control = radeon_get_ib_value(p, idx);
  1084. track->db_dirty = true;
  1085. break;
  1086. case CAYMAN_DB_EQAA:
  1087. if (p->rdev->family < CHIP_CAYMAN) {
  1088. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1089. "0x%04X\n", reg);
  1090. return -EINVAL;
  1091. }
  1092. break;
  1093. case CAYMAN_DB_DEPTH_INFO:
  1094. if (p->rdev->family < CHIP_CAYMAN) {
  1095. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1096. "0x%04X\n", reg);
  1097. return -EINVAL;
  1098. }
  1099. break;
  1100. case DB_Z_INFO:
  1101. track->db_z_info = radeon_get_ib_value(p, idx);
  1102. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1103. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1104. if (r) {
  1105. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1106. "0x%04X\n", reg);
  1107. return -EINVAL;
  1108. }
  1109. ib[idx] &= ~Z_ARRAY_MODE(0xf);
  1110. track->db_z_info &= ~Z_ARRAY_MODE(0xf);
  1111. ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
  1112. track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
  1113. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
  1114. unsigned bankw, bankh, mtaspect, tile_split;
  1115. evergreen_tiling_fields(reloc->lobj.tiling_flags,
  1116. &bankw, &bankh, &mtaspect,
  1117. &tile_split);
  1118. ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
  1119. ib[idx] |= DB_TILE_SPLIT(tile_split) |
  1120. DB_BANK_WIDTH(bankw) |
  1121. DB_BANK_HEIGHT(bankh) |
  1122. DB_MACRO_TILE_ASPECT(mtaspect);
  1123. }
  1124. }
  1125. track->db_dirty = true;
  1126. break;
  1127. case DB_STENCIL_INFO:
  1128. track->db_s_info = radeon_get_ib_value(p, idx);
  1129. track->db_dirty = true;
  1130. break;
  1131. case DB_DEPTH_VIEW:
  1132. track->db_depth_view = radeon_get_ib_value(p, idx);
  1133. track->db_dirty = true;
  1134. break;
  1135. case DB_DEPTH_SIZE:
  1136. track->db_depth_size = radeon_get_ib_value(p, idx);
  1137. track->db_dirty = true;
  1138. break;
  1139. case R_02805C_DB_DEPTH_SLICE:
  1140. track->db_depth_slice = radeon_get_ib_value(p, idx);
  1141. track->db_dirty = true;
  1142. break;
  1143. case DB_Z_READ_BASE:
  1144. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1145. if (r) {
  1146. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1147. "0x%04X\n", reg);
  1148. return -EINVAL;
  1149. }
  1150. track->db_z_read_offset = radeon_get_ib_value(p, idx);
  1151. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1152. track->db_z_read_bo = reloc->robj;
  1153. track->db_dirty = true;
  1154. break;
  1155. case DB_Z_WRITE_BASE:
  1156. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1157. if (r) {
  1158. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1159. "0x%04X\n", reg);
  1160. return -EINVAL;
  1161. }
  1162. track->db_z_write_offset = radeon_get_ib_value(p, idx);
  1163. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1164. track->db_z_write_bo = reloc->robj;
  1165. track->db_dirty = true;
  1166. break;
  1167. case DB_STENCIL_READ_BASE:
  1168. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1169. if (r) {
  1170. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1171. "0x%04X\n", reg);
  1172. return -EINVAL;
  1173. }
  1174. track->db_s_read_offset = radeon_get_ib_value(p, idx);
  1175. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1176. track->db_s_read_bo = reloc->robj;
  1177. track->db_dirty = true;
  1178. break;
  1179. case DB_STENCIL_WRITE_BASE:
  1180. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1181. if (r) {
  1182. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1183. "0x%04X\n", reg);
  1184. return -EINVAL;
  1185. }
  1186. track->db_s_write_offset = radeon_get_ib_value(p, idx);
  1187. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1188. track->db_s_write_bo = reloc->robj;
  1189. track->db_dirty = true;
  1190. break;
  1191. case VGT_STRMOUT_CONFIG:
  1192. track->vgt_strmout_config = radeon_get_ib_value(p, idx);
  1193. track->streamout_dirty = true;
  1194. break;
  1195. case VGT_STRMOUT_BUFFER_CONFIG:
  1196. track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
  1197. track->streamout_dirty = true;
  1198. break;
  1199. case VGT_STRMOUT_BUFFER_BASE_0:
  1200. case VGT_STRMOUT_BUFFER_BASE_1:
  1201. case VGT_STRMOUT_BUFFER_BASE_2:
  1202. case VGT_STRMOUT_BUFFER_BASE_3:
  1203. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1204. if (r) {
  1205. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1206. "0x%04X\n", reg);
  1207. return -EINVAL;
  1208. }
  1209. tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
  1210. track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
  1211. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1212. track->vgt_strmout_bo[tmp] = reloc->robj;
  1213. track->streamout_dirty = true;
  1214. break;
  1215. case VGT_STRMOUT_BUFFER_SIZE_0:
  1216. case VGT_STRMOUT_BUFFER_SIZE_1:
  1217. case VGT_STRMOUT_BUFFER_SIZE_2:
  1218. case VGT_STRMOUT_BUFFER_SIZE_3:
  1219. tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
  1220. /* size in register is DWs, convert to bytes */
  1221. track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
  1222. track->streamout_dirty = true;
  1223. break;
  1224. case CP_COHER_BASE:
  1225. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1226. if (r) {
  1227. dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
  1228. "0x%04X\n", reg);
  1229. return -EINVAL;
  1230. }
  1231. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1232. case CB_TARGET_MASK:
  1233. track->cb_target_mask = radeon_get_ib_value(p, idx);
  1234. track->cb_dirty = true;
  1235. break;
  1236. case CB_SHADER_MASK:
  1237. track->cb_shader_mask = radeon_get_ib_value(p, idx);
  1238. track->cb_dirty = true;
  1239. break;
  1240. case PA_SC_AA_CONFIG:
  1241. if (p->rdev->family >= CHIP_CAYMAN) {
  1242. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1243. "0x%04X\n", reg);
  1244. return -EINVAL;
  1245. }
  1246. tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
  1247. track->nsamples = 1 << tmp;
  1248. break;
  1249. case CAYMAN_PA_SC_AA_CONFIG:
  1250. if (p->rdev->family < CHIP_CAYMAN) {
  1251. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1252. "0x%04X\n", reg);
  1253. return -EINVAL;
  1254. }
  1255. tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
  1256. track->nsamples = 1 << tmp;
  1257. break;
  1258. case CB_COLOR0_VIEW:
  1259. case CB_COLOR1_VIEW:
  1260. case CB_COLOR2_VIEW:
  1261. case CB_COLOR3_VIEW:
  1262. case CB_COLOR4_VIEW:
  1263. case CB_COLOR5_VIEW:
  1264. case CB_COLOR6_VIEW:
  1265. case CB_COLOR7_VIEW:
  1266. tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
  1267. track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
  1268. track->cb_dirty = true;
  1269. break;
  1270. case CB_COLOR8_VIEW:
  1271. case CB_COLOR9_VIEW:
  1272. case CB_COLOR10_VIEW:
  1273. case CB_COLOR11_VIEW:
  1274. tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
  1275. track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
  1276. track->cb_dirty = true;
  1277. break;
  1278. case CB_COLOR0_INFO:
  1279. case CB_COLOR1_INFO:
  1280. case CB_COLOR2_INFO:
  1281. case CB_COLOR3_INFO:
  1282. case CB_COLOR4_INFO:
  1283. case CB_COLOR5_INFO:
  1284. case CB_COLOR6_INFO:
  1285. case CB_COLOR7_INFO:
  1286. tmp = (reg - CB_COLOR0_INFO) / 0x3c;
  1287. track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
  1288. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1289. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1290. if (r) {
  1291. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1292. "0x%04X\n", reg);
  1293. return -EINVAL;
  1294. }
  1295. ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
  1296. track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
  1297. }
  1298. track->cb_dirty = true;
  1299. break;
  1300. case CB_COLOR8_INFO:
  1301. case CB_COLOR9_INFO:
  1302. case CB_COLOR10_INFO:
  1303. case CB_COLOR11_INFO:
  1304. tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
  1305. track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
  1306. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1307. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1308. if (r) {
  1309. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1310. "0x%04X\n", reg);
  1311. return -EINVAL;
  1312. }
  1313. ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
  1314. track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
  1315. }
  1316. track->cb_dirty = true;
  1317. break;
  1318. case CB_COLOR0_PITCH:
  1319. case CB_COLOR1_PITCH:
  1320. case CB_COLOR2_PITCH:
  1321. case CB_COLOR3_PITCH:
  1322. case CB_COLOR4_PITCH:
  1323. case CB_COLOR5_PITCH:
  1324. case CB_COLOR6_PITCH:
  1325. case CB_COLOR7_PITCH:
  1326. tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
  1327. track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
  1328. track->cb_dirty = true;
  1329. break;
  1330. case CB_COLOR8_PITCH:
  1331. case CB_COLOR9_PITCH:
  1332. case CB_COLOR10_PITCH:
  1333. case CB_COLOR11_PITCH:
  1334. tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
  1335. track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
  1336. track->cb_dirty = true;
  1337. break;
  1338. case CB_COLOR0_SLICE:
  1339. case CB_COLOR1_SLICE:
  1340. case CB_COLOR2_SLICE:
  1341. case CB_COLOR3_SLICE:
  1342. case CB_COLOR4_SLICE:
  1343. case CB_COLOR5_SLICE:
  1344. case CB_COLOR6_SLICE:
  1345. case CB_COLOR7_SLICE:
  1346. tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
  1347. track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
  1348. track->cb_color_slice_idx[tmp] = idx;
  1349. track->cb_dirty = true;
  1350. break;
  1351. case CB_COLOR8_SLICE:
  1352. case CB_COLOR9_SLICE:
  1353. case CB_COLOR10_SLICE:
  1354. case CB_COLOR11_SLICE:
  1355. tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
  1356. track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
  1357. track->cb_color_slice_idx[tmp] = idx;
  1358. track->cb_dirty = true;
  1359. break;
  1360. case CB_COLOR0_ATTRIB:
  1361. case CB_COLOR1_ATTRIB:
  1362. case CB_COLOR2_ATTRIB:
  1363. case CB_COLOR3_ATTRIB:
  1364. case CB_COLOR4_ATTRIB:
  1365. case CB_COLOR5_ATTRIB:
  1366. case CB_COLOR6_ATTRIB:
  1367. case CB_COLOR7_ATTRIB:
  1368. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1369. if (r) {
  1370. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1371. "0x%04X\n", reg);
  1372. return -EINVAL;
  1373. }
  1374. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1375. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
  1376. unsigned bankw, bankh, mtaspect, tile_split;
  1377. evergreen_tiling_fields(reloc->lobj.tiling_flags,
  1378. &bankw, &bankh, &mtaspect,
  1379. &tile_split);
  1380. ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
  1381. ib[idx] |= CB_TILE_SPLIT(tile_split) |
  1382. CB_BANK_WIDTH(bankw) |
  1383. CB_BANK_HEIGHT(bankh) |
  1384. CB_MACRO_TILE_ASPECT(mtaspect);
  1385. }
  1386. }
  1387. tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
  1388. track->cb_color_attrib[tmp] = ib[idx];
  1389. track->cb_dirty = true;
  1390. break;
  1391. case CB_COLOR8_ATTRIB:
  1392. case CB_COLOR9_ATTRIB:
  1393. case CB_COLOR10_ATTRIB:
  1394. case CB_COLOR11_ATTRIB:
  1395. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1396. if (r) {
  1397. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1398. "0x%04X\n", reg);
  1399. return -EINVAL;
  1400. }
  1401. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1402. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
  1403. unsigned bankw, bankh, mtaspect, tile_split;
  1404. evergreen_tiling_fields(reloc->lobj.tiling_flags,
  1405. &bankw, &bankh, &mtaspect,
  1406. &tile_split);
  1407. ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
  1408. ib[idx] |= CB_TILE_SPLIT(tile_split) |
  1409. CB_BANK_WIDTH(bankw) |
  1410. CB_BANK_HEIGHT(bankh) |
  1411. CB_MACRO_TILE_ASPECT(mtaspect);
  1412. }
  1413. }
  1414. tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
  1415. track->cb_color_attrib[tmp] = ib[idx];
  1416. track->cb_dirty = true;
  1417. break;
  1418. case CB_COLOR0_FMASK:
  1419. case CB_COLOR1_FMASK:
  1420. case CB_COLOR2_FMASK:
  1421. case CB_COLOR3_FMASK:
  1422. case CB_COLOR4_FMASK:
  1423. case CB_COLOR5_FMASK:
  1424. case CB_COLOR6_FMASK:
  1425. case CB_COLOR7_FMASK:
  1426. tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
  1427. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1428. if (r) {
  1429. dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
  1430. return -EINVAL;
  1431. }
  1432. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1433. track->cb_color_fmask_bo[tmp] = reloc->robj;
  1434. break;
  1435. case CB_COLOR0_CMASK:
  1436. case CB_COLOR1_CMASK:
  1437. case CB_COLOR2_CMASK:
  1438. case CB_COLOR3_CMASK:
  1439. case CB_COLOR4_CMASK:
  1440. case CB_COLOR5_CMASK:
  1441. case CB_COLOR6_CMASK:
  1442. case CB_COLOR7_CMASK:
  1443. tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
  1444. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1445. if (r) {
  1446. dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
  1447. return -EINVAL;
  1448. }
  1449. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1450. track->cb_color_cmask_bo[tmp] = reloc->robj;
  1451. break;
  1452. case CB_COLOR0_FMASK_SLICE:
  1453. case CB_COLOR1_FMASK_SLICE:
  1454. case CB_COLOR2_FMASK_SLICE:
  1455. case CB_COLOR3_FMASK_SLICE:
  1456. case CB_COLOR4_FMASK_SLICE:
  1457. case CB_COLOR5_FMASK_SLICE:
  1458. case CB_COLOR6_FMASK_SLICE:
  1459. case CB_COLOR7_FMASK_SLICE:
  1460. tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
  1461. track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
  1462. break;
  1463. case CB_COLOR0_CMASK_SLICE:
  1464. case CB_COLOR1_CMASK_SLICE:
  1465. case CB_COLOR2_CMASK_SLICE:
  1466. case CB_COLOR3_CMASK_SLICE:
  1467. case CB_COLOR4_CMASK_SLICE:
  1468. case CB_COLOR5_CMASK_SLICE:
  1469. case CB_COLOR6_CMASK_SLICE:
  1470. case CB_COLOR7_CMASK_SLICE:
  1471. tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
  1472. track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
  1473. break;
  1474. case CB_COLOR0_BASE:
  1475. case CB_COLOR1_BASE:
  1476. case CB_COLOR2_BASE:
  1477. case CB_COLOR3_BASE:
  1478. case CB_COLOR4_BASE:
  1479. case CB_COLOR5_BASE:
  1480. case CB_COLOR6_BASE:
  1481. case CB_COLOR7_BASE:
  1482. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1483. if (r) {
  1484. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1485. "0x%04X\n", reg);
  1486. return -EINVAL;
  1487. }
  1488. tmp = (reg - CB_COLOR0_BASE) / 0x3c;
  1489. track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
  1490. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1491. track->cb_color_bo[tmp] = reloc->robj;
  1492. track->cb_dirty = true;
  1493. break;
  1494. case CB_COLOR8_BASE:
  1495. case CB_COLOR9_BASE:
  1496. case CB_COLOR10_BASE:
  1497. case CB_COLOR11_BASE:
  1498. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1499. if (r) {
  1500. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1501. "0x%04X\n", reg);
  1502. return -EINVAL;
  1503. }
  1504. tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
  1505. track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
  1506. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1507. track->cb_color_bo[tmp] = reloc->robj;
  1508. track->cb_dirty = true;
  1509. break;
  1510. case DB_HTILE_DATA_BASE:
  1511. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1512. if (r) {
  1513. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1514. "0x%04X\n", reg);
  1515. return -EINVAL;
  1516. }
  1517. track->htile_offset = radeon_get_ib_value(p, idx);
  1518. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1519. track->htile_bo = reloc->robj;
  1520. track->db_dirty = true;
  1521. break;
  1522. case DB_HTILE_SURFACE:
  1523. /* 8x8 only */
  1524. track->htile_surface = radeon_get_ib_value(p, idx);
  1525. /* force 8x8 htile width and height */
  1526. ib[idx] |= 3;
  1527. track->db_dirty = true;
  1528. break;
  1529. case CB_IMMED0_BASE:
  1530. case CB_IMMED1_BASE:
  1531. case CB_IMMED2_BASE:
  1532. case CB_IMMED3_BASE:
  1533. case CB_IMMED4_BASE:
  1534. case CB_IMMED5_BASE:
  1535. case CB_IMMED6_BASE:
  1536. case CB_IMMED7_BASE:
  1537. case CB_IMMED8_BASE:
  1538. case CB_IMMED9_BASE:
  1539. case CB_IMMED10_BASE:
  1540. case CB_IMMED11_BASE:
  1541. case SQ_PGM_START_FS:
  1542. case SQ_PGM_START_ES:
  1543. case SQ_PGM_START_VS:
  1544. case SQ_PGM_START_GS:
  1545. case SQ_PGM_START_PS:
  1546. case SQ_PGM_START_HS:
  1547. case SQ_PGM_START_LS:
  1548. case SQ_CONST_MEM_BASE:
  1549. case SQ_ALU_CONST_CACHE_GS_0:
  1550. case SQ_ALU_CONST_CACHE_GS_1:
  1551. case SQ_ALU_CONST_CACHE_GS_2:
  1552. case SQ_ALU_CONST_CACHE_GS_3:
  1553. case SQ_ALU_CONST_CACHE_GS_4:
  1554. case SQ_ALU_CONST_CACHE_GS_5:
  1555. case SQ_ALU_CONST_CACHE_GS_6:
  1556. case SQ_ALU_CONST_CACHE_GS_7:
  1557. case SQ_ALU_CONST_CACHE_GS_8:
  1558. case SQ_ALU_CONST_CACHE_GS_9:
  1559. case SQ_ALU_CONST_CACHE_GS_10:
  1560. case SQ_ALU_CONST_CACHE_GS_11:
  1561. case SQ_ALU_CONST_CACHE_GS_12:
  1562. case SQ_ALU_CONST_CACHE_GS_13:
  1563. case SQ_ALU_CONST_CACHE_GS_14:
  1564. case SQ_ALU_CONST_CACHE_GS_15:
  1565. case SQ_ALU_CONST_CACHE_PS_0:
  1566. case SQ_ALU_CONST_CACHE_PS_1:
  1567. case SQ_ALU_CONST_CACHE_PS_2:
  1568. case SQ_ALU_CONST_CACHE_PS_3:
  1569. case SQ_ALU_CONST_CACHE_PS_4:
  1570. case SQ_ALU_CONST_CACHE_PS_5:
  1571. case SQ_ALU_CONST_CACHE_PS_6:
  1572. case SQ_ALU_CONST_CACHE_PS_7:
  1573. case SQ_ALU_CONST_CACHE_PS_8:
  1574. case SQ_ALU_CONST_CACHE_PS_9:
  1575. case SQ_ALU_CONST_CACHE_PS_10:
  1576. case SQ_ALU_CONST_CACHE_PS_11:
  1577. case SQ_ALU_CONST_CACHE_PS_12:
  1578. case SQ_ALU_CONST_CACHE_PS_13:
  1579. case SQ_ALU_CONST_CACHE_PS_14:
  1580. case SQ_ALU_CONST_CACHE_PS_15:
  1581. case SQ_ALU_CONST_CACHE_VS_0:
  1582. case SQ_ALU_CONST_CACHE_VS_1:
  1583. case SQ_ALU_CONST_CACHE_VS_2:
  1584. case SQ_ALU_CONST_CACHE_VS_3:
  1585. case SQ_ALU_CONST_CACHE_VS_4:
  1586. case SQ_ALU_CONST_CACHE_VS_5:
  1587. case SQ_ALU_CONST_CACHE_VS_6:
  1588. case SQ_ALU_CONST_CACHE_VS_7:
  1589. case SQ_ALU_CONST_CACHE_VS_8:
  1590. case SQ_ALU_CONST_CACHE_VS_9:
  1591. case SQ_ALU_CONST_CACHE_VS_10:
  1592. case SQ_ALU_CONST_CACHE_VS_11:
  1593. case SQ_ALU_CONST_CACHE_VS_12:
  1594. case SQ_ALU_CONST_CACHE_VS_13:
  1595. case SQ_ALU_CONST_CACHE_VS_14:
  1596. case SQ_ALU_CONST_CACHE_VS_15:
  1597. case SQ_ALU_CONST_CACHE_HS_0:
  1598. case SQ_ALU_CONST_CACHE_HS_1:
  1599. case SQ_ALU_CONST_CACHE_HS_2:
  1600. case SQ_ALU_CONST_CACHE_HS_3:
  1601. case SQ_ALU_CONST_CACHE_HS_4:
  1602. case SQ_ALU_CONST_CACHE_HS_5:
  1603. case SQ_ALU_CONST_CACHE_HS_6:
  1604. case SQ_ALU_CONST_CACHE_HS_7:
  1605. case SQ_ALU_CONST_CACHE_HS_8:
  1606. case SQ_ALU_CONST_CACHE_HS_9:
  1607. case SQ_ALU_CONST_CACHE_HS_10:
  1608. case SQ_ALU_CONST_CACHE_HS_11:
  1609. case SQ_ALU_CONST_CACHE_HS_12:
  1610. case SQ_ALU_CONST_CACHE_HS_13:
  1611. case SQ_ALU_CONST_CACHE_HS_14:
  1612. case SQ_ALU_CONST_CACHE_HS_15:
  1613. case SQ_ALU_CONST_CACHE_LS_0:
  1614. case SQ_ALU_CONST_CACHE_LS_1:
  1615. case SQ_ALU_CONST_CACHE_LS_2:
  1616. case SQ_ALU_CONST_CACHE_LS_3:
  1617. case SQ_ALU_CONST_CACHE_LS_4:
  1618. case SQ_ALU_CONST_CACHE_LS_5:
  1619. case SQ_ALU_CONST_CACHE_LS_6:
  1620. case SQ_ALU_CONST_CACHE_LS_7:
  1621. case SQ_ALU_CONST_CACHE_LS_8:
  1622. case SQ_ALU_CONST_CACHE_LS_9:
  1623. case SQ_ALU_CONST_CACHE_LS_10:
  1624. case SQ_ALU_CONST_CACHE_LS_11:
  1625. case SQ_ALU_CONST_CACHE_LS_12:
  1626. case SQ_ALU_CONST_CACHE_LS_13:
  1627. case SQ_ALU_CONST_CACHE_LS_14:
  1628. case SQ_ALU_CONST_CACHE_LS_15:
  1629. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1630. if (r) {
  1631. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1632. "0x%04X\n", reg);
  1633. return -EINVAL;
  1634. }
  1635. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1636. break;
  1637. case SX_MEMORY_EXPORT_BASE:
  1638. if (p->rdev->family >= CHIP_CAYMAN) {
  1639. dev_warn(p->dev, "bad SET_CONFIG_REG "
  1640. "0x%04X\n", reg);
  1641. return -EINVAL;
  1642. }
  1643. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1644. if (r) {
  1645. dev_warn(p->dev, "bad SET_CONFIG_REG "
  1646. "0x%04X\n", reg);
  1647. return -EINVAL;
  1648. }
  1649. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1650. break;
  1651. case CAYMAN_SX_SCATTER_EXPORT_BASE:
  1652. if (p->rdev->family < CHIP_CAYMAN) {
  1653. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1654. "0x%04X\n", reg);
  1655. return -EINVAL;
  1656. }
  1657. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1658. if (r) {
  1659. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1660. "0x%04X\n", reg);
  1661. return -EINVAL;
  1662. }
  1663. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1664. break;
  1665. case SX_MISC:
  1666. track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
  1667. break;
  1668. default:
  1669. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  1670. return -EINVAL;
  1671. }
  1672. return 0;
  1673. }
  1674. static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
  1675. {
  1676. u32 last_reg, m, i;
  1677. if (p->rdev->family >= CHIP_CAYMAN)
  1678. last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
  1679. else
  1680. last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
  1681. i = (reg >> 7);
  1682. if (i >= last_reg) {
  1683. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  1684. return false;
  1685. }
  1686. m = 1 << ((reg >> 2) & 31);
  1687. if (p->rdev->family >= CHIP_CAYMAN) {
  1688. if (!(cayman_reg_safe_bm[i] & m))
  1689. return true;
  1690. } else {
  1691. if (!(evergreen_reg_safe_bm[i] & m))
  1692. return true;
  1693. }
  1694. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  1695. return false;
  1696. }
  1697. static int evergreen_packet3_check(struct radeon_cs_parser *p,
  1698. struct radeon_cs_packet *pkt)
  1699. {
  1700. struct radeon_cs_reloc *reloc;
  1701. struct evergreen_cs_track *track;
  1702. volatile u32 *ib;
  1703. unsigned idx;
  1704. unsigned i;
  1705. unsigned start_reg, end_reg, reg;
  1706. int r;
  1707. u32 idx_value;
  1708. track = (struct evergreen_cs_track *)p->track;
  1709. ib = p->ib.ptr;
  1710. idx = pkt->idx + 1;
  1711. idx_value = radeon_get_ib_value(p, idx);
  1712. switch (pkt->opcode) {
  1713. case PACKET3_SET_PREDICATION:
  1714. {
  1715. int pred_op;
  1716. int tmp;
  1717. uint64_t offset;
  1718. if (pkt->count != 1) {
  1719. DRM_ERROR("bad SET PREDICATION\n");
  1720. return -EINVAL;
  1721. }
  1722. tmp = radeon_get_ib_value(p, idx + 1);
  1723. pred_op = (tmp >> 16) & 0x7;
  1724. /* for the clear predicate operation */
  1725. if (pred_op == 0)
  1726. return 0;
  1727. if (pred_op > 2) {
  1728. DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
  1729. return -EINVAL;
  1730. }
  1731. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1732. if (r) {
  1733. DRM_ERROR("bad SET PREDICATION\n");
  1734. return -EINVAL;
  1735. }
  1736. offset = reloc->lobj.gpu_offset +
  1737. (idx_value & 0xfffffff0) +
  1738. ((u64)(tmp & 0xff) << 32);
  1739. ib[idx + 0] = offset;
  1740. ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
  1741. }
  1742. break;
  1743. case PACKET3_CONTEXT_CONTROL:
  1744. if (pkt->count != 1) {
  1745. DRM_ERROR("bad CONTEXT_CONTROL\n");
  1746. return -EINVAL;
  1747. }
  1748. break;
  1749. case PACKET3_INDEX_TYPE:
  1750. case PACKET3_NUM_INSTANCES:
  1751. case PACKET3_CLEAR_STATE:
  1752. if (pkt->count) {
  1753. DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
  1754. return -EINVAL;
  1755. }
  1756. break;
  1757. case CAYMAN_PACKET3_DEALLOC_STATE:
  1758. if (p->rdev->family < CHIP_CAYMAN) {
  1759. DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
  1760. return -EINVAL;
  1761. }
  1762. if (pkt->count) {
  1763. DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
  1764. return -EINVAL;
  1765. }
  1766. break;
  1767. case PACKET3_INDEX_BASE:
  1768. {
  1769. uint64_t offset;
  1770. if (pkt->count != 1) {
  1771. DRM_ERROR("bad INDEX_BASE\n");
  1772. return -EINVAL;
  1773. }
  1774. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1775. if (r) {
  1776. DRM_ERROR("bad INDEX_BASE\n");
  1777. return -EINVAL;
  1778. }
  1779. offset = reloc->lobj.gpu_offset +
  1780. idx_value +
  1781. ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
  1782. ib[idx+0] = offset;
  1783. ib[idx+1] = upper_32_bits(offset) & 0xff;
  1784. r = evergreen_cs_track_check(p);
  1785. if (r) {
  1786. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1787. return r;
  1788. }
  1789. break;
  1790. }
  1791. case PACKET3_DRAW_INDEX:
  1792. {
  1793. uint64_t offset;
  1794. if (pkt->count != 3) {
  1795. DRM_ERROR("bad DRAW_INDEX\n");
  1796. return -EINVAL;
  1797. }
  1798. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1799. if (r) {
  1800. DRM_ERROR("bad DRAW_INDEX\n");
  1801. return -EINVAL;
  1802. }
  1803. offset = reloc->lobj.gpu_offset +
  1804. idx_value +
  1805. ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
  1806. ib[idx+0] = offset;
  1807. ib[idx+1] = upper_32_bits(offset) & 0xff;
  1808. r = evergreen_cs_track_check(p);
  1809. if (r) {
  1810. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1811. return r;
  1812. }
  1813. break;
  1814. }
  1815. case PACKET3_DRAW_INDEX_2:
  1816. {
  1817. uint64_t offset;
  1818. if (pkt->count != 4) {
  1819. DRM_ERROR("bad DRAW_INDEX_2\n");
  1820. return -EINVAL;
  1821. }
  1822. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1823. if (r) {
  1824. DRM_ERROR("bad DRAW_INDEX_2\n");
  1825. return -EINVAL;
  1826. }
  1827. offset = reloc->lobj.gpu_offset +
  1828. radeon_get_ib_value(p, idx+1) +
  1829. ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
  1830. ib[idx+1] = offset;
  1831. ib[idx+2] = upper_32_bits(offset) & 0xff;
  1832. r = evergreen_cs_track_check(p);
  1833. if (r) {
  1834. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1835. return r;
  1836. }
  1837. break;
  1838. }
  1839. case PACKET3_DRAW_INDEX_AUTO:
  1840. if (pkt->count != 1) {
  1841. DRM_ERROR("bad DRAW_INDEX_AUTO\n");
  1842. return -EINVAL;
  1843. }
  1844. r = evergreen_cs_track_check(p);
  1845. if (r) {
  1846. dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
  1847. return r;
  1848. }
  1849. break;
  1850. case PACKET3_DRAW_INDEX_MULTI_AUTO:
  1851. if (pkt->count != 2) {
  1852. DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
  1853. return -EINVAL;
  1854. }
  1855. r = evergreen_cs_track_check(p);
  1856. if (r) {
  1857. dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
  1858. return r;
  1859. }
  1860. break;
  1861. case PACKET3_DRAW_INDEX_IMMD:
  1862. if (pkt->count < 2) {
  1863. DRM_ERROR("bad DRAW_INDEX_IMMD\n");
  1864. return -EINVAL;
  1865. }
  1866. r = evergreen_cs_track_check(p);
  1867. if (r) {
  1868. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1869. return r;
  1870. }
  1871. break;
  1872. case PACKET3_DRAW_INDEX_OFFSET:
  1873. if (pkt->count != 2) {
  1874. DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
  1875. return -EINVAL;
  1876. }
  1877. r = evergreen_cs_track_check(p);
  1878. if (r) {
  1879. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1880. return r;
  1881. }
  1882. break;
  1883. case PACKET3_DRAW_INDEX_OFFSET_2:
  1884. if (pkt->count != 3) {
  1885. DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
  1886. return -EINVAL;
  1887. }
  1888. r = evergreen_cs_track_check(p);
  1889. if (r) {
  1890. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1891. return r;
  1892. }
  1893. break;
  1894. case PACKET3_DISPATCH_DIRECT:
  1895. if (pkt->count != 3) {
  1896. DRM_ERROR("bad DISPATCH_DIRECT\n");
  1897. return -EINVAL;
  1898. }
  1899. r = evergreen_cs_track_check(p);
  1900. if (r) {
  1901. dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
  1902. return r;
  1903. }
  1904. break;
  1905. case PACKET3_DISPATCH_INDIRECT:
  1906. if (pkt->count != 1) {
  1907. DRM_ERROR("bad DISPATCH_INDIRECT\n");
  1908. return -EINVAL;
  1909. }
  1910. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1911. if (r) {
  1912. DRM_ERROR("bad DISPATCH_INDIRECT\n");
  1913. return -EINVAL;
  1914. }
  1915. ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1916. r = evergreen_cs_track_check(p);
  1917. if (r) {
  1918. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1919. return r;
  1920. }
  1921. break;
  1922. case PACKET3_WAIT_REG_MEM:
  1923. if (pkt->count != 5) {
  1924. DRM_ERROR("bad WAIT_REG_MEM\n");
  1925. return -EINVAL;
  1926. }
  1927. /* bit 4 is reg (0) or mem (1) */
  1928. if (idx_value & 0x10) {
  1929. uint64_t offset;
  1930. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1931. if (r) {
  1932. DRM_ERROR("bad WAIT_REG_MEM\n");
  1933. return -EINVAL;
  1934. }
  1935. offset = reloc->lobj.gpu_offset +
  1936. (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
  1937. ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
  1938. ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
  1939. ib[idx+2] = upper_32_bits(offset) & 0xff;
  1940. } else if (idx_value & 0x100) {
  1941. DRM_ERROR("cannot use PFP on REG wait\n");
  1942. return -EINVAL;
  1943. }
  1944. break;
  1945. case PACKET3_CP_DMA:
  1946. {
  1947. u32 command, size, info;
  1948. u64 offset, tmp;
  1949. if (pkt->count != 4) {
  1950. DRM_ERROR("bad CP DMA\n");
  1951. return -EINVAL;
  1952. }
  1953. command = radeon_get_ib_value(p, idx+4);
  1954. size = command & 0x1fffff;
  1955. info = radeon_get_ib_value(p, idx+1);
  1956. if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
  1957. (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */
  1958. ((((info & 0x00300000) >> 20) == 0) &&
  1959. (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */
  1960. ((((info & 0x60000000) >> 29) == 0) &&
  1961. (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */
  1962. /* non mem to mem copies requires dw aligned count */
  1963. if (size % 4) {
  1964. DRM_ERROR("CP DMA command requires dw count alignment\n");
  1965. return -EINVAL;
  1966. }
  1967. }
  1968. if (command & PACKET3_CP_DMA_CMD_SAS) {
  1969. /* src address space is register */
  1970. /* GDS is ok */
  1971. if (((info & 0x60000000) >> 29) != 1) {
  1972. DRM_ERROR("CP DMA SAS not supported\n");
  1973. return -EINVAL;
  1974. }
  1975. } else {
  1976. if (command & PACKET3_CP_DMA_CMD_SAIC) {
  1977. DRM_ERROR("CP DMA SAIC only supported for registers\n");
  1978. return -EINVAL;
  1979. }
  1980. /* src address space is memory */
  1981. if (((info & 0x60000000) >> 29) == 0) {
  1982. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1983. if (r) {
  1984. DRM_ERROR("bad CP DMA SRC\n");
  1985. return -EINVAL;
  1986. }
  1987. tmp = radeon_get_ib_value(p, idx) +
  1988. ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
  1989. offset = reloc->lobj.gpu_offset + tmp;
  1990. if ((tmp + size) > radeon_bo_size(reloc->robj)) {
  1991. dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
  1992. tmp + size, radeon_bo_size(reloc->robj));
  1993. return -EINVAL;
  1994. }
  1995. ib[idx] = offset;
  1996. ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
  1997. } else if (((info & 0x60000000) >> 29) != 2) {
  1998. DRM_ERROR("bad CP DMA SRC_SEL\n");
  1999. return -EINVAL;
  2000. }
  2001. }
  2002. if (command & PACKET3_CP_DMA_CMD_DAS) {
  2003. /* dst address space is register */
  2004. /* GDS is ok */
  2005. if (((info & 0x00300000) >> 20) != 1) {
  2006. DRM_ERROR("CP DMA DAS not supported\n");
  2007. return -EINVAL;
  2008. }
  2009. } else {
  2010. /* dst address space is memory */
  2011. if (command & PACKET3_CP_DMA_CMD_DAIC) {
  2012. DRM_ERROR("CP DMA DAIC only supported for registers\n");
  2013. return -EINVAL;
  2014. }
  2015. if (((info & 0x00300000) >> 20) == 0) {
  2016. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2017. if (r) {
  2018. DRM_ERROR("bad CP DMA DST\n");
  2019. return -EINVAL;
  2020. }
  2021. tmp = radeon_get_ib_value(p, idx+2) +
  2022. ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
  2023. offset = reloc->lobj.gpu_offset + tmp;
  2024. if ((tmp + size) > radeon_bo_size(reloc->robj)) {
  2025. dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
  2026. tmp + size, radeon_bo_size(reloc->robj));
  2027. return -EINVAL;
  2028. }
  2029. ib[idx+2] = offset;
  2030. ib[idx+3] = upper_32_bits(offset) & 0xff;
  2031. } else {
  2032. DRM_ERROR("bad CP DMA DST_SEL\n");
  2033. return -EINVAL;
  2034. }
  2035. }
  2036. break;
  2037. }
  2038. case PACKET3_SURFACE_SYNC:
  2039. if (pkt->count != 3) {
  2040. DRM_ERROR("bad SURFACE_SYNC\n");
  2041. return -EINVAL;
  2042. }
  2043. /* 0xffffffff/0x0 is flush all cache flag */
  2044. if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
  2045. radeon_get_ib_value(p, idx + 2) != 0) {
  2046. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2047. if (r) {
  2048. DRM_ERROR("bad SURFACE_SYNC\n");
  2049. return -EINVAL;
  2050. }
  2051. ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  2052. }
  2053. break;
  2054. case PACKET3_EVENT_WRITE:
  2055. if (pkt->count != 2 && pkt->count != 0) {
  2056. DRM_ERROR("bad EVENT_WRITE\n");
  2057. return -EINVAL;
  2058. }
  2059. if (pkt->count) {
  2060. uint64_t offset;
  2061. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2062. if (r) {
  2063. DRM_ERROR("bad EVENT_WRITE\n");
  2064. return -EINVAL;
  2065. }
  2066. offset = reloc->lobj.gpu_offset +
  2067. (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
  2068. ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
  2069. ib[idx+1] = offset & 0xfffffff8;
  2070. ib[idx+2] = upper_32_bits(offset) & 0xff;
  2071. }
  2072. break;
  2073. case PACKET3_EVENT_WRITE_EOP:
  2074. {
  2075. uint64_t offset;
  2076. if (pkt->count != 4) {
  2077. DRM_ERROR("bad EVENT_WRITE_EOP\n");
  2078. return -EINVAL;
  2079. }
  2080. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2081. if (r) {
  2082. DRM_ERROR("bad EVENT_WRITE_EOP\n");
  2083. return -EINVAL;
  2084. }
  2085. offset = reloc->lobj.gpu_offset +
  2086. (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
  2087. ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
  2088. ib[idx+1] = offset & 0xfffffffc;
  2089. ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
  2090. break;
  2091. }
  2092. case PACKET3_EVENT_WRITE_EOS:
  2093. {
  2094. uint64_t offset;
  2095. if (pkt->count != 3) {
  2096. DRM_ERROR("bad EVENT_WRITE_EOS\n");
  2097. return -EINVAL;
  2098. }
  2099. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2100. if (r) {
  2101. DRM_ERROR("bad EVENT_WRITE_EOS\n");
  2102. return -EINVAL;
  2103. }
  2104. offset = reloc->lobj.gpu_offset +
  2105. (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
  2106. ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
  2107. ib[idx+1] = offset & 0xfffffffc;
  2108. ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
  2109. break;
  2110. }
  2111. case PACKET3_SET_CONFIG_REG:
  2112. start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
  2113. end_reg = 4 * pkt->count + start_reg - 4;
  2114. if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
  2115. (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
  2116. (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
  2117. DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
  2118. return -EINVAL;
  2119. }
  2120. for (i = 0; i < pkt->count; i++) {
  2121. reg = start_reg + (4 * i);
  2122. r = evergreen_cs_check_reg(p, reg, idx+1+i);
  2123. if (r)
  2124. return r;
  2125. }
  2126. break;
  2127. case PACKET3_SET_CONTEXT_REG:
  2128. start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
  2129. end_reg = 4 * pkt->count + start_reg - 4;
  2130. if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
  2131. (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
  2132. (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
  2133. DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
  2134. return -EINVAL;
  2135. }
  2136. for (i = 0; i < pkt->count; i++) {
  2137. reg = start_reg + (4 * i);
  2138. r = evergreen_cs_check_reg(p, reg, idx+1+i);
  2139. if (r)
  2140. return r;
  2141. }
  2142. break;
  2143. case PACKET3_SET_RESOURCE:
  2144. if (pkt->count % 8) {
  2145. DRM_ERROR("bad SET_RESOURCE\n");
  2146. return -EINVAL;
  2147. }
  2148. start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
  2149. end_reg = 4 * pkt->count + start_reg - 4;
  2150. if ((start_reg < PACKET3_SET_RESOURCE_START) ||
  2151. (start_reg >= PACKET3_SET_RESOURCE_END) ||
  2152. (end_reg >= PACKET3_SET_RESOURCE_END)) {
  2153. DRM_ERROR("bad SET_RESOURCE\n");
  2154. return -EINVAL;
  2155. }
  2156. for (i = 0; i < (pkt->count / 8); i++) {
  2157. struct radeon_bo *texture, *mipmap;
  2158. u32 toffset, moffset;
  2159. u32 size, offset, mip_address, tex_dim;
  2160. switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
  2161. case SQ_TEX_VTX_VALID_TEXTURE:
  2162. /* tex base */
  2163. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2164. if (r) {
  2165. DRM_ERROR("bad SET_RESOURCE (tex)\n");
  2166. return -EINVAL;
  2167. }
  2168. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  2169. ib[idx+1+(i*8)+1] |=
  2170. TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
  2171. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
  2172. unsigned bankw, bankh, mtaspect, tile_split;
  2173. evergreen_tiling_fields(reloc->lobj.tiling_flags,
  2174. &bankw, &bankh, &mtaspect,
  2175. &tile_split);
  2176. ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
  2177. ib[idx+1+(i*8)+7] |=
  2178. TEX_BANK_WIDTH(bankw) |
  2179. TEX_BANK_HEIGHT(bankh) |
  2180. MACRO_TILE_ASPECT(mtaspect) |
  2181. TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
  2182. }
  2183. }
  2184. texture = reloc->robj;
  2185. toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  2186. /* tex mip base */
  2187. tex_dim = ib[idx+1+(i*8)+0] & 0x7;
  2188. mip_address = ib[idx+1+(i*8)+3];
  2189. if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&
  2190. !mip_address &&
  2191. !radeon_cs_packet_next_is_pkt3_nop(p)) {
  2192. /* MIP_ADDRESS should point to FMASK for an MSAA texture.
  2193. * It should be 0 if FMASK is disabled. */
  2194. moffset = 0;
  2195. mipmap = NULL;
  2196. } else {
  2197. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2198. if (r) {
  2199. DRM_ERROR("bad SET_RESOURCE (tex)\n");
  2200. return -EINVAL;
  2201. }
  2202. moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  2203. mipmap = reloc->robj;
  2204. }
  2205. r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
  2206. if (r)
  2207. return r;
  2208. ib[idx+1+(i*8)+2] += toffset;
  2209. ib[idx+1+(i*8)+3] += moffset;
  2210. break;
  2211. case SQ_TEX_VTX_VALID_BUFFER:
  2212. {
  2213. uint64_t offset64;
  2214. /* vtx base */
  2215. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2216. if (r) {
  2217. DRM_ERROR("bad SET_RESOURCE (vtx)\n");
  2218. return -EINVAL;
  2219. }
  2220. offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
  2221. size = radeon_get_ib_value(p, idx+1+(i*8)+1);
  2222. if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
  2223. /* force size to size of the buffer */
  2224. dev_warn(p->dev, "vbo resource seems too big for the bo\n");
  2225. ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
  2226. }
  2227. offset64 = reloc->lobj.gpu_offset + offset;
  2228. ib[idx+1+(i*8)+0] = offset64;
  2229. ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
  2230. (upper_32_bits(offset64) & 0xff);
  2231. break;
  2232. }
  2233. case SQ_TEX_VTX_INVALID_TEXTURE:
  2234. case SQ_TEX_VTX_INVALID_BUFFER:
  2235. default:
  2236. DRM_ERROR("bad SET_RESOURCE\n");
  2237. return -EINVAL;
  2238. }
  2239. }
  2240. break;
  2241. case PACKET3_SET_ALU_CONST:
  2242. /* XXX fix me ALU const buffers only */
  2243. break;
  2244. case PACKET3_SET_BOOL_CONST:
  2245. start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
  2246. end_reg = 4 * pkt->count + start_reg - 4;
  2247. if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
  2248. (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
  2249. (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
  2250. DRM_ERROR("bad SET_BOOL_CONST\n");
  2251. return -EINVAL;
  2252. }
  2253. break;
  2254. case PACKET3_SET_LOOP_CONST:
  2255. start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
  2256. end_reg = 4 * pkt->count + start_reg - 4;
  2257. if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
  2258. (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
  2259. (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
  2260. DRM_ERROR("bad SET_LOOP_CONST\n");
  2261. return -EINVAL;
  2262. }
  2263. break;
  2264. case PACKET3_SET_CTL_CONST:
  2265. start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
  2266. end_reg = 4 * pkt->count + start_reg - 4;
  2267. if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
  2268. (start_reg >= PACKET3_SET_CTL_CONST_END) ||
  2269. (end_reg >= PACKET3_SET_CTL_CONST_END)) {
  2270. DRM_ERROR("bad SET_CTL_CONST\n");
  2271. return -EINVAL;
  2272. }
  2273. break;
  2274. case PACKET3_SET_SAMPLER:
  2275. if (pkt->count % 3) {
  2276. DRM_ERROR("bad SET_SAMPLER\n");
  2277. return -EINVAL;
  2278. }
  2279. start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
  2280. end_reg = 4 * pkt->count + start_reg - 4;
  2281. if ((start_reg < PACKET3_SET_SAMPLER_START) ||
  2282. (start_reg >= PACKET3_SET_SAMPLER_END) ||
  2283. (end_reg >= PACKET3_SET_SAMPLER_END)) {
  2284. DRM_ERROR("bad SET_SAMPLER\n");
  2285. return -EINVAL;
  2286. }
  2287. break;
  2288. case PACKET3_STRMOUT_BUFFER_UPDATE:
  2289. if (pkt->count != 4) {
  2290. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
  2291. return -EINVAL;
  2292. }
  2293. /* Updating memory at DST_ADDRESS. */
  2294. if (idx_value & 0x1) {
  2295. u64 offset;
  2296. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2297. if (r) {
  2298. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
  2299. return -EINVAL;
  2300. }
  2301. offset = radeon_get_ib_value(p, idx+1);
  2302. offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
  2303. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  2304. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
  2305. offset + 4, radeon_bo_size(reloc->robj));
  2306. return -EINVAL;
  2307. }
  2308. offset += reloc->lobj.gpu_offset;
  2309. ib[idx+1] = offset;
  2310. ib[idx+2] = upper_32_bits(offset) & 0xff;
  2311. }
  2312. /* Reading data from SRC_ADDRESS. */
  2313. if (((idx_value >> 1) & 0x3) == 2) {
  2314. u64 offset;
  2315. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2316. if (r) {
  2317. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
  2318. return -EINVAL;
  2319. }
  2320. offset = radeon_get_ib_value(p, idx+3);
  2321. offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
  2322. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  2323. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
  2324. offset + 4, radeon_bo_size(reloc->robj));
  2325. return -EINVAL;
  2326. }
  2327. offset += reloc->lobj.gpu_offset;
  2328. ib[idx+3] = offset;
  2329. ib[idx+4] = upper_32_bits(offset) & 0xff;
  2330. }
  2331. break;
  2332. case PACKET3_MEM_WRITE:
  2333. {
  2334. u64 offset;
  2335. if (pkt->count != 3) {
  2336. DRM_ERROR("bad MEM_WRITE (invalid count)\n");
  2337. return -EINVAL;
  2338. }
  2339. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2340. if (r) {
  2341. DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
  2342. return -EINVAL;
  2343. }
  2344. offset = radeon_get_ib_value(p, idx+0);
  2345. offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
  2346. if (offset & 0x7) {
  2347. DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
  2348. return -EINVAL;
  2349. }
  2350. if ((offset + 8) > radeon_bo_size(reloc->robj)) {
  2351. DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
  2352. offset + 8, radeon_bo_size(reloc->robj));
  2353. return -EINVAL;
  2354. }
  2355. offset += reloc->lobj.gpu_offset;
  2356. ib[idx+0] = offset;
  2357. ib[idx+1] = upper_32_bits(offset) & 0xff;
  2358. break;
  2359. }
  2360. case PACKET3_COPY_DW:
  2361. if (pkt->count != 4) {
  2362. DRM_ERROR("bad COPY_DW (invalid count)\n");
  2363. return -EINVAL;
  2364. }
  2365. if (idx_value & 0x1) {
  2366. u64 offset;
  2367. /* SRC is memory. */
  2368. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2369. if (r) {
  2370. DRM_ERROR("bad COPY_DW (missing src reloc)\n");
  2371. return -EINVAL;
  2372. }
  2373. offset = radeon_get_ib_value(p, idx+1);
  2374. offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
  2375. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  2376. DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
  2377. offset + 4, radeon_bo_size(reloc->robj));
  2378. return -EINVAL;
  2379. }
  2380. offset += reloc->lobj.gpu_offset;
  2381. ib[idx+1] = offset;
  2382. ib[idx+2] = upper_32_bits(offset) & 0xff;
  2383. } else {
  2384. /* SRC is a reg. */
  2385. reg = radeon_get_ib_value(p, idx+1) << 2;
  2386. if (!evergreen_is_safe_reg(p, reg, idx+1))
  2387. return -EINVAL;
  2388. }
  2389. if (idx_value & 0x2) {
  2390. u64 offset;
  2391. /* DST is memory. */
  2392. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  2393. if (r) {
  2394. DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
  2395. return -EINVAL;
  2396. }
  2397. offset = radeon_get_ib_value(p, idx+3);
  2398. offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
  2399. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  2400. DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
  2401. offset + 4, radeon_bo_size(reloc->robj));
  2402. return -EINVAL;
  2403. }
  2404. offset += reloc->lobj.gpu_offset;
  2405. ib[idx+3] = offset;
  2406. ib[idx+4] = upper_32_bits(offset) & 0xff;
  2407. } else {
  2408. /* DST is a reg. */
  2409. reg = radeon_get_ib_value(p, idx+3) << 2;
  2410. if (!evergreen_is_safe_reg(p, reg, idx+3))
  2411. return -EINVAL;
  2412. }
  2413. break;
  2414. case PACKET3_NOP:
  2415. break;
  2416. default:
  2417. DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
  2418. return -EINVAL;
  2419. }
  2420. return 0;
  2421. }
  2422. int evergreen_cs_parse(struct radeon_cs_parser *p)
  2423. {
  2424. struct radeon_cs_packet pkt;
  2425. struct evergreen_cs_track *track;
  2426. u32 tmp;
  2427. int r;
  2428. if (p->track == NULL) {
  2429. /* initialize tracker, we are in kms */
  2430. track = kzalloc(sizeof(*track), GFP_KERNEL);
  2431. if (track == NULL)
  2432. return -ENOMEM;
  2433. evergreen_cs_track_init(track);
  2434. if (p->rdev->family >= CHIP_CAYMAN)
  2435. tmp = p->rdev->config.cayman.tile_config;
  2436. else
  2437. tmp = p->rdev->config.evergreen.tile_config;
  2438. switch (tmp & 0xf) {
  2439. case 0:
  2440. track->npipes = 1;
  2441. break;
  2442. case 1:
  2443. default:
  2444. track->npipes = 2;
  2445. break;
  2446. case 2:
  2447. track->npipes = 4;
  2448. break;
  2449. case 3:
  2450. track->npipes = 8;
  2451. break;
  2452. }
  2453. switch ((tmp & 0xf0) >> 4) {
  2454. case 0:
  2455. track->nbanks = 4;
  2456. break;
  2457. case 1:
  2458. default:
  2459. track->nbanks = 8;
  2460. break;
  2461. case 2:
  2462. track->nbanks = 16;
  2463. break;
  2464. }
  2465. switch ((tmp & 0xf00) >> 8) {
  2466. case 0:
  2467. track->group_size = 256;
  2468. break;
  2469. case 1:
  2470. default:
  2471. track->group_size = 512;
  2472. break;
  2473. }
  2474. switch ((tmp & 0xf000) >> 12) {
  2475. case 0:
  2476. track->row_size = 1;
  2477. break;
  2478. case 1:
  2479. default:
  2480. track->row_size = 2;
  2481. break;
  2482. case 2:
  2483. track->row_size = 4;
  2484. break;
  2485. }
  2486. p->track = track;
  2487. }
  2488. do {
  2489. r = radeon_cs_packet_parse(p, &pkt, p->idx);
  2490. if (r) {
  2491. kfree(p->track);
  2492. p->track = NULL;
  2493. return r;
  2494. }
  2495. p->idx += pkt.count + 2;
  2496. switch (pkt.type) {
  2497. case RADEON_PACKET_TYPE0:
  2498. r = evergreen_cs_parse_packet0(p, &pkt);
  2499. break;
  2500. case RADEON_PACKET_TYPE2:
  2501. break;
  2502. case RADEON_PACKET_TYPE3:
  2503. r = evergreen_packet3_check(p, &pkt);
  2504. break;
  2505. default:
  2506. DRM_ERROR("Unknown packet type %d !\n", pkt.type);
  2507. kfree(p->track);
  2508. p->track = NULL;
  2509. return -EINVAL;
  2510. }
  2511. if (r) {
  2512. kfree(p->track);
  2513. p->track = NULL;
  2514. return r;
  2515. }
  2516. } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
  2517. #if 0
  2518. for (r = 0; r < p->ib.length_dw; r++) {
  2519. printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
  2520. mdelay(1);
  2521. }
  2522. #endif
  2523. kfree(p->track);
  2524. p->track = NULL;
  2525. return 0;
  2526. }
  2527. /**
  2528. * evergreen_dma_cs_parse() - parse the DMA IB
  2529. * @p: parser structure holding parsing context.
  2530. *
  2531. * Parses the DMA IB from the CS ioctl and updates
  2532. * the GPU addresses based on the reloc information and
  2533. * checks for errors. (Evergreen-Cayman)
  2534. * Returns 0 for success and an error on failure.
  2535. **/
  2536. int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
  2537. {
  2538. struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
  2539. struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;
  2540. u32 header, cmd, count, sub_cmd;
  2541. volatile u32 *ib = p->ib.ptr;
  2542. u32 idx;
  2543. u64 src_offset, dst_offset, dst2_offset;
  2544. int r;
  2545. do {
  2546. if (p->idx >= ib_chunk->length_dw) {
  2547. DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
  2548. p->idx, ib_chunk->length_dw);
  2549. return -EINVAL;
  2550. }
  2551. idx = p->idx;
  2552. header = radeon_get_ib_value(p, idx);
  2553. cmd = GET_DMA_CMD(header);
  2554. count = GET_DMA_COUNT(header);
  2555. sub_cmd = GET_DMA_SUB_CMD(header);
  2556. switch (cmd) {
  2557. case DMA_PACKET_WRITE:
  2558. r = r600_dma_cs_next_reloc(p, &dst_reloc);
  2559. if (r) {
  2560. DRM_ERROR("bad DMA_PACKET_WRITE\n");
  2561. return -EINVAL;
  2562. }
  2563. switch (sub_cmd) {
  2564. /* tiled */
  2565. case 8:
  2566. dst_offset = radeon_get_ib_value(p, idx+1);
  2567. dst_offset <<= 8;
  2568. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2569. p->idx += count + 7;
  2570. break;
  2571. /* linear */
  2572. case 0:
  2573. dst_offset = radeon_get_ib_value(p, idx+1);
  2574. dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
  2575. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
  2576. ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2577. p->idx += count + 3;
  2578. break;
  2579. default:
  2580. DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header);
  2581. return -EINVAL;
  2582. }
  2583. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2584. dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
  2585. dst_offset, radeon_bo_size(dst_reloc->robj));
  2586. return -EINVAL;
  2587. }
  2588. break;
  2589. case DMA_PACKET_COPY:
  2590. r = r600_dma_cs_next_reloc(p, &src_reloc);
  2591. if (r) {
  2592. DRM_ERROR("bad DMA_PACKET_COPY\n");
  2593. return -EINVAL;
  2594. }
  2595. r = r600_dma_cs_next_reloc(p, &dst_reloc);
  2596. if (r) {
  2597. DRM_ERROR("bad DMA_PACKET_COPY\n");
  2598. return -EINVAL;
  2599. }
  2600. switch (sub_cmd) {
  2601. /* Copy L2L, DW aligned */
  2602. case 0x00:
  2603. /* L2L, dw */
  2604. src_offset = radeon_get_ib_value(p, idx+2);
  2605. src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
  2606. dst_offset = radeon_get_ib_value(p, idx+1);
  2607. dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
  2608. if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
  2609. dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
  2610. src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
  2611. return -EINVAL;
  2612. }
  2613. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2614. dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
  2615. dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
  2616. return -EINVAL;
  2617. }
  2618. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
  2619. ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2620. ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2621. ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2622. p->idx += 5;
  2623. break;
  2624. /* Copy L2T/T2L */
  2625. case 0x08:
  2626. /* detile bit */
  2627. if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
  2628. /* tiled src, linear dst */
  2629. src_offset = radeon_get_ib_value(p, idx+1);
  2630. src_offset <<= 8;
  2631. ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
  2632. dst_offset = radeon_get_ib_value(p, idx + 7);
  2633. dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
  2634. ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
  2635. ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2636. } else {
  2637. /* linear src, tiled dst */
  2638. src_offset = radeon_get_ib_value(p, idx+7);
  2639. src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
  2640. ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2641. ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2642. dst_offset = radeon_get_ib_value(p, idx+1);
  2643. dst_offset <<= 8;
  2644. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2645. }
  2646. if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
  2647. dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n",
  2648. src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
  2649. return -EINVAL;
  2650. }
  2651. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2652. dev_warn(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n",
  2653. dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
  2654. return -EINVAL;
  2655. }
  2656. p->idx += 9;
  2657. break;
  2658. /* Copy L2L, byte aligned */
  2659. case 0x40:
  2660. /* L2L, byte */
  2661. src_offset = radeon_get_ib_value(p, idx+2);
  2662. src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
  2663. dst_offset = radeon_get_ib_value(p, idx+1);
  2664. dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
  2665. if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
  2666. dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n",
  2667. src_offset + count, radeon_bo_size(src_reloc->robj));
  2668. return -EINVAL;
  2669. }
  2670. if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
  2671. dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n",
  2672. dst_offset + count, radeon_bo_size(dst_reloc->robj));
  2673. return -EINVAL;
  2674. }
  2675. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
  2676. ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
  2677. ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2678. ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2679. p->idx += 5;
  2680. break;
  2681. /* Copy L2L, partial */
  2682. case 0x41:
  2683. /* L2L, partial */
  2684. if (p->family < CHIP_CAYMAN) {
  2685. DRM_ERROR("L2L Partial is cayman only !\n");
  2686. return -EINVAL;
  2687. }
  2688. ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
  2689. ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2690. ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
  2691. ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2692. p->idx += 9;
  2693. break;
  2694. /* Copy L2L, DW aligned, broadcast */
  2695. case 0x44:
  2696. /* L2L, dw, broadcast */
  2697. r = r600_dma_cs_next_reloc(p, &dst2_reloc);
  2698. if (r) {
  2699. DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
  2700. return -EINVAL;
  2701. }
  2702. dst_offset = radeon_get_ib_value(p, idx+1);
  2703. dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
  2704. dst2_offset = radeon_get_ib_value(p, idx+2);
  2705. dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;
  2706. src_offset = radeon_get_ib_value(p, idx+3);
  2707. src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
  2708. if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
  2709. dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
  2710. src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
  2711. return -EINVAL;
  2712. }
  2713. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2714. dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n",
  2715. dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
  2716. return -EINVAL;
  2717. }
  2718. if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
  2719. dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n",
  2720. dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
  2721. return -EINVAL;
  2722. }
  2723. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
  2724. ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
  2725. ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2726. ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2727. ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
  2728. ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2729. p->idx += 7;
  2730. break;
  2731. /* Copy L2T Frame to Field */
  2732. case 0x48:
  2733. if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
  2734. DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
  2735. return -EINVAL;
  2736. }
  2737. r = r600_dma_cs_next_reloc(p, &dst2_reloc);
  2738. if (r) {
  2739. DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
  2740. return -EINVAL;
  2741. }
  2742. dst_offset = radeon_get_ib_value(p, idx+1);
  2743. dst_offset <<= 8;
  2744. dst2_offset = radeon_get_ib_value(p, idx+2);
  2745. dst2_offset <<= 8;
  2746. src_offset = radeon_get_ib_value(p, idx+8);
  2747. src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
  2748. if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
  2749. dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
  2750. src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
  2751. return -EINVAL;
  2752. }
  2753. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2754. dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
  2755. dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
  2756. return -EINVAL;
  2757. }
  2758. if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
  2759. dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
  2760. dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
  2761. return -EINVAL;
  2762. }
  2763. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2764. ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
  2765. ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2766. ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2767. p->idx += 10;
  2768. break;
  2769. /* Copy L2T/T2L, partial */
  2770. case 0x49:
  2771. /* L2T, T2L partial */
  2772. if (p->family < CHIP_CAYMAN) {
  2773. DRM_ERROR("L2T, T2L Partial is cayman only !\n");
  2774. return -EINVAL;
  2775. }
  2776. /* detile bit */
  2777. if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
  2778. /* tiled src, linear dst */
  2779. ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
  2780. ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
  2781. ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2782. } else {
  2783. /* linear src, tiled dst */
  2784. ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2785. ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2786. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2787. }
  2788. p->idx += 12;
  2789. break;
  2790. /* Copy L2T broadcast */
  2791. case 0x4b:
  2792. /* L2T, broadcast */
  2793. if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
  2794. DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
  2795. return -EINVAL;
  2796. }
  2797. r = r600_dma_cs_next_reloc(p, &dst2_reloc);
  2798. if (r) {
  2799. DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
  2800. return -EINVAL;
  2801. }
  2802. dst_offset = radeon_get_ib_value(p, idx+1);
  2803. dst_offset <<= 8;
  2804. dst2_offset = radeon_get_ib_value(p, idx+2);
  2805. dst2_offset <<= 8;
  2806. src_offset = radeon_get_ib_value(p, idx+8);
  2807. src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
  2808. if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
  2809. dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
  2810. src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
  2811. return -EINVAL;
  2812. }
  2813. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2814. dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
  2815. dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
  2816. return -EINVAL;
  2817. }
  2818. if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
  2819. dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
  2820. dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
  2821. return -EINVAL;
  2822. }
  2823. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2824. ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
  2825. ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2826. ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2827. p->idx += 10;
  2828. break;
  2829. /* Copy L2T/T2L (tile units) */
  2830. case 0x4c:
  2831. /* L2T, T2L */
  2832. /* detile bit */
  2833. if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
  2834. /* tiled src, linear dst */
  2835. src_offset = radeon_get_ib_value(p, idx+1);
  2836. src_offset <<= 8;
  2837. ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
  2838. dst_offset = radeon_get_ib_value(p, idx+7);
  2839. dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
  2840. ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
  2841. ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
  2842. } else {
  2843. /* linear src, tiled dst */
  2844. src_offset = radeon_get_ib_value(p, idx+7);
  2845. src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
  2846. ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2847. ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2848. dst_offset = radeon_get_ib_value(p, idx+1);
  2849. dst_offset <<= 8;
  2850. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2851. }
  2852. if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
  2853. dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
  2854. src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
  2855. return -EINVAL;
  2856. }
  2857. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2858. dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
  2859. dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
  2860. return -EINVAL;
  2861. }
  2862. p->idx += 9;
  2863. break;
  2864. /* Copy T2T, partial (tile units) */
  2865. case 0x4d:
  2866. /* T2T partial */
  2867. if (p->family < CHIP_CAYMAN) {
  2868. DRM_ERROR("L2T, T2L Partial is cayman only !\n");
  2869. return -EINVAL;
  2870. }
  2871. ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
  2872. ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2873. p->idx += 13;
  2874. break;
  2875. /* Copy L2T broadcast (tile units) */
  2876. case 0x4f:
  2877. /* L2T, broadcast */
  2878. if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
  2879. DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
  2880. return -EINVAL;
  2881. }
  2882. r = r600_dma_cs_next_reloc(p, &dst2_reloc);
  2883. if (r) {
  2884. DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
  2885. return -EINVAL;
  2886. }
  2887. dst_offset = radeon_get_ib_value(p, idx+1);
  2888. dst_offset <<= 8;
  2889. dst2_offset = radeon_get_ib_value(p, idx+2);
  2890. dst2_offset <<= 8;
  2891. src_offset = radeon_get_ib_value(p, idx+8);
  2892. src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
  2893. if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
  2894. dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
  2895. src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
  2896. return -EINVAL;
  2897. }
  2898. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2899. dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
  2900. dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
  2901. return -EINVAL;
  2902. }
  2903. if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
  2904. dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
  2905. dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
  2906. return -EINVAL;
  2907. }
  2908. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
  2909. ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
  2910. ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
  2911. ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
  2912. p->idx += 10;
  2913. break;
  2914. default:
  2915. DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header);
  2916. return -EINVAL;
  2917. }
  2918. break;
  2919. case DMA_PACKET_CONSTANT_FILL:
  2920. r = r600_dma_cs_next_reloc(p, &dst_reloc);
  2921. if (r) {
  2922. DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n");
  2923. return -EINVAL;
  2924. }
  2925. dst_offset = radeon_get_ib_value(p, idx+1);
  2926. dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
  2927. if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
  2928. dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
  2929. dst_offset, radeon_bo_size(dst_reloc->robj));
  2930. return -EINVAL;
  2931. }
  2932. ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
  2933. ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
  2934. p->idx += 4;
  2935. break;
  2936. case DMA_PACKET_NOP:
  2937. p->idx += 1;
  2938. break;
  2939. default:
  2940. DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
  2941. return -EINVAL;
  2942. }
  2943. } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
  2944. #if 0
  2945. for (r = 0; r < p->ib->length_dw; r++) {
  2946. printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
  2947. mdelay(1);
  2948. }
  2949. #endif
  2950. return 0;
  2951. }
  2952. /* vm parser */
  2953. static bool evergreen_vm_reg_valid(u32 reg)
  2954. {
  2955. /* context regs are fine */
  2956. if (reg >= 0x28000)
  2957. return true;
  2958. /* check config regs */
  2959. switch (reg) {
  2960. case WAIT_UNTIL:
  2961. case GRBM_GFX_INDEX:
  2962. case CP_STRMOUT_CNTL:
  2963. case CP_COHER_CNTL:
  2964. case CP_COHER_SIZE:
  2965. case VGT_VTX_VECT_EJECT_REG:
  2966. case VGT_CACHE_INVALIDATION:
  2967. case VGT_GS_VERTEX_REUSE:
  2968. case VGT_PRIMITIVE_TYPE:
  2969. case VGT_INDEX_TYPE:
  2970. case VGT_NUM_INDICES:
  2971. case VGT_NUM_INSTANCES:
  2972. case VGT_COMPUTE_DIM_X:
  2973. case VGT_COMPUTE_DIM_Y:
  2974. case VGT_COMPUTE_DIM_Z:
  2975. case VGT_COMPUTE_START_X:
  2976. case VGT_COMPUTE_START_Y:
  2977. case VGT_COMPUTE_START_Z:
  2978. case VGT_COMPUTE_INDEX:
  2979. case VGT_COMPUTE_THREAD_GROUP_SIZE:
  2980. case VGT_HS_OFFCHIP_PARAM:
  2981. case PA_CL_ENHANCE:
  2982. case PA_SU_LINE_STIPPLE_VALUE:
  2983. case PA_SC_LINE_STIPPLE_STATE:
  2984. case PA_SC_ENHANCE:
  2985. case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
  2986. case SQ_DYN_GPR_SIMD_LOCK_EN:
  2987. case SQ_CONFIG:
  2988. case SQ_GPR_RESOURCE_MGMT_1:
  2989. case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
  2990. case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
  2991. case SQ_CONST_MEM_BASE:
  2992. case SQ_STATIC_THREAD_MGMT_1:
  2993. case SQ_STATIC_THREAD_MGMT_2:
  2994. case SQ_STATIC_THREAD_MGMT_3:
  2995. case SPI_CONFIG_CNTL:
  2996. case SPI_CONFIG_CNTL_1:
  2997. case TA_CNTL_AUX:
  2998. case DB_DEBUG:
  2999. case DB_DEBUG2:
  3000. case DB_DEBUG3:
  3001. case DB_DEBUG4:
  3002. case DB_WATERMARKS:
  3003. case TD_PS_BORDER_COLOR_INDEX:
  3004. case TD_PS_BORDER_COLOR_RED:
  3005. case TD_PS_BORDER_COLOR_GREEN:
  3006. case TD_PS_BORDER_COLOR_BLUE:
  3007. case TD_PS_BORDER_COLOR_ALPHA:
  3008. case TD_VS_BORDER_COLOR_INDEX:
  3009. case TD_VS_BORDER_COLOR_RED:
  3010. case TD_VS_BORDER_COLOR_GREEN:
  3011. case TD_VS_BORDER_COLOR_BLUE:
  3012. case TD_VS_BORDER_COLOR_ALPHA:
  3013. case TD_GS_BORDER_COLOR_INDEX:
  3014. case TD_GS_BORDER_COLOR_RED:
  3015. case TD_GS_BORDER_COLOR_GREEN:
  3016. case TD_GS_BORDER_COLOR_BLUE:
  3017. case TD_GS_BORDER_COLOR_ALPHA:
  3018. case TD_HS_BORDER_COLOR_INDEX:
  3019. case TD_HS_BORDER_COLOR_RED:
  3020. case TD_HS_BORDER_COLOR_GREEN:
  3021. case TD_HS_BORDER_COLOR_BLUE:
  3022. case TD_HS_BORDER_COLOR_ALPHA:
  3023. case TD_LS_BORDER_COLOR_INDEX:
  3024. case TD_LS_BORDER_COLOR_RED:
  3025. case TD_LS_BORDER_COLOR_GREEN:
  3026. case TD_LS_BORDER_COLOR_BLUE:
  3027. case TD_LS_BORDER_COLOR_ALPHA:
  3028. case TD_CS_BORDER_COLOR_INDEX:
  3029. case TD_CS_BORDER_COLOR_RED:
  3030. case TD_CS_BORDER_COLOR_GREEN:
  3031. case TD_CS_BORDER_COLOR_BLUE:
  3032. case TD_CS_BORDER_COLOR_ALPHA:
  3033. case SQ_ESGS_RING_SIZE:
  3034. case SQ_GSVS_RING_SIZE:
  3035. case SQ_ESTMP_RING_SIZE:
  3036. case SQ_GSTMP_RING_SIZE:
  3037. case SQ_HSTMP_RING_SIZE:
  3038. case SQ_LSTMP_RING_SIZE:
  3039. case SQ_PSTMP_RING_SIZE:
  3040. case SQ_VSTMP_RING_SIZE:
  3041. case SQ_ESGS_RING_ITEMSIZE:
  3042. case SQ_ESTMP_RING_ITEMSIZE:
  3043. case SQ_GSTMP_RING_ITEMSIZE:
  3044. case SQ_GSVS_RING_ITEMSIZE:
  3045. case SQ_GS_VERT_ITEMSIZE:
  3046. case SQ_GS_VERT_ITEMSIZE_1:
  3047. case SQ_GS_VERT_ITEMSIZE_2:
  3048. case SQ_GS_VERT_ITEMSIZE_3:
  3049. case SQ_GSVS_RING_OFFSET_1:
  3050. case SQ_GSVS_RING_OFFSET_2:
  3051. case SQ_GSVS_RING_OFFSET_3:
  3052. case SQ_HSTMP_RING_ITEMSIZE:
  3053. case SQ_LSTMP_RING_ITEMSIZE:
  3054. case SQ_PSTMP_RING_ITEMSIZE:
  3055. case SQ_VSTMP_RING_ITEMSIZE:
  3056. case VGT_TF_RING_SIZE:
  3057. case SQ_ESGS_RING_BASE:
  3058. case SQ_GSVS_RING_BASE:
  3059. case SQ_ESTMP_RING_BASE:
  3060. case SQ_GSTMP_RING_BASE:
  3061. case SQ_HSTMP_RING_BASE:
  3062. case SQ_LSTMP_RING_BASE:
  3063. case SQ_PSTMP_RING_BASE:
  3064. case SQ_VSTMP_RING_BASE:
  3065. case CAYMAN_VGT_OFFCHIP_LDS_BASE:
  3066. case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
  3067. return true;
  3068. default:
  3069. DRM_ERROR("Invalid register 0x%x in CS\n", reg);
  3070. return false;
  3071. }
  3072. }
  3073. static int evergreen_vm_packet3_check(struct radeon_device *rdev,
  3074. u32 *ib, struct radeon_cs_packet *pkt)
  3075. {
  3076. u32 idx = pkt->idx + 1;
  3077. u32 idx_value = ib[idx];
  3078. u32 start_reg, end_reg, reg, i;
  3079. u32 command, info;
  3080. switch (pkt->opcode) {
  3081. case PACKET3_NOP:
  3082. case PACKET3_SET_BASE:
  3083. case PACKET3_CLEAR_STATE:
  3084. case PACKET3_INDEX_BUFFER_SIZE:
  3085. case PACKET3_DISPATCH_DIRECT:
  3086. case PACKET3_DISPATCH_INDIRECT:
  3087. case PACKET3_MODE_CONTROL:
  3088. case PACKET3_SET_PREDICATION:
  3089. case PACKET3_COND_EXEC:
  3090. case PACKET3_PRED_EXEC:
  3091. case PACKET3_DRAW_INDIRECT:
  3092. case PACKET3_DRAW_INDEX_INDIRECT:
  3093. case PACKET3_INDEX_BASE:
  3094. case PACKET3_DRAW_INDEX_2:
  3095. case PACKET3_CONTEXT_CONTROL:
  3096. case PACKET3_DRAW_INDEX_OFFSET:
  3097. case PACKET3_INDEX_TYPE:
  3098. case PACKET3_DRAW_INDEX:
  3099. case PACKET3_DRAW_INDEX_AUTO:
  3100. case PACKET3_DRAW_INDEX_IMMD:
  3101. case PACKET3_NUM_INSTANCES:
  3102. case PACKET3_DRAW_INDEX_MULTI_AUTO:
  3103. case PACKET3_STRMOUT_BUFFER_UPDATE:
  3104. case PACKET3_DRAW_INDEX_OFFSET_2:
  3105. case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
  3106. case PACKET3_MPEG_INDEX:
  3107. case PACKET3_WAIT_REG_MEM:
  3108. case PACKET3_MEM_WRITE:
  3109. case PACKET3_SURFACE_SYNC:
  3110. case PACKET3_EVENT_WRITE:
  3111. case PACKET3_EVENT_WRITE_EOP:
  3112. case PACKET3_EVENT_WRITE_EOS:
  3113. case PACKET3_SET_CONTEXT_REG:
  3114. case PACKET3_SET_BOOL_CONST:
  3115. case PACKET3_SET_LOOP_CONST:
  3116. case PACKET3_SET_RESOURCE:
  3117. case PACKET3_SET_SAMPLER:
  3118. case PACKET3_SET_CTL_CONST:
  3119. case PACKET3_SET_RESOURCE_OFFSET:
  3120. case PACKET3_SET_CONTEXT_REG_INDIRECT:
  3121. case PACKET3_SET_RESOURCE_INDIRECT:
  3122. case CAYMAN_PACKET3_DEALLOC_STATE:
  3123. break;
  3124. case PACKET3_COND_WRITE:
  3125. if (idx_value & 0x100) {
  3126. reg = ib[idx + 5] * 4;
  3127. if (!evergreen_vm_reg_valid(reg))
  3128. return -EINVAL;
  3129. }
  3130. break;
  3131. case PACKET3_COPY_DW:
  3132. if (idx_value & 0x2) {
  3133. reg = ib[idx + 3] * 4;
  3134. if (!evergreen_vm_reg_valid(reg))
  3135. return -EINVAL;
  3136. }
  3137. break;
  3138. case PACKET3_SET_CONFIG_REG:
  3139. start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
  3140. end_reg = 4 * pkt->count + start_reg - 4;
  3141. if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
  3142. (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
  3143. (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
  3144. DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
  3145. return -EINVAL;
  3146. }
  3147. for (i = 0; i < pkt->count; i++) {
  3148. reg = start_reg + (4 * i);
  3149. if (!evergreen_vm_reg_valid(reg))
  3150. return -EINVAL;
  3151. }
  3152. break;
  3153. case PACKET3_CP_DMA:
  3154. command = ib[idx + 4];
  3155. info = ib[idx + 1];
  3156. if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
  3157. (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */
  3158. ((((info & 0x00300000) >> 20) == 0) &&
  3159. (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */
  3160. ((((info & 0x60000000) >> 29) == 0) &&
  3161. (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */
  3162. /* non mem to mem copies requires dw aligned count */
  3163. if ((command & 0x1fffff) % 4) {
  3164. DRM_ERROR("CP DMA command requires dw count alignment\n");
  3165. return -EINVAL;
  3166. }
  3167. }
  3168. if (command & PACKET3_CP_DMA_CMD_SAS) {
  3169. /* src address space is register */
  3170. if (((info & 0x60000000) >> 29) == 0) {
  3171. start_reg = idx_value << 2;
  3172. if (command & PACKET3_CP_DMA_CMD_SAIC) {
  3173. reg = start_reg;
  3174. if (!evergreen_vm_reg_valid(reg)) {
  3175. DRM_ERROR("CP DMA Bad SRC register\n");
  3176. return -EINVAL;
  3177. }
  3178. } else {
  3179. for (i = 0; i < (command & 0x1fffff); i++) {
  3180. reg = start_reg + (4 * i);
  3181. if (!evergreen_vm_reg_valid(reg)) {
  3182. DRM_ERROR("CP DMA Bad SRC register\n");
  3183. return -EINVAL;
  3184. }
  3185. }
  3186. }
  3187. }
  3188. }
  3189. if (command & PACKET3_CP_DMA_CMD_DAS) {
  3190. /* dst address space is register */
  3191. if (((info & 0x00300000) >> 20) == 0) {
  3192. start_reg = ib[idx + 2];
  3193. if (command & PACKET3_CP_DMA_CMD_DAIC) {
  3194. reg = start_reg;
  3195. if (!evergreen_vm_reg_valid(reg)) {
  3196. DRM_ERROR("CP DMA Bad DST register\n");
  3197. return -EINVAL;
  3198. }
  3199. } else {
  3200. for (i = 0; i < (command & 0x1fffff); i++) {
  3201. reg = start_reg + (4 * i);
  3202. if (!evergreen_vm_reg_valid(reg)) {
  3203. DRM_ERROR("CP DMA Bad DST register\n");
  3204. return -EINVAL;
  3205. }
  3206. }
  3207. }
  3208. }
  3209. }
  3210. break;
  3211. default:
  3212. return -EINVAL;
  3213. }
  3214. return 0;
  3215. }
  3216. int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
  3217. {
  3218. int ret = 0;
  3219. u32 idx = 0;
  3220. struct radeon_cs_packet pkt;
  3221. do {
  3222. pkt.idx = idx;
  3223. pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
  3224. pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
  3225. pkt.one_reg_wr = 0;
  3226. switch (pkt.type) {
  3227. case RADEON_PACKET_TYPE0:
  3228. dev_err(rdev->dev, "Packet0 not allowed!\n");
  3229. ret = -EINVAL;
  3230. break;
  3231. case RADEON_PACKET_TYPE2:
  3232. idx += 1;
  3233. break;
  3234. case RADEON_PACKET_TYPE3:
  3235. pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
  3236. ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
  3237. idx += pkt.count + 2;
  3238. break;
  3239. default:
  3240. dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
  3241. ret = -EINVAL;
  3242. break;
  3243. }
  3244. if (ret)
  3245. break;
  3246. } while (idx < ib->length_dw);
  3247. return ret;
  3248. }
  3249. /**
  3250. * evergreen_dma_ib_parse() - parse the DMA IB for VM
  3251. * @rdev: radeon_device pointer
  3252. * @ib: radeon_ib pointer
  3253. *
  3254. * Parses the DMA IB from the VM CS ioctl
  3255. * checks for errors. (Cayman-SI)
  3256. * Returns 0 for success and an error on failure.
  3257. **/
  3258. int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
  3259. {
  3260. u32 idx = 0;
  3261. u32 header, cmd, count, sub_cmd;
  3262. do {
  3263. header = ib->ptr[idx];
  3264. cmd = GET_DMA_CMD(header);
  3265. count = GET_DMA_COUNT(header);
  3266. sub_cmd = GET_DMA_SUB_CMD(header);
  3267. switch (cmd) {
  3268. case DMA_PACKET_WRITE:
  3269. switch (sub_cmd) {
  3270. /* tiled */
  3271. case 8:
  3272. idx += count + 7;
  3273. break;
  3274. /* linear */
  3275. case 0:
  3276. idx += count + 3;
  3277. break;
  3278. default:
  3279. DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]);
  3280. return -EINVAL;
  3281. }
  3282. break;
  3283. case DMA_PACKET_COPY:
  3284. switch (sub_cmd) {
  3285. /* Copy L2L, DW aligned */
  3286. case 0x00:
  3287. idx += 5;
  3288. break;
  3289. /* Copy L2T/T2L */
  3290. case 0x08:
  3291. idx += 9;
  3292. break;
  3293. /* Copy L2L, byte aligned */
  3294. case 0x40:
  3295. idx += 5;
  3296. break;
  3297. /* Copy L2L, partial */
  3298. case 0x41:
  3299. idx += 9;
  3300. break;
  3301. /* Copy L2L, DW aligned, broadcast */
  3302. case 0x44:
  3303. idx += 7;
  3304. break;
  3305. /* Copy L2T Frame to Field */
  3306. case 0x48:
  3307. idx += 10;
  3308. break;
  3309. /* Copy L2T/T2L, partial */
  3310. case 0x49:
  3311. idx += 12;
  3312. break;
  3313. /* Copy L2T broadcast */
  3314. case 0x4b:
  3315. idx += 10;
  3316. break;
  3317. /* Copy L2T/T2L (tile units) */
  3318. case 0x4c:
  3319. idx += 9;
  3320. break;
  3321. /* Copy T2T, partial (tile units) */
  3322. case 0x4d:
  3323. idx += 13;
  3324. break;
  3325. /* Copy L2T broadcast (tile units) */
  3326. case 0x4f:
  3327. idx += 10;
  3328. break;
  3329. default:
  3330. DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]);
  3331. return -EINVAL;
  3332. }
  3333. break;
  3334. case DMA_PACKET_CONSTANT_FILL:
  3335. idx += 4;
  3336. break;
  3337. case DMA_PACKET_NOP:
  3338. idx += 1;
  3339. break;
  3340. default:
  3341. DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
  3342. return -EINVAL;
  3343. }
  3344. } while (idx < ib->length_dw);
  3345. return 0;
  3346. }