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/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0013-omap4-separate-mux-settings-into-essential-and-non-e.patch

http://github.com/OpenELEC/OpenELEC.tv
Patch | 1294 lines | 1274 code | 20 blank | 0 comment | 0 complexity | a4428fcc8ce4371f4cc8e1418ae10f75 MD5 | raw file
Possible License(s): CC0-1.0 
    

  1. From c46103152b4875805e05752b3684038798ffaf32 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Aneesh V <aneesh@ti.com>
    3. 

  3. Date: Thu, 17 Feb 2011 01:48:11 +0530
    4. 

  4. Subject: [PATCH 13/22] omap4: separate mux settings into essential and non essential parts
    5. 

  5. 

  6. Do the essential part from SPL and non-essential part from U-Boot
    7. 

  7. - Essential part is what is essential for u-boot to function
    8. 

  8. - Essential part is also largely board independent(at least
    9. 

  9.   as of now)
    10. 

  10. - So essential part is moved out to SoC directory instead of
    11. 

  11.   keeping in board directory. This helps in having single SPL
    12. 

  12.   that works for Panda and SDP.
    13. 

  13. - Non-essential part is what is set by u-boot for kernel to
    14. 

  14.   function correctly
    15. 

  15. - Ideally non-essential part should be phased out eventually
    16. 

  16. 

  17. Signed-off-by: Aneesh V <aneesh@ti.com>
    18. 

  18. ---
    19. 

  19.  arch/arm/cpu/armv7/omap4/board.c            |   53 +++++-
    20. 

  20.  arch/arm/cpu/armv7/omap4/omap4_mux_data.h   |   76 ++++++++
    21. 

  21.  arch/arm/include/asm/arch-omap4/sys_proto.h |    4 +-
    22. 

  22.  board/ti/panda/panda.c                      |   25 +--
    23. 

  23.  board/ti/panda/panda.h                      |  264 ---------------------------
    24. 

  24.  board/ti/panda/panda_mux_data.h             |  229 +++++++++++++++++++++++
    25. 

  25.  board/ti/sdp4430/sdp.c                      |   25 +--
    26. 

  26.  board/ti/sdp4430/sdp.h                      |  264 ---------------------------
    27. 

  27.  board/ti/sdp4430/sdp4430_mux_data.h         |  227 +++++++++++++++++++++++
    28. 

  28.  9 files changed, 597 insertions(+), 570 deletions(-)
    29. 

  29.  create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
    30. 

  30.  delete mode 100644 board/ti/panda/panda.h
    31. 

  31.  create mode 100644 board/ti/panda/panda_mux_data.h
    32. 

  32.  delete mode 100644 board/ti/sdp4430/sdp.h
    33. 

  33.  create mode 100644 board/ti/sdp4430/sdp4430_mux_data.h
    34. 

  34. 

  35. diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
    36. 

  36. index da79669..95b6a96 100644
    37. 

  37. --- a/arch/arm/cpu/armv7/omap4/board.c
    38. 

  38. +++ b/arch/arm/cpu/armv7/omap4/board.c
    39. 

  39. @@ -32,9 +32,30 @@
    40. 

  40.  #include <asm/arch/cpu.h>
    41. 

  41.  #include <asm/arch/sys_proto.h>
    42. 

  42.  #include <asm/sizes.h>
    43. 

  43. +#include "omap4_mux_data.h"
    44. 

  44.  
    45. 

  45.  DECLARE_GLOBAL_DATA_PTR;
    46. 

  46.  
    47. 

  47. +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
    48. 

  48. +{
    49. 

  49. +	int i;
    50. 

  50. +	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
    51. 

  51. +
    52. 

  52. +	for (i = 0; i < size; i++, pad++)
    53. 

  53. +		writew(pad->val, base + pad->offset);
    54. 

  54. +}
    55. 

  55. +
    56. 

  56. +static void set_muxconf_regs_essential(void)
    57. 

  57. +{
    58. 

  58. +	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
    59. 

  59. +		   sizeof(core_padconf_array_essential) /
    60. 

  60. +		   sizeof(struct pad_conf_entry));
    61. 

  61. +
    62. 

  62. +	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
    63. 

  63. +		   sizeof(wkup_padconf_array_essential) /
    64. 

  64. +		   sizeof(struct pad_conf_entry));
    65. 

  65. +}
    66. 

  66. +
    67. 

  67.  #ifdef CONFIG_PRELOADER
    68. 

  68.  u32 omap4_boot_device = BOOT_DEVICE_MMC1;
    69. 

  69.  u32 omap4_boot_mode = MMCSD_MODE_FAT;
    70. 

  70. @@ -49,14 +70,41 @@ u32 omap_boot_mode(void)
    71. 

  71.  }
    72. 

  72.  #endif
    73. 

  73.  
    74. 

  74. +static void set_mux_conf_regs(void)
    75. 

  75. +{
    76. 

  76. +	switch (omap4_hw_init_context()) {
    77. 

  77. +	case OMAP_INIT_CONTEXT_SPL:
    78. 

  78. +		set_muxconf_regs_essential();
    79. 

  79. +		break;
    80. 

  80. +	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL:
    81. 

  81. +		set_muxconf_regs_non_essential();
    82. 

  82. +		break;
    83. 

  83. +	case OMAP_INIT_CONTEXT_XIP_UBOOT:
    84. 

  84. +	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH:
    85. 

  85. +		set_muxconf_regs_essential();
    86. 

  86. +		set_muxconf_regs_non_essential();
    87. 

  87. +		break;
    88. 

  88. +	}
    89. 

  89. +}
    90. 

  90. +
    91. 

  91.  /*
    92. 

  92.   * Routine: s_init
    93. 

  93. - * Description: Does early system init of muxing and clocks.
    94. 

  94. - *              - Called path is with SRAM stack.
    95. 

  95. + * Description: Does early system init of watchdog, muxing, clocks, and
    96. 

  96. + * sdram. Watchdog disable is done always. For the rest what gets done
    97. 

  97. + * depends on the boot mode in which this function is executed
    98. 

  98. + *   1. s_init of SPL running from SRAM
    99. 

  99. + *   2. s_init of U-Boot running from FLASH
    100. 

  100. + *   3. s_init of U-Boot loaded to SDRAM by SPL
    101. 

  101. + *   4. s_init of U-Boot loaded to SDRAM by ROM code using the Configuration
    102. 

  102. + *	Header feature
    103. 

  103. + * Please have a look at the respective functions to see what gets done in
    104. 

  104. + * each of these cases
    105. 

  105. + * This function is called with SRAM stack.
    106. 

  106.   */
    107. 

  107.  void s_init(void)
    108. 

  108.  {
    109. 

  109.  	watchdog_init();
    110. 

  110. +	set_mux_conf_regs();
    111. 

  111.  #ifdef CONFIG_PRELOADER
    112. 

  112.  	preloader_console_init();
    113. 

  113.  #endif
    114. 

  114. @@ -142,7 +190,6 @@ int checkboard(void)
    115. 

  115.  */
    116. 

  116.  int arch_cpu_init(void)
    117. 

  117.  {
    118. 

  118. -	set_muxconf_regs();
    119. 

  119.  	return 0;
    120. 

  120.  }
    121. 

  121.  
    122. 

  122. diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
    123. 

  123. new file mode 100644
    124. 

  124. index 0000000..00c52f8
    125. 

  125. --- /dev/null
    126. 

  126. +++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
    127. 

  127. @@ -0,0 +1,76 @@
    128. 

  128. + /*
    129. 

  129. + * (C) Copyright 2010
    130. 

  130. + * Texas Instruments Incorporated, <www.ti.com>
    131. 

  131. + *
    132. 

  132. + *	Balaji Krishnamoorthy	<balajitk@ti.com>
    133. 

  133. + *	Aneesh V		<aneesh@ti.com>
    134. 

  134. + *
    135. 

  135. + * See file CREDITS for list of people who contributed to this
    136. 

  136. + * project.
    137. 

  137. + *
    138. 

  138. + * This program is free software; you can redistribute it and/or
    139. 

  139. + * modify it under the terms of the GNU General Public License as
    140. 

  140. + * published by the Free Software Foundation; either version 2 of
    141. 

  141. + * the License, or (at your option) any later version.
    142. 

  142. + *
    143. 

  143. + * This program is distributed in the hope that it will be useful,
    144. 

  144. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
    145. 

  145. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    146. 

  146. + * GNU General Public License for more details.
    147. 

  147. + *
    148. 

  148. + * You should have received a copy of the GNU General Public License
    149. 

  149. + * along with this program; if not, write to the Free Software
    150. 

  150. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    151. 

  151. + * MA 02111-1307 USA
    152. 

  152. + */
    153. 

  153. +#ifndef _OMAP4_MUX_DATA_H_
    154. 

  154. +#define _OMAP4_MUX_DATA_H_
    155. 

  155. +
    156. 

  156. +#include <asm/arch/mux_omap4.h>
    157. 

  157. +
    158. 

  158. +const struct pad_conf_entry core_padconf_array_essential[] = {
    159. 

  159. +
    160. 

  160. +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
    161. 

  161. +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
    162. 

  162. +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
    163. 

  163. +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
    164. 

  164. +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
    165. 

  165. +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
    166. 

  166. +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
    167. 

  167. +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
    168. 

  168. +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
    169. 

  169. +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
    170. 

  170. +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
    171. 

  171. +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
    172. 

  172. +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
    173. 

  173. +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
    174. 

  174. +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
    175. 

  175. +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
    176. 

  176. +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
    177. 

  177. +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
    178. 

  178. +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
    179. 

  179. +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
    180. 

  180. +{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
    181. 

  181. +{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
    182. 

  182. +{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
    183. 

  183. +{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
    184. 

  184. +{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
    185. 

  185. +{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
    186. 

  186. +{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
    187. 

  187. +{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
    188. 

  188. +{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
    189. 

  189. +{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
    190. 

  190. +{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
    191. 

  191. +{UART3_TX_IRTX, (M0)}					/* uart3_tx */
    192. 

  192. +
    193. 

  193. +};
    194. 

  194. +
    195. 

  195. +const struct pad_conf_entry wkup_padconf_array_essential[] = {
    196. 

  196. +
    197. 

  197. +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
    198. 

  198. +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
    199. 

  199. +{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
    200. 

  200. +
    201. 

  201. +};
    202. 

  202. +
    203. 

  203. +#endif  /* _OMAP4_MUX_DATA_H_ */
    204. 

  204. diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
    205. 

  205. index 19da2e1..33a1666 100644
    206. 

  206. --- a/arch/arm/include/asm/arch-omap4/sys_proto.h
    207. 

  207. +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
    208. 

  208. @@ -24,6 +24,7 @@
    209. 

  209.  #include <asm/arch/omap4.h>
    210. 

  210.  #include <asm/io.h>
    211. 

  211.  #include <asm/omap_common.h>
    212. 

  212. +#include <asm/arch/mux_omap4.h>
    213. 

  213.  
    214. 

  214.  struct omap_sysinfo {
    215. 

  215.  	char *board_string;
    216. 

  216. @@ -33,7 +34,8 @@ void gpmc_init(void);
    217. 

  217.  void watchdog_init(void);
    218. 

  218.  u32 get_device_type(void);
    219. 

  219.  void invalidate_dcache(u32);
    220. 

  220. -void set_muxconf_regs(void);
    221. 

  221. +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
    222. 

  222. +void set_muxconf_regs_non_essential(void);
    223. 

  223.  void sr32(void *, u32, u32, u32);
    224. 

  224.  u32 wait_on_value(u32, u32, void *, u32);
    225. 

  225.  void sdelay(unsigned long);
    226. 

  226. diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
    227. 

  227. index 78e1910..9afed80 100644
    228. 

  228. --- a/board/ti/panda/panda.c
    229. 

  229. +++ b/board/ti/panda/panda.c
    230. 

  230. @@ -25,7 +25,7 @@
    231. 

  231.  #include <asm/arch/sys_proto.h>
    232. 

  232.  #include <asm/arch/mmc_host_def.h>
    233. 

  233.  
    234. 

  234. -#include "panda.h"
    235. 

  235. +#include "panda_mux_data.h"
    236. 

  236.  
    237. 

  237.  DECLARE_GLOBAL_DATA_PTR;
    238. 

  238.  
    239. 

  239. @@ -65,27 +65,14 @@ int misc_init_r(void)
    240. 

  240.  	return 0;
    241. 

  241.  }
    242. 

  242.  
    243. 

  243. -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
    244. 

  244. +void set_muxconf_regs_non_essential(void)
    245. 

  245.  {
    246. 

  246. -	int i;
    247. 

  247. -	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
    248. 

  248. -
    249. 

  249. -	for (i = 0; i < size; i++, pad++)
    250. 

  250. -		writew(pad->val, base + pad->offset);
    251. 

  251. -}
    252. 

  252. -
    253. 

  253. -/**
    254. 

  254. - * @brief set_muxconf_regs Setting up the configuration Mux registers
    255. 

  255. - * specific to the board.
    256. 

  256. - */
    257. 

  257. -void set_muxconf_regs(void)
    258. 

  258. -{
    259. 

  259. -	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
    260. 

  260. -		   sizeof(core_padconf_array) /
    261. 

  261. +	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
    262. 

  262. +		   sizeof(core_padconf_array_non_essential) /
    263. 

  263.  		   sizeof(struct pad_conf_entry));
    264. 

  264.  
    265. 

  265. -	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
    266. 

  266. -		   sizeof(wkup_padconf_array) /
    267. 

  267. +	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
    268. 

  268. +		   sizeof(wkup_padconf_array_non_essential) /
    269. 

  269.  		   sizeof(struct pad_conf_entry));
    270. 

  270.  }
    271. 

  271.  
    272. 

  272. diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda.h
    273. 

  273. deleted file mode 100644
    274. 

  274. index e3d090e..0000000
    275. 

  275. --- a/board/ti/panda/panda.h
    276. 

  276. +++ /dev/null
    277. 

  277. @@ -1,264 +0,0 @@
    278. 

  278. -/*
    279. 

  279. - * (C) Copyright 2010
    280. 

  280. - * Texas Instruments Incorporated, <www.ti.com>
    281. 

  281. - *
    282. 

  282. - *	Balaji Krishnamoorthy	<balajitk@ti.com>
    283. 

  283. - *	Aneesh V		<aneesh@ti.com>
    284. 

  284. - *
    285. 

  285. - * See file CREDITS for list of people who contributed to this
    286. 

  286. - * project.
    287. 

  287. - *
    288. 

  288. - * This program is free software; you can redistribute it and/or
    289. 

  289. - * modify it under the terms of the GNU General Public License as
    290. 

  290. - * published by the Free Software Foundation; either version 2 of
    291. 

  291. - * the License, or (at your option) any later version.
    292. 

  292. - *
    293. 

  293. - * This program is distributed in the hope that it will be useful,
    294. 

  294. - * but WITHOUT ANY WARRANTY; without even the implied warranty of
    295. 

  295. - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    296. 

  296. - * GNU General Public License for more details.
    297. 

  297. - *
    298. 

  298. - * You should have received a copy of the GNU General Public License
    299. 

  299. - * along with this program; if not, write to the Free Software
    300. 

  300. - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    301. 

  301. - * MA 02111-1307 USA
    302. 

  302. - */
    303. 

  303. -
    304. 

  304. -#ifndef _PANDA_H_
    305. 

  305. -#define _PANDA_H_
    306. 

  306. -
    307. 

  307. -#include <asm/io.h>
    308. 

  308. -#include <asm/arch/mux_omap4.h>
    309. 

  309. -
    310. 

  310. -const struct pad_conf_entry core_padconf_array[] = {
    311. 

  311. -	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
    312. 

  312. -	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
    313. 

  313. -	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
    314. 

  314. -	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
    315. 

  315. -	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
    316. 

  316. -	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
    317. 

  317. -	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
    318. 

  318. -	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
    319. 

  319. -	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
    320. 

  320. -	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
    321. 

  321. -	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
    322. 

  322. -	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
    323. 

  323. -	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
    324. 

  324. -	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
    325. 

  325. -	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
    326. 

  326. -	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
    327. 

  327. -	{GPMC_A16, (M3)},						/* gpio_40 */
    328. 

  328. -	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
    329. 

  329. -	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
    330. 

  330. -	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
    331. 

  331. -	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
    332. 

  332. -	{GPMC_A21, (M3)},						/* gpio_45 */
    333. 

  333. -	{GPMC_A22, (M3)},						/* gpio_46 */
    334. 

  334. -	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
    335. 

  335. -	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
    336. 

  336. -	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
    337. 

  337. -	{GPMC_NCS0, (M3)},						/* gpio_50 */
    338. 

  338. -	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
    339. 

  339. -	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
    340. 

  340. -	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
    341. 

  341. -	{GPMC_NWP, (M3)},						/* gpio_54 */
    342. 

  342. -	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
    343. 

  343. -	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
    344. 

  344. -	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
    345. 

  345. -	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
    346. 

  346. -	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
    347. 

  347. -	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
    348. 

  348. -	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
    349. 

  349. -	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
    350. 

  350. -	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
    351. 

  351. -	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
    352. 

  352. -	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
    353. 

  353. -	{C2C_DATA14, (M1)},						/* dsi2_te0 */
    354. 

  354. -	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
    355. 

  355. -	{HDMI_HPD, (M0)},						/* hdmi_hpd */
    356. 

  356. -	{HDMI_CEC, (M0)},						/* hdmi_cec */
    357. 

  357. -	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
    358. 

  358. -	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
    359. 

  359. -	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
    360. 

  360. -	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
    361. 

  361. -	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
    362. 

  362. -	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
    363. 

  363. -	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
    364. 

  364. -	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
    365. 

  365. -	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
    366. 

  366. -	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
    367. 

  367. -	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
    368. 

  368. -	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
    369. 

  369. -	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
    370. 

  370. -	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
    371. 

  371. -	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
    372. 

  372. -	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
    373. 

  373. -	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
    374. 

  374. -	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
    375. 

  375. -	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
    376. 

  376. -	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
    377. 

  377. -	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
    378. 

  378. -	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
    379. 

  379. -	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
    380. 

  380. -	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
    381. 

  381. -	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
    382. 

  382. -	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
    383. 

  383. -	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
    384. 

  384. -	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
    385. 

  385. -	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
    386. 

  386. -	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
    387. 

  387. -	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
    388. 

  388. -	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
    389. 

  389. -	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
    390. 

  390. -	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
    391. 

  391. -	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
    392. 

  392. -	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
    393. 

  393. -	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
    394. 

  394. -	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
    395. 

  395. -	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
    396. 

  396. -	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
    397. 

  397. -	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
    398. 

  398. -	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
    399. 

  399. -	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
    400. 

  400. -	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
    401. 

  401. -	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
    402. 

  402. -	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
    403. 

  403. -	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
    404. 

  404. -	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
    405. 

  405. -	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
    406. 

  406. -	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
    407. 

  407. -	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
    408. 

  408. -	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
    409. 

  409. -	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
    410. 

  410. -	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
    411. 

  411. -	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
    412. 

  412. -	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
    413. 

  413. -	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
    414. 

  414. -	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
    415. 

  415. -	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
    416. 

  416. -	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
    417. 

  417. -	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
    418. 

  418. -	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
    419. 

  419. -	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
    420. 

  420. -	{UART2_RTS, (M0)},						/* uart2_rts */
    421. 

  421. -	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
    422. 

  422. -	{UART2_TX, (M0)},						/* uart2_tx */
    423. 

  423. -	{HDQ_SIO, (M3)},						/* gpio_127 */
    424. 

  424. -	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
    425. 

  425. -	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
    426. 

  426. -	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
    427. 

  427. -	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
    428. 

  428. -	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
    429. 

  429. -	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
    430. 

  430. -	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
    431. 

  431. -	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
    432. 

  432. -	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
    433. 

  433. -	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
    434. 

  434. -	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
    435. 

  435. -	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
    436. 

  436. -	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
    437. 

  437. -	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
    438. 

  438. -	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
    439. 

  439. -	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
    440. 

  440. -	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
    441. 

  441. -	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
    442. 

  442. -	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
    443. 

  443. -	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
    444. 

  444. -	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
    445. 

  445. -	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
    446. 

  446. -	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
    447. 

  447. -	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
    448. 

  448. -	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
    449. 

  449. -	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
    450. 

  450. -	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
    451. 

  451. -	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
    452. 

  452. -	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
    453. 

  453. -	{UART4_RX, (IEN | M0)},						/* uart4_rx */
    454. 

  454. -	{UART4_TX, (M0)},						/* uart4_tx */
    455. 

  455. -	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
    456. 

  456. -	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
    457. 

  457. -	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
    458. 

  458. -	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
    459. 

  459. -	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
    460. 

  460. -	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
    461. 

  461. -	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
    462. 

  462. -	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
    463. 

  463. -	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
    464. 

  464. -	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
    465. 

  465. -	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
    466. 

  466. -	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
    467. 

  467. -	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
    468. 

  468. -	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
    469. 

  469. -	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
    470. 

  470. -	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
    471. 

  471. -	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
    472. 

  472. -	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
    473. 

  473. -	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
    474. 

  474. -	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
    475. 

  475. -	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
    476. 

  476. -	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
    477. 

  477. -	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
    478. 

  478. -	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
    479. 

  479. -	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
    480. 

  480. -	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
    481. 

  481. -	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
    482. 

  482. -	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
    483. 

  483. -	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
    484. 

  484. -	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
    485. 

  485. -	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
    486. 

  486. -	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
    487. 

  487. -	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
    488. 

  488. -	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
    489. 

  489. -	{SYS_BOOT1, (M3)},						/* gpio_185 */
    490. 

  490. -	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
    491. 

  491. -	{SYS_BOOT3, (M3)},						/* gpio_187 */
    492. 

  492. -	{SYS_BOOT4, (M3)},						/* gpio_188 */
    493. 

  493. -	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
    494. 

  494. -	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
    495. 

  495. -	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
    496. 

  496. -	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
    497. 

  497. -	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
    498. 

  498. -	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
    499. 

  499. -	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
    500. 

  500. -	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
    501. 

  501. -	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
    502. 

  502. -	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
    503. 

  503. -	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
    504. 

  504. -	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
    505. 

  505. -	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
    506. 

  506. -	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
    507. 

  507. -	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
    508. 

  508. -	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
    509. 

  509. -	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
    510. 

  510. -	{DPM_EMU16, (M3)},						/* gpio_27 */
    511. 

  511. -	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
    512. 

  512. -	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
    513. 

  513. -	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
    514. 

  514. -};
    515. 

  515. -
    516. 

  516. -const struct pad_conf_entry wkup_padconf_array[] = {
    517. 

  517. -	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
    518. 

  518. -	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
    519. 

  519. -	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
    520. 

  520. -	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
    521. 

  521. -	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
    522. 

  522. -	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
    523. 

  523. -	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
    524. 

  524. -	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
    525. 

  525. -	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
    526. 

  526. -	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
    527. 

  527. -	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
    528. 

  528. -	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
    529. 

  529. -	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
    530. 

  530. -	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
    531. 

  531. -	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
    532. 

  532. -	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
    533. 

  533. -	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
    534. 

  534. -	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
    535. 

  535. -	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
    536. 

  536. -	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
    537. 

  537. -	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
    538. 

  538. -	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
    539. 

  539. -};
    540. 

  540. -
    541. 

  541. -#endif
    542. 

  542. diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
    543. 

  543. new file mode 100644
    544. 

  544. index 0000000..8bb7fe5
    545. 

  545. --- /dev/null
    546. 

  546. +++ b/board/ti/panda/panda_mux_data.h
    547. 

  547. @@ -0,0 +1,229 @@
    548. 

  548. +/*
    549. 

  549. + * (C) Copyright 2010
    550. 

  550. + * Texas Instruments Incorporated, <www.ti.com>
    551. 

  551. + *
    552. 

  552. + *	Balaji Krishnamoorthy	<balajitk@ti.com>
    553. 

  553. + *	Aneesh V		<aneesh@ti.com>
    554. 

  554. + *
    555. 

  555. + * See file CREDITS for list of people who contributed to this
    556. 

  556. + * project.
    557. 

  557. + *
    558. 

  558. + * This program is free software; you can redistribute it and/or
    559. 

  559. + * modify it under the terms of the GNU General Public License as
    560. 

  560. + * published by the Free Software Foundation; either version 2 of
    561. 

  561. + * the License, or (at your option) any later version.
    562. 

  562. + *
    563. 

  563. + * This program is distributed in the hope that it will be useful,
    564. 

  564. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
    565. 

  565. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    566. 

  566. + * GNU General Public License for more details.
    567. 

  567. + *
    568. 

  568. + * You should have received a copy of the GNU General Public License
    569. 

  569. + * along with this program; if not, write to the Free Software
    570. 

  570. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    571. 

  571. + * MA 02111-1307 USA
    572. 

  572. + */
    573. 

  573. +
    574. 

  574. +#ifndef _PANDA_MUX_DATA_H_
    575. 

  575. +#define _PANDA_MUX_DATA_H_
    576. 

  576. +
    577. 

  577. +#include <asm/io.h>
    578. 

  578. +#include <asm/arch/mux_omap4.h>
    579. 

  579. +
    580. 

  580. +const struct pad_conf_entry core_padconf_array_non_essential[] = {
    581. 

  581. +	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
    582. 

  582. +	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
    583. 

  583. +	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
    584. 

  584. +	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
    585. 

  585. +	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
    586. 

  586. +	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
    587. 

  587. +	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
    588. 

  588. +	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
    589. 

  589. +	{GPMC_A16, (M3)},						/* gpio_40 */
    590. 

  590. +	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
    591. 

  591. +	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
    592. 

  592. +	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
    593. 

  593. +	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
    594. 

  594. +	{GPMC_A21, (M3)},						/* gpio_45 */
    595. 

  595. +	{GPMC_A22, (M3)},						/* gpio_46 */
    596. 

  596. +	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
    597. 

  597. +	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
    598. 

  598. +	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
    599. 

  599. +	{GPMC_NCS0, (M3)},						/* gpio_50 */
    600. 

  600. +	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
    601. 

  601. +	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
    602. 

  602. +	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
    603. 

  603. +	{GPMC_NWP, (M3)},						/* gpio_54 */
    604. 

  604. +	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
    605. 

  605. +	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
    606. 

  606. +	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
    607. 

  607. +	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
    608. 

  608. +	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
    609. 

  609. +	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
    610. 

  610. +	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
    611. 

  611. +	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
    612. 

  612. +	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
    613. 

  613. +	{C2C_DATA14, (M1)},						/* dsi2_te0 */
    614. 

  614. +	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
    615. 

  615. +	{HDMI_HPD, (M0)},						/* hdmi_hpd */
    616. 

  616. +	{HDMI_CEC, (M0)},						/* hdmi_cec */
    617. 

  617. +	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
    618. 

  618. +	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
    619. 

  619. +	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
    620. 

  620. +	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
    621. 

  621. +	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
    622. 

  622. +	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
    623. 

  623. +	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
    624. 

  624. +	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
    625. 

  625. +	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
    626. 

  626. +	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
    627. 

  627. +	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
    628. 

  628. +	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
    629. 

  629. +	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
    630. 

  630. +	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
    631. 

  631. +	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
    632. 

  632. +	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
    633. 

  633. +	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
    634. 

  634. +	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
    635. 

  635. +	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
    636. 

  636. +	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
    637. 

  637. +	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
    638. 

  638. +	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
    639. 

  639. +	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
    640. 

  640. +	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
    641. 

  641. +	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
    642. 

  642. +	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
    643. 

  643. +	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
    644. 

  644. +	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
    645. 

  645. +	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
    646. 

  646. +	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
    647. 

  647. +	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
    648. 

  648. +	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
    649. 

  649. +	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
    650. 

  650. +	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
    651. 

  651. +	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
    652. 

  652. +	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
    653. 

  653. +	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
    654. 

  654. +	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
    655. 

  655. +	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
    656. 

  656. +	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
    657. 

  657. +	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
    658. 

  658. +	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
    659. 

  659. +	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
    660. 

  660. +	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
    661. 

  661. +	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
    662. 

  662. +	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
    663. 

  663. +	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
    664. 

  664. +	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
    665. 

  665. +	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
    666. 

  666. +	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
    667. 

  667. +	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
    668. 

  668. +	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
    669. 

  669. +	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
    670. 

  670. +	{UART2_RTS, (M0)},						/* uart2_rts */
    671. 

  671. +	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
    672. 

  672. +	{UART2_TX, (M0)},						/* uart2_tx */
    673. 

  673. +	{HDQ_SIO, (M3)},						/* gpio_127 */
    674. 

  674. +	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
    675. 

  675. +	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
    676. 

  676. +	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
    677. 

  677. +	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
    678. 

  678. +	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
    679. 

  679. +	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
    680. 

  680. +	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
    681. 

  681. +	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
    682. 

  682. +	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
    683. 

  683. +	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
    684. 

  684. +	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
    685. 

  685. +	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
    686. 

  686. +	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
    687. 

  687. +	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
    688. 

  688. +	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
    689. 

  689. +	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
    690. 

  690. +	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
    691. 

  691. +	{UART4_RX, (IEN | M0)},						/* uart4_rx */
    692. 

  692. +	{UART4_TX, (M0)},						/* uart4_tx */
    693. 

  693. +	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
    694. 

  694. +	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
    695. 

  695. +	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
    696. 

  696. +	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
    697. 

  697. +	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
    698. 

  698. +	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
    699. 

  699. +	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
    700. 

  700. +	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
    701. 

  701. +	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
    702. 

  702. +	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
    703. 

  703. +	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
    704. 

  704. +	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
    705. 

  705. +	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
    706. 

  706. +	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
    707. 

  707. +	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
    708. 

  708. +	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
    709. 

  709. +	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
    710. 

  710. +	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
    711. 

  711. +	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
    712. 

  712. +	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
    713. 

  713. +	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
    714. 

  714. +	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
    715. 

  715. +	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
    716. 

  716. +	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
    717. 

  717. +	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
    718. 

  718. +	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
    719. 

  719. +	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
    720. 

  720. +	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
    721. 

  721. +	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
    722. 

  722. +	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
    723. 

  723. +	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
    724. 

  724. +	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
    725. 

  725. +	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
    726. 

  726. +	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
    727. 

  727. +	{SYS_BOOT1, (M3)},						/* gpio_185 */
    728. 

  728. +	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
    729. 

  729. +	{SYS_BOOT3, (M3)},						/* gpio_187 */
    730. 

  730. +	{SYS_BOOT4, (M3)},						/* gpio_188 */
    731. 

  731. +	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
    732. 

  732. +	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
    733. 

  733. +	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
    734. 

  734. +	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
    735. 

  735. +	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
    736. 

  736. +	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
    737. 

  737. +	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
    738. 

  738. +	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
    739. 

  739. +	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
    740. 

  740. +	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
    741. 

  741. +	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
    742. 

  742. +	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
    743. 

  743. +	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
    744. 

  744. +	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
    745. 

  745. +	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
    746. 

  746. +	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
    747. 

  747. +	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
    748. 

  748. +	{DPM_EMU16, (M3)},						/* gpio_27 */
    749. 

  749. +	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
    750. 

  750. +	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
    751. 

  751. +	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
    752. 

  752. +};
    753. 

  753. +
    754. 

  754. +const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
    755. 

  755. +	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
    756. 

  756. +	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
    757. 

  757. +	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
    758. 

  758. +	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
    759. 

  759. +	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
    760. 

  760. +	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
    761. 

  761. +	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
    762. 

  762. +	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
    763. 

  763. +	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
    764. 

  764. +	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
    765. 

  765. +	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
    766. 

  766. +	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
    767. 

  767. +	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
    768. 

  768. +	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
    769. 

  769. +	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
    770. 

  770. +	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
    771. 

  771. +	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
    772. 

  772. +	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
    773. 

  773. +	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
    774. 

  774. +};
    775. 

  775. +
    776. 

  776. +#endif /* _PANDA_MUX_DATA_H_ */
    777. 

  777. diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
    778. 

  778. index b13c4c5..a5ea682 100644
    779. 

  779. --- a/board/ti/sdp4430/sdp.c
    780. 

  780. +++ b/board/ti/sdp4430/sdp.c
    781. 

  781. @@ -27,7 +27,7 @@
    782. 

  782.  #include <asm/arch/sys_proto.h>
    783. 

  783.  #include <asm/arch/mmc_host_def.h>
    784. 

  784.  
    785. 

  785. -#include "sdp.h"
    786. 

  786. +#include "sdp4430_mux_data.h"
    787. 

  787.  
    788. 

  788.  DECLARE_GLOBAL_DATA_PTR;
    789. 

  789.  
    790. 

  790. @@ -70,27 +70,14 @@ int misc_init_r(void)
    791. 

  791.  	return 0;
    792. 

  792.  }
    793. 

  793.  
    794. 

  794. -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
    795. 

  795. +void set_muxconf_regs_non_essential(void)
    796. 

  796.  {
    797. 

  797. -	int i;
    798. 

  798. -	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
    799. 

  799. -
    800. 

  800. -	for (i = 0; i < size; i++, pad++)
    801. 

  801. -		writew(pad->val, base + pad->offset);
    802. 

  802. -}
    803. 

  803. -
    804. 

  804. -/**
    805. 

  805. - * @brief set_muxconf_regs Setting up the configuration Mux registers
    806. 

  806. - * specific to the board.
    807. 

  807. - */
    808. 

  808. -void set_muxconf_regs(void)
    809. 

  809. -{
    810. 

  810. -	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
    811. 

  811. -		   sizeof(core_padconf_array) /
    812. 

  812. +	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
    813. 

  813. +		   sizeof(core_padconf_array_non_essential) /
    814. 

  814.  		   sizeof(struct pad_conf_entry));
    815. 

  815.  
    816. 

  816. -	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
    817. 

  817. -		   sizeof(wkup_padconf_array) /
    818. 

  818. +	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
    819. 

  819. +		   sizeof(wkup_padconf_array_non_essential) /
    820. 

  820.  		   sizeof(struct pad_conf_entry));
    821. 

  821.  }
    822. 

  822.  
    823. 

  823. diff --git a/board/ti/sdp4430/sdp.h b/board/ti/sdp4430/sdp.h
    824. 

  824. deleted file mode 100644
    825. 

  825. index bf41067..0000000
    826. 

  826. --- a/board/ti/sdp4430/sdp.h
    827. 

  827. +++ /dev/null
    828. 

  828. @@ -1,264 +0,0 @@
    829. 

  829. -/*
    830. 

  830. - * (C) Copyright 2010
    831. 

  831. - * Texas Instruments Incorporated, <www.ti.com>
    832. 

  832. - *
    833. 

  833. - *	Balaji Krishnamoorthy	<balajitk@ti.com>
    834. 

  834. - *	Aneesh V		<aneesh@ti.com>
    835. 

  835. - *
    836. 

  836. - * See file CREDITS for list of people who contributed to this
    837. 

  837. - * project.
    838. 

  838. - *
    839. 

  839. - * This program is free software; you can redistribute it and/or
    840. 

  840. - * modify it under the terms of the GNU General Public License as
    841. 

  841. - * published by the Free Software Foundation; either version 2 of
    842. 

  842. - * the License, or (at your option) any later version.
    843. 

  843. - *
    844. 

  844. - * This program is distributed in the hope that it will be useful,
    845. 

  845. - * but WITHOUT ANY WARRANTY; without even the implied warranty of
    846. 

  846. - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    847. 

  847. - * GNU General Public License for more details.
    848. 

  848. - *
    849. 

  849. - * You should have received a copy of the GNU General Public License
    850. 

  850. - * along with this program; if not, write to the Free Software
    851. 

  851. - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    852. 

  852. - * MA 02111-1307 USA
    853. 

  853. - */
    854. 

  854. -
    855. 

  855. -#ifndef _SDP_H_
    856. 

  856. -#define _SDP_H_
    857. 

  857. -
    858. 

  858. -#include <asm/io.h>
    859. 

  859. -#include <asm/arch/mux_omap4.h>
    860. 

  860. -
    861. 

  861. -const struct pad_conf_entry core_padconf_array[] = {
    862. 

  862. -	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
    863. 

  863. -	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
    864. 

  864. -	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
    865. 

  865. -	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
    866. 

  866. -	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
    867. 

  867. -	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
    868. 

  868. -	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
    869. 

  869. -	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
    870. 

  870. -	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
    871. 

  871. -	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
    872. 

  872. -	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
    873. 

  873. -	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
    874. 

  874. -	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
    875. 

  875. -	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
    876. 

  876. -	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
    877. 

  877. -	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
    878. 

  878. -	{GPMC_A16, (M3)},						/* gpio_40 */
    879. 

  879. -	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
    880. 

  880. -	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
    881. 

  881. -	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
    882. 

  882. -	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
    883. 

  883. -	{GPMC_A21, (M3)},						/* gpio_45 */
    884. 

  884. -	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
    885. 

  885. -	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
    886. 

  886. -	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
    887. 

  887. -	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
    888. 

  888. -	{GPMC_NCS0, (M3)},						/* gpio_50 */
    889. 

  889. -	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
    890. 

  890. -	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
    891. 

  891. -	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
    892. 

  892. -	{GPMC_NWP, (M3)},						/* gpio_54 */
    893. 

  893. -	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
    894. 

  894. -	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
    895. 

  895. -	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
    896. 

  896. -	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
    897. 

  897. -	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
    898. 

  898. -	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
    899. 

  899. -	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
    900. 

  900. -	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
    901. 

  901. -	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
    902. 

  902. -	{C2C_DATA12, (M1)},						/* dsi1_te0 */
    903. 

  903. -	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
    904. 

  904. -	{C2C_DATA14, (M1)},						/* dsi2_te0 */
    905. 

  905. -	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
    906. 

  906. -	{HDMI_HPD, (M0)},						/* hdmi_hpd */
    907. 

  907. -	{HDMI_CEC, (M0)},						/* hdmi_cec */
    908. 

  908. -	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
    909. 

  909. -	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
    910. 

  910. -	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
    911. 

  911. -	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
    912. 

  912. -	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
    913. 

  913. -	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
    914. 

  914. -	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
    915. 

  915. -	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
    916. 

  916. -	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
    917. 

  917. -	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
    918. 

  918. -	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
    919. 

  919. -	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
    920. 

  920. -	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
    921. 

  921. -	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
    922. 

  922. -	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
    923. 

  923. -	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
    924. 

  924. -	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
    925. 

  925. -	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
    926. 

  926. -	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
    927. 

  927. -	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
    928. 

  928. -	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
    929. 

  929. -	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
    930. 

  930. -	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
    931. 

  931. -	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
    932. 

  932. -	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
    933. 

  933. -	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
    934. 

  934. -	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
    935. 

  935. -	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
    936. 

  936. -	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
    937. 

  937. -	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
    938. 

  938. -	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
    939. 

  939. -	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
    940. 

  940. -	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
    941. 

  941. -	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
    942. 

  942. -	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
    943. 

  943. -	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
    944. 

  944. -	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
    945. 

  945. -	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
    946. 

  946. -	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
    947. 

  947. -	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
    948. 

  948. -	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
    949. 

  949. -	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
    950. 

  950. -	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
    951. 

  951. -	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
    952. 

  952. -	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
    953. 

  953. -	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
    954. 

  954. -	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
    955. 

  955. -	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
    956. 

  956. -	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
    957. 

  957. -	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
    958. 

  958. -	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
    959. 

  959. -	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
    960. 

  960. -	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
    961. 

  961. -	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
    962. 

  962. -	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
    963. 

  963. -	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
    964. 

  964. -	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
    965. 

  965. -	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
    966. 

  966. -	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
    967. 

  967. -	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
    968. 

  968. -	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
    969. 

  969. -	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
    970. 

  970. -	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
    971. 

  971. -	{UART2_RTS, (M0)},						/* uart2_rts */
    972. 

  972. -	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
    973. 

  973. -	{UART2_TX, (M0)},						/* uart2_tx */
    974. 

  974. -	{HDQ_SIO, (M3)},						/* gpio_127 */
    975. 

  975. -	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
    976. 

  976. -	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
    977. 

  977. -	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
    978. 

  978. -	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
    979. 

  979. -	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
    980. 

  980. -	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
    981. 

  981. -	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
    982. 

  982. -	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
    983. 

  983. -	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
    984. 

  984. -	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
    985. 

  985. -	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
    986. 

  986. -	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
    987. 

  987. -	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
    988. 

  988. -	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
    989. 

  989. -	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
    990. 

  990. -	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
    991. 

  991. -	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
    992. 

  992. -	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
    993. 

  993. -	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
    994. 

  994. -	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
    995. 

  995. -	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
    996. 

  996. -	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
    997. 

  997. -	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
    998. 

  998. -	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
    999. 

  999. -	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
    1000. 

  1000. -	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
    1001. 

  1001. -	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
    1002. 

  1002. -	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
    1003. 

  1003. -	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
    1004. 

  1004. -	{UART4_RX, (IEN | M0)},						/* uart4_rx */
    1005. 

  1005. -	{UART4_TX, (M0)},						/* uart4_tx */
    1006. 

  1006. -	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
    1007. 

  1007. -	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
    1008. 

  1008. -	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
    1009. 

  1009. -	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
    1010. 

  1010. -	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
    1011. 

  1011. -	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
    1012. 

  1012. -	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
    1013. 

  1013. -	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
    1014. 

  1014. -	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
    1015. 

  1015. -	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
    1016. 

  1016. -	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
    1017. 

  1017. -	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
    1018. 

  1018. -	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
    1019. 

  1019. -	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
    1020. 

  1020. -	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
    1021. 

  1021. -	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
    1022. 

  1022. -	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
    1023. 

  1023. -	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
    1024. 

  1024. -	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
    1025. 

  1025. -	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
    1026. 

  1026. -	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
    1027. 

  1027. -	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
    1028. 

  1028. -	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
    1029. 

  1029. -	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
    1030. 

  1030. -	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
    1031. 

  1031. -	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
    1032. 

  1032. -	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
    1033. 

  1033. -	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
    1034. 

  1034. -	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
    1035. 

  1035. -	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
    1036. 

  1036. -	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
    1037. 

  1037. -	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
    1038. 

  1038. -	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
    1039. 

  1039. -	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
    1040. 

  1040. -	{SYS_BOOT1, (M3)},						/* gpio_185 */
    1041. 

  1041. -	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
    1042. 

  1042. -	{SYS_BOOT3, (M3)},						/* gpio_187 */
    1043. 

  1043. -	{SYS_BOOT4, (M3)},						/* gpio_188 */
    1044. 

  1044. -	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
    1045. 

  1045. -	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
    1046. 

  1046. -	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
    1047. 

  1047. -	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
    1048. 

  1048. -	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
    1049. 

  1049. -	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
    1050. 

  1050. -	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
    1051. 

  1051. -	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
    1052. 

  1052. -	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
    1053. 

  1053. -	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
    1054. 

  1054. -	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
    1055. 

  1055. -	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
    1056. 

  1056. -	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
    1057. 

  1057. -	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
    1058. 

  1058. -	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
    1059. 

  1059. -	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
    1060. 

  1060. -	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
    1061. 

  1061. -	{DPM_EMU16, (M3)},						/* gpio_27 */
    1062. 

  1062. -	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
    1063. 

  1063. -	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
    1064. 

  1064. -	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
    1065. 

  1065. -};
    1066. 

  1066. -
    1067. 

  1067. -const struct pad_conf_entry wkup_padconf_array[] = {
    1068. 

  1068. -	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
    1069. 

  1069. -	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
    1070. 

  1070. -	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
    1071. 

  1071. -	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
    1072. 

  1072. -	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
    1073. 

  1073. -	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
    1074. 

  1074. -	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
    1075. 

  1075. -	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
    1076. 

  1076. -	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
    1077. 

  1077. -	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
    1078. 

  1078. -	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
    1079. 

  1079. -	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
    1080. 

  1080. -	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
    1081. 

  1081. -	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
    1082. 

  1082. -	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
    1083. 

  1083. -	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
    1084. 

  1084. -	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
    1085. 

  1085. -	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
    1086. 

  1086. -	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
    1087. 

  1087. -	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
    1088. 

  1088. -	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
    1089. 

  1089. -	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
    1090. 

  1090. -};
    1091. 

  1091. -
    1092. 

  1092. -#endif
    1093. 

  1093. diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
    1094. 

  1094. new file mode 100644
    1095. 

  1095. index 0000000..e6081dc
    1096. 

  1096. --- /dev/null
    1097. 

  1097. +++ b/board/ti/sdp4430/sdp4430_mux_data.h
    1098. 

  1098. @@ -0,0 +1,227 @@
    1099. 

  1099. +/*
    1100. 

  1100. + * (C) Copyright 2010
    1101. 

  1101. + * Texas Instruments Incorporated, <www.ti.com>
    1102. 

  1102. + *
    1103. 

  1103. + *	Balaji Krishnamoorthy	<balajitk@ti.com>
    1104. 

  1104. + *	Aneesh V		<aneesh@ti.com>
    1105. 

  1105. + *
    1106. 

  1106. + * See file CREDITS for list of people who contributed to this
    1107. 

  1107. + * project.
    1108. 

  1108. + *
    1109. 

  1109. + * This program is free software; you can redistribute it and/or
    1110. 

  1110. + * modify it under the terms of the GNU General Public License as
    1111. 

  1111. + * published by the Free Software Foundation; either version 2 of
    1112. 

  1112. + * the License, or (at your option) any later version.
    1113. 

  1113. + *
    1114. 

  1114. + * This program is distributed in the hope that it will be useful,
    1115. 

  1115. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
    1116. 

  1116. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    1117. 

  1117. + * GNU General Public License for more details.
    1118. 

  1118. + *
    1119. 

  1119. + * You should have received a copy of the GNU General Public License
    1120. 

  1120. + * along with this program; if not, write to the Free Software
    1121. 

  1121. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    1122. 

  1122. + * MA 02111-1307 USA
    1123. 

  1123. + */
    1124. 

  1124. +#ifndef _SDP4430_MUX_DATA_H
    1125. 

  1125. +#define _SDP4430_MUX_DATA_H
    1126. 

  1126. +
    1127. 

  1127. +#include <asm/arch/mux_omap4.h>
    1128. 

  1128. +
    1129. 

  1129. +const struct pad_conf_entry core_padconf_array_non_essential[] = {
    1130. 

  1130. +	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
    1131. 

  1131. +	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
    1132. 

  1132. +	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
    1133. 

  1133. +	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
    1134. 

  1134. +	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
    1135. 

  1135. +	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
    1136. 

  1136. +	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
    1137. 

  1137. +	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
    1138. 

  1138. +	{GPMC_A16, (M3)},						/* gpio_40 */
    1139. 

  1139. +	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
    1140. 

  1140. +	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
    1141. 

  1141. +	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
    1142. 

  1142. +	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
    1143. 

  1143. +	{GPMC_A21, (M3)},						/* gpio_45 */
    1144. 

  1144. +	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
    1145. 

  1145. +	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
    1146. 

  1146. +	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
    1147. 

  1147. +	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
    1148. 

  1148. +	{GPMC_NCS0, (M3)},						/* gpio_50 */
    1149. 

  1149. +	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
    1150. 

  1150. +	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
    1151. 

  1151. +	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
    1152. 

  1152. +	{GPMC_NWP, (M3)},						/* gpio_54 */
    1153. 

  1153. +	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
    1154. 

  1154. +	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
    1155. 

  1155. +	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
    1156. 

  1156. +	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
    1157. 

  1157. +	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
    1158. 

  1158. +	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
    1159. 

  1159. +	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
    1160. 

  1160. +	{C2C_DATA12, (M1)},						/* dsi1_te0 */
    1161. 

  1161. +	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
    1162. 

  1162. +	{C2C_DATA14, (M1)},						/* dsi2_te0 */
    1163. 

  1163. +	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
    1164. 

  1164. +	{HDMI_HPD, (M0)},						/* hdmi_hpd */
    1165. 

  1165. +	{HDMI_CEC, (M0)},						/* hdmi_cec */
    1166. 

  1166. +	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
    1167. 

  1167. +	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
    1168. 

  1168. +	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
    1169. 

  1169. +	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
    1170. 

  1170. +	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
    1171. 

  1171. +	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
    1172. 

  1172. +	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
    1173. 

  1173. +	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
    1174. 

  1174. +	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
    1175. 

  1175. +	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
    1176. 

  1176. +	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
    1177. 

  1177. +	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
    1178. 

  1178. +	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
    1179. 

  1179. +	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
    1180. 

  1180. +	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
    1181. 

  1181. +	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
    1182. 

  1182. +	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
    1183. 

  1183. +	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
    1184. 

  1184. +	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
    1185. 

  1185. +	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
    1186. 

  1186. +	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
    1187. 

  1187. +	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
    1188. 

  1188. +	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
    1189. 

  1189. +	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
    1190. 

  1190. +	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
    1191. 

  1191. +	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
    1192. 

  1192. +	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
    1193. 

  1193. +	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
    1194. 

  1194. +	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
    1195. 

  1195. +	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
    1196. 

  1196. +	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
    1197. 

  1197. +	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
    1198. 

  1198. +	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
    1199. 

  1199. +	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
    1200. 

  1200. +	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
    1201. 

  1201. +	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
    1202. 

  1202. +	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
    1203. 

  1203. +	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
    1204. 

  1204. +	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
    1205. 

  1205. +	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
    1206. 

  1206. +	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
    1207. 

  1207. +	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
    1208. 

  1208. +	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
    1209. 

  1209. +	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
    1210. 

  1210. +	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
    1211. 

  1211. +	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
    1212. 

  1212. +	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
    1213. 

  1213. +	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
    1214. 

  1214. +	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
    1215. 

  1215. +	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
    1216. 

  1216. +	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
    1217. 

  1217. +	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
    1218. 

  1218. +	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
    1219. 

  1219. +	{UART2_RTS, (M0)},						/* uart2_rts */
    1220. 

  1220. +	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
    1221. 

  1221. +	{UART2_TX, (M0)},						/* uart2_tx */
    1222. 

  1222. +	{HDQ_SIO, (M3)},						/* gpio_127 */
    1223. 

  1223. +	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
    1224. 

  1224. +	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
    1225. 

  1225. +	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
    1226. 

  1226. +	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
    1227. 

  1227. +	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
    1228. 

  1228. +	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
    1229. 

  1229. +	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
    1230. 

  1230. +	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
    1231. 

  1231. +	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
    1232. 

  1232. +	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
    1233. 

  1233. +	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
    1234. 

  1234. +	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
    1235. 

  1235. +	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
    1236. 

  1236. +	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
    1237. 

  1237. +	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
    1238. 

  1238. +	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
    1239. 

  1239. +	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
    1240. 

  1240. +	{UART4_RX, (IEN | M0)},						/* uart4_rx */
    1241. 

  1241. +	{UART4_TX, (M0)},						/* uart4_tx */
    1242. 

  1242. +	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
    1243. 

  1243. +	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
    1244. 

  1244. +	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
    1245. 

  1245. +	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
    1246. 

  1246. +	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
    1247. 

  1247. +	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
    1248. 

  1248. +	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
    1249. 

  1249. +	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
    1250. 

  1250. +	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
    1251. 

  1251. +	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
    1252. 

  1252. +	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
    1253. 

  1253. +	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
    1254. 

  1254. +	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
    1255. 

  1255. +	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
    1256. 

  1256. +	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
    1257. 

  1257. +	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
    1258. 

  1258. +	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
    1259. 

  1259. +	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
    1260. 

  1260. +	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
    1261. 

  1261. +	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
    1262. 

  1262. +	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
    1263. 

  1263. +	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
    1264. 

  1264. +	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
    1265. 

  1265. +	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
    1266. 

  1266. +	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
    1267. 

  1267. +	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
    1268. 

  1268. +	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
    1269. 

  1269. +	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
    1270. 

  1270. +	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
    1271. 

  1271. +	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
    1272. 

  1272. +	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
    1273. 

  1273. +	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
    1274. 

  1274. +	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
    1275. 

  1275. +	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
    1276. 

  1276. +	{SYS_BOOT1, (M3)},						/* gpio_185 */
    1277. 

  1277. +	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
    1278. 

  1278. +	{SYS_BOOT3, (M3)},						/* gpio_187 */
    1279. 

  1279. +	{SYS_BOOT4, (M3)},						/* gpio_188 */
    1280. 

  1280. +	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
    1281. 

  1281. +	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
    1282. 

  1282. +	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
    1283. 

  1283. +	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
    1284. 

  1284. +	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
    1285. 

  1285. +	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
    1286. 

  1286. +	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
    1287. 

  1287. +	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
    1288. 

  1288. +	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
    1289. 

  1289. +	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
    1290. 

  1290. +	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
    1291. 

  1291. +	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
    1292. 

  1292. +	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
    1293. 

  1293. +	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
    1294. 

  1294. +	{DPM_EMU13, (IEN | M5)},					/* disp
    1295.