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/arch/arm/mach-msm/board-8064.c

https://github.com/AICP/kernel_google_msm
C | 3408 lines | 2970 code | 330 blank | 108 comment | 126 complexity | 051bd07c1991f5e7e260656d7a5d82d1 MD5 | raw file
   1/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
   2 *
   3 * This program is free software; you can redistribute it and/or modify
   4 * it under the terms of the GNU General Public License version 2 and
   5 * only version 2 as published by the Free Software Foundation.
   6 *
   7 * This program is distributed in the hope that it will be useful,
   8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10 * GNU General Public License for more details.
  11 *
  12 */
  13#include <linux/kernel.h>
  14#include <linux/bitops.h>
  15#include <linux/platform_device.h>
  16#include <linux/gpio.h>
  17#include <linux/io.h>
  18#include <linux/irq.h>
  19#include <linux/i2c.h>
  20#include <linux/i2c/smb349.h>
  21#include <linux/i2c/sx150x.h>
  22#include <linux/slimbus/slimbus.h>
  23#include <linux/mfd/wcd9xxx/core.h>
  24#include <linux/mfd/wcd9xxx/pdata.h>
  25#include <linux/mfd/pm8xxx/misc.h>
  26#include <linux/msm_ssbi.h>
  27#include <linux/spi/spi.h>
  28#include <linux/dma-contiguous.h>
  29#include <linux/dma-mapping.h>
  30#include <linux/platform_data/qcom_crypto_device.h>
  31#include <linux/msm_ion.h>
  32#include <linux/memory.h>
  33#include <linux/memblock.h>
  34#include <linux/msm_thermal.h>
  35#include <linux/i2c/atmel_mxt_ts.h>
  36#include <linux/cyttsp-qc.h>
  37#include <linux/i2c/isa1200.h>
  38#include <linux/gpio_keys.h>
  39#include <linux/epm_adc.h>
  40#include <linux/i2c/sx150x.h>
  41#include <asm/mach-types.h>
  42#include <asm/mach/arch.h>
  43#include <asm/hardware/gic.h>
  44#include <asm/mach/mmc.h>
  45#include <linux/platform_data/qcom_wcnss_device.h>
  46
  47#include <mach/board.h>
  48#include <mach/msm_iomap.h>
  49#include <mach/ion.h>
  50#include <linux/usb/msm_hsusb.h>
  51#include <linux/usb/android.h>
  52#include <mach/socinfo.h>
  53#include <mach/msm_spi.h>
  54#include "timer.h"
  55#include "devices.h"
  56#include <mach/gpiomux.h>
  57#include <mach/rpm.h>
  58#ifdef CONFIG_ANDROID_PMEM
  59#include <linux/android_pmem.h>
  60#endif
  61#include <mach/msm_memtypes.h>
  62#include <linux/bootmem.h>
  63#include <asm/setup.h>
  64#include <mach/dma.h>
  65#include <mach/msm_dsps.h>
  66#include <mach/msm_bus_board.h>
  67#include <mach/cpuidle.h>
  68#include <mach/mdm2.h>
  69#include <linux/msm_tsens.h>
  70#include <mach/msm_xo.h>
  71#include <mach/msm_rtb.h>
  72#include <sound/cs8427.h>
  73#include <media/gpio-ir-recv.h>
  74#include <linux/fmem.h>
  75#include <mach/msm_pcie.h>
  76#include <mach/restart.h>
  77#include <mach/msm_iomap.h>
  78
  79#include "msm_watchdog.h"
  80#include "board-8064.h"
  81#include "clock.h"
  82#include "spm.h"
  83#include <mach/mpm.h>
  84#include "rpm_resources.h"
  85#include "pm.h"
  86#include "pm-boot.h"
  87#include "devices-msm8x60.h"
  88#include "smd_private.h"
  89#include "sysmon.h"
  90
  91#define MSM_PMEM_ADSP_SIZE         0x7800000
  92#define MSM_PMEM_AUDIO_SIZE        0x4CF000
  93#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
  94#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
  95#else
  96#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
  97#endif
  98
  99#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
 100#define HOLE_SIZE		0x20000
 101#define MSM_ION_MFC_META_SIZE  0x40000 /* 256 Kbytes */
 102#define MSM_CONTIG_MEM_SIZE  0x65000
 103#ifdef CONFIG_MSM_IOMMU
 104#define MSM_ION_MM_SIZE		0x3800000
 105#define MSM_ION_SF_SIZE		0
 106#define MSM_ION_QSECOM_SIZE	0x780000 /* (7.5MB) */
 107#define MSM_ION_HEAP_NUM	8
 108#else
 109#define MSM_ION_MM_SIZE		MSM_PMEM_ADSP_SIZE
 110#define MSM_ION_SF_SIZE		MSM_PMEM_SIZE
 111#define MSM_ION_QSECOM_SIZE	0x600000 /* (6MB) */
 112#define MSM_ION_HEAP_NUM	8
 113#endif
 114#define MSM_ION_MM_FW_SIZE	(0x200000 - HOLE_SIZE) /* (2MB - 128KB) */
 115#define MSM_ION_MFC_SIZE	(SZ_8K + MSM_ION_MFC_META_SIZE)
 116#define MSM_ION_AUDIO_SIZE	MSM_PMEM_AUDIO_SIZE
 117#else
 118#define MSM_CONTIG_MEM_SIZE  0x110C000
 119#define MSM_ION_HEAP_NUM	1
 120#endif
 121
 122#define APQ8064_FIXED_AREA_START (0xa0000000 - (MSM_ION_MM_FW_SIZE + \
 123							HOLE_SIZE))
 124#define MAX_FIXED_AREA_SIZE	0x10000000
 125#define MSM_MM_FW_SIZE		(0x200000 - HOLE_SIZE)
 126#define APQ8064_FW_START	APQ8064_FIXED_AREA_START
 127#define MSM_ION_ADSP_SIZE	SZ_8M
 128
 129#define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB     (MSM_QFPROM_BASE + 0x23c)
 130#define QFPROM_RAW_OEM_CONFIG_ROW0_LSB      (MSM_QFPROM_BASE + 0x220)
 131
 132/* PCIE AXI address space */
 133#define PCIE_AXI_BAR_PHYS   0x08000000
 134#define PCIE_AXI_BAR_SIZE   SZ_128M
 135
 136/* PCIe pmic gpios */
 137#define PCIE_WAKE_N_PMIC_GPIO 12
 138#define PCIE_PWR_EN_PMIC_GPIO 13
 139#define PCIE_RST_N_PMIC_MPP 1
 140
 141#ifdef CONFIG_KERNEL_MSM_CONTIG_MEM_REGION
 142static unsigned msm_contig_mem_size = MSM_CONTIG_MEM_SIZE;
 143static int __init msm_contig_mem_size_setup(char *p)
 144{
 145	msm_contig_mem_size = memparse(p, NULL);
 146	return 0;
 147}
 148early_param("msm_contig_mem_size", msm_contig_mem_size_setup);
 149#endif
 150
 151#ifdef CONFIG_ANDROID_PMEM
 152static unsigned pmem_size = MSM_PMEM_SIZE;
 153static int __init pmem_size_setup(char *p)
 154{
 155	pmem_size = memparse(p, NULL);
 156	return 0;
 157}
 158early_param("pmem_size", pmem_size_setup);
 159
 160static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
 161
 162static int __init pmem_adsp_size_setup(char *p)
 163{
 164	pmem_adsp_size = memparse(p, NULL);
 165	return 0;
 166}
 167early_param("pmem_adsp_size", pmem_adsp_size_setup);
 168
 169static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
 170
 171static int __init pmem_audio_size_setup(char *p)
 172{
 173	pmem_audio_size = memparse(p, NULL);
 174	return 0;
 175}
 176early_param("pmem_audio_size", pmem_audio_size_setup);
 177#endif
 178
 179#ifdef CONFIG_ANDROID_PMEM
 180#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 181static struct android_pmem_platform_data android_pmem_pdata = {
 182	.name = "pmem",
 183	.allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
 184	.cached = 1,
 185	.memory_type = MEMTYPE_EBI1,
 186};
 187
 188static struct platform_device apq8064_android_pmem_device = {
 189	.name = "android_pmem",
 190	.id = 0,
 191	.dev = {.platform_data = &android_pmem_pdata},
 192};
 193
 194static struct android_pmem_platform_data android_pmem_adsp_pdata = {
 195	.name = "pmem_adsp",
 196	.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
 197	.cached = 0,
 198	.memory_type = MEMTYPE_EBI1,
 199};
 200static struct platform_device apq8064_android_pmem_adsp_device = {
 201	.name = "android_pmem",
 202	.id = 2,
 203	.dev = { .platform_data = &android_pmem_adsp_pdata },
 204};
 205
 206static struct android_pmem_platform_data android_pmem_audio_pdata = {
 207	.name = "pmem_audio",
 208	.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
 209	.cached = 0,
 210	.memory_type = MEMTYPE_EBI1,
 211};
 212
 213static struct platform_device apq8064_android_pmem_audio_device = {
 214	.name = "android_pmem",
 215	.id = 4,
 216	.dev = { .platform_data = &android_pmem_audio_pdata },
 217};
 218#endif /* CONFIG_MSM_MULTIMEDIA_USE_ION */
 219#endif /* CONFIG_ANDROID_PMEM */
 220
 221struct fmem_platform_data apq8064_fmem_pdata = {
 222};
 223
 224static struct memtype_reserve apq8064_reserve_table[] __initdata = {
 225	[MEMTYPE_SMI] = {
 226	},
 227	[MEMTYPE_EBI0] = {
 228		.flags	=	MEMTYPE_FLAGS_1M_ALIGN,
 229	},
 230	[MEMTYPE_EBI1] = {
 231		.flags	=	MEMTYPE_FLAGS_1M_ALIGN,
 232	},
 233};
 234
 235static void __init reserve_rtb_memory(void)
 236{
 237#if defined(CONFIG_MSM_RTB)
 238	apq8064_reserve_table[MEMTYPE_EBI1].size += apq8064_rtb_pdata.size;
 239#endif
 240}
 241
 242
 243static void __init size_pmem_devices(void)
 244{
 245#ifdef CONFIG_ANDROID_PMEM
 246#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 247	android_pmem_adsp_pdata.size = pmem_adsp_size;
 248	android_pmem_pdata.size = pmem_size;
 249	android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
 250#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
 251#endif /*CONFIG_ANDROID_PMEM*/
 252}
 253
 254#ifdef CONFIG_ANDROID_PMEM
 255#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 256static void __init reserve_memory_for(struct android_pmem_platform_data *p)
 257{
 258	apq8064_reserve_table[p->memory_type].size += p->size;
 259}
 260#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
 261#endif /*CONFIG_ANDROID_PMEM*/
 262
 263static void __init reserve_pmem_memory(void)
 264{
 265#ifdef CONFIG_ANDROID_PMEM
 266#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 267	reserve_memory_for(&android_pmem_adsp_pdata);
 268	reserve_memory_for(&android_pmem_pdata);
 269	reserve_memory_for(&android_pmem_audio_pdata);
 270#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
 271	apq8064_reserve_table[MEMTYPE_EBI1].size += msm_contig_mem_size;
 272#endif /*CONFIG_ANDROID_PMEM*/
 273}
 274
 275static int apq8064_paddr_to_memtype(unsigned int paddr)
 276{
 277	return MEMTYPE_EBI1;
 278}
 279
 280#define FMEM_ENABLED 0
 281
 282#ifdef CONFIG_ION_MSM
 283#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
 284static struct ion_cp_heap_pdata cp_mm_apq8064_ion_pdata = {
 285	.permission_type = IPT_TYPE_MM_CARVEOUT,
 286	.align = PAGE_SIZE,
 287	.reusable = FMEM_ENABLED,
 288	.mem_is_fmem = FMEM_ENABLED,
 289	.fixed_position = FIXED_MIDDLE,
 290	.is_cma = 1,
 291	.no_nonsecure_alloc = 1,
 292};
 293
 294static struct ion_cp_heap_pdata cp_mfc_apq8064_ion_pdata = {
 295	.permission_type = IPT_TYPE_MFC_SHAREDMEM,
 296	.align = PAGE_SIZE,
 297	.reusable = 0,
 298	.mem_is_fmem = FMEM_ENABLED,
 299	.fixed_position = FIXED_HIGH,
 300	.no_nonsecure_alloc = 1,
 301};
 302
 303static struct ion_co_heap_pdata co_apq8064_ion_pdata = {
 304	.adjacent_mem_id = INVALID_HEAP_ID,
 305	.align = PAGE_SIZE,
 306	.mem_is_fmem = 0,
 307};
 308
 309static struct ion_co_heap_pdata fw_co_apq8064_ion_pdata = {
 310	.adjacent_mem_id = ION_CP_MM_HEAP_ID,
 311	.align = SZ_128K,
 312	.mem_is_fmem = FMEM_ENABLED,
 313	.fixed_position = FIXED_LOW,
 314};
 315#endif
 316
 317static u64 msm_dmamask = DMA_BIT_MASK(32);
 318
 319static struct platform_device ion_mm_heap_device = {
 320	.name = "ion-mm-heap-device",
 321	.id = -1,
 322	.dev = {
 323		.dma_mask = &msm_dmamask,
 324		.coherent_dma_mask = DMA_BIT_MASK(32),
 325	}
 326};
 327
 328static struct platform_device ion_adsp_heap_device = {
 329	.name = "ion-adsp-heap-device",
 330	.id = -1,
 331	.dev = {
 332		.dma_mask = &msm_dmamask,
 333		.coherent_dma_mask = DMA_BIT_MASK(32),
 334	}
 335};
 336/**
 337 * These heaps are listed in the order they will be allocated. Due to
 338 * video hardware restrictions and content protection the FW heap has to
 339 * be allocated adjacent (below) the MM heap and the MFC heap has to be
 340 * allocated after the MM heap to ensure MFC heap is not more than 256MB
 341 * away from the base address of the FW heap.
 342 * However, the order of FW heap and MM heap doesn't matter since these
 343 * two heaps are taken care of by separate code to ensure they are adjacent
 344 * to each other.
 345 * Don't swap the order unless you know what you are doing!
 346 */
 347struct ion_platform_heap apq8064_heaps[] = {
 348		{
 349			.id	= ION_SYSTEM_HEAP_ID,
 350			.type	= ION_HEAP_TYPE_SYSTEM,
 351			.name	= ION_VMALLOC_HEAP_NAME,
 352		},
 353#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
 354		{
 355			.id	= ION_CP_MM_HEAP_ID,
 356			.type	= ION_HEAP_TYPE_CP,
 357			.name	= ION_MM_HEAP_NAME,
 358			.size	= MSM_ION_MM_SIZE,
 359			.memory_type = ION_EBI_TYPE,
 360			.extra_data = (void *) &cp_mm_apq8064_ion_pdata,
 361			.priv	= &ion_mm_heap_device.dev
 362		},
 363		{
 364			.id	= ION_MM_FIRMWARE_HEAP_ID,
 365			.type	= ION_HEAP_TYPE_CARVEOUT,
 366			.name	= ION_MM_FIRMWARE_HEAP_NAME,
 367			.size	= MSM_ION_MM_FW_SIZE,
 368			.memory_type = ION_EBI_TYPE,
 369			.extra_data = (void *) &fw_co_apq8064_ion_pdata,
 370		},
 371		{
 372			.id	= ION_CP_MFC_HEAP_ID,
 373			.type	= ION_HEAP_TYPE_CP,
 374			.name	= ION_MFC_HEAP_NAME,
 375			.size	= MSM_ION_MFC_SIZE,
 376			.memory_type = ION_EBI_TYPE,
 377			.extra_data = (void *) &cp_mfc_apq8064_ion_pdata,
 378		},
 379#ifndef CONFIG_MSM_IOMMU
 380		{
 381			.id	= ION_SF_HEAP_ID,
 382			.type	= ION_HEAP_TYPE_CARVEOUT,
 383			.name	= ION_SF_HEAP_NAME,
 384			.size	= MSM_ION_SF_SIZE,
 385			.memory_type = ION_EBI_TYPE,
 386			.extra_data = (void *) &co_apq8064_ion_pdata,
 387		},
 388#endif
 389		{
 390			.id	= ION_IOMMU_HEAP_ID,
 391			.type	= ION_HEAP_TYPE_IOMMU,
 392			.name	= ION_IOMMU_HEAP_NAME,
 393		},
 394		{
 395			.id	= ION_QSECOM_HEAP_ID,
 396			.type	= ION_HEAP_TYPE_CARVEOUT,
 397			.name	= ION_QSECOM_HEAP_NAME,
 398			.size	= MSM_ION_QSECOM_SIZE,
 399			.memory_type = ION_EBI_TYPE,
 400			.extra_data = (void *) &co_apq8064_ion_pdata,
 401		},
 402		{
 403			.id	= ION_AUDIO_HEAP_ID,
 404			.type	= ION_HEAP_TYPE_CARVEOUT,
 405			.name	= ION_AUDIO_HEAP_NAME,
 406			.size	= MSM_ION_AUDIO_SIZE,
 407			.memory_type = ION_EBI_TYPE,
 408			.extra_data = (void *) &co_apq8064_ion_pdata,
 409		},
 410		{
 411			.id     = ION_ADSP_HEAP_ID,
 412			.type   = ION_HEAP_TYPE_DMA,
 413			.name   = ION_ADSP_HEAP_NAME,
 414			.size   = MSM_ION_ADSP_SIZE,
 415			.memory_type = ION_EBI_TYPE,
 416			.extra_data = (void *) &co_apq8064_ion_pdata,
 417			.priv = &ion_adsp_heap_device.dev,
 418		},
 419#endif
 420};
 421
 422static struct ion_platform_data apq8064_ion_pdata = {
 423	.nr = MSM_ION_HEAP_NUM,
 424	.heaps = apq8064_heaps,
 425};
 426
 427static struct platform_device apq8064_ion_dev = {
 428	.name = "ion-msm",
 429	.id = 1,
 430	.dev = { .platform_data = &apq8064_ion_pdata },
 431};
 432#endif
 433
 434static struct platform_device apq8064_fmem_device = {
 435	.name = "fmem",
 436	.id = 1,
 437	.dev = { .platform_data = &apq8064_fmem_pdata },
 438};
 439
 440static void __init reserve_mem_for_ion(enum ion_memory_types mem_type,
 441				      unsigned long size)
 442{
 443	apq8064_reserve_table[mem_type].size += size;
 444}
 445
 446static void __init apq8064_reserve_fixed_area(unsigned long fixed_area_size)
 447{
 448#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
 449	int ret;
 450
 451	if (fixed_area_size > MAX_FIXED_AREA_SIZE)
 452		panic("fixed area size is larger than %dM\n",
 453			MAX_FIXED_AREA_SIZE >> 20);
 454
 455	reserve_info->fixed_area_size = fixed_area_size;
 456	reserve_info->fixed_area_start = APQ8064_FW_START;
 457
 458	ret = memblock_remove(reserve_info->fixed_area_start,
 459		reserve_info->fixed_area_size);
 460	BUG_ON(ret);
 461#endif
 462}
 463
 464/**
 465 * Reserve memory for ION and calculate amount of reusable memory for fmem.
 466 * We only reserve memory for heaps that are not reusable. However, we only
 467 * support one reusable heap at the moment so we ignore the reusable flag for
 468 * other than the first heap with reusable flag set. Also handle special case
 469 * for video heaps (MM,FW, and MFC). Video requires heaps MM and MFC to be
 470 * at a higher address than FW in addition to not more than 256MB away from the
 471 * base address of the firmware. This means that if MM is reusable the other
 472 * two heaps must be allocated in the same region as FW. This is handled by the
 473 * mem_is_fmem flag in the platform data. In addition the MM heap must be
 474 * adjacent to the FW heap for content protection purposes.
 475 */
 476static void __init reserve_ion_memory(void)
 477{
 478#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
 479	unsigned int i;
 480	unsigned int ret;
 481	unsigned int fixed_size = 0;
 482	unsigned int fixed_low_size, fixed_middle_size, fixed_high_size;
 483	unsigned long fixed_low_start, fixed_middle_start, fixed_high_start;
 484	unsigned long cma_alignment;
 485	unsigned int low_use_cma = 0;
 486	unsigned int middle_use_cma = 0;
 487	unsigned int high_use_cma = 0;
 488
 489
 490	fixed_low_size = 0;
 491	fixed_middle_size = 0;
 492	fixed_high_size = 0;
 493
 494	cma_alignment = PAGE_SIZE << max(MAX_ORDER, pageblock_order);
 495
 496	for (i = 0; i < apq8064_ion_pdata.nr; ++i) {
 497		struct ion_platform_heap *heap =
 498			&(apq8064_ion_pdata.heaps[i]);
 499		int use_cma = 0;
 500
 501
 502		if (heap->extra_data) {
 503			int fixed_position = NOT_FIXED;
 504
 505			switch ((int)heap->type) {
 506			case ION_HEAP_TYPE_CP:
 507				if (((struct ion_cp_heap_pdata *)
 508					heap->extra_data)->is_cma) {
 509					heap->size = ALIGN(heap->size,
 510						cma_alignment);
 511					use_cma = 1;
 512				}
 513				fixed_position = ((struct ion_cp_heap_pdata *)
 514					heap->extra_data)->fixed_position;
 515				break;
 516			case ION_HEAP_TYPE_DMA:
 517				use_cma = 1;
 518				/* Purposely fall through here */
 519			case ION_HEAP_TYPE_CARVEOUT:
 520				fixed_position = ((struct ion_co_heap_pdata *)
 521					heap->extra_data)->fixed_position;
 522				break;
 523			default:
 524				break;
 525			}
 526
 527			if (fixed_position != NOT_FIXED)
 528				fixed_size += heap->size;
 529			else
 530				reserve_mem_for_ion(MEMTYPE_EBI1, heap->size);
 531
 532			if (fixed_position == FIXED_LOW) {
 533				fixed_low_size += heap->size;
 534				low_use_cma = use_cma;
 535			} else if (fixed_position == FIXED_MIDDLE) {
 536				fixed_middle_size += heap->size;
 537				middle_use_cma = use_cma;
 538			} else if (fixed_position == FIXED_HIGH) {
 539				fixed_high_size += heap->size;
 540				high_use_cma = use_cma;
 541			} else if (use_cma) {
 542				/*
 543				 * Heaps that use CMA but are not part of the
 544				 * fixed set. Create wherever.
 545				 */
 546				dma_declare_contiguous(
 547					heap->priv,
 548					heap->size,
 549					0,
 550					0xb0000000);
 551
 552			}
 553		}
 554	}
 555
 556	if (!fixed_size)
 557		return;
 558
 559	/*
 560	 * Given the setup for the fixed area, we can't round up all sizes.
 561	 * Some sizes must be set up exactly and aligned correctly. Incorrect
 562	 * alignments are considered a configuration issue
 563	 */
 564
 565	fixed_low_start = APQ8064_FIXED_AREA_START;
 566	if (low_use_cma) {
 567		BUG_ON(!IS_ALIGNED(fixed_low_size + HOLE_SIZE, cma_alignment));
 568		BUG_ON(!IS_ALIGNED(fixed_low_start, cma_alignment));
 569	} else {
 570		BUG_ON(!IS_ALIGNED(fixed_low_size + HOLE_SIZE, SECTION_SIZE));
 571		ret = memblock_remove(fixed_low_start,
 572				      fixed_low_size + HOLE_SIZE);
 573		BUG_ON(ret);
 574	}
 575
 576	fixed_middle_start = fixed_low_start + fixed_low_size + HOLE_SIZE;
 577	if (middle_use_cma) {
 578		BUG_ON(!IS_ALIGNED(fixed_middle_start, cma_alignment));
 579		BUG_ON(!IS_ALIGNED(fixed_middle_size, cma_alignment));
 580	} else {
 581		BUG_ON(!IS_ALIGNED(fixed_middle_size, SECTION_SIZE));
 582		ret = memblock_remove(fixed_middle_start, fixed_middle_size);
 583		BUG_ON(ret);
 584	}
 585
 586	fixed_high_start = fixed_middle_start + fixed_middle_size;
 587	if (high_use_cma) {
 588		fixed_high_size = ALIGN(fixed_high_size, cma_alignment);
 589		BUG_ON(!IS_ALIGNED(fixed_high_start, cma_alignment));
 590	} else {
 591		/* This is the end of the fixed area so it's okay to round up */
 592		fixed_high_size = ALIGN(fixed_high_size, SECTION_SIZE);
 593		ret = memblock_remove(fixed_high_start, fixed_high_size);
 594		BUG_ON(ret);
 595	}
 596
 597	for (i = 0; i < apq8064_ion_pdata.nr; ++i) {
 598		struct ion_platform_heap *heap = &(apq8064_ion_pdata.heaps[i]);
 599
 600		if (heap->extra_data) {
 601			int fixed_position = NOT_FIXED;
 602			struct ion_cp_heap_pdata *pdata = NULL;
 603
 604			switch ((int) heap->type) {
 605			case ION_HEAP_TYPE_CP:
 606				pdata =
 607				(struct ion_cp_heap_pdata *)heap->extra_data;
 608				fixed_position = pdata->fixed_position;
 609				break;
 610			case ION_HEAP_TYPE_CARVEOUT:
 611			case ION_HEAP_TYPE_DMA:
 612				fixed_position = ((struct ion_co_heap_pdata *)
 613					heap->extra_data)->fixed_position;
 614				break;
 615			default:
 616				break;
 617			}
 618
 619			switch (fixed_position) {
 620			case FIXED_LOW:
 621				heap->base = fixed_low_start;
 622				break;
 623			case FIXED_MIDDLE:
 624				heap->base = fixed_middle_start;
 625				if (middle_use_cma) {
 626					ret = dma_declare_contiguous(
 627						heap->priv,
 628						heap->size,
 629						fixed_middle_start,
 630						0xa0000000);
 631					WARN_ON(ret);
 632				}
 633				pdata->secure_base = fixed_middle_start
 634								- HOLE_SIZE;
 635				pdata->secure_size = HOLE_SIZE + heap->size;
 636				break;
 637			case FIXED_HIGH:
 638				heap->base = fixed_high_start;
 639				break;
 640			default:
 641				break;
 642			}
 643		}
 644	}
 645#endif
 646}
 647
 648static void __init reserve_mdp_memory(void)
 649{
 650	apq8064_mdp_writeback(apq8064_reserve_table);
 651}
 652
 653static void __init reserve_cache_dump_memory(void)
 654{
 655#ifdef CONFIG_MSM_CACHE_DUMP
 656	unsigned int total;
 657
 658	total = apq8064_cache_dump_pdata.l1_size +
 659		apq8064_cache_dump_pdata.l2_size;
 660	apq8064_reserve_table[MEMTYPE_EBI1].size += total;
 661#endif
 662}
 663
 664static void __init reserve_mpdcvs_memory(void)
 665{
 666	apq8064_reserve_table[MEMTYPE_EBI1].size += SZ_32K;
 667}
 668
 669static void __init apq8064_calculate_reserve_sizes(void)
 670{
 671	size_pmem_devices();
 672	reserve_pmem_memory();
 673	reserve_ion_memory();
 674	reserve_mdp_memory();
 675	reserve_rtb_memory();
 676	reserve_cache_dump_memory();
 677	reserve_mpdcvs_memory();
 678}
 679
 680static struct reserve_info apq8064_reserve_info __initdata = {
 681	.memtype_reserve_table = apq8064_reserve_table,
 682	.calculate_reserve_sizes = apq8064_calculate_reserve_sizes,
 683	.reserve_fixed_area = apq8064_reserve_fixed_area,
 684	.paddr_to_memtype = apq8064_paddr_to_memtype,
 685};
 686
 687static int apq8064_memory_bank_size(void)
 688{
 689	return 1<<29;
 690}
 691
 692static void __init locate_unstable_memory(void)
 693{
 694	struct membank *mb = &meminfo.bank[meminfo.nr_banks - 1];
 695	unsigned long bank_size;
 696	unsigned long low, high;
 697
 698	bank_size = apq8064_memory_bank_size();
 699	low = meminfo.bank[0].start;
 700	high = mb->start + mb->size;
 701
 702	/* Check if 32 bit overflow occured */
 703	if (high < mb->start)
 704		high = -PAGE_SIZE;
 705
 706	low &= ~(bank_size - 1);
 707
 708	if (high - low <= bank_size)
 709		goto no_dmm;
 710
 711#ifdef CONFIG_ENABLE_DMM
 712	apq8064_reserve_info.low_unstable_address = mb->start -
 713					MIN_MEMORY_BLOCK_SIZE + mb->size;
 714	apq8064_reserve_info.max_unstable_size = MIN_MEMORY_BLOCK_SIZE;
 715
 716	apq8064_reserve_info.bank_size = bank_size;
 717	pr_info("low unstable address %lx max size %lx bank size %lx\n",
 718		apq8064_reserve_info.low_unstable_address,
 719		apq8064_reserve_info.max_unstable_size,
 720		apq8064_reserve_info.bank_size);
 721	return;
 722#endif
 723no_dmm:
 724	apq8064_reserve_info.low_unstable_address = high;
 725	apq8064_reserve_info.max_unstable_size = 0;
 726}
 727
 728static int apq8064_change_memory_power(u64 start, u64 size,
 729	int change_type)
 730{
 731	return soc_change_memory_power(start, size, change_type);
 732}
 733
 734static char prim_panel_name[PANEL_NAME_MAX_LEN];
 735static char ext_panel_name[PANEL_NAME_MAX_LEN];
 736
 737static int ext_resolution;
 738
 739static int __init prim_display_setup(char *param)
 740{
 741	if (strnlen(param, PANEL_NAME_MAX_LEN))
 742		strlcpy(prim_panel_name, param, PANEL_NAME_MAX_LEN);
 743	return 0;
 744}
 745early_param("prim_display", prim_display_setup);
 746
 747static int __init ext_display_setup(char *param)
 748{
 749	if (strnlen(param, PANEL_NAME_MAX_LEN))
 750		strlcpy(ext_panel_name, param, PANEL_NAME_MAX_LEN);
 751	return 0;
 752}
 753early_param("ext_display", ext_display_setup);
 754
 755static int __init hdmi_resulution_setup(char *param)
 756{
 757	int ret;
 758	ret = kstrtoint(param, 10, &ext_resolution);
 759	return ret;
 760}
 761early_param("ext_resolution", hdmi_resulution_setup);
 762
 763static void __init apq8064_reserve(void)
 764{
 765	apq8064_set_display_params(prim_panel_name, ext_panel_name,
 766		ext_resolution);
 767	msm_reserve();
 768}
 769
 770static void __init place_movable_zone(void)
 771{
 772#ifdef CONFIG_ENABLE_DMM
 773	movable_reserved_start = apq8064_reserve_info.low_unstable_address;
 774	movable_reserved_size = apq8064_reserve_info.max_unstable_size;
 775	pr_info("movable zone start %lx size %lx\n",
 776		movable_reserved_start, movable_reserved_size);
 777#endif
 778}
 779
 780static void __init apq8064_early_reserve(void)
 781{
 782	reserve_info = &apq8064_reserve_info;
 783	locate_unstable_memory();
 784	place_movable_zone();
 785
 786}
 787#ifdef CONFIG_USB_EHCI_MSM_HSIC
 788/* Bandwidth requests (zero) if no vote placed */
 789static struct msm_bus_vectors hsic_init_vectors[] = {
 790	{
 791		.src = MSM_BUS_MASTER_SPS,
 792		.dst = MSM_BUS_SLAVE_SPS,
 793		.ab = 0,
 794		.ib = 0,
 795	},
 796};
 797
 798/* Bus bandwidth requests in Bytes/sec */
 799static struct msm_bus_vectors hsic_max_vectors[] = {
 800	{
 801		.src = MSM_BUS_MASTER_SPS,
 802		.dst = MSM_BUS_SLAVE_SPS,
 803		.ab = 0,
 804		.ib = 256000000, /*vote for 32Mhz dfab clk rate*/
 805	},
 806};
 807
 808static struct msm_bus_paths hsic_bus_scale_usecases[] = {
 809	{
 810		ARRAY_SIZE(hsic_init_vectors),
 811		hsic_init_vectors,
 812	},
 813	{
 814		ARRAY_SIZE(hsic_max_vectors),
 815		hsic_max_vectors,
 816	},
 817};
 818
 819static struct msm_bus_scale_pdata hsic_bus_scale_pdata = {
 820	hsic_bus_scale_usecases,
 821	ARRAY_SIZE(hsic_bus_scale_usecases),
 822	.name = "hsic",
 823};
 824
 825static struct msm_hsic_host_platform_data msm_hsic_pdata = {
 826	.strobe			= 88,
 827	.data			= 89,
 828	.bus_scale_table	= &hsic_bus_scale_pdata,
 829};
 830#else
 831static struct msm_hsic_host_platform_data msm_hsic_pdata;
 832#endif
 833
 834#define PID_MAGIC_ID		0x71432909
 835#define SERIAL_NUM_MAGIC_ID	0x61945374
 836#define SERIAL_NUMBER_LENGTH	127
 837#define DLOAD_USB_BASE_ADD	0x2A03F0C8
 838
 839struct magic_num_struct {
 840	uint32_t pid;
 841	uint32_t serial_num;
 842};
 843
 844struct dload_struct {
 845	uint32_t	reserved1;
 846	uint32_t	reserved2;
 847	uint32_t	reserved3;
 848	uint16_t	reserved4;
 849	uint16_t	pid;
 850	char		serial_number[SERIAL_NUMBER_LENGTH];
 851	uint16_t	reserved5;
 852	struct magic_num_struct magic_struct;
 853};
 854
 855static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
 856{
 857	struct dload_struct __iomem *dload = 0;
 858
 859	dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
 860	if (!dload) {
 861		pr_err("%s: cannot remap I/O memory region: %08x\n",
 862					__func__, DLOAD_USB_BASE_ADD);
 863		return -ENXIO;
 864	}
 865
 866	pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
 867				__func__, dload, pid, snum);
 868	/* update pid */
 869	dload->magic_struct.pid = PID_MAGIC_ID;
 870	dload->pid = pid;
 871
 872	/* update serial number */
 873	dload->magic_struct.serial_num = 0;
 874	if (!snum) {
 875		memset(dload->serial_number, 0, SERIAL_NUMBER_LENGTH);
 876		goto out;
 877	}
 878
 879	dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
 880	strlcpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
 881out:
 882	iounmap(dload);
 883	return 0;
 884}
 885
 886static struct android_usb_platform_data android_usb_pdata = {
 887	.update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
 888};
 889
 890static struct platform_device android_usb_device = {
 891	.name	= "android_usb",
 892	.id	= -1,
 893	.dev	= {
 894		.platform_data = &android_usb_pdata,
 895	},
 896};
 897
 898/* Bandwidth requests (zero) if no vote placed */
 899static struct msm_bus_vectors usb_init_vectors[] = {
 900	{
 901		.src = MSM_BUS_MASTER_SPS,
 902		.dst = MSM_BUS_SLAVE_EBI_CH0,
 903		.ab = 0,
 904		.ib = 0,
 905	},
 906};
 907
 908/* Bus bandwidth requests in Bytes/sec */
 909static struct msm_bus_vectors usb_max_vectors[] = {
 910	{
 911		.src = MSM_BUS_MASTER_SPS,
 912		.dst = MSM_BUS_SLAVE_EBI_CH0,
 913		.ab = 60000000,		/* At least 480Mbps on bus. */
 914		.ib = 960000000,	/* MAX bursts rate */
 915	},
 916};
 917
 918static struct msm_bus_paths usb_bus_scale_usecases[] = {
 919	{
 920		ARRAY_SIZE(usb_init_vectors),
 921		usb_init_vectors,
 922	},
 923	{
 924		ARRAY_SIZE(usb_max_vectors),
 925		usb_max_vectors,
 926	},
 927};
 928
 929static struct msm_bus_scale_pdata usb_bus_scale_pdata = {
 930	usb_bus_scale_usecases,
 931	ARRAY_SIZE(usb_bus_scale_usecases),
 932	.name = "usb",
 933};
 934
 935static int phy_init_seq[] = {
 936	0x38, 0x81, /* update DC voltage level */
 937	0x24, 0x82, /* set pre-emphasis and rise/fall time */
 938	-1
 939};
 940
 941#define PMIC_GPIO_DP		27    /* PMIC GPIO for D+ change */
 942#define PMIC_GPIO_DP_IRQ	PM8921_GPIO_IRQ(PM8921_IRQ_BASE, PMIC_GPIO_DP)
 943#define MSM_MPM_PIN_USB1_OTGSESSVLD	40
 944
 945static struct msm_otg_platform_data msm_otg_pdata = {
 946	.mode			= USB_OTG,
 947	.otg_control		= OTG_PMIC_CONTROL,
 948	.phy_type		= SNPS_28NM_INTEGRATED_PHY,
 949	.pmic_id_irq		= PM8921_USB_ID_IN_IRQ(PM8921_IRQ_BASE),
 950	.power_budget		= 750,
 951	.bus_scale_table	= &usb_bus_scale_pdata,
 952	.phy_init_seq		= phy_init_seq,
 953	.mpm_otgsessvld_int	= MSM_MPM_PIN_USB1_OTGSESSVLD,
 954};
 955
 956static struct msm_usb_host_platform_data msm_ehci_host_pdata3 = {
 957	.power_budget = 500,
 958};
 959
 960#ifdef CONFIG_USB_EHCI_MSM_HOST4
 961static struct msm_usb_host_platform_data msm_ehci_host_pdata4;
 962#endif
 963
 964static void __init apq8064_ehci_host_init(void)
 965{
 966	if (machine_is_apq8064_liquid() || machine_is_mpq8064_cdp() ||
 967		machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()) {
 968		if (machine_is_apq8064_liquid())
 969			msm_ehci_host_pdata3.dock_connect_irq =
 970					PM8921_MPP_IRQ(PM8921_IRQ_BASE, 9);
 971		else
 972			msm_ehci_host_pdata3.pmic_gpio_dp_irq =
 973							PMIC_GPIO_DP_IRQ;
 974
 975		apq8064_device_ehci_host3.dev.platform_data =
 976				&msm_ehci_host_pdata3;
 977		platform_device_register(&apq8064_device_ehci_host3);
 978
 979#ifdef CONFIG_USB_EHCI_MSM_HOST4
 980		apq8064_device_ehci_host4.dev.platform_data =
 981				&msm_ehci_host_pdata4;
 982		platform_device_register(&apq8064_device_ehci_host4);
 983#endif
 984	}
 985}
 986
 987static struct smb349_platform_data smb349_data __initdata = {
 988	.en_n_gpio		= PM8921_GPIO_PM_TO_SYS(37),
 989	.chg_susp_gpio		= PM8921_GPIO_PM_TO_SYS(30),
 990	.chg_current_ma		= 2200,
 991};
 992
 993static struct i2c_board_info smb349_charger_i2c_info[] __initdata = {
 994	{
 995		I2C_BOARD_INFO(SMB349_NAME, 0x1B),
 996		.platform_data	= &smb349_data,
 997	},
 998};
 999
1000struct sx150x_platform_data apq8064_sx150x_data[] = {
1001	[SX150X_EPM] = {
1002		.gpio_base	= GPIO_EPM_EXPANDER_BASE,
1003		.oscio_is_gpo	= false,
1004		.io_pullup_ena	= 0x0,
1005		.io_pulldn_ena	= 0x0,
1006		.io_open_drain_ena = 0x0,
1007		.io_polarity	= 0,
1008		.irq_summary	= -1,
1009	},
1010};
1011
1012static struct epm_chan_properties ads_adc_channel_data[] = {
1013	{10, 100}, {1000, 1}, {10, 100}, {1000, 1},
1014	{10, 100}, {1000, 1}, {10, 100}, {1000, 1},
1015	{10, 100}, {20, 100}, {500, 100}, {5, 100},
1016	{1000, 1}, {200, 100}, {50, 100}, {10, 100},
1017	{510, 100}, {50, 100}, {20, 100}, {100, 100},
1018	{510, 100}, {20, 100}, {50, 100}, {200, 100},
1019	{10, 100}, {20, 100}, {1000, 1}, {10, 100},
1020	{200, 100}, {510, 100}, {1000, 100}, {200, 100},
1021};
1022
1023static struct epm_adc_platform_data epm_adc_pdata = {
1024	.channel		= ads_adc_channel_data,
1025	.bus_id	= 0x0,
1026	.epm_i2c_board_info = {
1027		.type	= "sx1509q",
1028		.addr = 0x3e,
1029		.platform_data = &apq8064_sx150x_data[SX150X_EPM],
1030	},
1031	.gpio_expander_base_addr = GPIO_EPM_EXPANDER_BASE,
1032};
1033
1034static struct platform_device epm_adc_device = {
1035	.name   = "epm_adc",
1036	.id = -1,
1037	.dev = {
1038		.platform_data = &epm_adc_pdata,
1039	},
1040};
1041
1042static void __init apq8064_epm_adc_init(void)
1043{
1044	epm_adc_pdata.num_channels = 32;
1045	epm_adc_pdata.num_adc = 2;
1046	epm_adc_pdata.chan_per_adc = 16;
1047	epm_adc_pdata.chan_per_mux = 8;
1048};
1049
1050/* Micbias setting is based on 8660 CDP/MTP/FLUID requirement
1051 * 4 micbiases are used to power various analog and digital
1052 * microphones operating at 1800 mV. Technically, all micbiases
1053 * can source from single cfilter since all microphones operate
1054 * at the same voltage level. The arrangement below is to make
1055 * sure all cfilters are exercised. LDO_H regulator ouput level
1056 * does not need to be as high as 2.85V. It is choosen for
1057 * microphone sensitivity purpose.
1058 */
1059static struct wcd9xxx_pdata apq8064_tabla_platform_data = {
1060	.slimbus_slave_device = {
1061		.name = "tabla-slave",
1062		.e_addr = {0, 0, 0x10, 0, 0x17, 2},
1063	},
1064	.irq = MSM_GPIO_TO_INT(42),
1065	.irq_base = TABLA_INTERRUPT_BASE,
1066	.num_irqs = NR_WCD9XXX_IRQS,
1067	.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
1068	.micbias = {
1069		.ldoh_v = TABLA_LDOH_2P85_V,
1070		.cfilt1_mv = 1800,
1071		.cfilt2_mv = 2700,
1072		.cfilt3_mv = 1800,
1073		.bias1_cfilt_sel = TABLA_CFILT1_SEL,
1074		.bias2_cfilt_sel = TABLA_CFILT2_SEL,
1075		.bias3_cfilt_sel = TABLA_CFILT3_SEL,
1076		.bias4_cfilt_sel = TABLA_CFILT3_SEL,
1077	},
1078	.regulator = {
1079	{
1080		.name = "CDC_VDD_CP",
1081		.min_uV = 1800000,
1082		.max_uV = 1800000,
1083		.optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
1084	},
1085	{
1086		.name = "CDC_VDDA_RX",
1087		.min_uV = 1800000,
1088		.max_uV = 1800000,
1089		.optimum_uA = WCD9XXX_CDC_VDDA_RX_CUR_MAX,
1090	},
1091	{
1092		.name = "CDC_VDDA_TX",
1093		.min_uV = 1800000,
1094		.max_uV = 1800000,
1095		.optimum_uA = WCD9XXX_CDC_VDDA_TX_CUR_MAX,
1096	},
1097	{
1098		.name = "VDDIO_CDC",
1099		.min_uV = 1800000,
1100		.max_uV = 1800000,
1101		.optimum_uA = WCD9XXX_VDDIO_CDC_CUR_MAX,
1102	},
1103	{
1104		.name = "VDDD_CDC_D",
1105		.min_uV = 1225000,
1106		.max_uV = 1250000,
1107		.optimum_uA = WCD9XXX_VDDD_CDC_D_CUR_MAX,
1108	},
1109	{
1110		.name = "CDC_VDDA_A_1P2V",
1111		.min_uV = 1225000,
1112		.max_uV = 1250000,
1113		.optimum_uA = WCD9XXX_VDDD_CDC_A_CUR_MAX,
1114	},
1115	},
1116};
1117
1118static struct slim_device apq8064_slim_tabla = {
1119	.name = "tabla-slim",
1120	.e_addr = {0, 1, 0x10, 0, 0x17, 2},
1121	.dev = {
1122		.platform_data = &apq8064_tabla_platform_data,
1123	},
1124};
1125
1126static struct wcd9xxx_pdata apq8064_tabla20_platform_data = {
1127	.slimbus_slave_device = {
1128		.name = "tabla-slave",
1129		.e_addr = {0, 0, 0x60, 0, 0x17, 2},
1130	},
1131	.irq = MSM_GPIO_TO_INT(42),
1132	.irq_base = TABLA_INTERRUPT_BASE,
1133	.num_irqs = NR_WCD9XXX_IRQS,
1134	.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
1135	.micbias = {
1136		.ldoh_v = TABLA_LDOH_2P85_V,
1137		.cfilt1_mv = 1800,
1138		.cfilt2_mv = 2700,
1139		.cfilt3_mv = 1800,
1140		.bias1_cfilt_sel = TABLA_CFILT1_SEL,
1141		.bias2_cfilt_sel = TABLA_CFILT2_SEL,
1142		.bias3_cfilt_sel = TABLA_CFILT3_SEL,
1143		.bias4_cfilt_sel = TABLA_CFILT3_SEL,
1144	},
1145	.regulator = {
1146	{
1147		.name = "CDC_VDD_CP",
1148		.min_uV = 1800000,
1149		.max_uV = 1800000,
1150		.optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
1151	},
1152	{
1153		.name = "CDC_VDDA_RX",
1154		.min_uV = 1800000,
1155		.max_uV = 1800000,
1156		.optimum_uA = WCD9XXX_CDC_VDDA_RX_CUR_MAX,
1157	},
1158	{
1159		.name = "CDC_VDDA_TX",
1160		.min_uV = 1800000,
1161		.max_uV = 1800000,
1162		.optimum_uA = WCD9XXX_CDC_VDDA_TX_CUR_MAX,
1163	},
1164	{
1165		.name = "VDDIO_CDC",
1166		.min_uV = 1800000,
1167		.max_uV = 1800000,
1168		.optimum_uA = WCD9XXX_VDDIO_CDC_CUR_MAX,
1169	},
1170	{
1171		.name = "VDDD_CDC_D",
1172		.min_uV = 1225000,
1173		.max_uV = 1250000,
1174		.optimum_uA = WCD9XXX_VDDD_CDC_D_CUR_MAX,
1175	},
1176	{
1177		.name = "CDC_VDDA_A_1P2V",
1178		.min_uV = 1225000,
1179		.max_uV = 1250000,
1180		.optimum_uA = WCD9XXX_VDDD_CDC_A_CUR_MAX,
1181	},
1182	},
1183};
1184
1185static struct slim_device apq8064_slim_tabla20 = {
1186	.name = "tabla2x-slim",
1187	.e_addr = {0, 1, 0x60, 0, 0x17, 2},
1188	.dev = {
1189		.platform_data = &apq8064_tabla20_platform_data,
1190	},
1191};
1192
1193/* enable the level shifter for cs8427 to make sure the I2C
1194 * clock is running at 100KHz and voltage levels are at 3.3
1195 * and 5 volts
1196 */
1197static int enable_100KHz_ls(int enable)
1198{
1199	int ret = 0;
1200	if (enable) {
1201		ret = gpio_request(SX150X_GPIO(1, 10),
1202					"cs8427_100KHZ_ENABLE");
1203		if (ret) {
1204			pr_err("%s: Failed to request gpio %d\n", __func__,
1205				SX150X_GPIO(1, 10));
1206			return ret;
1207		}
1208		gpio_direction_output(SX150X_GPIO(1, 10), 1);
1209	} else {
1210		gpio_direction_output(SX150X_GPIO(1, 10), 0);
1211		gpio_free(SX150X_GPIO(1, 10));
1212	}
1213	return ret;
1214}
1215
1216static struct cs8427_platform_data cs8427_i2c_platform_data = {
1217	.irq = SX150X_GPIO(1, 4),
1218	.reset_gpio = SX150X_GPIO(1, 6),
1219	.enable = enable_100KHz_ls,
1220};
1221
1222static struct i2c_board_info cs8427_device_info[] __initdata = {
1223	{
1224		I2C_BOARD_INFO("cs8427", CS8427_ADDR4),
1225		.platform_data = &cs8427_i2c_platform_data,
1226	},
1227};
1228
1229#define HAP_SHIFT_LVL_OE_GPIO		PM8921_MPP_PM_TO_SYS(8)
1230#define ISA1200_HAP_EN_GPIO		PM8921_GPIO_PM_TO_SYS(33)
1231#define ISA1200_HAP_LEN_GPIO		PM8921_GPIO_PM_TO_SYS(20)
1232#define ISA1200_HAP_CLK_PM8921		PM8921_GPIO_PM_TO_SYS(44)
1233#define ISA1200_HAP_CLK_PM8917		PM8921_GPIO_PM_TO_SYS(38)
1234
1235static int isa1200_clk_enable(bool on)
1236{
1237	unsigned int gpio = ISA1200_HAP_CLK_PM8921;
1238	int rc = 0;
1239
1240	if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
1241		gpio = ISA1200_HAP_CLK_PM8917;
1242
1243	gpio_set_value_cansleep(gpio, on);
1244
1245	if (on) {
1246		rc = pm8xxx_aux_clk_control(CLK_MP3_2, XO_DIV_1, true);
1247		if (rc) {
1248			pr_err("%s: unable to write aux clock register(%d)\n",
1249				__func__, rc);
1250			goto err_gpio_dis;
1251		}
1252	} else {
1253		rc = pm8xxx_aux_clk_control(CLK_MP3_2, XO_DIV_NONE, true);
1254		if (rc)
1255			pr_err("%s: unable to write aux clock register(%d)\n",
1256				__func__, rc);
1257	}
1258
1259	return rc;
1260
1261err_gpio_dis:
1262	gpio_set_value_cansleep(gpio, !on);
1263	return rc;
1264}
1265
1266static int isa1200_dev_setup(bool enable)
1267{
1268	unsigned int gpio = ISA1200_HAP_CLK_PM8921;
1269	int rc = 0;
1270
1271	if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
1272		gpio = ISA1200_HAP_CLK_PM8917;
1273
1274	if (!enable)
1275		goto free_gpio;
1276
1277	rc = gpio_request(gpio, "haptics_clk");
1278	if (rc) {
1279		pr_err("%s: unable to request gpio %d config(%d)\n",
1280			__func__, gpio, rc);
1281		return rc;
1282	}
1283
1284	rc = gpio_direction_output(gpio, 0);
1285	if (rc) {
1286		pr_err("%s: unable to set direction\n", __func__);
1287		goto free_gpio;
1288	}
1289
1290	return 0;
1291
1292free_gpio:
1293	gpio_free(gpio);
1294	return rc;
1295}
1296
1297static struct isa1200_regulator isa1200_reg_data[] = {
1298	{
1299		.name = "vddp",
1300		.min_uV = ISA_I2C_VTG_MIN_UV,
1301		.max_uV = ISA_I2C_VTG_MAX_UV,
1302		.load_uA = ISA_I2C_CURR_UA,
1303	},
1304};
1305
1306static struct isa1200_platform_data isa1200_1_pdata = {
1307	.name = "vibrator",
1308	.dev_setup = isa1200_dev_setup,
1309	.clk_enable = isa1200_clk_enable,
1310	.need_pwm_clk = true,
1311	.hap_en_gpio = ISA1200_HAP_EN_GPIO,
1312	.hap_len_gpio = ISA1200_HAP_LEN_GPIO,
1313	.max_timeout = 15000,
1314	.mode_ctrl = PWM_GEN_MODE,
1315	.pwm_fd = {
1316		.pwm_div = 256,
1317	},
1318	.is_erm = false,
1319	.smart_en = true,
1320	.ext_clk_en = true,
1321	.chip_en = 1,
1322	.regulator_info = isa1200_reg_data,
1323	.num_regulators = ARRAY_SIZE(isa1200_reg_data),
1324};
1325
1326static struct i2c_board_info isa1200_board_info[] __initdata = {
1327	{
1328		I2C_BOARD_INFO("isa1200_1", 0x90>>1),
1329		.platform_data = &isa1200_1_pdata,
1330	},
1331};
1332/* configuration data for mxt1386e using V2.1 firmware */
1333static const u8 mxt1386e_config_data_v2_1[] = {
1334	/* T6 Object */
1335	0, 0, 0, 0, 0, 0,
1336	/* T38 Object */
1337	14, 3, 0, 5, 7, 12, 0, 0, 0, 0,
1338	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1339	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1340	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1341	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1342	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1343	0, 0, 0, 0,
1344	/* T7 Object */
1345	32, 10, 50,
1346	/* T8 Object */
1347	25, 0, 20, 20, 0, 0, 0, 0, 0, 0,
1348	/* T9 Object */
1349	139, 0, 0, 26, 42, 0, 32, 80, 2, 5,
1350	0, 5, 5, 79, 10, 30, 10, 10, 255, 2,
1351	85, 5, 0, 5, 9, 5, 12, 35, 70, 40,
1352	20, 5, 0, 0, 0,
1353	/* T18 Object */
1354	0, 0,
1355	/* T24 Object */
1356	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1357	0, 0, 0, 0, 0, 0, 0, 0, 0,
1358	/* T25 Object */
1359	1, 0, 60, 115, 156, 99,
1360	/* T27 Object */
1361	0, 0, 0, 0, 0, 0, 0,
1362	/* T40 Object */
1363	0, 0, 0, 0, 0,
1364	/* T42 Object */
1365	0, 0, 255, 0, 255, 0, 0, 0, 0, 0,
1366	/* T43 Object */
1367	0, 0, 0, 0, 0, 0, 0, 64, 0, 8,
1368	16,
1369	/* T46 Object */
1370	68, 0, 16, 16, 0, 0, 0, 0, 0,
1371	/* T47 Object */
1372	0, 0, 0, 0, 0, 0, 3, 64, 66, 0,
1373	/* T48 Object */
1374	1, 64, 64, 0, 0, 0, 0, 0, 0, 0,
1375	32, 40, 0, 10, 10, 0, 0, 100, 10, 90,
1376	0, 0, 0, 0, 0, 0, 0, 10, 1, 10,
1377	52, 10, 12, 0, 33, 0, 1, 0, 0, 0,
1378	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1379	0, 0, 0, 0,
1380	/* T56 Object */
1381	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1382	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1383	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1384	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1385	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1386	0,
1387};
1388
1389#define MXT_TS_GPIO_IRQ			6
1390#define MXT_TS_PWR_EN_GPIO		PM8921_GPIO_PM_TO_SYS(23)
1391#define MXT_TS_RESET_GPIO		33
1392
1393static struct mxt_config_info mxt_config_array[] = {
1394	{
1395		.config		= mxt1386e_config_data_v2_1,
1396		.config_length	= ARRAY_SIZE(mxt1386e_config_data_v2_1),
1397		.family_id	= 0xA0,
1398		.variant_id	= 0x7,
1399		.version	= 0x21,
1400		.build		= 0xAA,
1401		.bootldr_id	= MXT_BOOTLOADER_ID_1386E,
1402		.fw_name	= "atmel_8064_liquid_v2_2_AA.hex",
1403	},
1404	{
1405		/* The config data for V2.2.AA is the same as for V2.1.AA */
1406		.config		= mxt1386e_config_data_v2_1,
1407		.config_length	= ARRAY_SIZE(mxt1386e_config_data_v2_1),
1408		.family_id	= 0xA0,
1409		.variant_id	= 0x7,
1410		.version	= 0x22,
1411		.build		= 0xAA,
1412		.bootldr_id	= MXT_BOOTLOADER_ID_1386E,
1413	},
1414};
1415
1416static struct mxt_platform_data mxt_platform_data = {
1417	.config_array		= mxt_config_array,
1418	.config_array_size	= ARRAY_SIZE(mxt_config_array),
1419	.panel_minx		= 0,
1420	.panel_maxx		= 1365,
1421	.panel_miny		= 0,
1422	.panel_maxy		= 767,
1423	.disp_minx		= 0,
1424	.disp_maxx		= 1365,
1425	.disp_miny		= 0,
1426	.disp_maxy		= 767,
1427	.irqflags		= IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1428	.i2c_pull_up		= true,
1429	.reset_gpio		= MXT_TS_RESET_GPIO,
1430	.irq_gpio		= MXT_TS_GPIO_IRQ,
1431};
1432
1433static struct i2c_board_info mxt_device_info[] __initdata = {
1434	{
1435		I2C_BOARD_INFO("atmel_mxt_ts", 0x5b),
1436		.platform_data = &mxt_platform_data,
1437		.irq = MSM_GPIO_TO_INT(MXT_TS_GPIO_IRQ),
1438	},
1439};
1440#define CYTTSP_TS_GPIO_IRQ		6
1441#define CYTTSP_TS_GPIO_SLEEP		33
1442#define CYTTSP_TS_GPIO_SLEEP_ALT	12
1443
1444static ssize_t tma340_vkeys_show(struct kobject *kobj,
1445			struct kobj_attribute *attr, char *buf)
1446{
1447	return snprintf(buf, 200,
1448	__stringify(EV_KEY) ":" __stringify(KEY_BACK) ":73:1120:97:97"
1449	":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":230:1120:97:97"
1450	":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":389:1120:97:97"
1451	":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":544:1120:97:97"
1452	"\n");
1453}
1454
1455static struct kobj_attribute tma340_vkeys_attr = {
1456	.attr = {
1457		.mode = S_IRUGO,
1458	},
1459	.show = &tma340_vkeys_show,
1460};
1461
1462static struct attribute *tma340_properties_attrs[] = {
1463	&tma340_vkeys_attr.attr,
1464	NULL
1465};
1466
1467static struct attribute_group tma340_properties_attr_group = {
1468	.attrs = tma340_properties_attrs,
1469};
1470
1471static int cyttsp_platform_init(struct i2c_client *client)
1472{
1473	int rc = 0;
1474	static struct kobject *tma340_properties_kobj;
1475
1476	tma340_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
1477	tma340_properties_kobj = kobject_create_and_add("board_properties",
1478								NULL);
1479	if (tma340_properties_kobj)
1480		rc = sysfs_create_group(tma340_properties_kobj,
1481					&tma340_properties_attr_group);
1482	if (!tma340_properties_kobj || rc)
1483		pr_err("%s: failed to create board_properties\n",
1484				__func__);
1485
1486	return 0;
1487}
1488
1489static struct cyttsp_regulator cyttsp_regulator_data[] = {
1490	{
1491		.name = "vdd",
1492		.min_uV = CY_TMA300_VTG_MIN_UV,
1493		.max_uV = CY_TMA300_VTG_MAX_UV,
1494		.hpm_load_uA = CY_TMA300_CURR_24HZ_UA,
1495		.lpm_load_uA = CY_TMA300_CURR_24HZ_UA,
1496	},
1497	{
1498		.name = "vcc_i2c",
1499		.min_uV = CY_I2C_VTG_MIN_UV,
1500		.max_uV = CY_I2C_VTG_MAX_UV,
1501		.hpm_load_uA = CY_I2C_CURR_UA,
1502		.lpm_load_uA = CY_I2C_CURR_UA,
1503	},
1504};
1505
1506static struct cyttsp_platform_data cyttsp_pdata = {
1507	.panel_maxx = 634,
1508	.panel_maxy = 1166,
1509	.disp_minx = 18,
1510	.disp_maxx = 617,
1511	.disp_miny = 18,
1512	.disp_maxy = 1041,
1513	.flags = 0x01,
1514	.gen = CY_GEN3,
1515	.use_st = CY_USE_ST,
1516	.use_mt = CY_USE_MT,
1517	.use_hndshk = CY_SEND_HNDSHK,
1518	.use_trk_id = CY_USE_TRACKING_ID,
1519	.use_sleep = CY_USE_DEEP_SLEEP_SEL,
1520	.use_gestures = CY_USE_GESTURES,
1521	.fw_fname = "cyttsp_8064_mtp.hex",
1522	/* change act_intrvl to customize the Active power state
1523	 * scanning/processing refresh interval for Operating mode
1524	 */
1525	.act_intrvl = CY_ACT_INTRVL_DFLT,
1526	/* change tch_tmout to customize the touch timeout for the
1527	 * Active power state for Operating mode
1528	 */
1529	.tch_tmout = CY_TCH_TMOUT_DFLT,
1530	/* change lp_intrvl to customize the Low Power power state
1531	 * scanning/processing refresh interval for Operating mode
1532	 */
1533	.lp_intrvl = CY_LP_INTRVL_DFLT,
1534	.sleep_gpio = CYTTSP_TS_GPIO_SLEEP,
1535	.resout_gpio = -1,
1536	.irq_gpio = CYTTSP_TS_GPIO_IRQ,
1537	.regulator_info = cyttsp_regulator_data,
1538	.num_regulators = ARRAY_SIZE(cyttsp_regulator_data),
1539	.init = cyttsp_platform_init,
1540	.correct_fw_ver = 17,
1541};
1542
1543static struct i2c_board_info cyttsp_info[] __initdata = {
1544	{
1545		I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
1546		.platform_data = &cyttsp_pdata,
1547		.irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
1548	},
1549};
1550
1551#define MSM_WCNSS_PHYS	0x03000000
1552#define MSM_WCNSS_SIZE	0x280000
1553
1554static struct resource resources_wcnss_wlan[] = {
1555	{
1556		.start	= RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
1557		.end	= RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
1558		.name	= "wcnss_wlanrx_irq",
1559		.flags	= IORESOURCE_IRQ,
1560	},
1561	{
1562		.start	= RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
1563		.end	= RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
1564		.name	= "wcnss_wlantx_irq",
1565		.flags	= IORESOURCE_IRQ,
1566	},
1567	{
1568		.start	= MSM_WCNSS_PHYS,
1569		.end	= MSM_WCNSS_PHYS + MSM_WCNSS_SIZE - 1,
1570		.name	= "wcnss_mmio",
1571		.flags	= IORESOURCE_MEM,
1572	},
1573	{
1574		.start	= 64,
1575		.end	= 68,
1576		.name	= "wcnss_gpios_5wire",
1577		.flags	= IORESOURCE_IO,
1578	},
1579};
1580
1581static struct qcom_wcnss_opts qcom_wcnss_pdata = {
1582	.has_48mhz_xo	= 1,
1583};
1584
1585static struct platform_device msm_device_wcnss_wlan = {
1586	.name		= "wcnss_wlan",
1587	.id		= 0,
1588	.num_resources	= ARRAY_SIZE(resources_wcnss_wlan),
1589	.resource	= resources_wcnss_wlan,
1590	.dev		= {.platform_data = &qcom_wcnss_pdata},
1591};
1592
1593static struct platform_device msm_device_iris_fm __devinitdata = {
1594	.name = "iris_fm",
1595	.id   = -1,
1596};
1597
1598#ifdef CONFIG_QSEECOM
1599/* qseecom bus scaling */
1600static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
1601	{
1602		.src = MSM_BUS_MASTER_ADM_PORT0,
1603		.dst = MSM_BUS_SLAVE_EBI_CH0,
1604		.ab = 0,
1605		.ib = 0,
1606	},
1607	{
1608		.src = MSM_BUS_MASTER_ADM_PORT1,
1609		.dst = MSM_BUS_SLAVE_GSBI1_UART,
1610		.ab = 0,
1611		.ib = 0,
1612	},
1613	{
1614		.src = MSM_BUS_MASTER_SPDM,
1615		.dst = MSM_BUS_SLAVE_SPDM,
1616		.ib = 0,
1617		.ab = 0,
1618	},
1619};
1620
1621static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
1622	{
1623		.src = MSM_BUS_MASTER_ADM_PORT0,
1624		.dst = MSM_BUS_SLAVE_EBI_CH0,
1625		.ab = 70000000UL,
1626		.ib = 70000000UL,
1627	},
1628	{
1629		.src = MSM_BUS_MASTER_ADM_PORT1,
1630		.dst = MSM_BUS_SLAVE_GSBI1_UART,
1631		.ab = 2480000000UL,
1632		.ib = 2480000000UL,
1633	},
1634	{
1635		.src = MSM_BUS_MASTER_SPDM,
1636		.dst = MSM_BUS_SLAVE_SPDM,
1637		.ib = 0,
1638		.ab = 0,
1639	},
1640};
1641
1642static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
1643	{
1644		.src = MSM_BUS_MASTER_ADM_PORT0,
1645		.dst = MSM_BUS_SLAVE_EBI_CH0,
1646		.ab = 0,
1647		.ib = 0,
1648	},
1649	{
1650		.src = MSM_BUS_MASTER_ADM_PORT1,
1651		.dst = MSM_BUS_SLAVE_GSBI1_UART,
1652		.ab = 0,
1653		.ib = 0,
1654	},
1655	{
1656		.src = MSM_BUS_MASTER_SPDM,
1657		.dst = MSM_BUS_SLAVE_SPDM,
1658		.ib = (64 * 8) * 1000000UL,
1659		.ab = (64 * 8) *  100000UL,
1660	},
1661};
1662
1663static struct msm_bus_vectors qseecom_enable_dfab_sfpb_vectors[] = {
1664	{
1665		.src = MSM_BUS_MASTER_ADM_PORT0,
1666		.dst = MSM_BUS_SLAVE_EBI_CH0,
1667		.ab = 70000000UL,
1668		.ib = 70000000UL,
1669	},
1670	{
1671		.src = MSM_BUS_MASTER_ADM_PORT1,
1672		.dst = MSM_BUS_SLAVE_GSBI1_UART,
1673		.ab = 2480000000UL,
1674		.ib = 2480000000UL,
1675	},
1676	{
1677		.src = MSM_BUS_MASTER_SPDM,
1678		.dst = MSM_BUS_SLAVE_SPDM,
1679		.ib = (64 * 8) * 1000000UL,
1680		.ab = (64 * 8) *  100000UL,
1681	},
1682};
1683
1684static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = {
1685	{
1686		ARRAY_SIZE(qseecom_clks_init_vectors),
1687		qseecom_clks_init_vectors,
1688	},
1689	{
1690		ARRAY_SIZE(qseecom_enable_dfab_vectors),
1691		qseecom_enable_dfab_vectors,
1692	},
1693	{
1694		ARRAY_SIZE(qseecom_enable_sfpb_vectors),
1695		qseecom_enable_sfpb_vectors,
1696	},
1697	{
1698		ARRAY_SIZE(qseecom_enable_dfab_sfpb_vectors),
1699		qseecom_enable_dfab_sfpb_vectors,
1700	},
1701};
1702
1703static struct msm_bus_scale_pdata qseecom_bus_pdata = {
1704	qseecom_hw_bus_scale_usecases,
1705	ARRAY_SIZE(qseecom_hw_bus_scale_usecases),
1706	.name = "qsee",
1707};
1708
1709static struct platform_device qseecom_device = {
1710	.name		= "qseecom",
1711	.id		= 0,
1712	.dev		= {
1713		.platform_data = &qseecom_bus_pdata,
1714	},
1715};
1716#endif
1717
1718#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
1719		defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
1720		defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
1721		defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
1722
1723#define QCE_SIZE		0x10000
1724#define QCE_0_BASE		0x11000000
1725
1726#define QCE_HW_KEY_SUPPORT	0
1727#define QCE_SHA_HMAC_SUPPORT	1
1728#define QCE_SHARE_CE_RESOURCE	3
1729#define QCE_CE_SHARED		0
1730
1731static struct resource qcrypto_resources[] = {
1732	[0] = {
1733		.start = QCE_0_BASE,
1734		.end = QCE_0_BASE + QCE_SIZE - 1,
1735		.flags = IORESOURCE_MEM,
1736	},
1737	[1] = {
1738		.name = "crypto_channels",
1739		.start = DMOV8064_CE_IN_CHAN,
1740		.end = DMOV8064_CE_OUT_CHAN,
1741		.flags = IORESOURCE_DMA,
1742	},
1743	[2] = {
1744		.name = "crypto_crci_in",
1745		.start = DMOV8064_CE_IN_CRCI,
1746		.end = DMOV8064_CE_IN_CRCI,
1747		.flags = IORESOURCE_DMA,
1748	},
1749	[3] = {
1750		.name = "crypto_crci_out",
1751		.start = DMOV8064_CE_OUT_CRCI,
1752		.end = DMOV8064_CE_OUT_CRCI,
1753		.flags = IORESOURCE_DMA,
1754	},
1755};
1756
1757static struct resource qcedev_resources[] = {
1758	[0] = {
1759		.start = QCE_0_BASE,
1760		.end = QCE_0_BASE + QCE_SIZE - 1,
1761		.flags = IORESOURCE_MEM,
1762	},
1763	[1] = {
1764		.name = "crypto_channels",
1765		.start = DMOV8064_CE_IN_CHAN,
1766		.end = DMOV8064_CE_OUT_CHAN,
1767		.flags = IORESOURCE_DMA,
1768	},
1769	[2] = {
1770		.name = "crypto_crci_in",
1771		.start = DMOV8064_CE_IN_CRCI,
1772		.end = DMOV8064_CE_IN_CRCI,
1773		.flags = IORESOURCE_DMA,
1774	},
1775	[3] = {
1776		.name = "crypto_crci_out",
1777		.start = DMOV8064_CE_OUT_CRCI,
1778		.end = DMOV8064_CE_OUT_CRCI,
1779		.flags = IORESOURCE_DMA,
1780	},
1781};
1782
1783#endif
1784
1785#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
1786		defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
1787
1788static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
1789	.ce_shared = QCE_CE_SHARED,
1790	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
1791	.hw_key_support = QCE_HW_KEY_SUPPORT,
1792	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
1793	.bus_scale_table = NULL,
1794};
1795
1796static struct platform_device qcrypto_device = {
1797	.name		= "qcrypto",
1798	.id		= 0,
1799	.num_resources	= ARRAY_SIZE(qcrypto_resources),
1800	.resource	= qcrypto_resources,
1801	.dev		= {
1802		.coherent_dma_mask = DMA_BIT_MASK(32),
1803		.platform_data = &qcrypto_ce_hw_suppport,
1804	},
1805};
1806#endif
1807
1808#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
1809		defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
1810
1811static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
1812	.ce_shared = QCE_CE_SHARED,
1813	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
1814	.hw_key_support = QCE_HW_KEY_SUPPORT,
1815	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
1816	.bus_scale_table = NULL,
1817};
1818
1819static struct platform_device qcedev_device = {
1820	.name		= "qce",
1821	.id		= 0,
1822	.num_resources	= ARRAY_SIZE(qcedev_resources),
1823	.resource	= qcedev_resources,
1824	.dev		= {
1825		.coherent_dma_mask = DMA_BIT_MASK(32),
1826		.platform_data = &qcedev_ce_hw_suppport,
1827	},
1828};
1829#endif
1830
1831static struct mdm_vddmin_resource mdm_vddmin_rscs = {
1832	.rpm_id = MSM_RPM_ID_VDDMIN_GPIO,
1833	.ap2mdm_vddmin_gpio = 30,
1834	.modes  = 0x03,
1835	.drive_strength = 8,
1836	.mdm2ap_vddmin_gpio = 80,
1837};
1838
1839static struct gpiomux_setting mdm2ap_status_gpio_run_cfg = {
1840	.func = GPIOMUX_FUNC_GPIO,
1841	.drv = GPIOMUX_DRV_8MA,
1842	.pull = GPIOMUX_PULL_NONE,
1843};
1844
1845static struct mdm_platform_data mdm_platform_data = {
1846	.mdm_version = "3.0",
1847	.ramdump_delay_ms = 2000,
1848	.early_power_on = 1,
1849	.sfr_query = 1,
1850	.vddmin_resource = &mdm_vddmin_rscs,
1851	.peripheral_platform_device = &apq8064_device_hsic_host,
1852	.ramdump_timeout_ms = 120000,
1853	.mdm2ap_status_gpio_run_cfg = &mdm2ap_status_gpio_run_cfg,
1854	.sysmon_subsys_id_valid = 1,
1855	.sysmon_subsys_id = SYSMON_SS_EXT_MODEM,
1856};
1857
1858static struct mdm_platform_data amdm_platform_data = {
1859	.mdm_version = "3.0",
1860	.ramdump_delay_ms = 2000,
1861	.early_power_on = 1,
1862	.sfr_query = 1,
1863	.send_shdn = 1,
1864	.vddmin_resource = &mdm_vddmin_rscs,
1865	.peripheral_platform_device = &apq8064_device_hsic_host,
1866	.ramdump_timeout_ms = 120000,
1867	.mdm2ap_status_gpio_run_cfg = &mdm2ap_status_gpio_run_cfg,
1868	.sysmon_subsys_id_valid = 1,
1869	.sysmon_subsys_id = SYSMON_SS_EXT_MODEM,
1870	.no_a2m_errfatal_on_ssr = 1,
1871};
1872
1873static struct mdm_vddmin_resource bmdm_vddmin_rscs = {
1874	.rpm_id = MSM_RPM_ID_VDDMIN_GPIO,
1875	.ap2mdm_vddmin_gpio = 30,
1876	.modes  = 0x03,
1877	.drive_strength = 8,
1878	.mdm2ap_vddmin_gpio = 64,
1879};
1880
1881static struct mdm_platform_data bmdm_platform_data = {
1882	.mdm_version = "3.0",
1883	.ramdump_delay_ms = 2000,
1884	.sfr_query = 1,
1885	.send_shdn = 1,
1886	.vddmin_resource = &bmdm_vddmin_rscs,
1887	.peripheral_platform_device = &apq8064_device_ehci_host3,
1888	.ramdump_timeout_ms = 120000,
1889	.mdm2ap_status_gpio_run_cfg = &mdm2ap_status_gpio_run_cfg,
1890	.sysmon_subsys_id_valid = 1,
1891	.sysmon_subsys_id = SYSMON_SS_EXT_MODEM2,
1892	.no_a2m_errfatal_on_ssr = 1,
1893};
1894
1895static struct tsens_platform_data apq_tsens_pdata  = {
1896		.tsens_factor		= 1000,
1897		.hw_type		= APQ_8064,
1898		.tsens_num_sensor	= 11,
1899		.slope = {1176, 1176, 1154, 1176, 1111,
1900			1132, 1132, 1199, 1132, 1199, 1132},
1901};
1902
1903static struct platform_device msm_tsens_device = {
1904	.name   = "tsens8960-tm",
1905	.id = -1,
1906};
1907
1908static struct msm_thermal_data msm_thermal_pdata = {
1909	.sensor_id = 7,
1910	.poll_ms = 250,
1911	.limit_temp_degC = 60,
1912	.temp_hysteresis_degC = 10,
1913	.freq_step = 2,
1914};
1915
1916#define MSM_SHARED_RAM_PHYS 0x80000000
1917static void __init apq8064_map_io(void)
1918{
1919	msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
1920	msm_map_apq8064_io();
1921	if (socinfo_init() < 0)
1922		pr_err("socinfo_init() failed!\n");
1923}
1924
1925static void __init apq8064_init_irq(void)
1926{
1927	struct msm_mpm_device_data *data = NULL;
1928
1929#ifdef CONFIG_MSM_MPM
1930	data = &apq8064_mpm_dev_data;
1931#endif
1932
1933	msm_mpm_irq_extn_init(data);
1934	gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
1935						(void *)MSM_QGIC_CPU_BASE);
1936}
1937
1938static struct platform_device msm8064_device_saw_regulator_core0 = {
1939	.name	= "saw-regulator",
1940	.id	= 0,
1941	.dev	= {
1942		.platform_data = &msm8064_saw_regulator_pdata_8921_s5,
1943	},
1944};
1945
1946static struct platform_device msm8064_device_saw_regulator_core1 = {
1947	.name	= "saw-regulator",
1948	.id	= 1,
1949	.dev	= {
1950		.platform_data = &msm8064_saw_regulator_pdata_8921_s6,
1951	},
1952};
1953
1954static struct platform_device msm8064_device_saw_regulator_core2 = {
1955	.name	= "saw-regulator",
1956	.id	= 2,
1957	.dev	= {
1958		.platform_data = &msm8064_saw_regulator_pdata_8821_s0,
1959	},
1960};
1961
1962static struct platform_device msm8064_device_saw_regulator_core3 = {
1963	.name	= "saw-regulator",
1964	.id	= 3,
1965	.dev	= {
1966		.platform_data = &msm8064_saw_regulator_pdata_8821_s1,
1967
1968	},
1969};
1970
1971static struct msm_rpmrs_level msm_rpmrs_levels[] = {
1972	{
1973		MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
1974		MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
1975		true,
1976		1, 784, 180000, 100,
1977	},
1978
1979	{
1980		MSM_PM_SLEEP_MODE_RETENTION,
1981		MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
1982		true,
1983		415, 715, 340827, 475,
1984	},
1985
1986	{
1987		MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
1988		MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
1989		true,
1990		1300, 228, 1200000, 2000,
1991	},
1992
1993	{
1994		MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
1995		MSM_RPMRS_LIMITS(ON, GDHS, MAX, ACTIVE),
1996		false,
1997		2000, 138, 1208400, 3200,
1998	},
1999
2000	{
2001		MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
2002		MSM_RPMRS_LIMITS(ON, HSFS_OPEN, ACTIVE, RET_HIGH),
2003		false,
2004		6000, 119, 1850300, 9000,
2005	},
2006
2007	{
2008		MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
2009		MSM_RPMRS_LIMITS(OFF, GDHS, MAX, ACTIVE),
2010		false,
2011		9200, 68, 2839200, 16400,
2012	},
2013
2014	{
2015		MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
2016		MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
2017		false,
2018		10300, 63, 3128000, 18200,
2019	},
2020
2021	{
2022		MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
2023		MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
2024		false,
2025		18000, 10, 4602600, 27000,
2026	},
2027
2028	{
2029		MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
2030		MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
2031		false,
2032		20000, 2, 5752000, 32000,
2033	},
2034};
2035
2036static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
2037	.mode = MSM_PM_BOOT_CONFIG_TZ,
2038};
2039
2040static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
2041	.levels = &msm_rpmrs_levels[0],
2042	.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
2043	.vdd_mem_levels  = {
2044		[MSM_RPMRS_VDD_MEM_RET_LOW]	= 750000,
2045		[MSM_RPMRS_VDD_MEM_RET_HIGH]	= 750000,
2046		[MSM_RPMRS_VDD_MEM_ACTIVE]	= 1050000,
2047		[MSM_RPMRS_VDD_MEM_MAX]		= 1150000,
2048	},
2049	.vdd_dig_levels = {
2050		[MSM_RPMRS_VDD_DIG_RET_LOW]	= 500000,
2051		[MSM_RPMRS_VDD_DIG_RET_HIGH]	= 750000,
2052		[MSM_RPMRS_VDD_DIG_ACTIVE]	= 950000,
2053		[MSM_RPMRS_VDD_DIG_MAX]		= 1150000,
2054	},
2055	.vdd_mask = 0x7FFFFF,
2056	.rpmrs_target_id = {
2057		[MSM_RPMRS_ID_PXO_CLK]		= MSM_RPM_ID_PXO_CLK,
2058		[MSM_RPMRS_ID_L2_CACHE_CTL]	= MSM_RPM_ID_LAST,
2059		[MSM_RPMRS_ID_VDD_DIG_0]	= MSM_RPM_ID_PM8921_S3_0,
2060		[MSM_RPMRS_ID_VDD_DIG_1]	= MSM_RPM_ID_PM8921_S3_1,
2061		[MSM_RPMRS_ID_VDD_MEM_0]	= MSM_RPM_ID_PM8921_L24_0,
2062		[MSM_RPMRS_ID_VDD_MEM_1]	= MSM_RPM_ID_PM8921_L24_1,
2063		[MSM_RPMRS_ID_RPM_CTL]		= MSM_RPM_ID_RPM_CTL,
2064	},
2065};
2066
2067static uint8_t spm_wfi_cmd_sequence[] __initdata = {
2068	0x03, 0x0f,
2069};
2070
2071static uint8_t spm_power_collapse_without_rpm[] __initdata = {
2072	0x00, 0x24, 0x54, 0x10,
2073	0x09, 0x03, 0x01,
2074	0x10, 0x54, 0x30, 0x0C,
2075	0x24, 0x30, 0x0f,
2076};
2077
2078static uint8_t spm_retention_cmd_sequence[] __initdata = {
2079	0x00, 0x05, 0x03, 0x0D,
2080	0x0B, 0x00, 0x0f,
2081};
2082
2083static uint8_t spm_power_collapse_with_rpm[] __initdata = {
2084	0x00, 0x24, 0x54, 0x10,
2085	0x09, 0x07, 0x01, 0x0B,
2086	0x10, 0x54, 0x30, 0x0C,
2087	0x24, 0x30, 0x0f,
2088};
2089
2090/* 8064AB has a different command to assert apc_pdn */
2091static uint8_t spm_power_collapse_without_rpm_krait_v3[] __initdata = {
2092	0x00, 0x24, 0x84, 0x10,
2093	0x09, 0x03, 0x01,
2094	0x10, 0x84, 0x30, 0x0C,
2095	0x24, 0x30, 0x0f,
2096};
2097
2098static uint8_t spm_power_collapse_with_rpm_krait_v3[] __initdata = {
2099	0x00, 0x24, 0x84, 0x10,
2100	0x09, 0x07, 0x01, 0x0B,
2101	0x10, 0x84, 0x30, 0x0C,
2102	0x24, 0x30, 0x0f,
2103};
2104
2105static struct msm_spm_seq_entry msm_spm_boot_cpu_seq_list[] __initdata = {
2106	[0] = {
2107		.mode = MSM_SPM_MODE_CLOCK_GATING,
2108		.notify_rpm = false,
2109		.cmd = spm_wfi_cmd_sequence,
2110	},
2111	[1] = {
2112		.mode = MSM_SPM_MODE_POWER_RETENTION,
2113		.notify_rpm = false,
2114		.cmd = spm_retention_cmd_sequence,
2115	},
2116	[2] = {
2117		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
2118		.notify_rpm = false,
2119		.cmd = spm_power_collapse_without_rpm,
2120	},
2121	[3] = {
2122		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
2123		.notify_rpm = true,
2124		.cmd = spm_power_collapse_with_rpm,
2125	},
2126};
2127static struct msm_spm_seq_entry msm_spm_nonboot_cpu_seq_list[] __initdata = {
2128	[0] = {
2129		.mode = MSM_SPM_MODE_CLOCK_GATING,
2130		.notify_rpm = false,
2131		.cmd = spm_wfi_cmd_sequence,
2132	},
2133	[1] = {
2134		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
2135		.notify_rpm = false,
2136		.cmd = spm_power_collapse_without_rpm,
2137	},
2138	[2] = {
2139		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
2140		.notify_rpm = true,
2141		.cmd = spm_power_collapse_with_rpm,
2142	},
2143};
2144
2145static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
2146	0x00, 0x20, 0x03, 0x20,
2147	0x00, 0x0f,
2148};
2149
2150static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
2151	0x00, 0x20, 0x34, 0x64,
2152	0x48, 0x07, 0x48, 0x20,
2153	0x50, 0x64, 0x04, 0x34,
2154	0x50, 0x0f,
2155};
2156static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
2157	0x00, 0x10, 0x34, 0x64,
2158	0x48, 0x07, 0x48, 0x10,
2159	0x50, 0x64, 0x04, 0x34,
2160	0x50, 0x0F,
2161};
2162
2163static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
2164	[0] = {
2165		.mode = MSM_SPM_L2_MODE_RETENTION,
2166		.notify_rpm = false,
2167		.cmd = l2_spm_wfi_cmd_sequence,
2168	},
2169	[1] = {
2170		.mode = MSM_SPM_L2_MODE_GDHS,
2171		.notify_rpm = true,
2172		.cmd = l2_spm_gdhs_cmd_sequence,
2173	},
2174	[2] = {
2175		.mode = MSM_SPM_L2_MODE_POWER_COLLAPSE,
2176		.notify_rpm = true,
2177		.cmd = l2_spm_power_off_cmd_sequence,
2178	},
2179};
2180
2181
2182static struct msm_spm_platform_data msm_spm_l2_data[] __initdata = {
2183	[0] = {
2184		.reg_base_addr = MSM_SAW_L2_BASE,
2185		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x00,
2186		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
2187		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x00A000AE,
2188		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A00020,
2189		.modes = msm_spm_l2_seq_list,
2190		.num_modes = ARRAY_SIZE(msm_spm_l2_seq_list),
2191	},
2192};
2193
2194static struct msm_spm_platform_data msm_spm_data[] __initdata = {
2195	[0] = {
2196		.reg_base_addr = MSM_SAW0_BASE,
2197		.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
2198#if defined(CONFIG_MSM_AVS_HW)
2199		.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
2200		.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
2201#endif
2202		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
2203		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x03020004,
2204		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0084009C,
2205		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A4001C,
2206		.vctl_timeout_us = 50,
2207		.num_modes = ARRAY_SIZE(msm_spm_boot_cpu_seq_list),
2208		.modes = msm_spm_boot_cpu_seq_list,
2209	},
2210	[1] = {
2211		.reg_base_addr = MSM_SAW1_BASE,
2212		.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
2213#if defined(CONFIG_MSM_AVS_HW)
2214		.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
2215		.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
2216#endif
2217		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
2218		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
2219		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
2220		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
2221		.vctl_timeout_us = 50,
2222		.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
2223		.modes = msm_spm_nonboot_cpu_seq_list,
2224	},
2225	[2] = {
2226		.reg_base_addr = MSM_SAW2_BASE,
2227		.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
2228#if defined(CONFIG_MSM_AVS_HW)
2229		.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
2230		.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
2231#endif
2232		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
2233		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
2234		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
2235		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
2236		.vctl_timeout_us = 50,
2237		.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
2238		.modes = msm_spm_nonboot_cpu_seq_list,
2239	},
2240	[3] = {
2241		.reg_base_addr = MSM_SAW3_BASE,
2242		.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
2243#if defined(CONFIG_MSM_AVS_HW)
2244		.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
2245		.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
2246#endif
2247		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
2248		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
2249		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
2250		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
2251		.vctl_timeout_us = 50,
2252		.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
2253		.modes = msm_spm_nonboot_cpu_seq_list,
2254	},
2255};
2256
2257static void __init apq8064ab_update_krait_spm(void)
2258{
2259	int i;
2260
2261	/* Update the SPM sequences for SPC and PC */
2262	for (i = 0; i < ARRAY_SIZE(msm_spm_data); i++) {
2263		int j;
2264		struct msm_spm_platform_data *pdata = &msm_spm_data[i];
2265		for (j = 0; j < pdata->num_modes; j++) {
2266			if (pdata->modes[j].cmd ==
2267					spm_power_collapse_without_rpm)
2268				pdata->modes[j].cmd =
2269				spm_power_collapse_without_rpm_krait_v3;
2270			else if (pdata->modes[j].cmd ==
2271					spm_power_collapse_with_rpm)
2272				pdata->modes[j].cmd =
2273				spm_power_collapse_with_rpm_krait_v3;
2274		}
2275	}
2276}
2277
2278static void __init apq8064_init_buses(void)
2279{
2280	msm_bus_rpm_set_mt_mask();
2281	msm_bus_8064_apps_fabric_pdata.rpm_enabled = 1;
2282	msm_bus_8064_sys_fabric_pdata.rpm_enabled = 1;
2283	msm_bus_8064_mm_fabric_pdata.rpm_enabled = 1;
2284	msm_bus_8064_apps_fabric.dev.platform_data =
2285		&msm_bus_8064_apps_fabric_pdata;
2286	msm_bus_8064_sys_fabric.dev.platform_data =
2287		&msm_bus_8064_sys_fabric_pdata;
2288	msm_bus_8064_mm_fabric.dev.platform_data =
2289		&msm_bus_8064_mm_fabric_pdata;
2290	msm_bus_8064_sys_fpb.dev.platform_data = &msm_bus_8064_sys_fpb_pdata;
2291	msm_bus_8064_cpss_fpb.dev.platform_data = &msm_bus_8064_cpss_fpb_pdata;
2292}
2293
2294/* PCIe gpios */
2295static struct msm_pcie_gpio_info_t msm_pcie_gpio_info[MSM_PCIE_MAX_GPIO] = {
2296	{"rst_n", PM8921_MPP_PM_TO_SYS(PCIE_RST_N_PMIC_MPP), 0},
2297	{"pwr_en", PM8921_GPIO_PM_TO_SYS(PCIE_PWR_EN_PMIC_GPIO), 1},
2298};
2299
2300static struct msm_pcie_platform msm_pcie_platform_data = {
2301	.gpio = msm_pcie_gpio_info,
2302	.axi_addr = PCIE_AXI_BAR_PHYS,
2303	.axi_size = PCIE_AXI_BAR_SIZE,
2304	.wake_n = PM8921_GPIO_IRQ(PM8921_IRQ_BASE, PCIE_WAKE_N_PMIC_GPIO),
2305};
2306
2307static int __init mpq8064_pcie_enabled(void)
2308{
2309	return !((readl_relaxed(QFPROM_RAW_FEAT_CONFIG_ROW0_MSB) & BIT(21)) ||
2310		(readl_relaxed(QFPROM_RAW_OEM_CONFIG_ROW0_LSB) & BIT(4)));
2311}
2312
2313static void __init mpq8064_pcie_init(void)
2314{
2315	if (mpq8064_pcie_enabled()) {
2316		msm_device_pcie.dev.platform_data = &msm_pcie_platform_data;
2317		platform_device_register(&msm_device_pcie);
2318	}
2319}
2320
2321static struct platform_device apq8064_device_ext_5v_vreg __devinitdata = {
2322	.name	= GPIO_REGULATOR_DEV_NAME,
2323	.id	= PM8921_MPP_PM_TO_SYS(7),
2324	.dev	= {
2325		.platform_data
2326			= &apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_5V],
2327	},
2328};
2329
2330static struct platform_device apq8064_device_ext_mpp8_vreg __devinitdata = {
2331	.name	= GPIO_REGULATOR_DEV_NAME,
2332	.id	= PM8921_MPP_PM_TO_SYS(8),
2333	.dev	= {
2334		.platform_data
2335			= &apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_MPP8],
2336	},
2337};
2338
2339static struct platform_device apq8064_device_ext_3p3v_vreg __devinitdata = {
2340	.name	= GPIO_REGULATOR_DEV_NAME,
2341	.id	= APQ8064_EXT_3P3V_REG_EN_GPIO,
2342	.dev	= {
2343		.platform_data =
2344			&apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_3P3V],
2345	},
2346};
2347
2348static struct platform_device apq8064_device_ext_ts_sw_vreg __devinitdata = {
2349	.name	= GPIO_REGULATOR_DEV_NAME,
2350	.id	= PM8921_GPIO_PM_TO_SYS(23),
2351	.dev	= {
2352		.platform_data
2353			= &apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_TS_SW],
2354	},
2355};
2356
2357static struct platform_device apq8064_device_rpm_regulator __devinitdata = {
2358	.name	= "rpm-regulator",
2359	.id	= 0,
2360	.dev	= {
2361		.platform_data = &apq8064_rpm_regulator_pdata,
2362	},
2363};
2364
2365static struct platform_device
2366apq8064_pm8921_device_rpm_regulator __devinitdata = {
2367	.name	= "rpm-regulator",
2368	.id	= 1,
2369	.dev	= {
2370		.platform_data = &apq8064_rpm_regulator_pm8921_pdata,
2371	},
2372};
2373
2374static struct gpio_ir_recv_platform_data gpio_ir_recv_pdata = {
2375	.gpio_nr = 88,
2376	.active_low = 1,
2377};
2378
2379static struct platform_device gpio_ir_recv_pdev = {
2380	.name = "gpio-rc-recv",
2381	.dev = {
2382		.platform_data = &gpio_ir_recv_pdata,
2383	},
2384};
2385
2386static struct platform_device *common_not_mpq_devices[] __initdata = {
2387	&apq8064_device_qup_i2c_gsbi1,
2388	&apq8064_device_qup_i2c_gsbi3,
2389	&apq8064_device_qup_i2c_gsbi4,
2390};
2391
2392static struct platform_device *early_common_devices[] __initdata = {
2393	&apq8064_device_acpuclk,
2394	&apq8064_device_dmov,
2395	&apq8064_device_qup_spi_gsbi5,
2396};
2397
2398static struct platform_device *pm8921_common_devices[] __initdata = {
2399	&apq8064_device_ext_5v_vreg,
2400	&apq8064_device_ext_mpp8_vreg,
2401	&apq8064_device_ext_3p3v_vreg,
2402	&apq8064_device_ssbi_pmic1,
2403	&apq8064_device_ssbi_pmic2,
2404	&apq8064_device_ext_ts_sw_vreg,
2405};
2406
2407static struct platform_device *pm8917_common_devices[] __initdata = {
2408	&apq8064_device_ext_mpp8_vreg,
2409	&apq8064_device_ext_3p3v_vreg,
2410	&apq8064_device_ssbi_pmic1,
2411	&apq8064_device_ssbi_pmic2,
2412	&apq8064_device_ext_ts_sw_vreg,
2413};
2414
2415static struct platform_device *common_devices[] __initdata = {
2416	&msm_device_smd_apq8064,
2417	&apq8064_device_otg,
2418	&apq8064_device_gadget_peripheral,
2419	&apq8064_device_hsusb_host,
2420	&android_usb_device,
2421	&msm_device_wcnss_wlan,
2422	&msm_device_iris_fm,
2423	&apq8064_fmem_device,
2424#ifdef CONFIG_ANDROID_PMEM
2425#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
2426	&apq8064_android_pmem_device,
2427	&apq8064_android_pmem_adsp_device,
2428	&apq8064_android_pmem_audio_device,
2429#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
2430#endif /*CONFIG_ANDROID_PMEM*/
2431#ifdef CONFIG_ION_MSM
2432	&apq8064_ion_dev,
2433#endif
2434	&msm8064_device_watchdog,
2435	&msm8064_device_saw_regulator_core0,
2436	&msm8064_device_saw_regulator_core1,
2437	&msm8064_device_saw_regulator_core2,
2438	&msm8064_device_saw_regulator_core3,
2439#if defined(CONFIG_QSEECOM)
2440	&qseecom_device,
2441#endif
2442
2443	&msm_8064_device_tsif[0],
2444	&msm_8064_device_tsif[1],
2445
2446#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
2447		defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
2448	&qcrypto_device,
2449#endif
2450
2451#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
2452		defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
2453	&qcedev_device,
2454#endif
2455
2456#ifdef CONFIG_HW_RANDOM_MSM
2457	&apq8064_device_rng,
2458#endif
2459	&apq_pcm,
2460	&apq_pcm_routing,
2461	&apq_cpudai0,
2462	&apq_cpudai1,
2463	&mpq_cpudai_sec_i2s_rx,
2464	&mpq_cpudai_mi2s_tx,
2465	&apq_cpudai_hdmi_rx,
2466	&apq_cpudai_bt_rx,
2467	&apq_cpudai_bt_tx,
2468	&apq_cpudai_fm_rx,
2469	&apq_cpudai_fm_tx,
2470	&apq_cpu_fe,
2471	&apq_stub_codec,
2472	&apq_voice,
2473	&apq_voip,
2474	&apq_lpa_pcm,
2475	&apq_compr_dsp,
2476	&apq_multi_ch_pcm,
2477	&apq_lowlatency_pcm,
2478	&apq_pcm_hostless,
2479	&apq_cpudai_afe_01_rx,
2480	&apq_cpudai_afe_01_tx,
2481	&apq_cpudai_afe_02_rx,
2482	&apq_cpudai_afe_02_tx,
2483	&apq_pcm_afe,
2484	&apq_cpudai_auxpcm_rx,
2485	&apq_cpudai_auxpcm_tx,
2486	&apq_cpudai_stub,
2487	&apq_cpudai_slimbus_1_rx,
2488	&apq_cpudai_slimbus_1_tx,
2489	&apq_cpudai_slimbus_2_rx,
2490	&apq_cpudai_slimbus_2_tx,
2491	&apq_cpudai_slimbus_3_rx,
2492	&apq_cpudai_slimbus_3_tx,
2493	&apq8064_rpm_device,
2494	&apq8064_rpm_log_device,
2495	&apq8064_rpm_stat_device,
2496	&apq8064_rpm_master_stat_device,
2497	&apq_device_tz_log,
2498	&msm_bus_8064_apps_fabric,
2499	&msm_bus_8064_sys_fabric,
2500	&msm_bus_8064_mm_fabric,
2501	&msm_bus_8064_sys_fpb,
2502	&msm_bus_8064_cpss_fpb,
2503	&apq8064_msm_device_vidc,
2504	&msm_pil_dsps,
2505	&msm_8960_q6_lpass,
2506	&msm_pil_vidc,
2507	&msm_gss,
2508	&apq8064_rtb_device,
2509	&apq8064_dcvs_device,
2510	&apq8064_msm_gov_device,
2511	&apq8064_device_cache_erp,
2512	&msm8960_device_ebi1_ch0_erp,
2513	&msm8960_device_ebi1_ch1_erp,
2514	&epm_adc_device,
2515	&coresight_tpiu_device,
2516	&coresight_etb_device,
2517	&apq8064_coresight_funnel_device,
2518	&coresight_etm0_device,
2519	&coresight_etm1_device,
2520	&coresight_etm2_device,
2521	&coresight_etm3_device,
2522	&apq_cpudai_slim_4_rx,
2523	&apq_cpudai_slim_4_tx,
2524#ifdef CONFIG_MSM_GEMINI
2525	&msm8960_gemini_device,
2526#endif
2527	&apq8064_iommu_domain_device,
2528	&msm_tsens_device,
2529	&apq8064_cache_dump_device,
2530	&msm_8064_device_tspp,
2531#ifdef CONFIG_BATTERY_BCL
2532	&battery_bcl_device,
2533#endif
2534	&apq8064_msm_mpd_device,
2535};
2536
2537static struct platform_device *cdp_devices[] __initdata = {
2538	&apq8064_device_uart_gsbi1,
2539	&apq8064_device_uart_gsbi7,
2540	&msm_device_sps_apq8064,
2541#ifdef CONFIG_MSM_ROTATOR
2542	&msm_rotator_device,
2543#endif
2544	&msm8064_pc_cntr,
2545};
2546
2547static struct platform_device
2548mpq8064_device_ext_1p2_buck_vreg __devinitdata = {
2549	.name	= GPIO_REGULATOR_DEV_NAME,
2550	.id	= SX150X_GPIO(4, 2),
2551	.dev	= {
2552		.platform_data =
2553		 &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_1P2V],
2554	},
2555};
2556
2557static struct platform_device
2558mpq8064_device_ext_1p8_buck_vreg __devinitdata = {
2559	.name	= GPIO_REGULATOR_DEV_NAME,
2560	.id	= SX150X_GPIO(4, 4),
2561	.dev	= {
2562		.platform_data =
2563		&mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_1P8V],
2564	},
2565};
2566
2567static struct platform_device
2568mpq8064_device_ext_2p2_buck_vreg __devinitdata = {
2569	.name	= GPIO_REGULATOR_DEV_NAME,
2570	.id	= SX150X_GPIO(4, 14),
2571	.dev	= {
2572		.platform_data =
2573		&mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_2P2V],
2574	},
2575};
2576
2577static struct platform_device
2578mpq8064_device_ext_5v_buck_vreg __devinitdata = {
2579	.name	= GPIO_REGULATOR_DEV_NAME,
2580	.id	= SX150X_GPIO(4, 3),
2581	.dev	= {
2582		.platform_data =
2583		 &mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_5V],
2584	},
2585};
2586
2587static struct platform_device
2588mpq8064_device_ext_3p3v_ldo_vreg __devinitdata = {
2589	.name	= GPIO_REGULATOR_DEV_NAME,
2590	.id	= SX150X_GPIO(4, 15),
2591	.dev	= {
2592		.platform_data =
2593		&mpq8064_gpio_regulator_pdata[GPIO_VREG_ID_AVC_3P3V],
2594	},
2595};
2596
2597static struct platform_device rc_input_loopback_pdev = {
2598	.name	= "rc-user-input",
2599	.id	= -1,
2600};
2601
2602static int rf4ce_gpio_init(void)
2603{
2604	if (!machine_is_mpq8064_cdp() &&
2605		!machine_is_mpq8064_hrd() &&
2606			!machine_is_mpq8064_dtv())
2607		return -EINVAL;
2608
2609	/* CC2533 SRDY Input */
2610	if (!gpio_request(SX150X_GPIO(4, 6), "rf4ce_srdy")) {
2611		gpio_direction_input(SX150X_GPIO(4, 6));
2612		gpio_export(SX150X_GPIO(4, 6), true);
2613	}
2614
2615	/* CC2533 MRDY Output */
2616	if (!gpio_request(SX150X_GPIO(4, 5), "rf4ce_mrdy")) {
2617		gpio_direction_output(SX150X_GPIO(4, 5), 1);
2618		gpio_export(SX150X_GPIO(4, 5), true);
2619	}
2620
2621	/* CC2533 Reset Output */
2622	if (!gpio_request(SX150X_GPIO(4, 7), "rf4ce_reset")) {
2623		gpio_direction_output(SX150X_GPIO(4, 7), 0);
2624		gpio_export(SX150X_GPIO(4, 7), true);
2625	}
2626
2627	return 0;
2628}
2629late_initcall(rf4ce_gpio_init);
2630
2631static struct platform_device *mpq_devices[] __initdata = {
2632	&msm_device_sps_apq8064,
2633	&mpq8064_device_qup_i2c_gsbi5,
2634#ifdef CONFIG_MSM_ROTATOR
2635	&msm_rotator_device,
2636#endif
2637	&gpio_ir_recv_pdev,
2638	&mpq8064_device_ext_1p2_buck_vreg,
2639	&mpq8064_device_ext_1p8_buck_vreg,
2640	&mpq8064_device_ext_2p2_buck_vreg,
2641	&mpq8064_device_ext_5v_buck_vreg,
2642	&mpq8064_device_ext_3p3v_ldo_vreg,
2643#ifdef CONFIG_MSM_VCAP
2644	&msm8064_device_vcap,
2645#endif
2646	&rc_input_loopback_pdev,
2647};
2648
2649static struct msm_spi_platform_data apq8064_qup_spi_gsbi5_pdata = {
2650	.max_clock_speed = 1100000,
2651};
2652
2653#define KS8851_IRQ_GPIO		43
2654
2655static struct spi_board_info spi_board_info[] __initdata = {
2656	{
2657		.modalias               = "ks8851",
2658		.irq                    = MSM_GPIO_TO_INT(KS8851_IRQ_GPIO),
2659		.max_speed_hz           = 19200000,
2660		.bus_num                = 0,
2661		.chip_select            = 2,
2662		.mode                   = SPI_MODE_0,
2663	},
2664	{
2665		.modalias		= "epm_adc",
2666		.max_speed_hz		= 1100000,
2667		.bus_num		= 0,
2668		.chip_select		= 3,
2669		.mode			= SPI_MODE_0,
2670	},
2671};
2672
2673static struct slim_boardinfo apq8064_slim_devices[] = {
2674	{
2675		.bus_num = 1,
2676		.slim_slave = &apq8064_slim_tabla,
2677	},
2678	{
2679		.bus_num = 1,
2680		.slim_slave = &apq8064_slim_tabla20,
2681	},
2682	/* add more slimbus slaves as needed */
2683};
2684
2685static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi1_pdata = {
2686	.clk_freq = 100000,
2687	.src_clk_rate = 24000000,
2688};
2689
2690static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi3_pdata = {
2691	.clk_freq = 384000,
2692	.src_clk_rate = 24000000,
2693};
2694
2695static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi4_pdata = {
2696	.clk_freq = 100000,
2697	.src_clk_rate = 24000000,
2698};
2699
2700static struct msm_i2c_platform_data mpq8064_i2c_qup_gsbi5_pdata = {
2701	.clk_freq = 100000,
2702	.src_clk_rate = 24000000,
2703};
2704
2705#define GSBI_DUAL_MODE_CODE 0x60
2706#define MSM_GSBI1_PHYS		0x12440000
2707static void __init apq8064_i2c_init(void)
2708{
2709	void __iomem *gsbi_mem;
2710
2711	apq8064_device_qup_i2c_gsbi1.dev.platform_data =
2712					&apq8064_i2c_qup_gsbi1_pdata;
2713	gsbi_mem = ioremap_nocache(MSM_GSBI1_PHYS, 4);
2714	writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem);
2715	/* Ensure protocol code is written before proceeding */
2716	wmb();
2717	iounmap(gsbi_mem);
2718	apq8064_i2c_qup_gsbi1_pdata.use_gsbi_shared_mode = 1;
2719	apq8064_device_qup_i2c_gsbi3.dev.platform_data =
2720					&apq8064_i2c_qup_gsbi3_pdata;
2721	apq8064_device_qup_i2c_gsbi1.dev.platform_data =
2722					&apq8064_i2c_qup_gsbi1_pdata;
2723	apq8064_device_qup_i2c_gsbi4.dev.platform_data =
2724					&apq8064_i2c_qup_gsbi4_pdata;
2725	mpq8064_device_qup_i2c_gsbi5.dev.platform_data =
2726					&mpq8064_i2c_qup_gsbi5_pdata;
2727}
2728
2729#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
2730static int ethernet_init(void)
2731{
2732	int ret;
2733	ret = gpio_request(KS8851_IRQ_GPIO, "ks8851_irq");
2734	if (ret) {
2735		pr_err("ks8851 gpio_request failed: %d\n", ret);
2736		goto fail;
2737	}
2738
2739	return 0;
2740fail:
2741	return ret;
2742}
2743#else
2744static int ethernet_init(void)
2745{
2746	return 0;
2747}
2748#endif
2749
2750#define GPIO_KEY_HOME			PM8921_GPIO_PM_TO_SYS(27)
2751#define GPIO_KEY_VOLUME_UP		PM8921_GPIO_PM_TO_SYS(35)
2752#define GPIO_KEY_VOLUME_DOWN_PM8921	PM8921_GPIO_PM_TO_SYS(38)
2753#define GPIO_KEY_VOLUME_DOWN_PM8917	PM8921_GPIO_PM_TO_SYS(30)
2754#define GPIO_KEY_CAM_FOCUS		PM8921_GPIO_PM_TO_SYS(3)
2755#define GPIO_KEY_CAM_SNAP		PM8921_GPIO_PM_TO_SYS(4)
2756#define GPIO_KEY_ROTATION_PM8921	PM8921_GPIO_PM_TO_SYS(42)
2757#define GPIO_KEY_ROTATION_PM8917	PM8921_GPIO_PM_TO_SYS(8)
2758
2759static struct gpio_keys_button cdp_keys_pm8921[] = {
2760	{
2761		.code           = KEY_HOME,
2762		.gpio           = GPIO_KEY_HOME,
2763		.desc           = "home_key",
2764		.active_low     = 1,
2765		.type		= EV_KEY,
2766		.wakeup		= 1,
2767		.debounce_interval = 15,
2768	},
2769	{
2770		.code           = KEY_VOLUMEUP,
2771		.gpio           = GPIO_KEY_VOLUME_UP,
2772		.desc           = "volume_up_key",
2773		.active_low     = 1,
2774		.type		= EV_KEY,
2775		.wakeup		= 1,
2776		.debounce_interval = 15,
2777	},
2778	{
2779		.code           = KEY_VOLUMEDOWN,
2780		.gpio           = GPIO_KEY_VOLUME_DOWN_PM8921,
2781		.desc           = "volume_down_key",
2782		.active_low     = 1,
2783		.type		= EV_KEY,
2784		.wakeup		= 1,
2785		.debounce_interval = 15,
2786	},
2787	{
2788		.code           = SW_ROTATE_LOCK,
2789		.gpio           = GPIO_KEY_ROTATION_PM8921,
2790		.desc           = "rotate_key",
2791		.active_low     = 1,
2792		.type		= EV_SW,
2793		.debounce_interval = 15,
2794	},
2795};
2796
2797static struct gpio_keys_button cdp_keys_pm8917[] = {
2798	{
2799		.code           = KEY_HOME,
2800		.gpio           = GPIO_KEY_HOME,
2801		.desc           = "home_key",
2802		.active_low     = 1,
2803		.type		= EV_KEY,
2804		.wakeup		= 1,
2805		.debounce_interval = 15,
2806	},
2807	{
2808		.code           = KEY_VOLUMEUP,
2809		.gpio           = GPIO_KEY_VOLUME_UP,
2810		.desc           = "volume_up_key",
2811		.active_low     = 1,
2812		.type		= EV_KEY,
2813		.wakeup		= 1,
2814		.debounce_interval = 15,
2815	},
2816	{
2817		.code           = KEY_VOLUMEDOWN,
2818		.gpio           = GPIO_KEY_VOLUME_DOWN_PM8917,
2819		.desc           = "volume_down_key",
2820		.active_low     = 1,
2821		.type		= EV_KEY,
2822		.wakeup		= 1,
2823		.debounce_interval = 15,
2824	},
2825	{
2826		.code           = SW_ROTATE_LOCK,
2827		.gpio           = GPIO_KEY_ROTATION_PM8917,
2828		.desc           = "rotate_key",
2829		.active_low     = 1,
2830		.type		= EV_SW,
2831		.debounce_interval = 15,
2832	},
2833};
2834
2835static struct gpio_keys_platform_data cdp_keys_data = {
2836	.buttons        = cdp_keys_pm8921,
2837	.nbuttons       = ARRAY_SIZE(cdp_keys_pm8921),
2838};
2839
2840static struct platform_device cdp_kp_pdev = {
2841	.name           = "gpio-keys",
2842	.id             = -1,
2843	.dev            = {
2844		.platform_data  = &cdp_keys_data,
2845	},
2846};
2847
2848static struct gpio_keys_button mtp_keys[] = {
2849	{
2850		.code           = KEY_CAMERA_FOCUS,
2851		.gpio           = GPIO_KEY_CAM_FOCUS,
2852		.desc           = "cam_focus_key",
2853		.active_low     = 1,
2854		.type		= EV_KEY,
2855		.wakeup		= 1,
2856		.debounce_interval = 15,
2857	},
2858	{
2859		.code           = KEY_VOLUMEUP,
2860		.gpio           = GPIO_KEY_VOLUME_UP,
2861		.desc           = "volume_up_key",
2862		.active_low     = 1,
2863		.type		= EV_KEY,
2864		.wakeup		= 1,
2865		.debounce_interval = 15,
2866	},
2867	{
2868		.code           = KEY_VOLUMEDOWN,
2869		.gpio           = GPIO_KEY_VOLUME_DOWN_PM8921,
2870		.desc           = "volume_down_key",
2871		.active_low     = 1,
2872		.type		= EV_KEY,
2873		.wakeup		= 1,
2874		.debounce_interval = 15,
2875	},
2876	{
2877		.code           = KEY_CAMERA_SNAPSHOT,
2878		.gpio           = GPIO_KEY_CAM_SNAP,
2879		.desc           = "cam_snap_key",
2880		.active_low     = 1,
2881		.type		= EV_KEY,
2882		.debounce_interval = 15,
2883	},
2884};
2885
2886static struct gpio_keys_platform_data mtp_keys_data = {
2887	.buttons        = mtp_keys,
2888	.nbuttons       = ARRAY_SIZE(mtp_keys),
2889};
2890
2891static struct platform_device mtp_kp_pdev = {
2892	.name           = "gpio-keys",
2893	.id             = -1,
2894	.dev            = {
2895		.platform_data  = &mtp_keys_data,
2896	},
2897};
2898
2899static struct gpio_keys_button mpq_keys[] = {
2900	{
2901		.code           = KEY_VOLUMEDOWN,
2902		.gpio           = GPIO_KEY_VOLUME_DOWN_PM8921,
2903		.desc           = "volume_down_key",
2904		.active_low     = 1,
2905		.type		= EV_KEY,
2906		.wakeup		= 1,
2907		.debounce_interval = 15,
2908	},
2909	{
2910		.code           = KEY_VOLUMEUP,
2911		.gpio           = GPIO_KEY_VOLUME_UP,
2912		.desc           = "volume_up_key",
2913		.active_low     = 1,
2914		.type		= EV_KEY,
2915		.wakeup		= 1,
2916		.debounce_interval = 15,
2917	},
2918};
2919
2920static struct gpio_keys_platform_data mpq_keys_data = {
2921	.buttons        = mpq_keys,
2922	.nbuttons       = ARRAY_SIZE(mpq_keys),
2923};
2924
2925static struct platform_device mpq_gpio_keys_pdev = {
2926	.name           = "gpio-keys",
2927	.id             = -1,
2928	.dev            = {
2929		.platform_data  = &mpq_keys_data,
2930	},
2931};
2932
2933#define MPQ_KP_ROW_BASE		SX150X_EXP2_GPIO_BASE
2934#define MPQ_KP_COL_BASE		(SX150X_EXP2_GPIO_BASE + 4)
2935
2936static unsigned int mpq_row_gpios[] = {MPQ_KP_ROW_BASE, MPQ_KP_ROW_BASE + 1,
2937				MPQ_KP_ROW_BASE + 2, MPQ_KP_ROW_BASE + 3};
2938static unsigned int mpq_col_gpios[] = {MPQ_KP_COL_BASE, MPQ_KP_COL_BASE + 1,
2939				MPQ_KP_COL_BASE + 2};
2940
2941static const unsigned int mpq_keymap[] = {
2942	KEY(0, 0, KEY_UP),
2943	KEY(0, 1, KEY_ENTER),
2944	KEY(0, 2, KEY_3),
2945
2946	KEY(1, 0, KEY_DOWN),
2947	KEY(1, 1, KEY_EXIT),
2948	KEY(1, 2, KEY_4),
2949
2950	KEY(2, 0, KEY_LEFT),
2951	KEY(2, 1, KEY_1),
2952	KEY(2, 2, KEY_5),
2953
2954	KEY(3, 0, KEY_RIGHT),
2955	KEY(3, 1, KEY_2),
2956	KEY(3, 2, KEY_6),
2957};
2958
2959static struct matrix_keymap_data mpq_keymap_data = {
2960	.keymap_size	= ARRAY_SIZE(mpq_keymap),
2961	.keymap		= mpq_keymap,
2962};
2963
2964static struct matrix_keypad_platform_data mpq_keypad_data = {
2965	.keymap_data		= &mpq_keymap_data,
2966	.row_gpios		= mpq_row_gpios,
2967	.col_gpios		= mpq_col_gpios,
2968	.num_row_gpios		= ARRAY_SIZE(mpq_row_gpios),
2969	.num_col_gpios		= ARRAY_SIZE(mpq_col_gpios),
2970	.col_scan_delay_us	= 32000,
2971	.debounce_ms		= 20,
2972	.wakeup			= 1,
2973	.active_low		= 1,
2974	.no_autorepeat		= 1,
2975};
2976
2977static struct platform_device mpq_keypad_device = {
2978	.name           = "matrix-keypad",
2979	.id             = -1,
2980	.dev            = {
2981		.platform_data  = &mpq_keypad_data,
2982	},
2983};
2984
2985/* Sensors DSPS platform data */
2986#define DSPS_PIL_GENERIC_NAME		"dsps"
2987static void __init apq8064_init_dsps(void)
2988{
2989	struct msm_dsps_platform_data *pdata =
2990		msm_dsps_device_8064.dev.platform_data;
2991	pdata->pil_name = DSPS_PIL_GENERIC_NAME;
2992	pdata->gpios = NULL;
2993	pdata->gpios_num = 0;
2994
2995	platform_device_register(&msm_dsps_device_8064);
2996}
2997
2998#define I2C_SURF 1
2999#define I2C_FFA  (1 << 1)
3000#define I2C_RUMI (1 << 2)
3001#define I2C_SIM  (1 << 3)
3002#define I2C_LIQUID (1 << 4)
3003#define I2C_MPQ_CDP	BIT(5)
3004#define I2C_MPQ_HRD	BIT(6)
3005#define I2C_MPQ_DTV	BIT(7)
3006
3007struct i2c_registry {
3008	u8                     machs;
3009	int                    bus;
3010	struct i2c_board_info *info;
3011	int                    len;
3012};
3013
3014static struct i2c_registry apq8064_i2c_devices[] __initdata = {
3015	{
3016		I2C_LIQUID,
3017		APQ_8064_GSBI1_QUP_I2C_BUS_ID,
3018		smb349_charger_i2c_info,
3019		ARRAY_SIZE(smb349_charger_i2c_info)
3020	},
3021	{
3022		I2C_SURF | I2C_LIQUID,
3023		APQ_8064_GSBI3_QUP_I2C_BUS_ID,
3024		mxt_device_info,
3025		ARRAY_SIZE(mxt_device_info),
3026	},
3027	{
3028		I2C_FFA,
3029		APQ_8064_GSBI3_QUP_I2C_BUS_ID,
3030		cyttsp_info,
3031		ARRAY_SIZE(cyttsp_info),
3032	},
3033	{
3034		I2C_FFA | I2C_LIQUID,
3035		APQ_8064_GSBI1_QUP_I2C_BUS_ID,
3036		isa1200_board_info,
3037		ARRAY_SIZE(isa1200_board_info),
3038	},
3039	{
3040		I2C_MPQ_CDP,
3041		APQ_8064_GSBI5_QUP_I2C_BUS_ID,
3042		cs8427_device_info,
3043		ARRAY_SIZE(cs8427_device_info),
3044	},
3045};
3046
3047#define SX150X_EXP1_INT_N	PM8921_MPP_IRQ(PM8921_IRQ_BASE, 9)
3048#define SX150X_EXP2_INT_N	MSM_GPIO_TO_INT(81)
3049
3050struct sx150x_platform_data mpq8064_sx150x_pdata[] = {
3051	[SX150X_EXP1] = {
3052		.gpio_base	= SX150X_EXP1_GPIO_BASE,
3053		.oscio_is_gpo	= false,
3054		.io_pullup_ena	= 0x0,
3055		.io_pulldn_ena	= 0x0,
3056		.io_open_drain_ena = 0x0,
3057		.io_polarity	= 0,
3058		.irq_summary	= SX150X_EXP1_INT_N,
3059		.irq_base	= SX150X_EXP1_IRQ_BASE,
3060	},
3061	[SX150X_EXP2] = {
3062		.gpio_base	= SX150X_EXP2_GPIO_BASE,
3063		.oscio_is_gpo	= false,
3064		.io_pullup_ena	= 0x0f,
3065		.io_pulldn_ena	= 0x70,
3066		.io_open_drain_ena = 0x0,
3067		.io_polarity	= 0,
3068		.irq_summary	= SX150X_EXP2_INT_N,
3069		.irq_base	= SX150X_EXP2_IRQ_BASE,
3070	},
3071	[SX150X_EXP3] = {
3072		.gpio_base	= SX150X_EXP3_GPIO_BASE,
3073		.oscio_is_gpo	= false,
3074		.io_pullup_ena	= 0x0,
3075		.io_pulldn_ena	= 0x0,
3076		.io_open_drain_ena = 0x0,
3077		.io_polarity	= 0,
3078		.irq_summary	= -1,
3079	},
3080	[SX150X_EXP4] = {
3081		.gpio_base	= SX150X_EXP4_GPIO_BASE,
3082		.oscio_is_gpo	= false,
3083		.io_pullup_ena	= 0x0,
3084		.io_pulldn_ena	= 0x0,
3085		.io_open_drain_ena = 0x0,
3086		.io_polarity	= 0,
3087		.irq_summary	= -1,
3088	},
3089};
3090
3091static struct i2c_board_info sx150x_gpio_exp_info[] = {
3092	{
3093		I2C_BOARD_INFO("sx1509q", 0x70),
3094		.platform_data = &mpq8064_sx150x_pdata[SX150X_EXP1],
3095	},
3096	{
3097		I2C_BOARD_INFO("sx1508q", 0x23),
3098		.platform_data = &mpq8064_sx150x_pdata[SX150X_EXP2],
3099	},
3100	{
3101		I2C_BOARD_INFO("sx1508q", 0x22),
3102		.platform_data = &mpq8064_sx150x_pdata[SX150X_EXP3],
3103	},
3104	{
3105		I2C_BOARD_INFO("sx1509q", 0x3E),
3106		.platform_data = &mpq8064_sx150x_pdata[SX150X_EXP4],
3107	},
3108};
3109
3110#define MPQ8064_I2C_GSBI5_BUS_ID	5
3111
3112static struct i2c_registry mpq8064_i2c_devices[] __initdata = {
3113	{
3114		I2C_MPQ_CDP,
3115		MPQ8064_I2C_GSBI5_BUS_ID,
3116		sx150x_gpio_exp_info,
3117		ARRAY_SIZE(sx150x_gpio_exp_info),
3118	},
3119};
3120
3121static void __init register_i2c_devices(void)
3122{
3123	u8 mach_mask = 0;
3124	int i;
3125
3126#ifdef CONFIG_MSM_CAMERA
3127	struct i2c_registry apq8064_camera_i2c_devices = {
3128		I2C_SURF | I2C_FFA | I2C_LIQUID | I2C_RUMI,
3129		APQ_8064_GSBI4_QUP_I2C_BUS_ID,
3130		apq8064_camera_board_info.board_info,
3131		apq8064_camera_board_info.num_i2c_board_info,
3132	};
3133#endif
3134	/* Build the matching 'supported_machs' bitmask */
3135	if (machine_is_apq8064_cdp())
3136		mach_mask = I2C_SURF;
3137	else if (machine_is_apq8064_mtp())
3138		mach_mask = I2C_FFA;
3139	else if (machine_is_apq8064_liquid())
3140		mach_mask = I2C_LIQUID;
3141	else if (PLATFORM_IS_MPQ8064())
3142		mach_mask = I2C_MPQ_CDP;
3143	else
3144		pr_err("unmatched machine ID in register_i2c_devices\n");
3145
3146	/* Run the array and install devices as appropriate */
3147	for (i = 0; i < ARRAY_SIZE(apq8064_i2c_devices); ++i) {
3148		if (apq8064_i2c_devices[i].machs & mach_mask)
3149			i2c_register_board_info(apq8064_i2c_devices[i].bus,
3150						apq8064_i2c_devices[i].info,
3151						apq8064_i2c_devices[i].len);
3152	}
3153#ifdef CONFIG_MSM_CAMERA
3154	if (apq8064_camera_i2c_devices.machs & mach_mask)
3155		i2c_register_board_info(apq8064_camera_i2c_devices.bus,
3156			apq8064_camera_i2c_devices.info,
3157			apq8064_camera_i2c_devices.len);
3158#endif
3159
3160	for (i = 0; i < ARRAY_SIZE(mpq8064_i2c_devices); ++i) {
3161		if (mpq8064_i2c_devices[i].machs & mach_mask)
3162			i2c_register_board_info(
3163					mpq8064_i2c_devices[i].bus,
3164					mpq8064_i2c_devices[i].info,
3165					mpq8064_i2c_devices[i].len);
3166	}
3167}
3168
3169static void enable_avc_i2c_bus(void)
3170{
3171	int avc_i2c_en_mpp = PM8921_MPP_PM_TO_SYS(8);
3172	int rc;
3173
3174	rc = gpio_request(avc_i2c_en_mpp, "avc_i2c_en");
3175	if (rc)
3176		pr_err("request for avc_i2c_en mpp failed,"
3177						 "rc=%d\n", rc);
3178	else
3179		gpio_set_value_cansleep(avc_i2c_en_mpp, 1);
3180}
3181
3182/* Modify platform data values to match requirements for PM8917. */
3183static void __init apq8064_pm8917_pdata_fixup(void)
3184{
3185	cdp_keys_data.buttons = cdp_keys_pm8917;
3186	cdp_keys_data.nbuttons = ARRAY_SIZE(cdp_keys_pm8917);
3187}
3188
3189static void __init apq8064_common_init(void)
3190{
3191	u32 platform_version = socinfo_get_platform_version();
3192
3193	if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
3194		apq8064_pm8917_pdata_fixup();
3195	platform_device_register(&msm_gpio_device);
3196	msm_tsens_early_init(&apq_tsens_pdata);
3197	msm_thermal_init(&msm_thermal_pdata);
3198	if (socinfo_init() < 0)
3199		pr_err("socinfo_init() failed!\n");
3200	BUG_ON(msm_rpm_init(&apq8064_rpm_data));
3201	BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
3202	regulator_suppress_info_printing();
3203	if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
3204		configure_apq8064_pm8917_power_grid();
3205	platform_device_register(&apq8064_device_rpm_regulator);
3206	if (socinfo_get_pmic_model() != PMIC_MODEL_PM8917)
3207		platform_device_register(&apq8064_pm8921_device_rpm_regulator);
3208	if (msm_xo_init())
3209		pr_err("Failed to initialize XO votes\n");
3210	msm_clock_init(&apq8064_clock_init_data);
3211	apq8064_init_gpiomux();
3212	apq8064_i2c_init();
3213	register_i2c_devices();
3214
3215	apq8064_device_qup_spi_gsbi5.dev.platform_data =
3216						&apq8064_qup_spi_gsbi5_pdata;
3217	apq8064_init_pmic();
3218	if (machine_is_apq8064_liquid())
3219		msm_otg_pdata.mhl_enable = true;
3220
3221	android_usb_pdata.swfi_latency =
3222		msm_rpmrs_levels[0].latency_us;
3223
3224	apq8064_device_otg.dev.platform_data = &msm_otg_pdata;
3225	apq8064_ehci_host_init();
3226	apq8064_init_buses();
3227
3228	platform_add_devices(early_common_devices,
3229				ARRAY_SIZE(early_common_devices));
3230	if (socinfo_get_pmic_model() != PMIC_MODEL_PM8917)
3231		platform_add_devices(pm8921_common_devices,
3232					ARRAY_SIZE(pm8921_common_devices));
3233	else
3234		platform_add_devices(pm8917_common_devices,
3235					ARRAY_SIZE(pm8917_common_devices));
3236	platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
3237	if (!(machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
3238			machine_is_mpq8064_dtv()))
3239		platform_add_devices(common_not_mpq_devices,
3240			ARRAY_SIZE(common_not_mpq_devices));
3241	msm_hsic_pdata.swfi_latency =
3242		msm_rpmrs_levels[0].latency_us;
3243	if (machine_is_apq8064_mtp()) {
3244		msm_hsic_pdata.log2_irq_thresh = 5,
3245		apq8064_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
3246		device_initialize(&apq8064_device_hsic_host.dev);
3247		if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_DSDA2) {
3248			apq8064_device_ehci_host3.dev.platform_data =
3249				&msm_ehci_host_pdata3;
3250			device_initialize(&apq8064_device_ehci_host3.dev);
3251		}
3252	}
3253	apq8064_pm8xxx_gpio_mpp_init();
3254	apq8064_init_mmc();
3255
3256	if (machine_is_apq8064_mtp()) {
3257		if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_DSDA2) {
3258			amdm_8064_device.dev.platform_data =
3259				&amdm_platform_data;
3260			platform_device_register(&amdm_8064_device);
3261			bmdm_8064_device.dev.platform_data =
3262				&bmdm_platform_data;
3263			platform_device_register(&bmdm_8064_device);
3264		} else if (SOCINFO_VERSION_MINOR(platform_version) == 1) {
3265			i2s_mdm_8064_device.dev.platform_data =
3266				&mdm_platform_data;
3267			platform_device_register(&i2s_mdm_8064_device);
3268		} else {
3269			mdm_8064_device.dev.platform_data = &mdm_platform_data;
3270			platform_device_register(&mdm_8064_device);
3271		}
3272	}
3273	platform_device_register(&apq8064_slim_ctrl);
3274	slim_register_board_info(apq8064_slim_devices,
3275		ARRAY_SIZE(apq8064_slim_devices));
3276	if (!PLATFORM_IS_MPQ8064()) {
3277		apq8064_init_dsps();
3278		platform_device_register(&msm_8960_riva);
3279	}
3280	if (cpu_is_apq8064ab())
3281		apq8064ab_update_krait_spm();
3282	msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
3283	msm_spm_l2_init(msm_spm_l2_data);
3284	BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
3285	apq8064_epm_adc_init();
3286	msm_pm_set_tz_retention_flag(1);
3287}
3288
3289static void __init apq8064_allocate_memory_regions(void)
3290{
3291	apq8064_allocate_fb_region();
3292}
3293
3294static void __init apq8064_cdp_init(void)
3295{
3296	printk(KERN_NOTICE "MIDR      = 0x%08x\n", read_cpuid_id());
3297	if (meminfo_init(SYS_MEMORY, SZ_256M) < 0)
3298		pr_err("meminfo_init() failed!\n");
3299	if (machine_is_apq8064_mtp() &&
3300		SOCINFO_VERSION_MINOR(socinfo_get_platform_version()) == 1)
3301			cyttsp_pdata.sleep_gpio = CYTTSP_TS_GPIO_SLEEP_ALT;
3302	apq8064_common_init();
3303	if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
3304		machine_is_mpq8064_dtv()) {
3305		enable_avc_i2c_bus();
3306		msm_rotator_set_split_iommu_domain();
3307		platform_add_devices(mpq_devices, ARRAY_SIZE(mpq_devices));
3308		mpq8064_pcie_init();
3309	} else {
3310		ethernet_init();
3311		msm_rotator_set_split_iommu_domain();
3312		platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices));
3313		spi_register_board_info(spi_board_info,
3314						ARRAY_SIZE(spi_board_info));
3315	}
3316	apq8064_init_fb();
3317	apq8064_init_gpu();
3318	platform_add_devices(apq8064_footswitch, apq8064_num_footswitch);
3319#ifdef CONFIG_MSM_CAMERA
3320	apq8064_init_cam();
3321#endif
3322
3323	if (machine_is_apq8064_cdp() || machine_is_apq8064_liquid())
3324		platform_device_register(&cdp_kp_pdev);
3325
3326	if (machine_is_apq8064_mtp())
3327		platform_device_register(&mtp_kp_pdev);
3328
3329	change_memory_power = &apq8064_change_memory_power;
3330
3331	if (machine_is_mpq8064_cdp()) {
3332		platform_device_register(&mpq_gpio_keys_pdev);
3333		platform_device_register(&mpq_keypad_device);
3334	}
3335}
3336
3337MACHINE_START(APQ8064_CDP, "QCT APQ8064 CDP")
3338	.map_io = apq8064_map_io,
3339	.reserve = apq8064_reserve,
3340	.init_irq = apq8064_init_irq,
3341	.handle_irq = gic_handle_irq,
3342	.timer = &msm_timer,
3343	.init_machine = apq8064_cdp_init,
3344	.init_early = apq8064_allocate_memory_regions,
3345	.init_very_early = apq8064_early_reserve,
3346	.restart = msm_restart,
3347MACHINE_END
3348
3349MACHINE_START(APQ8064_MTP, "QCT APQ8064 MTP")
3350	.map_io = apq8064_map_io,
3351	.reserve = apq8064_reserve,
3352	.init_irq = apq8064_init_irq,
3353	.handle_irq = gic_handle_irq,
3354	.timer = &msm_timer,
3355	.init_machine = apq8064_cdp_init,
3356	.init_early = apq8064_allocate_memory_regions,
3357	.init_very_early = apq8064_early_reserve,
3358	.restart = msm_restart,
3359MACHINE_END
3360
3361MACHINE_START(APQ8064_LIQUID, "QCT APQ8064 LIQUID")
3362	.map_io = apq8064_map_io,
3363	.reserve = apq8064_reserve,
3364	.init_irq = apq8064_init_irq,
3365	.handle_irq = gic_handle_irq,
3366	.timer = &msm_timer,
3367	.init_machine = apq8064_cdp_init,
3368	.init_early = apq8064_allocate_memory_regions,
3369	.init_very_early = apq8064_early_reserve,
3370	.restart = msm_restart,
3371MACHINE_END
3372
3373MACHINE_START(MPQ8064_CDP, "QCT MPQ8064 CDP")
3374	.map_io = apq8064_map_io,
3375	.reserve = apq8064_reserve,
3376	.init_irq = apq8064_init_irq,
3377	.handle_irq = gic_handle_irq,
3378	.timer = &msm_timer,
3379	.init_machine = apq8064_cdp_init,
3380	.init_early = apq8064_allocate_memory_regions,
3381	.init_very_early = apq8064_early_reserve,
3382	.restart = msm_restart,
3383MACHINE_END
3384
3385MACHINE_START(MPQ8064_HRD, "QCT MPQ8064 HRD")
3386	.map_io = apq8064_map_io,
3387	.reserve = apq8064_reserve,
3388	.init_irq = apq8064_init_irq,
3389	.handle_irq = gic_handle_irq,
3390	.timer = &msm_timer,
3391	.init_machine = apq8064_cdp_init,
3392	.init_early = apq8064_allocate_memory_regions,
3393	.init_very_early = apq8064_early_reserve,
3394	.restart = msm_restart,
3395MACHINE_END
3396
3397MACHINE_START(MPQ8064_DTV, "QCT MPQ8064 DTV")
3398	.map_io = apq8064_map_io,
3399	.reserve = apq8064_reserve,
3400	.init_irq = apq8064_init_irq,
3401	.handle_irq = gic_handle_irq,
3402	.timer = &msm_timer,
3403	.init_machine = apq8064_cdp_init,
3404	.init_early = apq8064_allocate_memory_regions,
3405	.init_very_early = apq8064_early_reserve,
3406	.restart = msm_restart,
3407MACHINE_END
3408