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/arch/powerpc/kernel/ptrace.c

http://github.com/mirrors/linux
C | 3378 lines | 2347 code | 403 blank | 628 comment | 428 complexity | ded8c5fcfef1f6a76c1bdf310e429be0 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. /*
  2. * PowerPC version
  3. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  4. *
  5. * Derived from "arch/m68k/kernel/ptrace.c"
  6. * Copyright (C) 1994 by Hamish Macdonald
  7. * Taken from linux/kernel/ptrace.c and modified for M680x0.
  8. * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
  9. *
  10. * Modified by Cort Dougan (cort@hq.fsmlabs.com)
  11. * and Paul Mackerras (paulus@samba.org).
  12. *
  13. * This file is subject to the terms and conditions of the GNU General
  14. * Public License. See the file README.legal in the main directory of
  15. * this archive for more details.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/sched.h>
  19. #include <linux/mm.h>
  20. #include <linux/smp.h>
  21. #include <linux/errno.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/regset.h>
  24. #include <linux/tracehook.h>
  25. #include <linux/elf.h>
  26. #include <linux/user.h>
  27. #include <linux/security.h>
  28. #include <linux/signal.h>
  29. #include <linux/seccomp.h>
  30. #include <linux/audit.h>
  31. #include <trace/syscall.h>
  32. #include <linux/hw_breakpoint.h>
  33. #include <linux/perf_event.h>
  34. #include <linux/context_tracking.h>
  35. #include <asm/uaccess.h>
  36. #include <asm/page.h>
  37. #include <asm/pgtable.h>
  38. #include <asm/switch_to.h>
  39. #define CREATE_TRACE_POINTS
  40. #include <trace/events/syscalls.h>
  41. /*
  42. * The parameter save area on the stack is used to store arguments being passed
  43. * to callee function and is located at fixed offset from stack pointer.
  44. */
  45. #ifdef CONFIG_PPC32
  46. #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
  47. #else /* CONFIG_PPC32 */
  48. #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
  49. #endif
  50. struct pt_regs_offset {
  51. const char *name;
  52. int offset;
  53. };
  54. #define STR(s) #s /* convert to string */
  55. #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
  56. #define GPR_OFFSET_NAME(num) \
  57. {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
  58. {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
  59. #define REG_OFFSET_END {.name = NULL, .offset = 0}
  60. #define TVSO(f) (offsetof(struct thread_vr_state, f))
  61. #define TFSO(f) (offsetof(struct thread_fp_state, f))
  62. #define TSO(f) (offsetof(struct thread_struct, f))
  63. static const struct pt_regs_offset regoffset_table[] = {
  64. GPR_OFFSET_NAME(0),
  65. GPR_OFFSET_NAME(1),
  66. GPR_OFFSET_NAME(2),
  67. GPR_OFFSET_NAME(3),
  68. GPR_OFFSET_NAME(4),
  69. GPR_OFFSET_NAME(5),
  70. GPR_OFFSET_NAME(6),
  71. GPR_OFFSET_NAME(7),
  72. GPR_OFFSET_NAME(8),
  73. GPR_OFFSET_NAME(9),
  74. GPR_OFFSET_NAME(10),
  75. GPR_OFFSET_NAME(11),
  76. GPR_OFFSET_NAME(12),
  77. GPR_OFFSET_NAME(13),
  78. GPR_OFFSET_NAME(14),
  79. GPR_OFFSET_NAME(15),
  80. GPR_OFFSET_NAME(16),
  81. GPR_OFFSET_NAME(17),
  82. GPR_OFFSET_NAME(18),
  83. GPR_OFFSET_NAME(19),
  84. GPR_OFFSET_NAME(20),
  85. GPR_OFFSET_NAME(21),
  86. GPR_OFFSET_NAME(22),
  87. GPR_OFFSET_NAME(23),
  88. GPR_OFFSET_NAME(24),
  89. GPR_OFFSET_NAME(25),
  90. GPR_OFFSET_NAME(26),
  91. GPR_OFFSET_NAME(27),
  92. GPR_OFFSET_NAME(28),
  93. GPR_OFFSET_NAME(29),
  94. GPR_OFFSET_NAME(30),
  95. GPR_OFFSET_NAME(31),
  96. REG_OFFSET_NAME(nip),
  97. REG_OFFSET_NAME(msr),
  98. REG_OFFSET_NAME(ctr),
  99. REG_OFFSET_NAME(link),
  100. REG_OFFSET_NAME(xer),
  101. REG_OFFSET_NAME(ccr),
  102. #ifdef CONFIG_PPC64
  103. REG_OFFSET_NAME(softe),
  104. #else
  105. REG_OFFSET_NAME(mq),
  106. #endif
  107. REG_OFFSET_NAME(trap),
  108. REG_OFFSET_NAME(dar),
  109. REG_OFFSET_NAME(dsisr),
  110. REG_OFFSET_END,
  111. };
  112. /**
  113. * regs_query_register_offset() - query register offset from its name
  114. * @name: the name of a register
  115. *
  116. * regs_query_register_offset() returns the offset of a register in struct
  117. * pt_regs from its name. If the name is invalid, this returns -EINVAL;
  118. */
  119. int regs_query_register_offset(const char *name)
  120. {
  121. const struct pt_regs_offset *roff;
  122. for (roff = regoffset_table; roff->name != NULL; roff++)
  123. if (!strcmp(roff->name, name))
  124. return roff->offset;
  125. return -EINVAL;
  126. }
  127. /**
  128. * regs_query_register_name() - query register name from its offset
  129. * @offset: the offset of a register in struct pt_regs.
  130. *
  131. * regs_query_register_name() returns the name of a register from its
  132. * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
  133. */
  134. const char *regs_query_register_name(unsigned int offset)
  135. {
  136. const struct pt_regs_offset *roff;
  137. for (roff = regoffset_table; roff->name != NULL; roff++)
  138. if (roff->offset == offset)
  139. return roff->name;
  140. return NULL;
  141. }
  142. /*
  143. * does not yet catch signals sent when the child dies.
  144. * in exit.c or in signal.c.
  145. */
  146. /*
  147. * Set of msr bits that gdb can change on behalf of a process.
  148. */
  149. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  150. #define MSR_DEBUGCHANGE 0
  151. #else
  152. #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
  153. #endif
  154. /*
  155. * Max register writeable via put_reg
  156. */
  157. #ifdef CONFIG_PPC32
  158. #define PT_MAX_PUT_REG PT_MQ
  159. #else
  160. #define PT_MAX_PUT_REG PT_CCR
  161. #endif
  162. static unsigned long get_user_msr(struct task_struct *task)
  163. {
  164. return task->thread.regs->msr | task->thread.fpexc_mode;
  165. }
  166. static int set_user_msr(struct task_struct *task, unsigned long msr)
  167. {
  168. task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
  169. task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
  170. return 0;
  171. }
  172. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  173. static unsigned long get_user_ckpt_msr(struct task_struct *task)
  174. {
  175. return task->thread.ckpt_regs.msr | task->thread.fpexc_mode;
  176. }
  177. static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
  178. {
  179. task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
  180. task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
  181. return 0;
  182. }
  183. static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap)
  184. {
  185. task->thread.ckpt_regs.trap = trap & 0xfff0;
  186. return 0;
  187. }
  188. #endif
  189. #ifdef CONFIG_PPC64
  190. static int get_user_dscr(struct task_struct *task, unsigned long *data)
  191. {
  192. *data = task->thread.dscr;
  193. return 0;
  194. }
  195. static int set_user_dscr(struct task_struct *task, unsigned long dscr)
  196. {
  197. task->thread.dscr = dscr;
  198. task->thread.dscr_inherit = 1;
  199. return 0;
  200. }
  201. #else
  202. static int get_user_dscr(struct task_struct *task, unsigned long *data)
  203. {
  204. return -EIO;
  205. }
  206. static int set_user_dscr(struct task_struct *task, unsigned long dscr)
  207. {
  208. return -EIO;
  209. }
  210. #endif
  211. /*
  212. * We prevent mucking around with the reserved area of trap
  213. * which are used internally by the kernel.
  214. */
  215. static int set_user_trap(struct task_struct *task, unsigned long trap)
  216. {
  217. task->thread.regs->trap = trap & 0xfff0;
  218. return 0;
  219. }
  220. /*
  221. * Get contents of register REGNO in task TASK.
  222. */
  223. int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
  224. {
  225. if ((task->thread.regs == NULL) || !data)
  226. return -EIO;
  227. if (regno == PT_MSR) {
  228. *data = get_user_msr(task);
  229. return 0;
  230. }
  231. if (regno == PT_DSCR)
  232. return get_user_dscr(task, data);
  233. if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
  234. *data = ((unsigned long *)task->thread.regs)[regno];
  235. return 0;
  236. }
  237. return -EIO;
  238. }
  239. /*
  240. * Write contents of register REGNO in task TASK.
  241. */
  242. int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
  243. {
  244. if (task->thread.regs == NULL)
  245. return -EIO;
  246. if (regno == PT_MSR)
  247. return set_user_msr(task, data);
  248. if (regno == PT_TRAP)
  249. return set_user_trap(task, data);
  250. if (regno == PT_DSCR)
  251. return set_user_dscr(task, data);
  252. if (regno <= PT_MAX_PUT_REG) {
  253. ((unsigned long *)task->thread.regs)[regno] = data;
  254. return 0;
  255. }
  256. return -EIO;
  257. }
  258. static int gpr_get(struct task_struct *target, const struct user_regset *regset,
  259. unsigned int pos, unsigned int count,
  260. void *kbuf, void __user *ubuf)
  261. {
  262. int i, ret;
  263. if (target->thread.regs == NULL)
  264. return -EIO;
  265. if (!FULL_REGS(target->thread.regs)) {
  266. /* We have a partial register set. Fill 14-31 with bogus values */
  267. for (i = 14; i < 32; i++)
  268. target->thread.regs->gpr[i] = NV_REG_POISON;
  269. }
  270. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  271. target->thread.regs,
  272. 0, offsetof(struct pt_regs, msr));
  273. if (!ret) {
  274. unsigned long msr = get_user_msr(target);
  275. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
  276. offsetof(struct pt_regs, msr),
  277. offsetof(struct pt_regs, msr) +
  278. sizeof(msr));
  279. }
  280. BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
  281. offsetof(struct pt_regs, msr) + sizeof(long));
  282. if (!ret)
  283. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  284. &target->thread.regs->orig_gpr3,
  285. offsetof(struct pt_regs, orig_gpr3),
  286. sizeof(struct pt_regs));
  287. if (!ret)
  288. ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
  289. sizeof(struct pt_regs), -1);
  290. return ret;
  291. }
  292. static int gpr_set(struct task_struct *target, const struct user_regset *regset,
  293. unsigned int pos, unsigned int count,
  294. const void *kbuf, const void __user *ubuf)
  295. {
  296. unsigned long reg;
  297. int ret;
  298. if (target->thread.regs == NULL)
  299. return -EIO;
  300. CHECK_FULL_REGS(target->thread.regs);
  301. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  302. target->thread.regs,
  303. 0, PT_MSR * sizeof(reg));
  304. if (!ret && count > 0) {
  305. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
  306. PT_MSR * sizeof(reg),
  307. (PT_MSR + 1) * sizeof(reg));
  308. if (!ret)
  309. ret = set_user_msr(target, reg);
  310. }
  311. BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
  312. offsetof(struct pt_regs, msr) + sizeof(long));
  313. if (!ret)
  314. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  315. &target->thread.regs->orig_gpr3,
  316. PT_ORIG_R3 * sizeof(reg),
  317. (PT_MAX_PUT_REG + 1) * sizeof(reg));
  318. if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
  319. ret = user_regset_copyin_ignore(
  320. &pos, &count, &kbuf, &ubuf,
  321. (PT_MAX_PUT_REG + 1) * sizeof(reg),
  322. PT_TRAP * sizeof(reg));
  323. if (!ret && count > 0) {
  324. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
  325. PT_TRAP * sizeof(reg),
  326. (PT_TRAP + 1) * sizeof(reg));
  327. if (!ret)
  328. ret = set_user_trap(target, reg);
  329. }
  330. if (!ret)
  331. ret = user_regset_copyin_ignore(
  332. &pos, &count, &kbuf, &ubuf,
  333. (PT_TRAP + 1) * sizeof(reg), -1);
  334. return ret;
  335. }
  336. /*
  337. * When the transaction is active, 'transact_fp' holds the current running
  338. * value of all FPR registers and 'fp_state' holds the last checkpointed
  339. * value of all FPR registers for the current transaction. When transaction
  340. * is not active 'fp_state' holds the current running state of all the FPR
  341. * registers. So this function which returns the current running values of
  342. * all the FPR registers, needs to know whether any transaction is active
  343. * or not.
  344. *
  345. * Userspace interface buffer layout:
  346. *
  347. * struct data {
  348. * u64 fpr[32];
  349. * u64 fpscr;
  350. * };
  351. *
  352. * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
  353. * which determines the final code in this function. All the combinations of
  354. * these two config options are possible except the one below as transactional
  355. * memory config pulls in CONFIG_VSX automatically.
  356. *
  357. * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  358. */
  359. static int fpr_get(struct task_struct *target, const struct user_regset *regset,
  360. unsigned int pos, unsigned int count,
  361. void *kbuf, void __user *ubuf)
  362. {
  363. #ifdef CONFIG_VSX
  364. u64 buf[33];
  365. int i;
  366. #endif
  367. flush_fp_to_thread(target);
  368. #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  369. /* copy to local buffer then write that out */
  370. if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
  371. flush_altivec_to_thread(target);
  372. flush_tmregs_to_thread(target);
  373. for (i = 0; i < 32 ; i++)
  374. buf[i] = target->thread.TS_TRANS_FPR(i);
  375. buf[32] = target->thread.transact_fp.fpscr;
  376. } else {
  377. for (i = 0; i < 32 ; i++)
  378. buf[i] = target->thread.TS_FPR(i);
  379. buf[32] = target->thread.fp_state.fpscr;
  380. }
  381. return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
  382. #endif
  383. #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  384. /* copy to local buffer then write that out */
  385. for (i = 0; i < 32 ; i++)
  386. buf[i] = target->thread.TS_FPR(i);
  387. buf[32] = target->thread.fp_state.fpscr;
  388. return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
  389. #endif
  390. #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  391. BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
  392. offsetof(struct thread_fp_state, fpr[32]));
  393. return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  394. &target->thread.fp_state, 0, -1);
  395. #endif
  396. }
  397. /*
  398. * When the transaction is active, 'transact_fp' holds the current running
  399. * value of all FPR registers and 'fp_state' holds the last checkpointed
  400. * value of all FPR registers for the current transaction. When transaction
  401. * is not active 'fp_state' holds the current running state of all the FPR
  402. * registers. So this function which setss the current running values of
  403. * all the FPR registers, needs to know whether any transaction is active
  404. * or not.
  405. *
  406. * Userspace interface buffer layout:
  407. *
  408. * struct data {
  409. * u64 fpr[32];
  410. * u64 fpscr;
  411. * };
  412. *
  413. * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
  414. * which determines the final code in this function. All the combinations of
  415. * these two config options are possible except the one below as transactional
  416. * memory config pulls in CONFIG_VSX automatically.
  417. *
  418. * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  419. */
  420. static int fpr_set(struct task_struct *target, const struct user_regset *regset,
  421. unsigned int pos, unsigned int count,
  422. const void *kbuf, const void __user *ubuf)
  423. {
  424. #ifdef CONFIG_VSX
  425. u64 buf[33];
  426. int i;
  427. #endif
  428. flush_fp_to_thread(target);
  429. #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  430. /* copy to local buffer then write that out */
  431. i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
  432. if (i)
  433. return i;
  434. if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
  435. flush_altivec_to_thread(target);
  436. flush_tmregs_to_thread(target);
  437. for (i = 0; i < 32 ; i++)
  438. target->thread.TS_TRANS_FPR(i) = buf[i];
  439. target->thread.transact_fp.fpscr = buf[32];
  440. } else {
  441. for (i = 0; i < 32 ; i++)
  442. target->thread.TS_FPR(i) = buf[i];
  443. target->thread.fp_state.fpscr = buf[32];
  444. }
  445. return 0;
  446. #endif
  447. #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  448. /* copy to local buffer then write that out */
  449. i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
  450. if (i)
  451. return i;
  452. for (i = 0; i < 32 ; i++)
  453. target->thread.TS_FPR(i) = buf[i];
  454. target->thread.fp_state.fpscr = buf[32];
  455. return 0;
  456. #endif
  457. #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
  458. BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
  459. offsetof(struct thread_fp_state, fpr[32]));
  460. return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  461. &target->thread.fp_state, 0, -1);
  462. #endif
  463. }
  464. #ifdef CONFIG_ALTIVEC
  465. /*
  466. * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
  467. * The transfer totals 34 quadword. Quadwords 0-31 contain the
  468. * corresponding vector registers. Quadword 32 contains the vscr as the
  469. * last word (offset 12) within that quadword. Quadword 33 contains the
  470. * vrsave as the first word (offset 0) within the quadword.
  471. *
  472. * This definition of the VMX state is compatible with the current PPC32
  473. * ptrace interface. This allows signal handling and ptrace to use the
  474. * same structures. This also simplifies the implementation of a bi-arch
  475. * (combined (32- and 64-bit) gdb.
  476. */
  477. static int vr_active(struct task_struct *target,
  478. const struct user_regset *regset)
  479. {
  480. flush_altivec_to_thread(target);
  481. return target->thread.used_vr ? regset->n : 0;
  482. }
  483. /*
  484. * When the transaction is active, 'transact_vr' holds the current running
  485. * value of all the VMX registers and 'vr_state' holds the last checkpointed
  486. * value of all the VMX registers for the current transaction to fall back
  487. * on in case it aborts. When transaction is not active 'vr_state' holds
  488. * the current running state of all the VMX registers. So this function which
  489. * gets the current running values of all the VMX registers, needs to know
  490. * whether any transaction is active or not.
  491. *
  492. * Userspace interface buffer layout:
  493. *
  494. * struct data {
  495. * vector128 vr[32];
  496. * vector128 vscr;
  497. * vector128 vrsave;
  498. * };
  499. */
  500. static int vr_get(struct task_struct *target, const struct user_regset *regset,
  501. unsigned int pos, unsigned int count,
  502. void *kbuf, void __user *ubuf)
  503. {
  504. struct thread_vr_state *addr;
  505. int ret;
  506. flush_altivec_to_thread(target);
  507. BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
  508. offsetof(struct thread_vr_state, vr[32]));
  509. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  510. if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
  511. flush_fp_to_thread(target);
  512. flush_tmregs_to_thread(target);
  513. addr = &target->thread.transact_vr;
  514. } else {
  515. addr = &target->thread.vr_state;
  516. }
  517. #else
  518. addr = &target->thread.vr_state;
  519. #endif
  520. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  521. addr, 0,
  522. 33 * sizeof(vector128));
  523. if (!ret) {
  524. /*
  525. * Copy out only the low-order word of vrsave.
  526. */
  527. union {
  528. elf_vrreg_t reg;
  529. u32 word;
  530. } vrsave;
  531. memset(&vrsave, 0, sizeof(vrsave));
  532. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  533. if (MSR_TM_ACTIVE(target->thread.regs->msr))
  534. vrsave.word = target->thread.transact_vrsave;
  535. else
  536. vrsave.word = target->thread.vrsave;
  537. #else
  538. vrsave.word = target->thread.vrsave;
  539. #endif
  540. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
  541. 33 * sizeof(vector128), -1);
  542. }
  543. return ret;
  544. }
  545. /*
  546. * When the transaction is active, 'transact_vr' holds the current running
  547. * value of all the VMX registers and 'vr_state' holds the last checkpointed
  548. * value of all the VMX registers for the current transaction to fall back
  549. * on in case it aborts. When transaction is not active 'vr_state' holds
  550. * the current running state of all the VMX registers. So this function which
  551. * sets the current running values of all the VMX registers, needs to know
  552. * whether any transaction is active or not.
  553. *
  554. * Userspace interface buffer layout:
  555. *
  556. * struct data {
  557. * vector128 vr[32];
  558. * vector128 vscr;
  559. * vector128 vrsave;
  560. * };
  561. */
  562. static int vr_set(struct task_struct *target, const struct user_regset *regset,
  563. unsigned int pos, unsigned int count,
  564. const void *kbuf, const void __user *ubuf)
  565. {
  566. struct thread_vr_state *addr;
  567. int ret;
  568. flush_altivec_to_thread(target);
  569. BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
  570. offsetof(struct thread_vr_state, vr[32]));
  571. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  572. if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
  573. flush_fp_to_thread(target);
  574. flush_tmregs_to_thread(target);
  575. addr = &target->thread.transact_vr;
  576. } else {
  577. addr = &target->thread.vr_state;
  578. }
  579. #else
  580. addr = &target->thread.vr_state;
  581. #endif
  582. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  583. addr, 0,
  584. 33 * sizeof(vector128));
  585. if (!ret && count > 0) {
  586. /*
  587. * We use only the first word of vrsave.
  588. */
  589. union {
  590. elf_vrreg_t reg;
  591. u32 word;
  592. } vrsave;
  593. memset(&vrsave, 0, sizeof(vrsave));
  594. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  595. if (MSR_TM_ACTIVE(target->thread.regs->msr))
  596. vrsave.word = target->thread.transact_vrsave;
  597. else
  598. vrsave.word = target->thread.vrsave;
  599. #else
  600. vrsave.word = target->thread.vrsave;
  601. #endif
  602. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
  603. 33 * sizeof(vector128), -1);
  604. if (!ret) {
  605. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  606. if (MSR_TM_ACTIVE(target->thread.regs->msr))
  607. target->thread.transact_vrsave = vrsave.word;
  608. else
  609. target->thread.vrsave = vrsave.word;
  610. #else
  611. target->thread.vrsave = vrsave.word;
  612. #endif
  613. }
  614. }
  615. return ret;
  616. }
  617. #endif /* CONFIG_ALTIVEC */
  618. #ifdef CONFIG_VSX
  619. /*
  620. * Currently to set and and get all the vsx state, you need to call
  621. * the fp and VMX calls as well. This only get/sets the lower 32
  622. * 128bit VSX registers.
  623. */
  624. static int vsr_active(struct task_struct *target,
  625. const struct user_regset *regset)
  626. {
  627. flush_vsx_to_thread(target);
  628. return target->thread.used_vsr ? regset->n : 0;
  629. }
  630. /*
  631. * When the transaction is active, 'transact_fp' holds the current running
  632. * value of all FPR registers and 'fp_state' holds the last checkpointed
  633. * value of all FPR registers for the current transaction. When transaction
  634. * is not active 'fp_state' holds the current running state of all the FPR
  635. * registers. So this function which returns the current running values of
  636. * all the FPR registers, needs to know whether any transaction is active
  637. * or not.
  638. *
  639. * Userspace interface buffer layout:
  640. *
  641. * struct data {
  642. * u64 vsx[32];
  643. * };
  644. */
  645. static int vsr_get(struct task_struct *target, const struct user_regset *regset,
  646. unsigned int pos, unsigned int count,
  647. void *kbuf, void __user *ubuf)
  648. {
  649. u64 buf[32];
  650. int ret, i;
  651. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  652. flush_fp_to_thread(target);
  653. flush_altivec_to_thread(target);
  654. flush_tmregs_to_thread(target);
  655. #endif
  656. flush_vsx_to_thread(target);
  657. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  658. if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
  659. for (i = 0; i < 32 ; i++)
  660. buf[i] = target->thread.
  661. transact_fp.fpr[i][TS_VSRLOWOFFSET];
  662. } else {
  663. for (i = 0; i < 32 ; i++)
  664. buf[i] = target->thread.
  665. fp_state.fpr[i][TS_VSRLOWOFFSET];
  666. }
  667. #else
  668. for (i = 0; i < 32 ; i++)
  669. buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
  670. #endif
  671. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  672. buf, 0, 32 * sizeof(double));
  673. return ret;
  674. }
  675. /*
  676. * When the transaction is active, 'transact_fp' holds the current running
  677. * value of all FPR registers and 'fp_state' holds the last checkpointed
  678. * value of all FPR registers for the current transaction. When transaction
  679. * is not active 'fp_state' holds the current running state of all the FPR
  680. * registers. So this function which sets the current running values of all
  681. * the FPR registers, needs to know whether any transaction is active or not.
  682. *
  683. * Userspace interface buffer layout:
  684. *
  685. * struct data {
  686. * u64 vsx[32];
  687. * };
  688. */
  689. static int vsr_set(struct task_struct *target, const struct user_regset *regset,
  690. unsigned int pos, unsigned int count,
  691. const void *kbuf, const void __user *ubuf)
  692. {
  693. u64 buf[32];
  694. int ret,i;
  695. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  696. flush_fp_to_thread(target);
  697. flush_altivec_to_thread(target);
  698. flush_tmregs_to_thread(target);
  699. #endif
  700. flush_vsx_to_thread(target);
  701. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  702. buf, 0, 32 * sizeof(double));
  703. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  704. if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
  705. for (i = 0; i < 32 ; i++)
  706. target->thread.transact_fp.
  707. fpr[i][TS_VSRLOWOFFSET] = buf[i];
  708. } else {
  709. for (i = 0; i < 32 ; i++)
  710. target->thread.fp_state.
  711. fpr[i][TS_VSRLOWOFFSET] = buf[i];
  712. }
  713. #else
  714. for (i = 0; i < 32 ; i++)
  715. target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
  716. #endif
  717. return ret;
  718. }
  719. #endif /* CONFIG_VSX */
  720. #ifdef CONFIG_SPE
  721. /*
  722. * For get_evrregs/set_evrregs functions 'data' has the following layout:
  723. *
  724. * struct {
  725. * u32 evr[32];
  726. * u64 acc;
  727. * u32 spefscr;
  728. * }
  729. */
  730. static int evr_active(struct task_struct *target,
  731. const struct user_regset *regset)
  732. {
  733. flush_spe_to_thread(target);
  734. return target->thread.used_spe ? regset->n : 0;
  735. }
  736. static int evr_get(struct task_struct *target, const struct user_regset *regset,
  737. unsigned int pos, unsigned int count,
  738. void *kbuf, void __user *ubuf)
  739. {
  740. int ret;
  741. flush_spe_to_thread(target);
  742. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  743. &target->thread.evr,
  744. 0, sizeof(target->thread.evr));
  745. BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
  746. offsetof(struct thread_struct, spefscr));
  747. if (!ret)
  748. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  749. &target->thread.acc,
  750. sizeof(target->thread.evr), -1);
  751. return ret;
  752. }
  753. static int evr_set(struct task_struct *target, const struct user_regset *regset,
  754. unsigned int pos, unsigned int count,
  755. const void *kbuf, const void __user *ubuf)
  756. {
  757. int ret;
  758. flush_spe_to_thread(target);
  759. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  760. &target->thread.evr,
  761. 0, sizeof(target->thread.evr));
  762. BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
  763. offsetof(struct thread_struct, spefscr));
  764. if (!ret)
  765. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  766. &target->thread.acc,
  767. sizeof(target->thread.evr), -1);
  768. return ret;
  769. }
  770. #endif /* CONFIG_SPE */
  771. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  772. /**
  773. * tm_cgpr_active - get active number of registers in CGPR
  774. * @target: The target task.
  775. * @regset: The user regset structure.
  776. *
  777. * This function checks for the active number of available
  778. * regisers in transaction checkpointed GPR category.
  779. */
  780. static int tm_cgpr_active(struct task_struct *target,
  781. const struct user_regset *regset)
  782. {
  783. if (!cpu_has_feature(CPU_FTR_TM))
  784. return -ENODEV;
  785. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  786. return 0;
  787. return regset->n;
  788. }
  789. /**
  790. * tm_cgpr_get - get CGPR registers
  791. * @target: The target task.
  792. * @regset: The user regset structure.
  793. * @pos: The buffer position.
  794. * @count: Number of bytes to copy.
  795. * @kbuf: Kernel buffer to copy from.
  796. * @ubuf: User buffer to copy into.
  797. *
  798. * This function gets transaction checkpointed GPR registers.
  799. *
  800. * When the transaction is active, 'ckpt_regs' holds all the checkpointed
  801. * GPR register values for the current transaction to fall back on if it
  802. * aborts in between. This function gets those checkpointed GPR registers.
  803. * The userspace interface buffer layout is as follows.
  804. *
  805. * struct data {
  806. * struct pt_regs ckpt_regs;
  807. * };
  808. */
  809. static int tm_cgpr_get(struct task_struct *target,
  810. const struct user_regset *regset,
  811. unsigned int pos, unsigned int count,
  812. void *kbuf, void __user *ubuf)
  813. {
  814. int ret;
  815. if (!cpu_has_feature(CPU_FTR_TM))
  816. return -ENODEV;
  817. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  818. return -ENODATA;
  819. flush_fp_to_thread(target);
  820. flush_altivec_to_thread(target);
  821. flush_tmregs_to_thread(target);
  822. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  823. &target->thread.ckpt_regs,
  824. 0, offsetof(struct pt_regs, msr));
  825. if (!ret) {
  826. unsigned long msr = get_user_ckpt_msr(target);
  827. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
  828. offsetof(struct pt_regs, msr),
  829. offsetof(struct pt_regs, msr) +
  830. sizeof(msr));
  831. }
  832. BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
  833. offsetof(struct pt_regs, msr) + sizeof(long));
  834. if (!ret)
  835. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  836. &target->thread.ckpt_regs.orig_gpr3,
  837. offsetof(struct pt_regs, orig_gpr3),
  838. sizeof(struct pt_regs));
  839. if (!ret)
  840. ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
  841. sizeof(struct pt_regs), -1);
  842. return ret;
  843. }
  844. /*
  845. * tm_cgpr_set - set the CGPR registers
  846. * @target: The target task.
  847. * @regset: The user regset structure.
  848. * @pos: The buffer position.
  849. * @count: Number of bytes to copy.
  850. * @kbuf: Kernel buffer to copy into.
  851. * @ubuf: User buffer to copy from.
  852. *
  853. * This function sets in transaction checkpointed GPR registers.
  854. *
  855. * When the transaction is active, 'ckpt_regs' holds the checkpointed
  856. * GPR register values for the current transaction to fall back on if it
  857. * aborts in between. This function sets those checkpointed GPR registers.
  858. * The userspace interface buffer layout is as follows.
  859. *
  860. * struct data {
  861. * struct pt_regs ckpt_regs;
  862. * };
  863. */
  864. static int tm_cgpr_set(struct task_struct *target,
  865. const struct user_regset *regset,
  866. unsigned int pos, unsigned int count,
  867. const void *kbuf, const void __user *ubuf)
  868. {
  869. unsigned long reg;
  870. int ret;
  871. if (!cpu_has_feature(CPU_FTR_TM))
  872. return -ENODEV;
  873. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  874. return -ENODATA;
  875. flush_fp_to_thread(target);
  876. flush_altivec_to_thread(target);
  877. flush_tmregs_to_thread(target);
  878. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  879. &target->thread.ckpt_regs,
  880. 0, PT_MSR * sizeof(reg));
  881. if (!ret && count > 0) {
  882. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
  883. PT_MSR * sizeof(reg),
  884. (PT_MSR + 1) * sizeof(reg));
  885. if (!ret)
  886. ret = set_user_ckpt_msr(target, reg);
  887. }
  888. BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
  889. offsetof(struct pt_regs, msr) + sizeof(long));
  890. if (!ret)
  891. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  892. &target->thread.ckpt_regs.orig_gpr3,
  893. PT_ORIG_R3 * sizeof(reg),
  894. (PT_MAX_PUT_REG + 1) * sizeof(reg));
  895. if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
  896. ret = user_regset_copyin_ignore(
  897. &pos, &count, &kbuf, &ubuf,
  898. (PT_MAX_PUT_REG + 1) * sizeof(reg),
  899. PT_TRAP * sizeof(reg));
  900. if (!ret && count > 0) {
  901. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
  902. PT_TRAP * sizeof(reg),
  903. (PT_TRAP + 1) * sizeof(reg));
  904. if (!ret)
  905. ret = set_user_ckpt_trap(target, reg);
  906. }
  907. if (!ret)
  908. ret = user_regset_copyin_ignore(
  909. &pos, &count, &kbuf, &ubuf,
  910. (PT_TRAP + 1) * sizeof(reg), -1);
  911. return ret;
  912. }
  913. /**
  914. * tm_cfpr_active - get active number of registers in CFPR
  915. * @target: The target task.
  916. * @regset: The user regset structure.
  917. *
  918. * This function checks for the active number of available
  919. * regisers in transaction checkpointed FPR category.
  920. */
  921. static int tm_cfpr_active(struct task_struct *target,
  922. const struct user_regset *regset)
  923. {
  924. if (!cpu_has_feature(CPU_FTR_TM))
  925. return -ENODEV;
  926. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  927. return 0;
  928. return regset->n;
  929. }
  930. /**
  931. * tm_cfpr_get - get CFPR registers
  932. * @target: The target task.
  933. * @regset: The user regset structure.
  934. * @pos: The buffer position.
  935. * @count: Number of bytes to copy.
  936. * @kbuf: Kernel buffer to copy from.
  937. * @ubuf: User buffer to copy into.
  938. *
  939. * This function gets in transaction checkpointed FPR registers.
  940. *
  941. * When the transaction is active 'fp_state' holds the checkpointed
  942. * values for the current transaction to fall back on if it aborts
  943. * in between. This function gets those checkpointed FPR registers.
  944. * The userspace interface buffer layout is as follows.
  945. *
  946. * struct data {
  947. * u64 fpr[32];
  948. * u64 fpscr;
  949. *};
  950. */
  951. static int tm_cfpr_get(struct task_struct *target,
  952. const struct user_regset *regset,
  953. unsigned int pos, unsigned int count,
  954. void *kbuf, void __user *ubuf)
  955. {
  956. u64 buf[33];
  957. int i;
  958. if (!cpu_has_feature(CPU_FTR_TM))
  959. return -ENODEV;
  960. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  961. return -ENODATA;
  962. flush_fp_to_thread(target);
  963. flush_altivec_to_thread(target);
  964. flush_tmregs_to_thread(target);
  965. /* copy to local buffer then write that out */
  966. for (i = 0; i < 32 ; i++)
  967. buf[i] = target->thread.TS_FPR(i);
  968. buf[32] = target->thread.fp_state.fpscr;
  969. return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
  970. }
  971. /**
  972. * tm_cfpr_set - set CFPR registers
  973. * @target: The target task.
  974. * @regset: The user regset structure.
  975. * @pos: The buffer position.
  976. * @count: Number of bytes to copy.
  977. * @kbuf: Kernel buffer to copy into.
  978. * @ubuf: User buffer to copy from.
  979. *
  980. * This function sets in transaction checkpointed FPR registers.
  981. *
  982. * When the transaction is active 'fp_state' holds the checkpointed
  983. * FPR register values for the current transaction to fall back on
  984. * if it aborts in between. This function sets these checkpointed
  985. * FPR registers. The userspace interface buffer layout is as follows.
  986. *
  987. * struct data {
  988. * u64 fpr[32];
  989. * u64 fpscr;
  990. *};
  991. */
  992. static int tm_cfpr_set(struct task_struct *target,
  993. const struct user_regset *regset,
  994. unsigned int pos, unsigned int count,
  995. const void *kbuf, const void __user *ubuf)
  996. {
  997. u64 buf[33];
  998. int i;
  999. if (!cpu_has_feature(CPU_FTR_TM))
  1000. return -ENODEV;
  1001. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1002. return -ENODATA;
  1003. flush_fp_to_thread(target);
  1004. flush_altivec_to_thread(target);
  1005. flush_tmregs_to_thread(target);
  1006. /* copy to local buffer then write that out */
  1007. i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
  1008. if (i)
  1009. return i;
  1010. for (i = 0; i < 32 ; i++)
  1011. target->thread.TS_FPR(i) = buf[i];
  1012. target->thread.fp_state.fpscr = buf[32];
  1013. return 0;
  1014. }
  1015. /**
  1016. * tm_cvmx_active - get active number of registers in CVMX
  1017. * @target: The target task.
  1018. * @regset: The user regset structure.
  1019. *
  1020. * This function checks for the active number of available
  1021. * regisers in checkpointed VMX category.
  1022. */
  1023. static int tm_cvmx_active(struct task_struct *target,
  1024. const struct user_regset *regset)
  1025. {
  1026. if (!cpu_has_feature(CPU_FTR_TM))
  1027. return -ENODEV;
  1028. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1029. return 0;
  1030. return regset->n;
  1031. }
  1032. /**
  1033. * tm_cvmx_get - get CMVX registers
  1034. * @target: The target task.
  1035. * @regset: The user regset structure.
  1036. * @pos: The buffer position.
  1037. * @count: Number of bytes to copy.
  1038. * @kbuf: Kernel buffer to copy from.
  1039. * @ubuf: User buffer to copy into.
  1040. *
  1041. * This function gets in transaction checkpointed VMX registers.
  1042. *
  1043. * When the transaction is active 'vr_state' and 'vr_save' hold
  1044. * the checkpointed values for the current transaction to fall
  1045. * back on if it aborts in between. The userspace interface buffer
  1046. * layout is as follows.
  1047. *
  1048. * struct data {
  1049. * vector128 vr[32];
  1050. * vector128 vscr;
  1051. * vector128 vrsave;
  1052. *};
  1053. */
  1054. static int tm_cvmx_get(struct task_struct *target,
  1055. const struct user_regset *regset,
  1056. unsigned int pos, unsigned int count,
  1057. void *kbuf, void __user *ubuf)
  1058. {
  1059. int ret;
  1060. BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
  1061. if (!cpu_has_feature(CPU_FTR_TM))
  1062. return -ENODEV;
  1063. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1064. return -ENODATA;
  1065. /* Flush the state */
  1066. flush_fp_to_thread(target);
  1067. flush_altivec_to_thread(target);
  1068. flush_tmregs_to_thread(target);
  1069. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1070. &target->thread.vr_state, 0,
  1071. 33 * sizeof(vector128));
  1072. if (!ret) {
  1073. /*
  1074. * Copy out only the low-order word of vrsave.
  1075. */
  1076. union {
  1077. elf_vrreg_t reg;
  1078. u32 word;
  1079. } vrsave;
  1080. memset(&vrsave, 0, sizeof(vrsave));
  1081. vrsave.word = target->thread.vrsave;
  1082. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
  1083. 33 * sizeof(vector128), -1);
  1084. }
  1085. return ret;
  1086. }
  1087. /**
  1088. * tm_cvmx_set - set CMVX registers
  1089. * @target: The target task.
  1090. * @regset: The user regset structure.
  1091. * @pos: The buffer position.
  1092. * @count: Number of bytes to copy.
  1093. * @kbuf: Kernel buffer to copy into.
  1094. * @ubuf: User buffer to copy from.
  1095. *
  1096. * This function sets in transaction checkpointed VMX registers.
  1097. *
  1098. * When the transaction is active 'vr_state' and 'vr_save' hold
  1099. * the checkpointed values for the current transaction to fall
  1100. * back on if it aborts in between. The userspace interface buffer
  1101. * layout is as follows.
  1102. *
  1103. * struct data {
  1104. * vector128 vr[32];
  1105. * vector128 vscr;
  1106. * vector128 vrsave;
  1107. *};
  1108. */
  1109. static int tm_cvmx_set(struct task_struct *target,
  1110. const struct user_regset *regset,
  1111. unsigned int pos, unsigned int count,
  1112. const void *kbuf, const void __user *ubuf)
  1113. {
  1114. int ret;
  1115. BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
  1116. if (!cpu_has_feature(CPU_FTR_TM))
  1117. return -ENODEV;
  1118. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1119. return -ENODATA;
  1120. flush_fp_to_thread(target);
  1121. flush_altivec_to_thread(target);
  1122. flush_tmregs_to_thread(target);
  1123. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1124. &target->thread.vr_state, 0,
  1125. 33 * sizeof(vector128));
  1126. if (!ret && count > 0) {
  1127. /*
  1128. * We use only the low-order word of vrsave.
  1129. */
  1130. union {
  1131. elf_vrreg_t reg;
  1132. u32 word;
  1133. } vrsave;
  1134. memset(&vrsave, 0, sizeof(vrsave));
  1135. vrsave.word = target->thread.vrsave;
  1136. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
  1137. 33 * sizeof(vector128), -1);
  1138. if (!ret)
  1139. target->thread.vrsave = vrsave.word;
  1140. }
  1141. return ret;
  1142. }
  1143. /**
  1144. * tm_cvsx_active - get active number of registers in CVSX
  1145. * @target: The target task.
  1146. * @regset: The user regset structure.
  1147. *
  1148. * This function checks for the active number of available
  1149. * regisers in transaction checkpointed VSX category.
  1150. */
  1151. static int tm_cvsx_active(struct task_struct *target,
  1152. const struct user_regset *regset)
  1153. {
  1154. if (!cpu_has_feature(CPU_FTR_TM))
  1155. return -ENODEV;
  1156. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1157. return 0;
  1158. flush_vsx_to_thread(target);
  1159. return target->thread.used_vsr ? regset->n : 0;
  1160. }
  1161. /**
  1162. * tm_cvsx_get - get CVSX registers
  1163. * @target: The target task.
  1164. * @regset: The user regset structure.
  1165. * @pos: The buffer position.
  1166. * @count: Number of bytes to copy.
  1167. * @kbuf: Kernel buffer to copy from.
  1168. * @ubuf: User buffer to copy into.
  1169. *
  1170. * This function gets in transaction checkpointed VSX registers.
  1171. *
  1172. * When the transaction is active 'fp_state' holds the checkpointed
  1173. * values for the current transaction to fall back on if it aborts
  1174. * in between. This function gets those checkpointed VSX registers.
  1175. * The userspace interface buffer layout is as follows.
  1176. *
  1177. * struct data {
  1178. * u64 vsx[32];
  1179. *};
  1180. */
  1181. static int tm_cvsx_get(struct task_struct *target,
  1182. const struct user_regset *regset,
  1183. unsigned int pos, unsigned int count,
  1184. void *kbuf, void __user *ubuf)
  1185. {
  1186. u64 buf[32];
  1187. int ret, i;
  1188. if (!cpu_has_feature(CPU_FTR_TM))
  1189. return -ENODEV;
  1190. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1191. return -ENODATA;
  1192. /* Flush the state */
  1193. flush_fp_to_thread(target);
  1194. flush_altivec_to_thread(target);
  1195. flush_tmregs_to_thread(target);
  1196. flush_vsx_to_thread(target);
  1197. for (i = 0; i < 32 ; i++)
  1198. buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
  1199. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1200. buf, 0, 32 * sizeof(double));
  1201. return ret;
  1202. }
  1203. /**
  1204. * tm_cvsx_set - set CFPR registers
  1205. * @target: The target task.
  1206. * @regset: The user regset structure.
  1207. * @pos: The buffer position.
  1208. * @count: Number of bytes to copy.
  1209. * @kbuf: Kernel buffer to copy into.
  1210. * @ubuf: User buffer to copy from.
  1211. *
  1212. * This function sets in transaction checkpointed VSX registers.
  1213. *
  1214. * When the transaction is active 'fp_state' holds the checkpointed
  1215. * VSX register values for the current transaction to fall back on
  1216. * if it aborts in between. This function sets these checkpointed
  1217. * FPR registers. The userspace interface buffer layout is as follows.
  1218. *
  1219. * struct data {
  1220. * u64 vsx[32];
  1221. *};
  1222. */
  1223. static int tm_cvsx_set(struct task_struct *target,
  1224. const struct user_regset *regset,
  1225. unsigned int pos, unsigned int count,
  1226. const void *kbuf, const void __user *ubuf)
  1227. {
  1228. u64 buf[32];
  1229. int ret, i;
  1230. if (!cpu_has_feature(CPU_FTR_TM))
  1231. return -ENODEV;
  1232. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1233. return -ENODATA;
  1234. /* Flush the state */
  1235. flush_fp_to_thread(target);
  1236. flush_altivec_to_thread(target);
  1237. flush_tmregs_to_thread(target);
  1238. flush_vsx_to_thread(target);
  1239. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1240. buf, 0, 32 * sizeof(double));
  1241. for (i = 0; i < 32 ; i++)
  1242. target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
  1243. return ret;
  1244. }
  1245. /**
  1246. * tm_spr_active - get active number of registers in TM SPR
  1247. * @target: The target task.
  1248. * @regset: The user regset structure.
  1249. *
  1250. * This function checks the active number of available
  1251. * regisers in the transactional memory SPR category.
  1252. */
  1253. static int tm_spr_active(struct task_struct *target,
  1254. const struct user_regset *regset)
  1255. {
  1256. if (!cpu_has_feature(CPU_FTR_TM))
  1257. return -ENODEV;
  1258. return regset->n;
  1259. }
  1260. /**
  1261. * tm_spr_get - get the TM related SPR registers
  1262. * @target: The target task.
  1263. * @regset: The user regset structure.
  1264. * @pos: The buffer position.
  1265. * @count: Number of bytes to copy.
  1266. * @kbuf: Kernel buffer to copy from.
  1267. * @ubuf: User buffer to copy into.
  1268. *
  1269. * This function gets transactional memory related SPR registers.
  1270. * The userspace interface buffer layout is as follows.
  1271. *
  1272. * struct {
  1273. * u64 tm_tfhar;
  1274. * u64 tm_texasr;
  1275. * u64 tm_tfiar;
  1276. * };
  1277. */
  1278. static int tm_spr_get(struct task_struct *target,
  1279. const struct user_regset *regset,
  1280. unsigned int pos, unsigned int count,
  1281. void *kbuf, void __user *ubuf)
  1282. {
  1283. int ret;
  1284. /* Build tests */
  1285. BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
  1286. BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
  1287. BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
  1288. if (!cpu_has_feature(CPU_FTR_TM))
  1289. return -ENODEV;
  1290. /* Flush the states */
  1291. flush_fp_to_thread(target);
  1292. flush_altivec_to_thread(target);
  1293. flush_tmregs_to_thread(target);
  1294. /* TFHAR register */
  1295. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1296. &target->thread.tm_tfhar, 0, sizeof(u64));
  1297. /* TEXASR register */
  1298. if (!ret)
  1299. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1300. &target->thread.tm_texasr, sizeof(u64),
  1301. 2 * sizeof(u64));
  1302. /* TFIAR register */
  1303. if (!ret)
  1304. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1305. &target->thread.tm_tfiar,
  1306. 2 * sizeof(u64), 3 * sizeof(u64));
  1307. return ret;
  1308. }
  1309. /**
  1310. * tm_spr_set - set the TM related SPR registers
  1311. * @target: The target task.
  1312. * @regset: The user regset structure.
  1313. * @pos: The buffer position.
  1314. * @count: Number of bytes to copy.
  1315. * @kbuf: Kernel buffer to copy into.
  1316. * @ubuf: User buffer to copy from.
  1317. *
  1318. * This function sets transactional memory related SPR registers.
  1319. * The userspace interface buffer layout is as follows.
  1320. *
  1321. * struct {
  1322. * u64 tm_tfhar;
  1323. * u64 tm_texasr;
  1324. * u64 tm_tfiar;
  1325. * };
  1326. */
  1327. static int tm_spr_set(struct task_struct *target,
  1328. const struct user_regset *regset,
  1329. unsigned int pos, unsigned int count,
  1330. const void *kbuf, const void __user *ubuf)
  1331. {
  1332. int ret;
  1333. /* Build tests */
  1334. BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
  1335. BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
  1336. BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
  1337. if (!cpu_has_feature(CPU_FTR_TM))
  1338. return -ENODEV;
  1339. /* Flush the states */
  1340. flush_fp_to_thread(target);
  1341. flush_altivec_to_thread(target);
  1342. flush_tmregs_to_thread(target);
  1343. /* TFHAR register */
  1344. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1345. &target->thread.tm_tfhar, 0, sizeof(u64));
  1346. /* TEXASR register */
  1347. if (!ret)
  1348. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1349. &target->thread.tm_texasr, sizeof(u64),
  1350. 2 * sizeof(u64));
  1351. /* TFIAR register */
  1352. if (!ret)
  1353. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1354. &target->thread.tm_tfiar,
  1355. 2 * sizeof(u64), 3 * sizeof(u64));
  1356. return ret;
  1357. }
  1358. static int tm_tar_active(struct task_struct *target,
  1359. const struct user_regset *regset)
  1360. {
  1361. if (!cpu_has_feature(CPU_FTR_TM))
  1362. return -ENODEV;
  1363. if (MSR_TM_ACTIVE(target->thread.regs->msr))
  1364. return regset->n;
  1365. return 0;
  1366. }
  1367. static int tm_tar_get(struct task_struct *target,
  1368. const struct user_regset *regset,
  1369. unsigned int pos, unsigned int count,
  1370. void *kbuf, void __user *ubuf)
  1371. {
  1372. int ret;
  1373. if (!cpu_has_feature(CPU_FTR_TM))
  1374. return -ENODEV;
  1375. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1376. return -ENODATA;
  1377. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1378. &target->thread.tm_tar, 0, sizeof(u64));
  1379. return ret;
  1380. }
  1381. static int tm_tar_set(struct task_struct *target,
  1382. const struct user_regset *regset,
  1383. unsigned int pos, unsigned int count,
  1384. const void *kbuf, const void __user *ubuf)
  1385. {
  1386. int ret;
  1387. if (!cpu_has_feature(CPU_FTR_TM))
  1388. return -ENODEV;
  1389. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1390. return -ENODATA;
  1391. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1392. &target->thread.tm_tar, 0, sizeof(u64));
  1393. return ret;
  1394. }
  1395. static int tm_ppr_active(struct task_struct *target,
  1396. const struct user_regset *regset)
  1397. {
  1398. if (!cpu_has_feature(CPU_FTR_TM))
  1399. return -ENODEV;
  1400. if (MSR_TM_ACTIVE(target->thread.regs->msr))
  1401. return regset->n;
  1402. return 0;
  1403. }
  1404. static int tm_ppr_get(struct task_struct *target,
  1405. const struct user_regset *regset,
  1406. unsigned int pos, unsigned int count,
  1407. void *kbuf, void __user *ubuf)
  1408. {
  1409. int ret;
  1410. if (!cpu_has_feature(CPU_FTR_TM))
  1411. return -ENODEV;
  1412. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1413. return -ENODATA;
  1414. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1415. &target->thread.tm_ppr, 0, sizeof(u64));
  1416. return ret;
  1417. }
  1418. static int tm_ppr_set(struct task_struct *target,
  1419. const struct user_regset *regset,
  1420. unsigned int pos, unsigned int count,
  1421. const void *kbuf, const void __user *ubuf)
  1422. {
  1423. int ret;
  1424. if (!cpu_has_feature(CPU_FTR_TM))
  1425. return -ENODEV;
  1426. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1427. return -ENODATA;
  1428. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1429. &target->thread.tm_ppr, 0, sizeof(u64));
  1430. return ret;
  1431. }
  1432. static int tm_dscr_active(struct task_struct *target,
  1433. const struct user_regset *regset)
  1434. {
  1435. if (!cpu_has_feature(CPU_FTR_TM))
  1436. return -ENODEV;
  1437. if (MSR_TM_ACTIVE(target->thread.regs->msr))
  1438. return regset->n;
  1439. return 0;
  1440. }
  1441. static int tm_dscr_get(struct task_struct *target,
  1442. const struct user_regset *regset,
  1443. unsigned int pos, unsigned int count,
  1444. void *kbuf, void __user *ubuf)
  1445. {
  1446. int ret;
  1447. if (!cpu_has_feature(CPU_FTR_TM))
  1448. return -ENODEV;
  1449. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1450. return -ENODATA;
  1451. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1452. &target->thread.tm_dscr, 0, sizeof(u64));
  1453. return ret;
  1454. }
  1455. static int tm_dscr_set(struct task_struct *target,
  1456. const struct user_regset *regset,
  1457. unsigned int pos, unsigned int count,
  1458. const void *kbuf, const void __user *ubuf)
  1459. {
  1460. int ret;
  1461. if (!cpu_has_feature(CPU_FTR_TM))
  1462. return -ENODEV;
  1463. if (!MSR_TM_ACTIVE(target->thread.regs->msr))
  1464. return -ENODATA;
  1465. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1466. &target->thread.tm_dscr, 0, sizeof(u64));
  1467. return ret;
  1468. }
  1469. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  1470. #ifdef CONFIG_PPC64
  1471. static int ppr_get(struct task_struct *target,
  1472. const struct user_regset *regset,
  1473. unsigned int pos, unsigned int count,
  1474. void *kbuf, void __user *ubuf)
  1475. {
  1476. int ret;
  1477. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1478. &target->thread.ppr, 0, sizeof(u64));
  1479. return ret;
  1480. }
  1481. static int ppr_set(struct task_struct *target,
  1482. const struct user_regset *regset,
  1483. unsigned int pos, unsigned int count,
  1484. const void *kbuf, const void __user *ubuf)
  1485. {
  1486. int ret;
  1487. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1488. &target->thread.ppr, 0, sizeof(u64));
  1489. return ret;
  1490. }
  1491. static int dscr_get(struct task_struct *target,
  1492. const struct user_regset *regset,
  1493. unsigned int pos, unsigned int count,
  1494. void *kbuf, void __user *ubuf)
  1495. {
  1496. int ret;
  1497. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1498. &target->thread.dscr, 0, sizeof(u64));
  1499. return ret;
  1500. }
  1501. static int dscr_set(struct task_struct *target,
  1502. const struct user_regset *regset,
  1503. unsigned int pos, unsigned int count,
  1504. const void *kbuf, const void __user *ubuf)
  1505. {
  1506. int ret;
  1507. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1508. &target->thread.dscr, 0, sizeof(u64));
  1509. return ret;
  1510. }
  1511. #endif
  1512. #ifdef CONFIG_PPC_BOOK3S_64
  1513. static int tar_get(struct task_struct *target,
  1514. const struct user_regset *regset,
  1515. unsigned int pos, unsigned int count,
  1516. void *kbuf, void __user *ubuf)
  1517. {
  1518. int ret;
  1519. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1520. &target->thread.tar, 0, sizeof(u64));
  1521. return ret;
  1522. }
  1523. static int tar_set(struct task_struct *target,
  1524. const struct user_regset *regset,
  1525. unsigned int pos, unsigned int count,
  1526. const void *kbuf, const void __user *ubuf)
  1527. {
  1528. int ret;
  1529. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1530. &target->thread.tar, 0, sizeof(u64));
  1531. return ret;
  1532. }
  1533. static int ebb_active(struct task_struct *target,
  1534. const struct user_regset *regset)
  1535. {
  1536. if (!cpu_has_feature(CPU_FTR_ARCH_207S))
  1537. return -ENODEV;
  1538. if (target->thread.used_ebb)
  1539. return regset->n;
  1540. return 0;
  1541. }
  1542. static int ebb_get(struct task_struct *target,
  1543. const struct user_regset *regset,
  1544. unsigned int pos, unsigned int count,
  1545. void *kbuf, void __user *ubuf)
  1546. {
  1547. /* Build tests */
  1548. BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
  1549. BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
  1550. if (!cpu_has_feature(CPU_FTR_ARCH_207S))
  1551. return -ENODEV;
  1552. if (!target->thread.used_ebb)
  1553. return -ENODATA;
  1554. return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1555. &target->thread.ebbrr, 0, 3 * sizeof(unsigned long));
  1556. }
  1557. static int ebb_set(struct task_struct *target,
  1558. const struct user_regset *regset,
  1559. unsigned int pos, unsigned int count,
  1560. const void *kbuf, const void __user *ubuf)
  1561. {
  1562. int ret = 0;
  1563. /* Build tests */
  1564. BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
  1565. BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
  1566. if (!cpu_has_feature(CPU_FTR_ARCH_207S))
  1567. return -ENODEV;
  1568. if (target->thread.used_ebb)
  1569. return -ENODATA;
  1570. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1571. &target->thread.ebbrr, 0, sizeof(unsigned long));
  1572. if (!ret)
  1573. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1574. &target->thread.ebbhr, sizeof(unsigned long),
  1575. 2 * sizeof(unsigned long));
  1576. if (!ret)
  1577. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1578. &target->thread.bescr,
  1579. 2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
  1580. return ret;
  1581. }
  1582. static int pmu_active(struct task_struct *target,
  1583. const struct user_regset *regset)
  1584. {
  1585. if (!cpu_has_feature(CPU_FTR_ARCH_207S))
  1586. return -ENODEV;
  1587. return regset->n;
  1588. }
  1589. static int pmu_get(struct task_struct *target,
  1590. const struct user_regset *regset,
  1591. unsigned int pos, unsigned int count,
  1592. void *kbuf, void __user *ubuf)
  1593. {
  1594. /* Build tests */
  1595. BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
  1596. BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
  1597. BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
  1598. BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
  1599. if (!cpu_has_feature(CPU_FTR_ARCH_207S))
  1600. return -ENODEV;
  1601. return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  1602. &target->thread.siar, 0,
  1603. 5 * sizeof(unsigned long));
  1604. }
  1605. static int pmu_set(struct task_struct *target,
  1606. const struct user_regset *regset,
  1607. unsigned int pos, unsigned int count,
  1608. const void *kbuf, const void __user *ubuf)
  1609. {
  1610. int ret = 0;
  1611. /* Build tests */
  1612. BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
  1613. BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
  1614. BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
  1615. BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
  1616. if (!cpu_has_feature(CPU_FTR_ARCH_207S))
  1617. return -ENODEV;
  1618. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1619. &target->thread.siar, 0,
  1620. sizeof(unsigned long));
  1621. if (!ret)
  1622. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1623. &target->thread.sdar, sizeof(unsigned long),
  1624. 2 * sizeof(unsigned long));
  1625. if (!ret)
  1626. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1627. &target->thread.sier, 2 * sizeof(unsigned long),
  1628. 3 * sizeof(unsigned long));
  1629. if (!ret)
  1630. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1631. &target->thread.mmcr2, 3 * sizeof(unsigned long),
  1632. 4 * sizeof(unsigned long));
  1633. if (!ret)
  1634. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  1635. &target->thread.mmcr0, 4 * sizeof(unsigned long),
  1636. 5 * sizeof(unsigned long));
  1637. return ret;
  1638. }
  1639. #endif
  1640. /*
  1641. * These are our native regset flavors.
  1642. */
  1643. enum powerpc_regset {
  1644. REGSET_GPR,
  1645. REGSET_FPR,
  1646. #ifdef CONFIG_ALTIVEC
  1647. REGSET_VMX,
  1648. #endif
  1649. #ifdef CONFIG_VSX
  1650. REGSET_VSX,
  1651. #endif
  1652. #ifdef CONFIG_SPE
  1653. REGSET_SPE,
  1654. #endif
  1655. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1656. REGSET_TM_CGPR, /* TM checkpointed GPR registers */
  1657. REGSET_TM_CFPR, /* TM checkpointed FPR registers */
  1658. REGSET_TM_CVMX, /* TM checkpointed VMX registers */
  1659. REGSET_TM_CVSX, /* TM checkpointed VSX registers */
  1660. REGSET_TM_SPR, /* TM specific SPR registers */
  1661. REGSET_TM_CTAR, /* TM checkpointed TAR register */
  1662. REGSET_TM_CPPR, /* TM checkpointed PPR register */
  1663. REGSET_TM_CDSCR, /* TM checkpointed DSCR register */
  1664. #endif
  1665. #ifdef CONFIG_PPC64
  1666. REGSET_PPR, /* PPR register */
  1667. REGSET_DSCR, /* DSCR register */
  1668. #endif
  1669. #ifdef CONFIG_PPC_BOOK3S_64
  1670. REGSET_TAR, /* TAR register */
  1671. REGSET_EBB, /* EBB registers */
  1672. REGSET_PMR, /* Performance Monitor Registers */
  1673. #endif
  1674. };
  1675. static const struct user_regset native_regsets[] = {
  1676. [REGSET_GPR] = {
  1677. .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
  1678. .size = sizeof(long), .align = sizeof(long),
  1679. .get = gpr_get, .set = gpr_set
  1680. },
  1681. [REGSET_FPR] = {
  1682. .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
  1683. .size = sizeof(double), .align = sizeof(double),
  1684. .get = fpr_get, .set = fpr_set
  1685. },
  1686. #ifdef CONFIG_ALTIVEC
  1687. [REGSET_VMX] = {
  1688. .core_note_type = NT_PPC_VMX, .n = 34,
  1689. .size = sizeof(vector128), .align = sizeof(vector128),
  1690. .active = vr_active, .get = vr_get, .set = vr_set
  1691. },
  1692. #endif
  1693. #ifdef CONFIG_VSX
  1694. [REGSET_VSX] = {
  1695. .core_note_type = NT_PPC_VSX, .n = 32,
  1696. .size = sizeof(double), .align = sizeof(double),
  1697. .active = vsr_active, .get = vsr_get, .set = vsr_set
  1698. },
  1699. #endif
  1700. #ifdef CONFIG_SPE
  1701. [REGSET_SPE] = {
  1702. .core_note_type = NT_PPC_SPE, .n = 35,
  1703. .size = sizeof(u32), .align = sizeof(u32),
  1704. .active = evr_active, .get = evr_get, .set = evr_set
  1705. },
  1706. #endif
  1707. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1708. [REGSET_TM_CGPR] = {
  1709. .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
  1710. .size = sizeof(long), .align = sizeof(long),
  1711. .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set
  1712. },
  1713. [REGSET_TM_CFPR] = {
  1714. .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
  1715. .size = sizeof(double), .align = sizeof(double),
  1716. .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
  1717. },
  1718. [REGSET_TM_CVMX] = {
  1719. .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
  1720. .size = sizeof(vector128), .align = sizeof(vector128),
  1721. .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
  1722. },
  1723. [REGSET_TM_CVSX] = {
  1724. .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
  1725. .size = sizeof(double), .align = sizeof(double),
  1726. .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
  1727. },
  1728. [REGSET_TM_SPR] = {
  1729. .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
  1730. .size = sizeof(u64), .align = sizeof(u64),
  1731. .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
  1732. },
  1733. [REGSET_TM_CTAR] = {
  1734. .core_note_type = NT_PPC_TM_CTAR, .n = 1,
  1735. .size = sizeof(u64), .align = sizeof(u64),
  1736. .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
  1737. },
  1738. [REGSET_TM_CPPR] = {
  1739. .core_note_type = NT_PPC_TM_CPPR, .n = 1,
  1740. .size = sizeof(u64), .align = sizeof(u64),
  1741. .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
  1742. },
  1743. [REGSET_TM_CDSCR] = {
  1744. .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
  1745. .size = sizeof(u64), .align = sizeof(u64),
  1746. .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
  1747. },
  1748. #endif
  1749. #ifdef CONFIG_PPC64
  1750. [REGSET_PPR] = {
  1751. .core_note_type = NT_PPC_PPR, .n = 1,
  1752. .size = sizeof(u64), .align = sizeof(u64),
  1753. .get = ppr_get, .set = ppr_set
  1754. },
  1755. [REGSET_DSCR] = {
  1756. .core_note_type = NT_PPC_DSCR, .n = 1,
  1757. .size = sizeof(u64), .align = sizeof(u64),
  1758. .get = dscr_get, .set = dscr_set
  1759. },
  1760. #endif
  1761. #ifdef CONFIG_PPC_BOOK3S_64
  1762. [REGSET_TAR] = {
  1763. .core_note_type = NT_PPC_TAR, .n = 1,
  1764. .size = sizeof(u64), .align = sizeof(u64),
  1765. .get = tar_get, .set = tar_set
  1766. },
  1767. [REGSET_EBB] = {
  1768. .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
  1769. .size = sizeof(u64), .align = sizeof(u64),
  1770. .active = ebb_active, .get = ebb_get, .set = ebb_set
  1771. },
  1772. [REGSET_PMR] = {
  1773. .core_note_type = NT_PPC_PMU, .n = ELF_NPMU,
  1774. .size = sizeof(u64), .align = sizeof(u64),
  1775. .active = pmu_active, .get = pmu_get, .set = pmu_set
  1776. },
  1777. #endif
  1778. };
  1779. static const struct user_regset_view user_ppc_native_view = {
  1780. .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
  1781. .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
  1782. };
  1783. #ifdef CONFIG_PPC64
  1784. #include <linux/compat.h>
  1785. static int gpr32_get_common(struct task_struct *target,
  1786. const struct user_regset *regset,
  1787. unsigned int pos, unsigned int count,
  1788. void *kbuf, void __user *ubuf, bool tm_active)
  1789. {
  1790. const unsigned long *regs = &target->thread.regs->gpr[0];
  1791. const unsigned long *ckpt_regs;
  1792. compat_ulong_t *k = kbuf;
  1793. compat_ulong_t __user *u = ubuf;
  1794. compat_ulong_t reg;
  1795. int i;
  1796. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1797. ckpt_regs = &target->thread.ckpt_regs.gpr[0];
  1798. #endif
  1799. if (tm_active) {
  1800. regs = ckpt_regs;
  1801. } else {
  1802. if (target->thread.regs == NULL)
  1803. return -EIO;
  1804. if (!FULL_REGS(target->thread.regs)) {
  1805. /*
  1806. * We have a partial register set.
  1807. * Fill 14-31 with bogus values.
  1808. */
  1809. for (i = 14; i < 32; i++)
  1810. target->thread.regs->gpr[i] = NV_REG_POISON;
  1811. }
  1812. }
  1813. pos /= sizeof(reg);
  1814. count /= sizeof(reg);
  1815. if (kbuf)
  1816. for (; count > 0 && pos < PT_MSR; --count)
  1817. *k++ = regs[pos++];
  1818. else
  1819. for (; count > 0 && pos < PT_MSR; --count)
  1820. if (__put_user((compat_ulong_t) regs[pos++], u++))
  1821. return -EFAULT;
  1822. if (count > 0 && pos == PT_MSR) {
  1823. reg = get_user_msr(target);
  1824. if (kbuf)
  1825. *k++ = reg;
  1826. else if (__put_user(reg, u++))
  1827. return -EFAULT;
  1828. ++pos;
  1829. --count;
  1830. }
  1831. if (kbuf)
  1832. for (; count > 0 && pos < PT_REGS_COUNT; --count)
  1833. *k++ = regs[pos++];
  1834. else
  1835. for (; count > 0 && pos < PT_REGS_COUNT; --count)
  1836. if (__put_user((compat_ulong_t) regs[pos++], u++))
  1837. return -EFAULT;
  1838. kbuf = k;
  1839. ubuf = u;
  1840. pos *= sizeof(reg);
  1841. count *= sizeof(reg);
  1842. return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
  1843. PT_REGS_COUNT * sizeof(reg), -1);
  1844. }
  1845. static int gpr32_set_common(struct task_struct *target,
  1846. const struct user_regset *regset,
  1847. unsigned int pos, unsigned int count,
  1848. const void *kbuf, const void __user *ubuf, bool tm_active)
  1849. {
  1850. unsigned long *regs = &target->thread.regs->gpr[0];
  1851. unsigned long *ckpt_regs;
  1852. const compat_ulong_t *k = kbuf;
  1853. const compat_ulong_t __user *u = ubuf;
  1854. compat_ulong_t reg;
  1855. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1856. ckpt_regs = &target->thread.ckpt_regs.gpr[0];
  1857. #endif
  1858. if (tm_active) {
  1859. regs = ckpt_regs;
  1860. } else {
  1861. regs = &target->thread.regs->gpr[0];
  1862. if (target->thread.regs == NULL)
  1863. return -EIO;
  1864. CHECK_FULL_REGS(target->thread.regs);
  1865. }
  1866. pos /= sizeof(reg);
  1867. count /= sizeof(reg);
  1868. if (kbuf)
  1869. for (; count > 0 && pos < PT_MSR; --count)
  1870. regs[pos++] = *k++;
  1871. else
  1872. for (; count > 0 && pos < PT_MSR; --count) {
  1873. if (__get_user(reg, u++))
  1874. return -EFAULT;
  1875. regs[pos++] = reg;
  1876. }
  1877. if (count > 0 && pos == PT_MSR) {
  1878. if (kbuf)
  1879. reg = *k++;
  1880. else if (__get_user(reg, u++))
  1881. return -EFAULT;
  1882. set_user_msr(target, reg);
  1883. ++pos;
  1884. --count;
  1885. }
  1886. if (kbuf) {
  1887. for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
  1888. regs[pos++] = *k++;
  1889. for (; count > 0 && pos < PT_TRAP; --count, ++pos)
  1890. ++k;
  1891. } else {
  1892. for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
  1893. if (__get_user(reg, u++))
  1894. return -EFAULT;
  1895. regs[pos++] = reg;
  1896. }
  1897. for (; count > 0 && pos < PT_TRAP; --count, ++pos)
  1898. if (__get_user(reg, u++))
  1899. return -EFAULT;
  1900. }
  1901. if (count > 0 && pos == PT_TRAP) {
  1902. if (kbuf)
  1903. reg = *k++;
  1904. else if (__get_user(reg, u++))
  1905. return -EFAULT;
  1906. set_user_trap(target, reg);
  1907. ++pos;
  1908. --count;
  1909. }
  1910. kbuf = k;
  1911. ubuf = u;
  1912. pos *= sizeof(reg);
  1913. count *= sizeof(reg);
  1914. return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
  1915. (PT_TRAP + 1) * sizeof(reg), -1);
  1916. }
  1917. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1918. static int tm_cgpr32_get(struct task_struct *target,
  1919. const struct user_regset *regset,
  1920. unsigned int pos, unsigned int count,
  1921. void *kbuf, void __user *ubuf)
  1922. {
  1923. return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 1);
  1924. }
  1925. static int tm_cgpr32_set(struct task_struct *target,
  1926. const struct user_regset *regset,
  1927. unsigned int pos, unsigned int count,
  1928. const void *kbuf, const void __user *ubuf)
  1929. {
  1930. return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 1);
  1931. }
  1932. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  1933. static int gpr32_get(struct task_struct *target,
  1934. const struct user_regset *regset,
  1935. unsigned int pos, unsigned int count,
  1936. void *kbuf, void __user *ubuf)
  1937. {
  1938. return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 0);
  1939. }
  1940. static int gpr32_set(struct task_struct *target,
  1941. const struct user_regset *regset,
  1942. unsigned int pos, unsigned int count,
  1943. const void *kbuf, const void __user *ubuf)
  1944. {
  1945. return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 0);
  1946. }
  1947. /*
  1948. * These are the regset flavors matching the CONFIG_PPC32 native set.
  1949. */
  1950. static const struct user_regset compat_regsets[] = {
  1951. [REGSET_GPR] = {
  1952. .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
  1953. .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
  1954. .get = gpr32_get, .set = gpr32_set
  1955. },
  1956. [REGSET_FPR] = {
  1957. .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
  1958. .size = sizeof(double), .align = sizeof(double),
  1959. .get = fpr_get, .set = fpr_set
  1960. },
  1961. #ifdef CONFIG_ALTIVEC
  1962. [REGSET_VMX] = {
  1963. .core_note_type = NT_PPC_VMX, .n = 34,
  1964. .size = sizeof(vector128), .align = sizeof(vector128),
  1965. .active = vr_active, .get = vr_get, .set = vr_set
  1966. },
  1967. #endif
  1968. #ifdef CONFIG_SPE
  1969. [REGSET_SPE] = {
  1970. .core_note_type = NT_PPC_SPE, .n = 35,
  1971. .size = sizeof(u32), .align = sizeof(u32),
  1972. .active = evr_active, .get = evr_get, .set = evr_set
  1973. },
  1974. #endif
  1975. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1976. [REGSET_TM_CGPR] = {
  1977. .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
  1978. .size = sizeof(long), .align = sizeof(long),
  1979. .active = tm_cgpr_active,
  1980. .get = tm_cgpr32_get, .set = tm_cgpr32_set
  1981. },
  1982. [REGSET_TM_CFPR] = {
  1983. .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
  1984. .size = sizeof(double), .align = sizeof(double),
  1985. .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
  1986. },
  1987. [REGSET_TM_CVMX] = {
  1988. .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
  1989. .size = sizeof(vector128), .align = sizeof(vector128),
  1990. .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
  1991. },
  1992. [REGSET_TM_CVSX] = {
  1993. .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
  1994. .size = sizeof(double), .align = sizeof(double),
  1995. .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
  1996. },
  1997. [REGSET_TM_SPR] = {
  1998. .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
  1999. .size = sizeof(u64), .align = sizeof(u64),
  2000. .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
  2001. },
  2002. [REGSET_TM_CTAR] = {
  2003. .core_note_type = NT_PPC_TM_CTAR, .n = 1,
  2004. .size = sizeof(u64), .align = sizeof(u64),
  2005. .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
  2006. },
  2007. [REGSET_TM_CPPR] = {
  2008. .core_note_type = NT_PPC_TM_CPPR, .n = 1,
  2009. .size = sizeof(u64), .align = sizeof(u64),
  2010. .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
  2011. },
  2012. [REGSET_TM_CDSCR] = {
  2013. .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
  2014. .size = sizeof(u64), .align = sizeof(u64),
  2015. .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
  2016. },
  2017. #endif
  2018. #ifdef CONFIG_PPC64
  2019. [REGSET_PPR] = {
  2020. .core_note_type = NT_PPC_PPR, .n = 1,
  2021. .size = sizeof(u64), .align = sizeof(u64),
  2022. .get = ppr_get, .set = ppr_set
  2023. },
  2024. [REGSET_DSCR] = {
  2025. .core_note_type = NT_PPC_DSCR, .n = 1,
  2026. .size = sizeof(u64), .align = sizeof(u64),
  2027. .get = dscr_get, .set = dscr_set
  2028. },
  2029. #endif
  2030. #ifdef CONFIG_PPC_BOOK3S_64
  2031. [REGSET_TAR] = {
  2032. .core_note_type = NT_PPC_TAR, .n = 1,
  2033. .size = sizeof(u64), .align = sizeof(u64),
  2034. .get = tar_get, .set = tar_set
  2035. },
  2036. [REGSET_EBB] = {
  2037. .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
  2038. .size = sizeof(u64), .align = sizeof(u64),
  2039. .active = ebb_active, .get = ebb_get, .set = ebb_set
  2040. },
  2041. #endif
  2042. };
  2043. static const struct user_regset_view user_ppc_compat_view = {
  2044. .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
  2045. .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
  2046. };
  2047. #endif /* CONFIG_PPC64 */
  2048. const struct user_regset_view *task_user_regset_view(struct task_struct *task)
  2049. {
  2050. #ifdef CONFIG_PPC64
  2051. if (test_tsk_thread_flag(task, TIF_32BIT))
  2052. return &user_ppc_compat_view;
  2053. #endif
  2054. return &user_ppc_native_view;
  2055. }
  2056. void user_enable_single_step(struct task_struct *task)
  2057. {
  2058. struct pt_regs *regs = task->thread.regs;
  2059. if (regs != NULL) {
  2060. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2061. task->thread.debug.dbcr0 &= ~DBCR0_BT;
  2062. task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
  2063. regs->msr |= MSR_DE;
  2064. #else
  2065. regs->msr &= ~MSR_BE;
  2066. regs->msr |= MSR_SE;
  2067. #endif
  2068. }
  2069. set_tsk_thread_flag(task, TIF_SINGLESTEP);
  2070. }
  2071. void user_enable_block_step(struct task_struct *task)
  2072. {
  2073. struct pt_regs *regs = task->thread.regs;
  2074. if (regs != NULL) {
  2075. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2076. task->thread.debug.dbcr0 &= ~DBCR0_IC;
  2077. task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
  2078. regs->msr |= MSR_DE;
  2079. #else
  2080. regs->msr &= ~MSR_SE;
  2081. regs->msr |= MSR_BE;
  2082. #endif
  2083. }
  2084. set_tsk_thread_flag(task, TIF_SINGLESTEP);
  2085. }
  2086. void user_disable_single_step(struct task_struct *task)
  2087. {
  2088. struct pt_regs *regs = task->thread.regs;
  2089. if (regs != NULL) {
  2090. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2091. /*
  2092. * The logic to disable single stepping should be as
  2093. * simple as turning off the Instruction Complete flag.
  2094. * And, after doing so, if all debug flags are off, turn
  2095. * off DBCR0(IDM) and MSR(DE) .... Torez
  2096. */
  2097. task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
  2098. /*
  2099. * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
  2100. */
  2101. if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
  2102. task->thread.debug.dbcr1)) {
  2103. /*
  2104. * All debug events were off.....
  2105. */
  2106. task->thread.debug.dbcr0 &= ~DBCR0_IDM;
  2107. regs->msr &= ~MSR_DE;
  2108. }
  2109. #else
  2110. regs->msr &= ~(MSR_SE | MSR_BE);
  2111. #endif
  2112. }
  2113. clear_tsk_thread_flag(task, TIF_SINGLESTEP);
  2114. }
  2115. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2116. void ptrace_triggered(struct perf_event *bp,
  2117. struct perf_sample_data *data, struct pt_regs *regs)
  2118. {
  2119. struct perf_event_attr attr;
  2120. /*
  2121. * Disable the breakpoint request here since ptrace has defined a
  2122. * one-shot behaviour for breakpoint exceptions in PPC64.
  2123. * The SIGTRAP signal is generated automatically for us in do_dabr().
  2124. * We don't have to do anything about that here
  2125. */
  2126. attr = bp->attr;
  2127. attr.disabled = true;
  2128. modify_user_hw_breakpoint(bp, &attr);
  2129. }
  2130. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2131. static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
  2132. unsigned long data)
  2133. {
  2134. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2135. int ret;
  2136. struct thread_struct *thread = &(task->thread);
  2137. struct perf_event *bp;
  2138. struct perf_event_attr attr;
  2139. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2140. #ifndef CONFIG_PPC_ADV_DEBUG_REGS
  2141. struct arch_hw_breakpoint hw_brk;
  2142. #endif
  2143. /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
  2144. * For embedded processors we support one DAC and no IAC's at the
  2145. * moment.
  2146. */
  2147. if (addr > 0)
  2148. return -EINVAL;
  2149. /* The bottom 3 bits in dabr are flags */
  2150. if ((data & ~0x7UL) >= TASK_SIZE)
  2151. return -EIO;
  2152. #ifndef CONFIG_PPC_ADV_DEBUG_REGS
  2153. /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
  2154. * It was assumed, on previous implementations, that 3 bits were
  2155. * passed together with the data address, fitting the design of the
  2156. * DABR register, as follows:
  2157. *
  2158. * bit 0: Read flag
  2159. * bit 1: Write flag
  2160. * bit 2: Breakpoint translation
  2161. *
  2162. * Thus, we use them here as so.
  2163. */
  2164. /* Ensure breakpoint translation bit is set */
  2165. if (data && !(data & HW_BRK_TYPE_TRANSLATE))
  2166. return -EIO;
  2167. hw_brk.address = data & (~HW_BRK_TYPE_DABR);
  2168. hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
  2169. hw_brk.len = 8;
  2170. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2171. bp = thread->ptrace_bps[0];
  2172. if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) {
  2173. if (bp) {
  2174. unregister_hw_breakpoint(bp);
  2175. thread->ptrace_bps[0] = NULL;
  2176. }
  2177. return 0;
  2178. }
  2179. if (bp) {
  2180. attr = bp->attr;
  2181. attr.bp_addr = hw_brk.address;
  2182. arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
  2183. /* Enable breakpoint */
  2184. attr.disabled = false;
  2185. ret = modify_user_hw_breakpoint(bp, &attr);
  2186. if (ret) {
  2187. return ret;
  2188. }
  2189. thread->ptrace_bps[0] = bp;
  2190. thread->hw_brk = hw_brk;
  2191. return 0;
  2192. }
  2193. /* Create a new breakpoint request if one doesn't exist already */
  2194. hw_breakpoint_init(&attr);
  2195. attr.bp_addr = hw_brk.address;
  2196. arch_bp_generic_fields(hw_brk.type,
  2197. &attr.bp_type);
  2198. thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
  2199. ptrace_triggered, NULL, task);
  2200. if (IS_ERR(bp)) {
  2201. thread->ptrace_bps[0] = NULL;
  2202. return PTR_ERR(bp);
  2203. }
  2204. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2205. task->thread.hw_brk = hw_brk;
  2206. #else /* CONFIG_PPC_ADV_DEBUG_REGS */
  2207. /* As described above, it was assumed 3 bits were passed with the data
  2208. * address, but we will assume only the mode bits will be passed
  2209. * as to not cause alignment restrictions for DAC-based processors.
  2210. */
  2211. /* DAC's hold the whole address without any mode flags */
  2212. task->thread.debug.dac1 = data & ~0x3UL;
  2213. if (task->thread.debug.dac1 == 0) {
  2214. dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
  2215. if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
  2216. task->thread.debug.dbcr1)) {
  2217. task->thread.regs->msr &= ~MSR_DE;
  2218. task->thread.debug.dbcr0 &= ~DBCR0_IDM;
  2219. }
  2220. return 0;
  2221. }
  2222. /* Read or Write bits must be set */
  2223. if (!(data & 0x3UL))
  2224. return -EINVAL;
  2225. /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
  2226. register */
  2227. task->thread.debug.dbcr0 |= DBCR0_IDM;
  2228. /* Check for write and read flags and set DBCR0
  2229. accordingly */
  2230. dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
  2231. if (data & 0x1UL)
  2232. dbcr_dac(task) |= DBCR_DAC1R;
  2233. if (data & 0x2UL)
  2234. dbcr_dac(task) |= DBCR_DAC1W;
  2235. task->thread.regs->msr |= MSR_DE;
  2236. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  2237. return 0;
  2238. }
  2239. /*
  2240. * Called by kernel/ptrace.c when detaching..
  2241. *
  2242. * Make sure single step bits etc are not set.
  2243. */
  2244. void ptrace_disable(struct task_struct *child)
  2245. {
  2246. /* make sure the single step bit is not set. */
  2247. user_disable_single_step(child);
  2248. }
  2249. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2250. static long set_instruction_bp(struct task_struct *child,
  2251. struct ppc_hw_breakpoint *bp_info)
  2252. {
  2253. int slot;
  2254. int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
  2255. int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
  2256. int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
  2257. int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
  2258. if (dbcr_iac_range(child) & DBCR_IAC12MODE)
  2259. slot2_in_use = 1;
  2260. if (dbcr_iac_range(child) & DBCR_IAC34MODE)
  2261. slot4_in_use = 1;
  2262. if (bp_info->addr >= TASK_SIZE)
  2263. return -EIO;
  2264. if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
  2265. /* Make sure range is valid. */
  2266. if (bp_info->addr2 >= TASK_SIZE)
  2267. return -EIO;
  2268. /* We need a pair of IAC regsisters */
  2269. if ((!slot1_in_use) && (!slot2_in_use)) {
  2270. slot = 1;
  2271. child->thread.debug.iac1 = bp_info->addr;
  2272. child->thread.debug.iac2 = bp_info->addr2;
  2273. child->thread.debug.dbcr0 |= DBCR0_IAC1;
  2274. if (bp_info->addr_mode ==
  2275. PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
  2276. dbcr_iac_range(child) |= DBCR_IAC12X;
  2277. else
  2278. dbcr_iac_range(child) |= DBCR_IAC12I;
  2279. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  2280. } else if ((!slot3_in_use) && (!slot4_in_use)) {
  2281. slot = 3;
  2282. child->thread.debug.iac3 = bp_info->addr;
  2283. child->thread.debug.iac4 = bp_info->addr2;
  2284. child->thread.debug.dbcr0 |= DBCR0_IAC3;
  2285. if (bp_info->addr_mode ==
  2286. PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
  2287. dbcr_iac_range(child) |= DBCR_IAC34X;
  2288. else
  2289. dbcr_iac_range(child) |= DBCR_IAC34I;
  2290. #endif
  2291. } else
  2292. return -ENOSPC;
  2293. } else {
  2294. /* We only need one. If possible leave a pair free in
  2295. * case a range is needed later
  2296. */
  2297. if (!slot1_in_use) {
  2298. /*
  2299. * Don't use iac1 if iac1-iac2 are free and either
  2300. * iac3 or iac4 (but not both) are free
  2301. */
  2302. if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
  2303. slot = 1;
  2304. child->thread.debug.iac1 = bp_info->addr;
  2305. child->thread.debug.dbcr0 |= DBCR0_IAC1;
  2306. goto out;
  2307. }
  2308. }
  2309. if (!slot2_in_use) {
  2310. slot = 2;
  2311. child->thread.debug.iac2 = bp_info->addr;
  2312. child->thread.debug.dbcr0 |= DBCR0_IAC2;
  2313. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  2314. } else if (!slot3_in_use) {
  2315. slot = 3;
  2316. child->thread.debug.iac3 = bp_info->addr;
  2317. child->thread.debug.dbcr0 |= DBCR0_IAC3;
  2318. } else if (!slot4_in_use) {
  2319. slot = 4;
  2320. child->thread.debug.iac4 = bp_info->addr;
  2321. child->thread.debug.dbcr0 |= DBCR0_IAC4;
  2322. #endif
  2323. } else
  2324. return -ENOSPC;
  2325. }
  2326. out:
  2327. child->thread.debug.dbcr0 |= DBCR0_IDM;
  2328. child->thread.regs->msr |= MSR_DE;
  2329. return slot;
  2330. }
  2331. static int del_instruction_bp(struct task_struct *child, int slot)
  2332. {
  2333. switch (slot) {
  2334. case 1:
  2335. if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
  2336. return -ENOENT;
  2337. if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
  2338. /* address range - clear slots 1 & 2 */
  2339. child->thread.debug.iac2 = 0;
  2340. dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
  2341. }
  2342. child->thread.debug.iac1 = 0;
  2343. child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
  2344. break;
  2345. case 2:
  2346. if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
  2347. return -ENOENT;
  2348. if (dbcr_iac_range(child) & DBCR_IAC12MODE)
  2349. /* used in a range */
  2350. return -EINVAL;
  2351. child->thread.debug.iac2 = 0;
  2352. child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
  2353. break;
  2354. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  2355. case 3:
  2356. if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
  2357. return -ENOENT;
  2358. if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
  2359. /* address range - clear slots 3 & 4 */
  2360. child->thread.debug.iac4 = 0;
  2361. dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
  2362. }
  2363. child->thread.debug.iac3 = 0;
  2364. child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
  2365. break;
  2366. case 4:
  2367. if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
  2368. return -ENOENT;
  2369. if (dbcr_iac_range(child) & DBCR_IAC34MODE)
  2370. /* Used in a range */
  2371. return -EINVAL;
  2372. child->thread.debug.iac4 = 0;
  2373. child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
  2374. break;
  2375. #endif
  2376. default:
  2377. return -EINVAL;
  2378. }
  2379. return 0;
  2380. }
  2381. static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
  2382. {
  2383. int byte_enable =
  2384. (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
  2385. & 0xf;
  2386. int condition_mode =
  2387. bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
  2388. int slot;
  2389. if (byte_enable && (condition_mode == 0))
  2390. return -EINVAL;
  2391. if (bp_info->addr >= TASK_SIZE)
  2392. return -EIO;
  2393. if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
  2394. slot = 1;
  2395. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
  2396. dbcr_dac(child) |= DBCR_DAC1R;
  2397. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
  2398. dbcr_dac(child) |= DBCR_DAC1W;
  2399. child->thread.debug.dac1 = (unsigned long)bp_info->addr;
  2400. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  2401. if (byte_enable) {
  2402. child->thread.debug.dvc1 =
  2403. (unsigned long)bp_info->condition_value;
  2404. child->thread.debug.dbcr2 |=
  2405. ((byte_enable << DBCR2_DVC1BE_SHIFT) |
  2406. (condition_mode << DBCR2_DVC1M_SHIFT));
  2407. }
  2408. #endif
  2409. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  2410. } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
  2411. /* Both dac1 and dac2 are part of a range */
  2412. return -ENOSPC;
  2413. #endif
  2414. } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
  2415. slot = 2;
  2416. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
  2417. dbcr_dac(child) |= DBCR_DAC2R;
  2418. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
  2419. dbcr_dac(child) |= DBCR_DAC2W;
  2420. child->thread.debug.dac2 = (unsigned long)bp_info->addr;
  2421. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  2422. if (byte_enable) {
  2423. child->thread.debug.dvc2 =
  2424. (unsigned long)bp_info->condition_value;
  2425. child->thread.debug.dbcr2 |=
  2426. ((byte_enable << DBCR2_DVC2BE_SHIFT) |
  2427. (condition_mode << DBCR2_DVC2M_SHIFT));
  2428. }
  2429. #endif
  2430. } else
  2431. return -ENOSPC;
  2432. child->thread.debug.dbcr0 |= DBCR0_IDM;
  2433. child->thread.regs->msr |= MSR_DE;
  2434. return slot + 4;
  2435. }
  2436. static int del_dac(struct task_struct *child, int slot)
  2437. {
  2438. if (slot == 1) {
  2439. if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
  2440. return -ENOENT;
  2441. child->thread.debug.dac1 = 0;
  2442. dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
  2443. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  2444. if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
  2445. child->thread.debug.dac2 = 0;
  2446. child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
  2447. }
  2448. child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
  2449. #endif
  2450. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  2451. child->thread.debug.dvc1 = 0;
  2452. #endif
  2453. } else if (slot == 2) {
  2454. if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
  2455. return -ENOENT;
  2456. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  2457. if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
  2458. /* Part of a range */
  2459. return -EINVAL;
  2460. child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
  2461. #endif
  2462. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  2463. child->thread.debug.dvc2 = 0;
  2464. #endif
  2465. child->thread.debug.dac2 = 0;
  2466. dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
  2467. } else
  2468. return -EINVAL;
  2469. return 0;
  2470. }
  2471. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  2472. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  2473. static int set_dac_range(struct task_struct *child,
  2474. struct ppc_hw_breakpoint *bp_info)
  2475. {
  2476. int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
  2477. /* We don't allow range watchpoints to be used with DVC */
  2478. if (bp_info->condition_mode)
  2479. return -EINVAL;
  2480. /*
  2481. * Best effort to verify the address range. The user/supervisor bits
  2482. * prevent trapping in kernel space, but let's fail on an obvious bad
  2483. * range. The simple test on the mask is not fool-proof, and any
  2484. * exclusive range will spill over into kernel space.
  2485. */
  2486. if (bp_info->addr >= TASK_SIZE)
  2487. return -EIO;
  2488. if (mode == PPC_BREAKPOINT_MODE_MASK) {
  2489. /*
  2490. * dac2 is a bitmask. Don't allow a mask that makes a
  2491. * kernel space address from a valid dac1 value
  2492. */
  2493. if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
  2494. return -EIO;
  2495. } else {
  2496. /*
  2497. * For range breakpoints, addr2 must also be a valid address
  2498. */
  2499. if (bp_info->addr2 >= TASK_SIZE)
  2500. return -EIO;
  2501. }
  2502. if (child->thread.debug.dbcr0 &
  2503. (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
  2504. return -ENOSPC;
  2505. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
  2506. child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
  2507. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
  2508. child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
  2509. child->thread.debug.dac1 = bp_info->addr;
  2510. child->thread.debug.dac2 = bp_info->addr2;
  2511. if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
  2512. child->thread.debug.dbcr2 |= DBCR2_DAC12M;
  2513. else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
  2514. child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
  2515. else /* PPC_BREAKPOINT_MODE_MASK */
  2516. child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
  2517. child->thread.regs->msr |= MSR_DE;
  2518. return 5;
  2519. }
  2520. #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
  2521. static long ppc_set_hwdebug(struct task_struct *child,
  2522. struct ppc_hw_breakpoint *bp_info)
  2523. {
  2524. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2525. int len = 0;
  2526. struct thread_struct *thread = &(child->thread);
  2527. struct perf_event *bp;
  2528. struct perf_event_attr attr;
  2529. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2530. #ifndef CONFIG_PPC_ADV_DEBUG_REGS
  2531. struct arch_hw_breakpoint brk;
  2532. #endif
  2533. if (bp_info->version != 1)
  2534. return -ENOTSUPP;
  2535. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2536. /*
  2537. * Check for invalid flags and combinations
  2538. */
  2539. if ((bp_info->trigger_type == 0) ||
  2540. (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
  2541. PPC_BREAKPOINT_TRIGGER_RW)) ||
  2542. (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
  2543. (bp_info->condition_mode &
  2544. ~(PPC_BREAKPOINT_CONDITION_MODE |
  2545. PPC_BREAKPOINT_CONDITION_BE_ALL)))
  2546. return -EINVAL;
  2547. #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
  2548. if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
  2549. return -EINVAL;
  2550. #endif
  2551. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
  2552. if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
  2553. (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
  2554. return -EINVAL;
  2555. return set_instruction_bp(child, bp_info);
  2556. }
  2557. if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
  2558. return set_dac(child, bp_info);
  2559. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  2560. return set_dac_range(child, bp_info);
  2561. #else
  2562. return -EINVAL;
  2563. #endif
  2564. #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
  2565. /*
  2566. * We only support one data breakpoint
  2567. */
  2568. if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
  2569. (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
  2570. bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
  2571. return -EINVAL;
  2572. if ((unsigned long)bp_info->addr >= TASK_SIZE)
  2573. return -EIO;
  2574. brk.address = bp_info->addr & ~7UL;
  2575. brk.type = HW_BRK_TYPE_TRANSLATE;
  2576. brk.len = 8;
  2577. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
  2578. brk.type |= HW_BRK_TYPE_READ;
  2579. if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
  2580. brk.type |= HW_BRK_TYPE_WRITE;
  2581. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2582. /*
  2583. * Check if the request is for 'range' breakpoints. We can
  2584. * support it if range < 8 bytes.
  2585. */
  2586. if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
  2587. len = bp_info->addr2 - bp_info->addr;
  2588. else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
  2589. len = 1;
  2590. else
  2591. return -EINVAL;
  2592. bp = thread->ptrace_bps[0];
  2593. if (bp)
  2594. return -ENOSPC;
  2595. /* Create a new breakpoint request if one doesn't exist already */
  2596. hw_breakpoint_init(&attr);
  2597. attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
  2598. attr.bp_len = len;
  2599. arch_bp_generic_fields(brk.type, &attr.bp_type);
  2600. thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
  2601. ptrace_triggered, NULL, child);
  2602. if (IS_ERR(bp)) {
  2603. thread->ptrace_bps[0] = NULL;
  2604. return PTR_ERR(bp);
  2605. }
  2606. return 1;
  2607. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2608. if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
  2609. return -EINVAL;
  2610. if (child->thread.hw_brk.address)
  2611. return -ENOSPC;
  2612. child->thread.hw_brk = brk;
  2613. return 1;
  2614. #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
  2615. }
  2616. static long ppc_del_hwdebug(struct task_struct *child, long data)
  2617. {
  2618. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2619. int ret = 0;
  2620. struct thread_struct *thread = &(child->thread);
  2621. struct perf_event *bp;
  2622. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2623. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2624. int rc;
  2625. if (data <= 4)
  2626. rc = del_instruction_bp(child, (int)data);
  2627. else
  2628. rc = del_dac(child, (int)data - 4);
  2629. if (!rc) {
  2630. if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
  2631. child->thread.debug.dbcr1)) {
  2632. child->thread.debug.dbcr0 &= ~DBCR0_IDM;
  2633. child->thread.regs->msr &= ~MSR_DE;
  2634. }
  2635. }
  2636. return rc;
  2637. #else
  2638. if (data != 1)
  2639. return -EINVAL;
  2640. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2641. bp = thread->ptrace_bps[0];
  2642. if (bp) {
  2643. unregister_hw_breakpoint(bp);
  2644. thread->ptrace_bps[0] = NULL;
  2645. } else
  2646. ret = -ENOENT;
  2647. return ret;
  2648. #else /* CONFIG_HAVE_HW_BREAKPOINT */
  2649. if (child->thread.hw_brk.address == 0)
  2650. return -ENOENT;
  2651. child->thread.hw_brk.address = 0;
  2652. child->thread.hw_brk.type = 0;
  2653. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2654. return 0;
  2655. #endif
  2656. }
  2657. long arch_ptrace(struct task_struct *child, long request,
  2658. unsigned long addr, unsigned long data)
  2659. {
  2660. int ret = -EPERM;
  2661. void __user *datavp = (void __user *) data;
  2662. unsigned long __user *datalp = datavp;
  2663. switch (request) {
  2664. /* read the word at location addr in the USER area. */
  2665. case PTRACE_PEEKUSR: {
  2666. unsigned long index, tmp;
  2667. ret = -EIO;
  2668. /* convert to index and check */
  2669. #ifdef CONFIG_PPC32
  2670. index = addr >> 2;
  2671. if ((addr & 3) || (index > PT_FPSCR)
  2672. || (child->thread.regs == NULL))
  2673. #else
  2674. index = addr >> 3;
  2675. if ((addr & 7) || (index > PT_FPSCR))
  2676. #endif
  2677. break;
  2678. CHECK_FULL_REGS(child->thread.regs);
  2679. if (index < PT_FPR0) {
  2680. ret = ptrace_get_reg(child, (int) index, &tmp);
  2681. if (ret)
  2682. break;
  2683. } else {
  2684. unsigned int fpidx = index - PT_FPR0;
  2685. flush_fp_to_thread(child);
  2686. if (fpidx < (PT_FPSCR - PT_FPR0))
  2687. memcpy(&tmp, &child->thread.TS_FPR(fpidx),
  2688. sizeof(long));
  2689. else
  2690. tmp = child->thread.fp_state.fpscr;
  2691. }
  2692. ret = put_user(tmp, datalp);
  2693. break;
  2694. }
  2695. /* write the word at location addr in the USER area */
  2696. case PTRACE_POKEUSR: {
  2697. unsigned long index;
  2698. ret = -EIO;
  2699. /* convert to index and check */
  2700. #ifdef CONFIG_PPC32
  2701. index = addr >> 2;
  2702. if ((addr & 3) || (index > PT_FPSCR)
  2703. || (child->thread.regs == NULL))
  2704. #else
  2705. index = addr >> 3;
  2706. if ((addr & 7) || (index > PT_FPSCR))
  2707. #endif
  2708. break;
  2709. CHECK_FULL_REGS(child->thread.regs);
  2710. if (index < PT_FPR0) {
  2711. ret = ptrace_put_reg(child, index, data);
  2712. } else {
  2713. unsigned int fpidx = index - PT_FPR0;
  2714. flush_fp_to_thread(child);
  2715. if (fpidx < (PT_FPSCR - PT_FPR0))
  2716. memcpy(&child->thread.TS_FPR(fpidx), &data,
  2717. sizeof(long));
  2718. else
  2719. child->thread.fp_state.fpscr = data;
  2720. ret = 0;
  2721. }
  2722. break;
  2723. }
  2724. case PPC_PTRACE_GETHWDBGINFO: {
  2725. struct ppc_debug_info dbginfo;
  2726. dbginfo.version = 1;
  2727. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2728. dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
  2729. dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
  2730. dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
  2731. dbginfo.data_bp_alignment = 4;
  2732. dbginfo.sizeof_condition = 4;
  2733. dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
  2734. PPC_DEBUG_FEATURE_INSN_BP_MASK;
  2735. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  2736. dbginfo.features |=
  2737. PPC_DEBUG_FEATURE_DATA_BP_RANGE |
  2738. PPC_DEBUG_FEATURE_DATA_BP_MASK;
  2739. #endif
  2740. #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
  2741. dbginfo.num_instruction_bps = 0;
  2742. dbginfo.num_data_bps = 1;
  2743. dbginfo.num_condition_regs = 0;
  2744. #ifdef CONFIG_PPC64
  2745. dbginfo.data_bp_alignment = 8;
  2746. #else
  2747. dbginfo.data_bp_alignment = 4;
  2748. #endif
  2749. dbginfo.sizeof_condition = 0;
  2750. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  2751. dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
  2752. if (cpu_has_feature(CPU_FTR_DAWR))
  2753. dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
  2754. #else
  2755. dbginfo.features = 0;
  2756. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  2757. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  2758. if (!access_ok(VERIFY_WRITE, datavp,
  2759. sizeof(struct ppc_debug_info)))
  2760. return -EFAULT;
  2761. ret = __copy_to_user(datavp, &dbginfo,
  2762. sizeof(struct ppc_debug_info)) ?
  2763. -EFAULT : 0;
  2764. break;
  2765. }
  2766. case PPC_PTRACE_SETHWDEBUG: {
  2767. struct ppc_hw_breakpoint bp_info;
  2768. if (!access_ok(VERIFY_READ, datavp,
  2769. sizeof(struct ppc_hw_breakpoint)))
  2770. return -EFAULT;
  2771. ret = __copy_from_user(&bp_info, datavp,
  2772. sizeof(struct ppc_hw_breakpoint)) ?
  2773. -EFAULT : 0;
  2774. if (!ret)
  2775. ret = ppc_set_hwdebug(child, &bp_info);
  2776. break;
  2777. }
  2778. case PPC_PTRACE_DELHWDEBUG: {
  2779. ret = ppc_del_hwdebug(child, data);
  2780. break;
  2781. }
  2782. case PTRACE_GET_DEBUGREG: {
  2783. #ifndef CONFIG_PPC_ADV_DEBUG_REGS
  2784. unsigned long dabr_fake;
  2785. #endif
  2786. ret = -EINVAL;
  2787. /* We only support one DABR and no IABRS at the moment */
  2788. if (addr > 0)
  2789. break;
  2790. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  2791. ret = put_user(child->thread.debug.dac1, datalp);
  2792. #else
  2793. dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
  2794. (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
  2795. ret = put_user(dabr_fake, datalp);
  2796. #endif
  2797. break;
  2798. }
  2799. case PTRACE_SET_DEBUGREG:
  2800. ret = ptrace_set_debugreg(child, addr, data);
  2801. break;
  2802. #ifdef CONFIG_PPC64
  2803. case PTRACE_GETREGS64:
  2804. #endif
  2805. case PTRACE_GETREGS: /* Get all pt_regs from the child. */
  2806. return copy_regset_to_user(child, &user_ppc_native_view,
  2807. REGSET_GPR,
  2808. 0, sizeof(struct pt_regs),
  2809. datavp);
  2810. #ifdef CONFIG_PPC64
  2811. case PTRACE_SETREGS64:
  2812. #endif
  2813. case PTRACE_SETREGS: /* Set all gp regs in the child. */
  2814. return copy_regset_from_user(child, &user_ppc_native_view,
  2815. REGSET_GPR,
  2816. 0, sizeof(struct pt_regs),
  2817. datavp);
  2818. case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
  2819. return copy_regset_to_user(child, &user_ppc_native_view,
  2820. REGSET_FPR,
  2821. 0, sizeof(elf_fpregset_t),
  2822. datavp);
  2823. case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
  2824. return copy_regset_from_user(child, &user_ppc_native_view,
  2825. REGSET_FPR,
  2826. 0, sizeof(elf_fpregset_t),
  2827. datavp);
  2828. #ifdef CONFIG_ALTIVEC
  2829. case PTRACE_GETVRREGS:
  2830. return copy_regset_to_user(child, &user_ppc_native_view,
  2831. REGSET_VMX,
  2832. 0, (33 * sizeof(vector128) +
  2833. sizeof(u32)),
  2834. datavp);
  2835. case PTRACE_SETVRREGS:
  2836. return copy_regset_from_user(child, &user_ppc_native_view,
  2837. REGSET_VMX,
  2838. 0, (33 * sizeof(vector128) +
  2839. sizeof(u32)),
  2840. datavp);
  2841. #endif
  2842. #ifdef CONFIG_VSX
  2843. case PTRACE_GETVSRREGS:
  2844. return copy_regset_to_user(child, &user_ppc_native_view,
  2845. REGSET_VSX,
  2846. 0, 32 * sizeof(double),
  2847. datavp);
  2848. case PTRACE_SETVSRREGS:
  2849. return copy_regset_from_user(child, &user_ppc_native_view,
  2850. REGSET_VSX,
  2851. 0, 32 * sizeof(double),
  2852. datavp);
  2853. #endif
  2854. #ifdef CONFIG_SPE
  2855. case PTRACE_GETEVRREGS:
  2856. /* Get the child spe register state. */
  2857. return copy_regset_to_user(child, &user_ppc_native_view,
  2858. REGSET_SPE, 0, 35 * sizeof(u32),
  2859. datavp);
  2860. case PTRACE_SETEVRREGS:
  2861. /* Set the child spe register state. */
  2862. return copy_regset_from_user(child, &user_ppc_native_view,
  2863. REGSET_SPE, 0, 35 * sizeof(u32),
  2864. datavp);
  2865. #endif
  2866. default:
  2867. ret = ptrace_request(child, request, addr, data);
  2868. break;
  2869. }
  2870. return ret;
  2871. }
  2872. #ifdef CONFIG_SECCOMP
  2873. static int do_seccomp(struct pt_regs *regs)
  2874. {
  2875. if (!test_thread_flag(TIF_SECCOMP))
  2876. return 0;
  2877. /*
  2878. * The ABI we present to seccomp tracers is that r3 contains
  2879. * the syscall return value and orig_gpr3 contains the first
  2880. * syscall parameter. This is different to the ptrace ABI where
  2881. * both r3 and orig_gpr3 contain the first syscall parameter.
  2882. */
  2883. regs->gpr[3] = -ENOSYS;
  2884. /*
  2885. * We use the __ version here because we have already checked
  2886. * TIF_SECCOMP. If this fails, there is nothing left to do, we
  2887. * have already loaded -ENOSYS into r3, or seccomp has put
  2888. * something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
  2889. */
  2890. if (__secure_computing(NULL))
  2891. return -1;
  2892. /*
  2893. * The syscall was allowed by seccomp, restore the register
  2894. * state to what audit expects.
  2895. * Note that we use orig_gpr3, which means a seccomp tracer can
  2896. * modify the first syscall parameter (in orig_gpr3) and also
  2897. * allow the syscall to proceed.
  2898. */
  2899. regs->gpr[3] = regs->orig_gpr3;
  2900. return 0;
  2901. }
  2902. #else
  2903. static inline int do_seccomp(struct pt_regs *regs) { return 0; }
  2904. #endif /* CONFIG_SECCOMP */
  2905. /**
  2906. * do_syscall_trace_enter() - Do syscall tracing on kernel entry.
  2907. * @regs: the pt_regs of the task to trace (current)
  2908. *
  2909. * Performs various types of tracing on syscall entry. This includes seccomp,
  2910. * ptrace, syscall tracepoints and audit.
  2911. *
  2912. * The pt_regs are potentially visible to userspace via ptrace, so their
  2913. * contents is ABI.
  2914. *
  2915. * One or more of the tracers may modify the contents of pt_regs, in particular
  2916. * to modify arguments or even the syscall number itself.
  2917. *
  2918. * It's also possible that a tracer can choose to reject the system call. In
  2919. * that case this function will return an illegal syscall number, and will put
  2920. * an appropriate return value in regs->r3.
  2921. *
  2922. * Return: the (possibly changed) syscall number.
  2923. */
  2924. long do_syscall_trace_enter(struct pt_regs *regs)
  2925. {
  2926. user_exit();
  2927. /*
  2928. * The tracer may decide to abort the syscall, if so tracehook
  2929. * will return !0. Note that the tracer may also just change
  2930. * regs->gpr[0] to an invalid syscall number, that is handled
  2931. * below on the exit path.
  2932. */
  2933. if (test_thread_flag(TIF_SYSCALL_TRACE) &&
  2934. tracehook_report_syscall_entry(regs))
  2935. goto skip;
  2936. /* Run seccomp after ptrace; allow it to set gpr[3]. */
  2937. if (do_seccomp(regs))
  2938. return -1;
  2939. /* Avoid trace and audit when syscall is invalid. */
  2940. if (regs->gpr[0] >= NR_syscalls)
  2941. goto skip;
  2942. if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
  2943. trace_sys_enter(regs, regs->gpr[0]);
  2944. #ifdef CONFIG_PPC64
  2945. if (!is_32bit_task())
  2946. audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4],
  2947. regs->gpr[5], regs->gpr[6]);
  2948. else
  2949. #endif
  2950. audit_syscall_entry(regs->gpr[0],
  2951. regs->gpr[3] & 0xffffffff,
  2952. regs->gpr[4] & 0xffffffff,
  2953. regs->gpr[5] & 0xffffffff,
  2954. regs->gpr[6] & 0xffffffff);
  2955. /* Return the possibly modified but valid syscall number */
  2956. return regs->gpr[0];
  2957. skip:
  2958. /*
  2959. * If we are aborting explicitly, or if the syscall number is
  2960. * now invalid, set the return value to -ENOSYS.
  2961. */
  2962. regs->gpr[3] = -ENOSYS;
  2963. return -1;
  2964. }
  2965. void do_syscall_trace_leave(struct pt_regs *regs)
  2966. {
  2967. int step;
  2968. audit_syscall_exit(regs);
  2969. if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
  2970. trace_sys_exit(regs, regs->result);
  2971. step = test_thread_flag(TIF_SINGLESTEP);
  2972. if (step || test_thread_flag(TIF_SYSCALL_TRACE))
  2973. tracehook_report_syscall_exit(regs, step);
  2974. user_enter();
  2975. }