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/arch/powerpc/kernel/traps.c

http://github.com/mirrors/linux
C | 2299 lines | 1568 code | 326 blank | 405 comment | 347 complexity | 50237b531a1132d55e3e85896e80f25b MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  4. * Copyright 2007-2010 Freescale Semiconductor, Inc.
  5. *
  6. * Modified by Cort Dougan (cort@cs.nmt.edu)
  7. * and Paul Mackerras (paulus@samba.org)
  8. */
  9. /*
  10. * This file handles the architecture-dependent parts of hardware exceptions
  11. */
  12. #include <linux/errno.h>
  13. #include <linux/sched.h>
  14. #include <linux/sched/debug.h>
  15. #include <linux/kernel.h>
  16. #include <linux/mm.h>
  17. #include <linux/pkeys.h>
  18. #include <linux/stddef.h>
  19. #include <linux/unistd.h>
  20. #include <linux/ptrace.h>
  21. #include <linux/user.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/init.h>
  24. #include <linux/extable.h>
  25. #include <linux/module.h> /* print_modules */
  26. #include <linux/prctl.h>
  27. #include <linux/delay.h>
  28. #include <linux/kprobes.h>
  29. #include <linux/kexec.h>
  30. #include <linux/backlight.h>
  31. #include <linux/bug.h>
  32. #include <linux/kdebug.h>
  33. #include <linux/ratelimit.h>
  34. #include <linux/context_tracking.h>
  35. #include <linux/smp.h>
  36. #include <linux/console.h>
  37. #include <linux/kmsg_dump.h>
  38. #include <asm/emulated_ops.h>
  39. #include <asm/pgtable.h>
  40. #include <linux/uaccess.h>
  41. #include <asm/debugfs.h>
  42. #include <asm/io.h>
  43. #include <asm/machdep.h>
  44. #include <asm/rtas.h>
  45. #include <asm/pmc.h>
  46. #include <asm/reg.h>
  47. #ifdef CONFIG_PMAC_BACKLIGHT
  48. #include <asm/backlight.h>
  49. #endif
  50. #ifdef CONFIG_PPC64
  51. #include <asm/firmware.h>
  52. #include <asm/processor.h>
  53. #include <asm/tm.h>
  54. #endif
  55. #include <asm/kexec.h>
  56. #include <asm/ppc-opcode.h>
  57. #include <asm/rio.h>
  58. #include <asm/fadump.h>
  59. #include <asm/switch_to.h>
  60. #include <asm/tm.h>
  61. #include <asm/debug.h>
  62. #include <asm/asm-prototypes.h>
  63. #include <asm/hmi.h>
  64. #include <sysdev/fsl_pci.h>
  65. #include <asm/kprobes.h>
  66. #include <asm/stacktrace.h>
  67. #include <asm/nmi.h>
  68. #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
  69. int (*__debugger)(struct pt_regs *regs) __read_mostly;
  70. int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
  71. int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
  72. int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
  73. int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
  74. int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
  75. int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
  76. EXPORT_SYMBOL(__debugger);
  77. EXPORT_SYMBOL(__debugger_ipi);
  78. EXPORT_SYMBOL(__debugger_bpt);
  79. EXPORT_SYMBOL(__debugger_sstep);
  80. EXPORT_SYMBOL(__debugger_iabr_match);
  81. EXPORT_SYMBOL(__debugger_break_match);
  82. EXPORT_SYMBOL(__debugger_fault_handler);
  83. #endif
  84. /* Transactional Memory trap debug */
  85. #ifdef TM_DEBUG_SW
  86. #define TM_DEBUG(x...) printk(KERN_INFO x)
  87. #else
  88. #define TM_DEBUG(x...) do { } while(0)
  89. #endif
  90. static const char *signame(int signr)
  91. {
  92. switch (signr) {
  93. case SIGBUS: return "bus error";
  94. case SIGFPE: return "floating point exception";
  95. case SIGILL: return "illegal instruction";
  96. case SIGSEGV: return "segfault";
  97. case SIGTRAP: return "unhandled trap";
  98. }
  99. return "unknown signal";
  100. }
  101. /*
  102. * Trap & Exception support
  103. */
  104. #ifdef CONFIG_PMAC_BACKLIGHT
  105. static void pmac_backlight_unblank(void)
  106. {
  107. mutex_lock(&pmac_backlight_mutex);
  108. if (pmac_backlight) {
  109. struct backlight_properties *props;
  110. props = &pmac_backlight->props;
  111. props->brightness = props->max_brightness;
  112. props->power = FB_BLANK_UNBLANK;
  113. backlight_update_status(pmac_backlight);
  114. }
  115. mutex_unlock(&pmac_backlight_mutex);
  116. }
  117. #else
  118. static inline void pmac_backlight_unblank(void) { }
  119. #endif
  120. /*
  121. * If oops/die is expected to crash the machine, return true here.
  122. *
  123. * This should not be expected to be 100% accurate, there may be
  124. * notifiers registered or other unexpected conditions that may bring
  125. * down the kernel. Or if the current process in the kernel is holding
  126. * locks or has other critical state, the kernel may become effectively
  127. * unusable anyway.
  128. */
  129. bool die_will_crash(void)
  130. {
  131. if (should_fadump_crash())
  132. return true;
  133. if (kexec_should_crash(current))
  134. return true;
  135. if (in_interrupt() || panic_on_oops ||
  136. !current->pid || is_global_init(current))
  137. return true;
  138. return false;
  139. }
  140. static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
  141. static int die_owner = -1;
  142. static unsigned int die_nest_count;
  143. static int die_counter;
  144. extern void panic_flush_kmsg_start(void)
  145. {
  146. /*
  147. * These are mostly taken from kernel/panic.c, but tries to do
  148. * relatively minimal work. Don't use delay functions (TB may
  149. * be broken), don't crash dump (need to set a firmware log),
  150. * don't run notifiers. We do want to get some information to
  151. * Linux console.
  152. */
  153. console_verbose();
  154. bust_spinlocks(1);
  155. }
  156. extern void panic_flush_kmsg_end(void)
  157. {
  158. printk_safe_flush_on_panic();
  159. kmsg_dump(KMSG_DUMP_PANIC);
  160. bust_spinlocks(0);
  161. debug_locks_off();
  162. console_flush_on_panic(CONSOLE_FLUSH_PENDING);
  163. }
  164. static unsigned long oops_begin(struct pt_regs *regs)
  165. {
  166. int cpu;
  167. unsigned long flags;
  168. oops_enter();
  169. /* racy, but better than risking deadlock. */
  170. raw_local_irq_save(flags);
  171. cpu = smp_processor_id();
  172. if (!arch_spin_trylock(&die_lock)) {
  173. if (cpu == die_owner)
  174. /* nested oops. should stop eventually */;
  175. else
  176. arch_spin_lock(&die_lock);
  177. }
  178. die_nest_count++;
  179. die_owner = cpu;
  180. console_verbose();
  181. bust_spinlocks(1);
  182. if (machine_is(powermac))
  183. pmac_backlight_unblank();
  184. return flags;
  185. }
  186. NOKPROBE_SYMBOL(oops_begin);
  187. static void oops_end(unsigned long flags, struct pt_regs *regs,
  188. int signr)
  189. {
  190. bust_spinlocks(0);
  191. add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
  192. die_nest_count--;
  193. oops_exit();
  194. printk("\n");
  195. if (!die_nest_count) {
  196. /* Nest count reaches zero, release the lock. */
  197. die_owner = -1;
  198. arch_spin_unlock(&die_lock);
  199. }
  200. raw_local_irq_restore(flags);
  201. /*
  202. * system_reset_excption handles debugger, crash dump, panic, for 0x100
  203. */
  204. if (TRAP(regs) == 0x100)
  205. return;
  206. crash_fadump(regs, "die oops");
  207. if (kexec_should_crash(current))
  208. crash_kexec(regs);
  209. if (!signr)
  210. return;
  211. /*
  212. * While our oops output is serialised by a spinlock, output
  213. * from panic() called below can race and corrupt it. If we
  214. * know we are going to panic, delay for 1 second so we have a
  215. * chance to get clean backtraces from all CPUs that are oopsing.
  216. */
  217. if (in_interrupt() || panic_on_oops || !current->pid ||
  218. is_global_init(current)) {
  219. mdelay(MSEC_PER_SEC);
  220. }
  221. if (panic_on_oops)
  222. panic("Fatal exception");
  223. do_exit(signr);
  224. }
  225. NOKPROBE_SYMBOL(oops_end);
  226. static char *get_mmu_str(void)
  227. {
  228. if (early_radix_enabled())
  229. return " MMU=Radix";
  230. if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE))
  231. return " MMU=Hash";
  232. return "";
  233. }
  234. static int __die(const char *str, struct pt_regs *regs, long err)
  235. {
  236. printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  237. printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
  238. IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
  239. PAGE_SIZE / 1024, get_mmu_str(),
  240. IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
  241. IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
  242. IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
  243. debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
  244. IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "",
  245. ppc_md.name ? ppc_md.name : "");
  246. if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
  247. return 1;
  248. print_modules();
  249. show_regs(regs);
  250. return 0;
  251. }
  252. NOKPROBE_SYMBOL(__die);
  253. void die(const char *str, struct pt_regs *regs, long err)
  254. {
  255. unsigned long flags;
  256. /*
  257. * system_reset_excption handles debugger, crash dump, panic, for 0x100
  258. */
  259. if (TRAP(regs) != 0x100) {
  260. if (debugger(regs))
  261. return;
  262. }
  263. flags = oops_begin(regs);
  264. if (__die(str, regs, err))
  265. err = 0;
  266. oops_end(flags, regs, err);
  267. }
  268. NOKPROBE_SYMBOL(die);
  269. void user_single_step_report(struct pt_regs *regs)
  270. {
  271. force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip);
  272. }
  273. static void show_signal_msg(int signr, struct pt_regs *regs, int code,
  274. unsigned long addr)
  275. {
  276. static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
  277. DEFAULT_RATELIMIT_BURST);
  278. if (!show_unhandled_signals)
  279. return;
  280. if (!unhandled_signal(current, signr))
  281. return;
  282. if (!__ratelimit(&rs))
  283. return;
  284. pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
  285. current->comm, current->pid, signame(signr), signr,
  286. addr, regs->nip, regs->link, code);
  287. print_vma_addr(KERN_CONT " in ", regs->nip);
  288. pr_cont("\n");
  289. show_user_instructions(regs);
  290. }
  291. static bool exception_common(int signr, struct pt_regs *regs, int code,
  292. unsigned long addr)
  293. {
  294. if (!user_mode(regs)) {
  295. die("Exception in kernel mode", regs, signr);
  296. return false;
  297. }
  298. show_signal_msg(signr, regs, code, addr);
  299. if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
  300. local_irq_enable();
  301. current->thread.trap_nr = code;
  302. /*
  303. * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need
  304. * to capture the content, if the task gets killed.
  305. */
  306. thread_pkey_regs_save(&current->thread);
  307. return true;
  308. }
  309. void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key)
  310. {
  311. if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr))
  312. return;
  313. force_sig_pkuerr((void __user *) addr, key);
  314. }
  315. void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
  316. {
  317. if (!exception_common(signr, regs, code, addr))
  318. return;
  319. force_sig_fault(signr, code, (void __user *)addr);
  320. }
  321. /*
  322. * The interrupt architecture has a quirk in that the HV interrupts excluding
  323. * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
  324. * that an interrupt handler must do is save off a GPR into a scratch register,
  325. * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
  326. * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
  327. * that it is non-reentrant, which leads to random data corruption.
  328. *
  329. * The solution is for NMI interrupts in HV mode to check if they originated
  330. * from these critical HV interrupt regions. If so, then mark them not
  331. * recoverable.
  332. *
  333. * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
  334. * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
  335. * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
  336. * that would work. However any other guest OS that may have the SPRG live
  337. * and MSR[RI]=1 could encounter silent corruption.
  338. *
  339. * Builds that do not support KVM could take this second option to increase
  340. * the recoverability of NMIs.
  341. */
  342. void hv_nmi_check_nonrecoverable(struct pt_regs *regs)
  343. {
  344. #ifdef CONFIG_PPC_POWERNV
  345. unsigned long kbase = (unsigned long)_stext;
  346. unsigned long nip = regs->nip;
  347. if (!(regs->msr & MSR_RI))
  348. return;
  349. if (!(regs->msr & MSR_HV))
  350. return;
  351. if (regs->msr & MSR_PR)
  352. return;
  353. /*
  354. * Now test if the interrupt has hit a range that may be using
  355. * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
  356. * problem ranges all run un-relocated. Test real and virt modes
  357. * at the same time by droping the high bit of the nip (virt mode
  358. * entry points still have the +0x4000 offset).
  359. */
  360. nip &= ~0xc000000000000000ULL;
  361. if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600))
  362. goto nonrecoverable;
  363. if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00))
  364. goto nonrecoverable;
  365. if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0))
  366. goto nonrecoverable;
  367. if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0))
  368. goto nonrecoverable;
  369. /* Trampoline code runs un-relocated so subtract kbase. */
  370. if (nip >= (unsigned long)(start_real_trampolines - kbase) &&
  371. nip < (unsigned long)(end_real_trampolines - kbase))
  372. goto nonrecoverable;
  373. if (nip >= (unsigned long)(start_virt_trampolines - kbase) &&
  374. nip < (unsigned long)(end_virt_trampolines - kbase))
  375. goto nonrecoverable;
  376. return;
  377. nonrecoverable:
  378. regs->msr &= ~MSR_RI;
  379. #endif
  380. }
  381. void system_reset_exception(struct pt_regs *regs)
  382. {
  383. unsigned long hsrr0, hsrr1;
  384. bool nested = in_nmi();
  385. bool saved_hsrrs = false;
  386. /*
  387. * Avoid crashes in case of nested NMI exceptions. Recoverability
  388. * is determined by RI and in_nmi
  389. */
  390. if (!nested)
  391. nmi_enter();
  392. /*
  393. * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
  394. * The system reset interrupt itself may clobber HSRRs (e.g., to call
  395. * OPAL), so save them here and restore them before returning.
  396. *
  397. * Machine checks don't need to save HSRRs, as the real mode handler
  398. * is careful to avoid them, and the regular handler is not delivered
  399. * as an NMI.
  400. */
  401. if (cpu_has_feature(CPU_FTR_HVMODE)) {
  402. hsrr0 = mfspr(SPRN_HSRR0);
  403. hsrr1 = mfspr(SPRN_HSRR1);
  404. saved_hsrrs = true;
  405. }
  406. hv_nmi_check_nonrecoverable(regs);
  407. __this_cpu_inc(irq_stat.sreset_irqs);
  408. /* See if any machine dependent calls */
  409. if (ppc_md.system_reset_exception) {
  410. if (ppc_md.system_reset_exception(regs))
  411. goto out;
  412. }
  413. if (debugger(regs))
  414. goto out;
  415. kmsg_dump(KMSG_DUMP_OOPS);
  416. /*
  417. * A system reset is a request to dump, so we always send
  418. * it through the crashdump code (if fadump or kdump are
  419. * registered).
  420. */
  421. crash_fadump(regs, "System Reset");
  422. crash_kexec(regs);
  423. /*
  424. * We aren't the primary crash CPU. We need to send it
  425. * to a holding pattern to avoid it ending up in the panic
  426. * code.
  427. */
  428. crash_kexec_secondary(regs);
  429. /*
  430. * No debugger or crash dump registered, print logs then
  431. * panic.
  432. */
  433. die("System Reset", regs, SIGABRT);
  434. mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
  435. add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
  436. nmi_panic(regs, "System Reset");
  437. out:
  438. #ifdef CONFIG_PPC_BOOK3S_64
  439. BUG_ON(get_paca()->in_nmi == 0);
  440. if (get_paca()->in_nmi > 1)
  441. nmi_panic(regs, "Unrecoverable nested System Reset");
  442. #endif
  443. /* Must die if the interrupt is not recoverable */
  444. if (!(regs->msr & MSR_RI))
  445. nmi_panic(regs, "Unrecoverable System Reset");
  446. if (saved_hsrrs) {
  447. mtspr(SPRN_HSRR0, hsrr0);
  448. mtspr(SPRN_HSRR1, hsrr1);
  449. }
  450. if (!nested)
  451. nmi_exit();
  452. /* What should we do here? We could issue a shutdown or hard reset. */
  453. }
  454. /*
  455. * I/O accesses can cause machine checks on powermacs.
  456. * Check if the NIP corresponds to the address of a sync
  457. * instruction for which there is an entry in the exception
  458. * table.
  459. * Note that the 601 only takes a machine check on TEA
  460. * (transfer error ack) signal assertion, and does not
  461. * set any of the top 16 bits of SRR1.
  462. * -- paulus.
  463. */
  464. static inline int check_io_access(struct pt_regs *regs)
  465. {
  466. #ifdef CONFIG_PPC32
  467. unsigned long msr = regs->msr;
  468. const struct exception_table_entry *entry;
  469. unsigned int *nip = (unsigned int *)regs->nip;
  470. if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
  471. && (entry = search_exception_tables(regs->nip)) != NULL) {
  472. /*
  473. * Check that it's a sync instruction, or somewhere
  474. * in the twi; isync; nop sequence that inb/inw/inl uses.
  475. * As the address is in the exception table
  476. * we should be able to read the instr there.
  477. * For the debug message, we look at the preceding
  478. * load or store.
  479. */
  480. if (*nip == PPC_INST_NOP)
  481. nip -= 2;
  482. else if (*nip == PPC_INST_ISYNC)
  483. --nip;
  484. if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
  485. unsigned int rb;
  486. --nip;
  487. rb = (*nip >> 11) & 0x1f;
  488. printk(KERN_DEBUG "%s bad port %lx at %p\n",
  489. (*nip & 0x100)? "OUT to": "IN from",
  490. regs->gpr[rb] - _IO_BASE, nip);
  491. regs->msr |= MSR_RI;
  492. regs->nip = extable_fixup(entry);
  493. return 1;
  494. }
  495. }
  496. #endif /* CONFIG_PPC32 */
  497. return 0;
  498. }
  499. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  500. /* On 4xx, the reason for the machine check or program exception
  501. is in the ESR. */
  502. #define get_reason(regs) ((regs)->dsisr)
  503. #define REASON_FP ESR_FP
  504. #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
  505. #define REASON_PRIVILEGED ESR_PPR
  506. #define REASON_TRAP ESR_PTR
  507. /* single-step stuff */
  508. #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
  509. #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
  510. #define clear_br_trace(regs) do {} while(0)
  511. #else
  512. /* On non-4xx, the reason for the machine check or program
  513. exception is in the MSR. */
  514. #define get_reason(regs) ((regs)->msr)
  515. #define REASON_TM SRR1_PROGTM
  516. #define REASON_FP SRR1_PROGFPE
  517. #define REASON_ILLEGAL SRR1_PROGILL
  518. #define REASON_PRIVILEGED SRR1_PROGPRIV
  519. #define REASON_TRAP SRR1_PROGTRAP
  520. #define single_stepping(regs) ((regs)->msr & MSR_SE)
  521. #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
  522. #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
  523. #endif
  524. #if defined(CONFIG_E500)
  525. int machine_check_e500mc(struct pt_regs *regs)
  526. {
  527. unsigned long mcsr = mfspr(SPRN_MCSR);
  528. unsigned long pvr = mfspr(SPRN_PVR);
  529. unsigned long reason = mcsr;
  530. int recoverable = 1;
  531. if (reason & MCSR_LD) {
  532. recoverable = fsl_rio_mcheck_exception(regs);
  533. if (recoverable == 1)
  534. goto silent_out;
  535. }
  536. printk("Machine check in kernel mode.\n");
  537. printk("Caused by (from MCSR=%lx): ", reason);
  538. if (reason & MCSR_MCP)
  539. pr_cont("Machine Check Signal\n");
  540. if (reason & MCSR_ICPERR) {
  541. pr_cont("Instruction Cache Parity Error\n");
  542. /*
  543. * This is recoverable by invalidating the i-cache.
  544. */
  545. mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
  546. while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
  547. ;
  548. /*
  549. * This will generally be accompanied by an instruction
  550. * fetch error report -- only treat MCSR_IF as fatal
  551. * if it wasn't due to an L1 parity error.
  552. */
  553. reason &= ~MCSR_IF;
  554. }
  555. if (reason & MCSR_DCPERR_MC) {
  556. pr_cont("Data Cache Parity Error\n");
  557. /*
  558. * In write shadow mode we auto-recover from the error, but it
  559. * may still get logged and cause a machine check. We should
  560. * only treat the non-write shadow case as non-recoverable.
  561. */
  562. /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
  563. * is not implemented but L1 data cache always runs in write
  564. * shadow mode. Hence on data cache parity errors HW will
  565. * automatically invalidate the L1 Data Cache.
  566. */
  567. if (PVR_VER(pvr) != PVR_VER_E6500) {
  568. if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
  569. recoverable = 0;
  570. }
  571. }
  572. if (reason & MCSR_L2MMU_MHIT) {
  573. pr_cont("Hit on multiple TLB entries\n");
  574. recoverable = 0;
  575. }
  576. if (reason & MCSR_NMI)
  577. pr_cont("Non-maskable interrupt\n");
  578. if (reason & MCSR_IF) {
  579. pr_cont("Instruction Fetch Error Report\n");
  580. recoverable = 0;
  581. }
  582. if (reason & MCSR_LD) {
  583. pr_cont("Load Error Report\n");
  584. recoverable = 0;
  585. }
  586. if (reason & MCSR_ST) {
  587. pr_cont("Store Error Report\n");
  588. recoverable = 0;
  589. }
  590. if (reason & MCSR_LDG) {
  591. pr_cont("Guarded Load Error Report\n");
  592. recoverable = 0;
  593. }
  594. if (reason & MCSR_TLBSYNC)
  595. pr_cont("Simultaneous tlbsync operations\n");
  596. if (reason & MCSR_BSL2_ERR) {
  597. pr_cont("Level 2 Cache Error\n");
  598. recoverable = 0;
  599. }
  600. if (reason & MCSR_MAV) {
  601. u64 addr;
  602. addr = mfspr(SPRN_MCAR);
  603. addr |= (u64)mfspr(SPRN_MCARU) << 32;
  604. pr_cont("Machine Check %s Address: %#llx\n",
  605. reason & MCSR_MEA ? "Effective" : "Physical", addr);
  606. }
  607. silent_out:
  608. mtspr(SPRN_MCSR, mcsr);
  609. return mfspr(SPRN_MCSR) == 0 && recoverable;
  610. }
  611. int machine_check_e500(struct pt_regs *regs)
  612. {
  613. unsigned long reason = mfspr(SPRN_MCSR);
  614. if (reason & MCSR_BUS_RBERR) {
  615. if (fsl_rio_mcheck_exception(regs))
  616. return 1;
  617. if (fsl_pci_mcheck_exception(regs))
  618. return 1;
  619. }
  620. printk("Machine check in kernel mode.\n");
  621. printk("Caused by (from MCSR=%lx): ", reason);
  622. if (reason & MCSR_MCP)
  623. pr_cont("Machine Check Signal\n");
  624. if (reason & MCSR_ICPERR)
  625. pr_cont("Instruction Cache Parity Error\n");
  626. if (reason & MCSR_DCP_PERR)
  627. pr_cont("Data Cache Push Parity Error\n");
  628. if (reason & MCSR_DCPERR)
  629. pr_cont("Data Cache Parity Error\n");
  630. if (reason & MCSR_BUS_IAERR)
  631. pr_cont("Bus - Instruction Address Error\n");
  632. if (reason & MCSR_BUS_RAERR)
  633. pr_cont("Bus - Read Address Error\n");
  634. if (reason & MCSR_BUS_WAERR)
  635. pr_cont("Bus - Write Address Error\n");
  636. if (reason & MCSR_BUS_IBERR)
  637. pr_cont("Bus - Instruction Data Error\n");
  638. if (reason & MCSR_BUS_RBERR)
  639. pr_cont("Bus - Read Data Bus Error\n");
  640. if (reason & MCSR_BUS_WBERR)
  641. pr_cont("Bus - Write Data Bus Error\n");
  642. if (reason & MCSR_BUS_IPERR)
  643. pr_cont("Bus - Instruction Parity Error\n");
  644. if (reason & MCSR_BUS_RPERR)
  645. pr_cont("Bus - Read Parity Error\n");
  646. return 0;
  647. }
  648. int machine_check_generic(struct pt_regs *regs)
  649. {
  650. return 0;
  651. }
  652. #elif defined(CONFIG_E200)
  653. int machine_check_e200(struct pt_regs *regs)
  654. {
  655. unsigned long reason = mfspr(SPRN_MCSR);
  656. printk("Machine check in kernel mode.\n");
  657. printk("Caused by (from MCSR=%lx): ", reason);
  658. if (reason & MCSR_MCP)
  659. pr_cont("Machine Check Signal\n");
  660. if (reason & MCSR_CP_PERR)
  661. pr_cont("Cache Push Parity Error\n");
  662. if (reason & MCSR_CPERR)
  663. pr_cont("Cache Parity Error\n");
  664. if (reason & MCSR_EXCP_ERR)
  665. pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
  666. if (reason & MCSR_BUS_IRERR)
  667. pr_cont("Bus - Read Bus Error on instruction fetch\n");
  668. if (reason & MCSR_BUS_DRERR)
  669. pr_cont("Bus - Read Bus Error on data load\n");
  670. if (reason & MCSR_BUS_WRERR)
  671. pr_cont("Bus - Write Bus Error on buffered store or cache line push\n");
  672. return 0;
  673. }
  674. #elif defined(CONFIG_PPC32)
  675. int machine_check_generic(struct pt_regs *regs)
  676. {
  677. unsigned long reason = regs->msr;
  678. printk("Machine check in kernel mode.\n");
  679. printk("Caused by (from SRR1=%lx): ", reason);
  680. switch (reason & 0x601F0000) {
  681. case 0x80000:
  682. pr_cont("Machine check signal\n");
  683. break;
  684. case 0: /* for 601 */
  685. case 0x40000:
  686. case 0x140000: /* 7450 MSS error and TEA */
  687. pr_cont("Transfer error ack signal\n");
  688. break;
  689. case 0x20000:
  690. pr_cont("Data parity error signal\n");
  691. break;
  692. case 0x10000:
  693. pr_cont("Address parity error signal\n");
  694. break;
  695. case 0x20000000:
  696. pr_cont("L1 Data Cache error\n");
  697. break;
  698. case 0x40000000:
  699. pr_cont("L1 Instruction Cache error\n");
  700. break;
  701. case 0x00100000:
  702. pr_cont("L2 data cache parity error\n");
  703. break;
  704. default:
  705. pr_cont("Unknown values in msr\n");
  706. }
  707. return 0;
  708. }
  709. #endif /* everything else */
  710. void machine_check_exception(struct pt_regs *regs)
  711. {
  712. int recover = 0;
  713. bool nested = in_nmi();
  714. if (!nested)
  715. nmi_enter();
  716. __this_cpu_inc(irq_stat.mce_exceptions);
  717. add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
  718. /* See if any machine dependent calls. In theory, we would want
  719. * to call the CPU first, and call the ppc_md. one if the CPU
  720. * one returns a positive number. However there is existing code
  721. * that assumes the board gets a first chance, so let's keep it
  722. * that way for now and fix things later. --BenH.
  723. */
  724. if (ppc_md.machine_check_exception)
  725. recover = ppc_md.machine_check_exception(regs);
  726. else if (cur_cpu_spec->machine_check)
  727. recover = cur_cpu_spec->machine_check(regs);
  728. if (recover > 0)
  729. goto bail;
  730. if (debugger_fault_handler(regs))
  731. goto bail;
  732. if (check_io_access(regs))
  733. goto bail;
  734. if (!nested)
  735. nmi_exit();
  736. die("Machine check", regs, SIGBUS);
  737. /* Must die if the interrupt is not recoverable */
  738. if (!(regs->msr & MSR_RI))
  739. nmi_panic(regs, "Unrecoverable Machine check");
  740. return;
  741. bail:
  742. if (!nested)
  743. nmi_exit();
  744. }
  745. void SMIException(struct pt_regs *regs)
  746. {
  747. die("System Management Interrupt", regs, SIGABRT);
  748. }
  749. #ifdef CONFIG_VSX
  750. static void p9_hmi_special_emu(struct pt_regs *regs)
  751. {
  752. unsigned int ra, rb, t, i, sel, instr, rc;
  753. const void __user *addr;
  754. u8 vbuf[16], *vdst;
  755. unsigned long ea, msr, msr_mask;
  756. bool swap;
  757. if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
  758. return;
  759. /*
  760. * lxvb16x opcode: 0x7c0006d8
  761. * lxvd2x opcode: 0x7c000698
  762. * lxvh8x opcode: 0x7c000658
  763. * lxvw4x opcode: 0x7c000618
  764. */
  765. if ((instr & 0xfc00073e) != 0x7c000618) {
  766. pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
  767. " instr=%08x\n",
  768. smp_processor_id(), current->comm, current->pid,
  769. regs->nip, instr);
  770. return;
  771. }
  772. /* Grab vector registers into the task struct */
  773. msr = regs->msr; /* Grab msr before we flush the bits */
  774. flush_vsx_to_thread(current);
  775. enable_kernel_altivec();
  776. /*
  777. * Is userspace running with a different endian (this is rare but
  778. * not impossible)
  779. */
  780. swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
  781. /* Decode the instruction */
  782. ra = (instr >> 16) & 0x1f;
  783. rb = (instr >> 11) & 0x1f;
  784. t = (instr >> 21) & 0x1f;
  785. if (instr & 1)
  786. vdst = (u8 *)&current->thread.vr_state.vr[t];
  787. else
  788. vdst = (u8 *)&current->thread.fp_state.fpr[t][0];
  789. /* Grab the vector address */
  790. ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
  791. if (is_32bit_task())
  792. ea &= 0xfffffffful;
  793. addr = (__force const void __user *)ea;
  794. /* Check it */
  795. if (!access_ok(addr, 16)) {
  796. pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
  797. " instr=%08x addr=%016lx\n",
  798. smp_processor_id(), current->comm, current->pid,
  799. regs->nip, instr, (unsigned long)addr);
  800. return;
  801. }
  802. /* Read the vector */
  803. rc = 0;
  804. if ((unsigned long)addr & 0xfUL)
  805. /* unaligned case */
  806. rc = __copy_from_user_inatomic(vbuf, addr, 16);
  807. else
  808. __get_user_atomic_128_aligned(vbuf, addr, rc);
  809. if (rc) {
  810. pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
  811. " instr=%08x addr=%016lx\n",
  812. smp_processor_id(), current->comm, current->pid,
  813. regs->nip, instr, (unsigned long)addr);
  814. return;
  815. }
  816. pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
  817. " instr=%08x addr=%016lx\n",
  818. smp_processor_id(), current->comm, current->pid, regs->nip,
  819. instr, (unsigned long) addr);
  820. /* Grab instruction "selector" */
  821. sel = (instr >> 6) & 3;
  822. /*
  823. * Check to make sure the facility is actually enabled. This
  824. * could happen if we get a false positive hit.
  825. *
  826. * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
  827. * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
  828. */
  829. msr_mask = MSR_VSX;
  830. if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
  831. msr_mask = MSR_VEC;
  832. if (!(msr & msr_mask)) {
  833. pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
  834. " instr=%08x msr:%016lx\n",
  835. smp_processor_id(), current->comm, current->pid,
  836. regs->nip, instr, msr);
  837. return;
  838. }
  839. /* Do logging here before we modify sel based on endian */
  840. switch (sel) {
  841. case 0: /* lxvw4x */
  842. PPC_WARN_EMULATED(lxvw4x, regs);
  843. break;
  844. case 1: /* lxvh8x */
  845. PPC_WARN_EMULATED(lxvh8x, regs);
  846. break;
  847. case 2: /* lxvd2x */
  848. PPC_WARN_EMULATED(lxvd2x, regs);
  849. break;
  850. case 3: /* lxvb16x */
  851. PPC_WARN_EMULATED(lxvb16x, regs);
  852. break;
  853. }
  854. #ifdef __LITTLE_ENDIAN__
  855. /*
  856. * An LE kernel stores the vector in the task struct as an LE
  857. * byte array (effectively swapping both the components and
  858. * the content of the components). Those instructions expect
  859. * the components to remain in ascending address order, so we
  860. * swap them back.
  861. *
  862. * If we are running a BE user space, the expectation is that
  863. * of a simple memcpy, so forcing the emulation to look like
  864. * a lxvb16x should do the trick.
  865. */
  866. if (swap)
  867. sel = 3;
  868. switch (sel) {
  869. case 0: /* lxvw4x */
  870. for (i = 0; i < 4; i++)
  871. ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
  872. break;
  873. case 1: /* lxvh8x */
  874. for (i = 0; i < 8; i++)
  875. ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
  876. break;
  877. case 2: /* lxvd2x */
  878. for (i = 0; i < 2; i++)
  879. ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
  880. break;
  881. case 3: /* lxvb16x */
  882. for (i = 0; i < 16; i++)
  883. vdst[i] = vbuf[15-i];
  884. break;
  885. }
  886. #else /* __LITTLE_ENDIAN__ */
  887. /* On a big endian kernel, a BE userspace only needs a memcpy */
  888. if (!swap)
  889. sel = 3;
  890. /* Otherwise, we need to swap the content of the components */
  891. switch (sel) {
  892. case 0: /* lxvw4x */
  893. for (i = 0; i < 4; i++)
  894. ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
  895. break;
  896. case 1: /* lxvh8x */
  897. for (i = 0; i < 8; i++)
  898. ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
  899. break;
  900. case 2: /* lxvd2x */
  901. for (i = 0; i < 2; i++)
  902. ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
  903. break;
  904. case 3: /* lxvb16x */
  905. memcpy(vdst, vbuf, 16);
  906. break;
  907. }
  908. #endif /* !__LITTLE_ENDIAN__ */
  909. /* Go to next instruction */
  910. regs->nip += 4;
  911. }
  912. #endif /* CONFIG_VSX */
  913. void handle_hmi_exception(struct pt_regs *regs)
  914. {
  915. struct pt_regs *old_regs;
  916. old_regs = set_irq_regs(regs);
  917. irq_enter();
  918. #ifdef CONFIG_VSX
  919. /* Real mode flagged P9 special emu is needed */
  920. if (local_paca->hmi_p9_special_emu) {
  921. local_paca->hmi_p9_special_emu = 0;
  922. /*
  923. * We don't want to take page faults while doing the
  924. * emulation, we just replay the instruction if necessary.
  925. */
  926. pagefault_disable();
  927. p9_hmi_special_emu(regs);
  928. pagefault_enable();
  929. }
  930. #endif /* CONFIG_VSX */
  931. if (ppc_md.handle_hmi_exception)
  932. ppc_md.handle_hmi_exception(regs);
  933. irq_exit();
  934. set_irq_regs(old_regs);
  935. }
  936. void unknown_exception(struct pt_regs *regs)
  937. {
  938. enum ctx_state prev_state = exception_enter();
  939. printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
  940. regs->nip, regs->msr, regs->trap);
  941. _exception(SIGTRAP, regs, TRAP_UNK, 0);
  942. exception_exit(prev_state);
  943. }
  944. void instruction_breakpoint_exception(struct pt_regs *regs)
  945. {
  946. enum ctx_state prev_state = exception_enter();
  947. if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
  948. 5, SIGTRAP) == NOTIFY_STOP)
  949. goto bail;
  950. if (debugger_iabr_match(regs))
  951. goto bail;
  952. _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
  953. bail:
  954. exception_exit(prev_state);
  955. }
  956. void RunModeException(struct pt_regs *regs)
  957. {
  958. _exception(SIGTRAP, regs, TRAP_UNK, 0);
  959. }
  960. void single_step_exception(struct pt_regs *regs)
  961. {
  962. enum ctx_state prev_state = exception_enter();
  963. clear_single_step(regs);
  964. clear_br_trace(regs);
  965. if (kprobe_post_handler(regs))
  966. return;
  967. if (notify_die(DIE_SSTEP, "single_step", regs, 5,
  968. 5, SIGTRAP) == NOTIFY_STOP)
  969. goto bail;
  970. if (debugger_sstep(regs))
  971. goto bail;
  972. _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
  973. bail:
  974. exception_exit(prev_state);
  975. }
  976. NOKPROBE_SYMBOL(single_step_exception);
  977. /*
  978. * After we have successfully emulated an instruction, we have to
  979. * check if the instruction was being single-stepped, and if so,
  980. * pretend we got a single-step exception. This was pointed out
  981. * by Kumar Gala. -- paulus
  982. */
  983. static void emulate_single_step(struct pt_regs *regs)
  984. {
  985. if (single_stepping(regs))
  986. single_step_exception(regs);
  987. }
  988. static inline int __parse_fpscr(unsigned long fpscr)
  989. {
  990. int ret = FPE_FLTUNK;
  991. /* Invalid operation */
  992. if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
  993. ret = FPE_FLTINV;
  994. /* Overflow */
  995. else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
  996. ret = FPE_FLTOVF;
  997. /* Underflow */
  998. else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
  999. ret = FPE_FLTUND;
  1000. /* Divide by zero */
  1001. else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
  1002. ret = FPE_FLTDIV;
  1003. /* Inexact result */
  1004. else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
  1005. ret = FPE_FLTRES;
  1006. return ret;
  1007. }
  1008. static void parse_fpe(struct pt_regs *regs)
  1009. {
  1010. int code = 0;
  1011. flush_fp_to_thread(current);
  1012. code = __parse_fpscr(current->thread.fp_state.fpscr);
  1013. _exception(SIGFPE, regs, code, regs->nip);
  1014. }
  1015. /*
  1016. * Illegal instruction emulation support. Originally written to
  1017. * provide the PVR to user applications using the mfspr rd, PVR.
  1018. * Return non-zero if we can't emulate, or -EFAULT if the associated
  1019. * memory access caused an access fault. Return zero on success.
  1020. *
  1021. * There are a couple of ways to do this, either "decode" the instruction
  1022. * or directly match lots of bits. In this case, matching lots of
  1023. * bits is faster and easier.
  1024. *
  1025. */
  1026. static int emulate_string_inst(struct pt_regs *regs, u32 instword)
  1027. {
  1028. u8 rT = (instword >> 21) & 0x1f;
  1029. u8 rA = (instword >> 16) & 0x1f;
  1030. u8 NB_RB = (instword >> 11) & 0x1f;
  1031. u32 num_bytes;
  1032. unsigned long EA;
  1033. int pos = 0;
  1034. /* Early out if we are an invalid form of lswx */
  1035. if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
  1036. if ((rT == rA) || (rT == NB_RB))
  1037. return -EINVAL;
  1038. EA = (rA == 0) ? 0 : regs->gpr[rA];
  1039. switch (instword & PPC_INST_STRING_MASK) {
  1040. case PPC_INST_LSWX:
  1041. case PPC_INST_STSWX:
  1042. EA += NB_RB;
  1043. num_bytes = regs->xer & 0x7f;
  1044. break;
  1045. case PPC_INST_LSWI:
  1046. case PPC_INST_STSWI:
  1047. num_bytes = (NB_RB == 0) ? 32 : NB_RB;
  1048. break;
  1049. default:
  1050. return -EINVAL;
  1051. }
  1052. while (num_bytes != 0)
  1053. {
  1054. u8 val;
  1055. u32 shift = 8 * (3 - (pos & 0x3));
  1056. /* if process is 32-bit, clear upper 32 bits of EA */
  1057. if ((regs->msr & MSR_64BIT) == 0)
  1058. EA &= 0xFFFFFFFF;
  1059. switch ((instword & PPC_INST_STRING_MASK)) {
  1060. case PPC_INST_LSWX:
  1061. case PPC_INST_LSWI:
  1062. if (get_user(val, (u8 __user *)EA))
  1063. return -EFAULT;
  1064. /* first time updating this reg,
  1065. * zero it out */
  1066. if (pos == 0)
  1067. regs->gpr[rT] = 0;
  1068. regs->gpr[rT] |= val << shift;
  1069. break;
  1070. case PPC_INST_STSWI:
  1071. case PPC_INST_STSWX:
  1072. val = regs->gpr[rT] >> shift;
  1073. if (put_user(val, (u8 __user *)EA))
  1074. return -EFAULT;
  1075. break;
  1076. }
  1077. /* move EA to next address */
  1078. EA += 1;
  1079. num_bytes--;
  1080. /* manage our position within the register */
  1081. if (++pos == 4) {
  1082. pos = 0;
  1083. if (++rT == 32)
  1084. rT = 0;
  1085. }
  1086. }
  1087. return 0;
  1088. }
  1089. static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
  1090. {
  1091. u32 ra,rs;
  1092. unsigned long tmp;
  1093. ra = (instword >> 16) & 0x1f;
  1094. rs = (instword >> 21) & 0x1f;
  1095. tmp = regs->gpr[rs];
  1096. tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
  1097. tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
  1098. tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
  1099. regs->gpr[ra] = tmp;
  1100. return 0;
  1101. }
  1102. static int emulate_isel(struct pt_regs *regs, u32 instword)
  1103. {
  1104. u8 rT = (instword >> 21) & 0x1f;
  1105. u8 rA = (instword >> 16) & 0x1f;
  1106. u8 rB = (instword >> 11) & 0x1f;
  1107. u8 BC = (instword >> 6) & 0x1f;
  1108. u8 bit;
  1109. unsigned long tmp;
  1110. tmp = (rA == 0) ? 0 : regs->gpr[rA];
  1111. bit = (regs->ccr >> (31 - BC)) & 0x1;
  1112. regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
  1113. return 0;
  1114. }
  1115. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1116. static inline bool tm_abort_check(struct pt_regs *regs, int cause)
  1117. {
  1118. /* If we're emulating a load/store in an active transaction, we cannot
  1119. * emulate it as the kernel operates in transaction suspended context.
  1120. * We need to abort the transaction. This creates a persistent TM
  1121. * abort so tell the user what caused it with a new code.
  1122. */
  1123. if (MSR_TM_TRANSACTIONAL(regs->msr)) {
  1124. tm_enable();
  1125. tm_abort(cause);
  1126. return true;
  1127. }
  1128. return false;
  1129. }
  1130. #else
  1131. static inline bool tm_abort_check(struct pt_regs *regs, int reason)
  1132. {
  1133. return false;
  1134. }
  1135. #endif
  1136. static int emulate_instruction(struct pt_regs *regs)
  1137. {
  1138. u32 instword;
  1139. u32 rd;
  1140. if (!user_mode(regs))
  1141. return -EINVAL;
  1142. CHECK_FULL_REGS(regs);
  1143. if (get_user(instword, (u32 __user *)(regs->nip)))
  1144. return -EFAULT;
  1145. /* Emulate the mfspr rD, PVR. */
  1146. if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
  1147. PPC_WARN_EMULATED(mfpvr, regs);
  1148. rd = (instword >> 21) & 0x1f;
  1149. regs->gpr[rd] = mfspr(SPRN_PVR);
  1150. return 0;
  1151. }
  1152. /* Emulating the dcba insn is just a no-op. */
  1153. if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
  1154. PPC_WARN_EMULATED(dcba, regs);
  1155. return 0;
  1156. }
  1157. /* Emulate the mcrxr insn. */
  1158. if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
  1159. int shift = (instword >> 21) & 0x1c;
  1160. unsigned long msk = 0xf0000000UL >> shift;
  1161. PPC_WARN_EMULATED(mcrxr, regs);
  1162. regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
  1163. regs->xer &= ~0xf0000000UL;
  1164. return 0;
  1165. }
  1166. /* Emulate load/store string insn. */
  1167. if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
  1168. if (tm_abort_check(regs,
  1169. TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
  1170. return -EINVAL;
  1171. PPC_WARN_EMULATED(string, regs);
  1172. return emulate_string_inst(regs, instword);
  1173. }
  1174. /* Emulate the popcntb (Population Count Bytes) instruction. */
  1175. if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
  1176. PPC_WARN_EMULATED(popcntb, regs);
  1177. return emulate_popcntb_inst(regs, instword);
  1178. }
  1179. /* Emulate isel (Integer Select) instruction */
  1180. if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
  1181. PPC_WARN_EMULATED(isel, regs);
  1182. return emulate_isel(regs, instword);
  1183. }
  1184. /* Emulate sync instruction variants */
  1185. if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
  1186. PPC_WARN_EMULATED(sync, regs);
  1187. asm volatile("sync");
  1188. return 0;
  1189. }
  1190. #ifdef CONFIG_PPC64
  1191. /* Emulate the mfspr rD, DSCR. */
  1192. if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
  1193. PPC_INST_MFSPR_DSCR_USER) ||
  1194. ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
  1195. PPC_INST_MFSPR_DSCR)) &&
  1196. cpu_has_feature(CPU_FTR_DSCR)) {
  1197. PPC_WARN_EMULATED(mfdscr, regs);
  1198. rd = (instword >> 21) & 0x1f;
  1199. regs->gpr[rd] = mfspr(SPRN_DSCR);
  1200. return 0;
  1201. }
  1202. /* Emulate the mtspr DSCR, rD. */
  1203. if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
  1204. PPC_INST_MTSPR_DSCR_USER) ||
  1205. ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
  1206. PPC_INST_MTSPR_DSCR)) &&
  1207. cpu_has_feature(CPU_FTR_DSCR)) {
  1208. PPC_WARN_EMULATED(mtdscr, regs);
  1209. rd = (instword >> 21) & 0x1f;
  1210. current->thread.dscr = regs->gpr[rd];
  1211. current->thread.dscr_inherit = 1;
  1212. mtspr(SPRN_DSCR, current->thread.dscr);
  1213. return 0;
  1214. }
  1215. #endif
  1216. return -EINVAL;
  1217. }
  1218. int is_valid_bugaddr(unsigned long addr)
  1219. {
  1220. return is_kernel_addr(addr);
  1221. }
  1222. #ifdef CONFIG_MATH_EMULATION
  1223. static int emulate_math(struct pt_regs *regs)
  1224. {
  1225. int ret;
  1226. extern int do_mathemu(struct pt_regs *regs);
  1227. ret = do_mathemu(regs);
  1228. if (ret >= 0)
  1229. PPC_WARN_EMULATED(math, regs);
  1230. switch (ret) {
  1231. case 0:
  1232. emulate_single_step(regs);
  1233. return 0;
  1234. case 1: {
  1235. int code = 0;
  1236. code = __parse_fpscr(current->thread.fp_state.fpscr);
  1237. _exception(SIGFPE, regs, code, regs->nip);
  1238. return 0;
  1239. }
  1240. case -EFAULT:
  1241. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  1242. return 0;
  1243. }
  1244. return -1;
  1245. }
  1246. #else
  1247. static inline int emulate_math(struct pt_regs *regs) { return -1; }
  1248. #endif
  1249. void program_check_exception(struct pt_regs *regs)
  1250. {
  1251. enum ctx_state prev_state = exception_enter();
  1252. unsigned int reason = get_reason(regs);
  1253. /* We can now get here via a FP Unavailable exception if the core
  1254. * has no FPU, in that case the reason flags will be 0 */
  1255. if (reason & REASON_FP) {
  1256. /* IEEE FP exception */
  1257. parse_fpe(regs);
  1258. goto bail;
  1259. }
  1260. if (reason & REASON_TRAP) {
  1261. unsigned long bugaddr;
  1262. /* Debugger is first in line to stop recursive faults in
  1263. * rcu_lock, notify_die, or atomic_notifier_call_chain */
  1264. if (debugger_bpt(regs))
  1265. goto bail;
  1266. if (kprobe_handler(regs))
  1267. goto bail;
  1268. /* trap exception */
  1269. if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
  1270. == NOTIFY_STOP)
  1271. goto bail;
  1272. bugaddr = regs->nip;
  1273. /*
  1274. * Fixup bugaddr for BUG_ON() in real mode
  1275. */
  1276. if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
  1277. bugaddr += PAGE_OFFSET;
  1278. if (!(regs->msr & MSR_PR) && /* not user-mode */
  1279. report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
  1280. regs->nip += 4;
  1281. goto bail;
  1282. }
  1283. _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
  1284. goto bail;
  1285. }
  1286. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1287. if (reason & REASON_TM) {
  1288. /* This is a TM "Bad Thing Exception" program check.
  1289. * This occurs when:
  1290. * - An rfid/hrfid/mtmsrd attempts to cause an illegal
  1291. * transition in TM states.
  1292. * - A trechkpt is attempted when transactional.
  1293. * - A treclaim is attempted when non transactional.
  1294. * - A tend is illegally attempted.
  1295. * - writing a TM SPR when transactional.
  1296. *
  1297. * If usermode caused this, it's done something illegal and
  1298. * gets a SIGILL slap on the wrist. We call it an illegal
  1299. * operand to distinguish from the instruction just being bad
  1300. * (e.g. executing a 'tend' on a CPU without TM!); it's an
  1301. * illegal /placement/ of a valid instruction.
  1302. */
  1303. if (user_mode(regs)) {
  1304. _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
  1305. goto bail;
  1306. } else {
  1307. printk(KERN_EMERG "Unexpected TM Bad Thing exception "
  1308. "at %lx (msr 0x%lx) tm_scratch=%llx\n",
  1309. regs->nip, regs->msr, get_paca()->tm_scratch);
  1310. die("Unrecoverable exception", regs, SIGABRT);
  1311. }
  1312. }
  1313. #endif
  1314. /*
  1315. * If we took the program check in the kernel skip down to sending a
  1316. * SIGILL. The subsequent cases all relate to emulating instructions
  1317. * which we should only do for userspace. We also do not want to enable
  1318. * interrupts for kernel faults because that might lead to further
  1319. * faults, and loose the context of the original exception.
  1320. */
  1321. if (!user_mode(regs))
  1322. goto sigill;
  1323. /* We restore the interrupt state now */
  1324. if (!arch_irq_disabled_regs(regs))
  1325. local_irq_enable();
  1326. /* (reason & REASON_ILLEGAL) would be the obvious thing here,
  1327. * but there seems to be a hardware bug on the 405GP (RevD)
  1328. * that means ESR is sometimes set incorrectly - either to
  1329. * ESR_DST (!?) or 0. In the process of chasing this with the
  1330. * hardware people - not sure if it can happen on any illegal
  1331. * instruction or only on FP instructions, whether there is a
  1332. * pattern to occurrences etc. -dgibson 31/Mar/2003
  1333. */
  1334. if (!emulate_math(regs))
  1335. goto bail;
  1336. /* Try to emulate it if we should. */
  1337. if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
  1338. switch (emulate_instruction(regs)) {
  1339. case 0:
  1340. regs->nip += 4;
  1341. emulate_single_step(regs);
  1342. goto bail;
  1343. case -EFAULT:
  1344. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  1345. goto bail;
  1346. }
  1347. }
  1348. sigill:
  1349. if (reason & REASON_PRIVILEGED)
  1350. _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
  1351. else
  1352. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1353. bail:
  1354. exception_exit(prev_state);
  1355. }
  1356. NOKPROBE_SYMBOL(program_check_exception);
  1357. /*
  1358. * This occurs when running in hypervisor mode on POWER6 or later
  1359. * and an illegal instruction is encountered.
  1360. */
  1361. void emulation_assist_interrupt(struct pt_regs *regs)
  1362. {
  1363. regs->msr |= REASON_ILLEGAL;
  1364. program_check_exception(regs);
  1365. }
  1366. NOKPROBE_SYMBOL(emulation_assist_interrupt);
  1367. void alignment_exception(struct pt_regs *regs)
  1368. {
  1369. enum ctx_state prev_state = exception_enter();
  1370. int sig, code, fixed = 0;
  1371. /* We restore the interrupt state now */
  1372. if (!arch_irq_disabled_regs(regs))
  1373. local_irq_enable();
  1374. if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
  1375. goto bail;
  1376. /* we don't implement logging of alignment exceptions */
  1377. if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
  1378. fixed = fix_alignment(regs);
  1379. if (fixed == 1) {
  1380. regs->nip += 4; /* skip over emulated instruction */
  1381. emulate_single_step(regs);
  1382. goto bail;
  1383. }
  1384. /* Operand address was bad */
  1385. if (fixed == -EFAULT) {
  1386. sig = SIGSEGV;
  1387. code = SEGV_ACCERR;
  1388. } else {
  1389. sig = SIGBUS;
  1390. code = BUS_ADRALN;
  1391. }
  1392. if (user_mode(regs))
  1393. _exception(sig, regs, code, regs->dar);
  1394. else
  1395. bad_page_fault(regs, regs->dar, sig);
  1396. bail:
  1397. exception_exit(prev_state);
  1398. }
  1399. void StackOverflow(struct pt_regs *regs)
  1400. {
  1401. pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
  1402. current->comm, task_pid_nr(current), regs->gpr[1]);
  1403. debugger(regs);
  1404. show_regs(regs);
  1405. panic("kernel stack overflow");
  1406. }
  1407. void stack_overflow_exception(struct pt_regs *regs)
  1408. {
  1409. enum ctx_state prev_state = exception_enter();
  1410. die("Kernel stack overflow", regs, SIGSEGV);
  1411. exception_exit(prev_state);
  1412. }
  1413. void kernel_fp_unavailable_exception(struct pt_regs *regs)
  1414. {
  1415. enum ctx_state prev_state = exception_enter();
  1416. printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
  1417. "%lx at %lx\n", regs->trap, regs->nip);
  1418. die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
  1419. exception_exit(prev_state);
  1420. }
  1421. void altivec_unavailable_exception(struct pt_regs *regs)
  1422. {
  1423. enum ctx_state prev_state = exception_enter();
  1424. if (user_mode(regs)) {
  1425. /* A user program has executed an altivec instruction,
  1426. but this kernel doesn't support altivec. */
  1427. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1428. goto bail;
  1429. }
  1430. printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
  1431. "%lx at %lx\n", regs->trap, regs->nip);
  1432. die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
  1433. bail:
  1434. exception_exit(prev_state);
  1435. }
  1436. void vsx_unavailable_exception(struct pt_regs *regs)
  1437. {
  1438. if (user_mode(regs)) {
  1439. /* A user program has executed an vsx instruction,
  1440. but this kernel doesn't support vsx. */
  1441. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1442. return;
  1443. }
  1444. printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
  1445. "%lx at %lx\n", regs->trap, regs->nip);
  1446. die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
  1447. }
  1448. #ifdef CONFIG_PPC64
  1449. static void tm_unavailable(struct pt_regs *regs)
  1450. {
  1451. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1452. if (user_mode(regs)) {
  1453. current->thread.load_tm++;
  1454. regs->msr |= MSR_TM;
  1455. tm_enable();
  1456. tm_restore_sprs(&current->thread);
  1457. return;
  1458. }
  1459. #endif
  1460. pr_emerg("Unrecoverable TM Unavailable Exception "
  1461. "%lx at %lx\n", regs->trap, regs->nip);
  1462. die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
  1463. }
  1464. void facility_unavailable_exception(struct pt_regs *regs)
  1465. {
  1466. static char *facility_strings[] = {
  1467. [FSCR_FP_LG] = "FPU",
  1468. [FSCR_VECVSX_LG] = "VMX/VSX",
  1469. [FSCR_DSCR_LG] = "DSCR",
  1470. [FSCR_PM_LG] = "PMU SPRs",
  1471. [FSCR_BHRB_LG] = "BHRB",
  1472. [FSCR_TM_LG] = "TM",
  1473. [FSCR_EBB_LG] = "EBB",
  1474. [FSCR_TAR_LG] = "TAR",
  1475. [FSCR_MSGP_LG] = "MSGP",
  1476. [FSCR_SCV_LG] = "SCV",
  1477. };
  1478. char *facility = "unknown";
  1479. u64 value;
  1480. u32 instword, rd;
  1481. u8 status;
  1482. bool hv;
  1483. hv = (TRAP(regs) == 0xf80);
  1484. if (hv)
  1485. value = mfspr(SPRN_HFSCR);
  1486. else
  1487. value = mfspr(SPRN_FSCR);
  1488. status = value >> 56;
  1489. if ((hv || status >= 2) &&
  1490. (status < ARRAY_SIZE(facility_strings)) &&
  1491. facility_strings[status])
  1492. facility = facility_strings[status];
  1493. /* We should not have taken this interrupt in kernel */
  1494. if (!user_mode(regs)) {
  1495. pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
  1496. facility, status, regs->nip);
  1497. die("Unexpected facility unavailable exception", regs, SIGABRT);
  1498. }
  1499. /* We restore the interrupt state now */
  1500. if (!arch_irq_disabled_regs(regs))
  1501. local_irq_enable();
  1502. if (status == FSCR_DSCR_LG) {
  1503. /*
  1504. * User is accessing the DSCR register using the problem
  1505. * state only SPR number (0x03) either through a mfspr or
  1506. * a mtspr instruction. If it is a write attempt through
  1507. * a mtspr, then we set the inherit bit. This also allows
  1508. * the user to write or read the register directly in the
  1509. * future by setting via the FSCR DSCR bit. But in case it
  1510. * is a read DSCR attempt through a mfspr instruction, we
  1511. * just emulate the instruction instead. This code path will
  1512. * always emulate all the mfspr instructions till the user
  1513. * has attempted at least one mtspr instruction. This way it
  1514. * preserves the same behaviour when the user is accessing
  1515. * the DSCR through privilege level only SPR number (0x11)
  1516. * which is emulated through illegal instruction exception.
  1517. * We always leave HFSCR DSCR set.
  1518. */
  1519. if (get_user(instword, (u32 __user *)(regs->nip))) {
  1520. pr_err("Failed to fetch the user instruction\n");
  1521. return;
  1522. }
  1523. /* Write into DSCR (mtspr 0x03, RS) */
  1524. if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
  1525. == PPC_INST_MTSPR_DSCR_USER) {
  1526. rd = (instword >> 21) & 0x1f;
  1527. current->thread.dscr = regs->gpr[rd];
  1528. current->thread.dscr_inherit = 1;
  1529. current->thread.fscr |= FSCR_DSCR;
  1530. mtspr(SPRN_FSCR, current->thread.fscr);
  1531. }
  1532. /* Read from DSCR (mfspr RT, 0x03) */
  1533. if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
  1534. == PPC_INST_MFSPR_DSCR_USER) {
  1535. if (emulate_instruction(regs)) {
  1536. pr_err("DSCR based mfspr emulation failed\n");
  1537. return;
  1538. }
  1539. regs->nip += 4;
  1540. emulate_single_step(regs);
  1541. }
  1542. return;
  1543. }
  1544. if (status == FSCR_TM_LG) {
  1545. /*
  1546. * If we're here then the hardware is TM aware because it
  1547. * generated an exception with FSRM_TM set.
  1548. *
  1549. * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
  1550. * told us not to do TM, or the kernel is not built with TM
  1551. * support.
  1552. *
  1553. * If both of those things are true, then userspace can spam the
  1554. * console by triggering the printk() below just by continually
  1555. * doing tbegin (or any TM instruction). So in that case just
  1556. * send the process a SIGILL immediately.
  1557. */
  1558. if (!cpu_has_feature(CPU_FTR_TM))
  1559. goto out;
  1560. tm_unavailable(regs);
  1561. return;
  1562. }
  1563. pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
  1564. hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
  1565. out:
  1566. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1567. }
  1568. #endif
  1569. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1570. void fp_unavailable_tm(struct pt_regs *regs)
  1571. {
  1572. /* Note: This does not handle any kind of FP laziness. */
  1573. TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
  1574. regs->nip, regs->msr);
  1575. /* We can only have got here if the task started using FP after
  1576. * beginning the transaction. So, the transactional regs are just a
  1577. * copy of the checkpointed ones. But, we still need to recheckpoint
  1578. * as we're enabling FP for the process; it will return, abort the
  1579. * transaction, and probably retry but now with FP enabled. So the
  1580. * checkpointed FP registers need to be loaded.
  1581. */
  1582. tm_reclaim_current(TM_CAUSE_FAC_UNAV);
  1583. /*
  1584. * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
  1585. * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
  1586. *
  1587. * At this point, ck{fp,vr}_state contains the exact values we want to
  1588. * recheckpoint.
  1589. */
  1590. /* Enable FP for the task: */
  1591. current->thread.load_fp = 1;
  1592. /*
  1593. * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
  1594. */
  1595. tm_recheckpoint(&current->thread);
  1596. }
  1597. void altivec_unavailable_tm(struct pt_regs *regs)
  1598. {
  1599. /* See the comments in fp_unavailable_tm(). This function operates
  1600. * the same way.
  1601. */
  1602. TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
  1603. "MSR=%lx\n",
  1604. regs->nip, regs->msr);
  1605. tm_reclaim_current(TM_CAUSE_FAC_UNAV);
  1606. current->thread.load_vec = 1;
  1607. tm_recheckpoint(&current->thread);
  1608. current->thread.used_vr = 1;
  1609. }
  1610. void vsx_unavailable_tm(struct pt_regs *regs)
  1611. {
  1612. /* See the comments in fp_unavailable_tm(). This works similarly,
  1613. * though we're loading both FP and VEC registers in here.
  1614. *
  1615. * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
  1616. * regs. Either way, set MSR_VSX.
  1617. */
  1618. TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
  1619. "MSR=%lx\n",
  1620. regs->nip, regs->msr);
  1621. current->thread.used_vsr = 1;
  1622. /* This reclaims FP and/or VR regs if they're already enabled */
  1623. tm_reclaim_current(TM_CAUSE_FAC_UNAV);
  1624. current->thread.load_vec = 1;
  1625. current->thread.load_fp = 1;
  1626. tm_recheckpoint(&current->thread);
  1627. }
  1628. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  1629. void performance_monitor_exception(struct pt_regs *regs)
  1630. {
  1631. __this_cpu_inc(irq_stat.pmu_irqs);
  1632. perf_irq(regs);
  1633. }
  1634. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  1635. static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
  1636. {
  1637. int changed = 0;
  1638. /*
  1639. * Determine the cause of the debug event, clear the
  1640. * event flags and send a trap to the handler. Torez
  1641. */
  1642. if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
  1643. dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
  1644. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  1645. current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
  1646. #endif
  1647. do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
  1648. 5);
  1649. changed |= 0x01;
  1650. } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
  1651. dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
  1652. do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
  1653. 6);
  1654. changed |= 0x01;
  1655. } else if (debug_status & DBSR_IAC1) {
  1656. current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
  1657. dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
  1658. do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
  1659. 1);
  1660. changed |= 0x01;
  1661. } else if (debug_status & DBSR_IAC2) {
  1662. current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
  1663. do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
  1664. 2);
  1665. changed |= 0x01;
  1666. } else if (debug_status & DBSR_IAC3) {
  1667. current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
  1668. dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
  1669. do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
  1670. 3);
  1671. changed |= 0x01;
  1672. } else if (debug_status & DBSR_IAC4) {
  1673. current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
  1674. do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
  1675. 4);
  1676. changed |= 0x01;
  1677. }
  1678. /*
  1679. * At the point this routine was called, the MSR(DE) was turned off.
  1680. * Check all other debug flags and see if that bit needs to be turned
  1681. * back on or not.
  1682. */
  1683. if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
  1684. current->thread.debug.dbcr1))
  1685. regs->msr |= MSR_DE;
  1686. else
  1687. /* Make sure the IDM flag is off */
  1688. current->thread.debug.dbcr0 &= ~DBCR0_IDM;
  1689. if (changed & 0x01)
  1690. mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
  1691. }
  1692. void DebugException(struct pt_regs *regs, unsigned long debug_status)
  1693. {
  1694. current->thread.debug.dbsr = debug_status;
  1695. /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
  1696. * on server, it stops on the target of the branch. In order to simulate
  1697. * the server behaviour, we thus restart right away with a single step
  1698. * instead of stopping here when hitting a BT
  1699. */
  1700. if (debug_status & DBSR_BT) {
  1701. regs->msr &= ~MSR_DE;
  1702. /* Disable BT */
  1703. mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
  1704. /* Clear the BT event */
  1705. mtspr(SPRN_DBSR, DBSR_BT);
  1706. /* Do the single step trick only when coming from userspace */
  1707. if (user_mode(regs)) {
  1708. current->thread.debug.dbcr0 &= ~DBCR0_BT;
  1709. current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
  1710. regs->msr |= MSR_DE;
  1711. return;
  1712. }
  1713. if (kprobe_post_handler(regs))
  1714. return;
  1715. if (notify_die(DIE_SSTEP, "block_step", regs, 5,
  1716. 5, SIGTRAP) == NOTIFY_STOP) {
  1717. return;
  1718. }
  1719. if (debugger_sstep(regs))
  1720. return;
  1721. } else if (debug_status & DBSR_IC) { /* Instruction complete */
  1722. regs->msr &= ~MSR_DE;
  1723. /* Disable instruction completion */
  1724. mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
  1725. /* Clear the instruction completion event */
  1726. mtspr(SPRN_DBSR, DBSR_IC);
  1727. if (kprobe_post_handler(regs))
  1728. return;
  1729. if (notify_die(DIE_SSTEP, "single_step", regs, 5,
  1730. 5, SIGTRAP) == NOTIFY_STOP) {
  1731. return;
  1732. }
  1733. if (debugger_sstep(regs))
  1734. return;
  1735. if (user_mode(regs)) {
  1736. current->thread.debug.dbcr0 &= ~DBCR0_IC;
  1737. if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
  1738. current->thread.debug.dbcr1))
  1739. regs->msr |= MSR_DE;
  1740. else
  1741. /* Make sure the IDM bit is off */
  1742. current->thread.debug.dbcr0 &= ~DBCR0_IDM;
  1743. }
  1744. _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
  1745. } else
  1746. handle_debug(regs, debug_status);
  1747. }
  1748. NOKPROBE_SYMBOL(DebugException);
  1749. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  1750. #if !defined(CONFIG_TAU_INT)
  1751. void TAUException(struct pt_regs *regs)
  1752. {
  1753. printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
  1754. regs->nip, regs->msr, regs->trap, print_tainted());
  1755. }
  1756. #endif /* CONFIG_INT_TAU */
  1757. #ifdef CONFIG_ALTIVEC
  1758. void altivec_assist_exception(struct pt_regs *regs)
  1759. {
  1760. int err;
  1761. if (!user_mode(regs)) {
  1762. printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
  1763. " at %lx\n", regs->nip);
  1764. die("Kernel VMX/Altivec assist exception", regs, SIGILL);
  1765. }
  1766. flush_altivec_to_thread(current);
  1767. PPC_WARN_EMULATED(altivec, regs);
  1768. err = emulate_altivec(regs);
  1769. if (err == 0) {
  1770. regs->nip += 4; /* skip emulated instruction */
  1771. emulate_single_step(regs);
  1772. return;
  1773. }
  1774. if (err == -EFAULT) {
  1775. /* got an error reading the instruction */
  1776. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1777. } else {
  1778. /* didn't recognize the instruction */
  1779. /* XXX quick hack for now: set the non-Java bit in the VSCR */
  1780. printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
  1781. "in %s at %lx\n", current->comm, regs->nip);
  1782. current->thread.vr_state.vscr.u[3] |= 0x10000;
  1783. }
  1784. }
  1785. #endif /* CONFIG_ALTIVEC */
  1786. #ifdef CONFIG_FSL_BOOKE
  1787. void CacheLockingException(struct pt_regs *regs, unsigned long address,
  1788. unsigned long error_code)
  1789. {
  1790. /* We treat cache locking instructions from the user
  1791. * as priv ops, in the future we could try to do
  1792. * something smarter
  1793. */
  1794. if (error_code & (ESR_DLK|ESR_ILK))
  1795. _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
  1796. return;
  1797. }
  1798. #endif /* CONFIG_FSL_BOOKE */
  1799. #ifdef CONFIG_SPE
  1800. void SPEFloatingPointException(struct pt_regs *regs)
  1801. {
  1802. extern int do_spe_mathemu(struct pt_regs *regs);
  1803. unsigned long spefscr;
  1804. int fpexc_mode;
  1805. int code = FPE_FLTUNK;
  1806. int err;
  1807. /* We restore the interrupt state now */
  1808. if (!arch_irq_disabled_regs(regs))
  1809. local_irq_enable();
  1810. flush_spe_to_thread(current);
  1811. spefscr = current->thread.spefscr;
  1812. fpexc_mode = current->thread.fpexc_mode;
  1813. if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
  1814. code = FPE_FLTOVF;
  1815. }
  1816. else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
  1817. code = FPE_FLTUND;
  1818. }
  1819. else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
  1820. code = FPE_FLTDIV;
  1821. else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
  1822. code = FPE_FLTINV;
  1823. }
  1824. else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
  1825. code = FPE_FLTRES;
  1826. err = do_spe_mathemu(regs);
  1827. if (err == 0) {
  1828. regs->nip += 4; /* skip emulated instruction */
  1829. emulate_single_step(regs);
  1830. return;
  1831. }
  1832. if (err == -EFAULT) {
  1833. /* got an error reading the instruction */
  1834. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1835. } else if (err == -EINVAL) {
  1836. /* didn't recognize the instruction */
  1837. printk(KERN_ERR "unrecognized spe instruction "
  1838. "in %s at %lx\n", current->comm, regs->nip);
  1839. } else {
  1840. _exception(SIGFPE, regs, code, regs->nip);
  1841. }
  1842. return;
  1843. }
  1844. void SPEFloatingPointRoundException(struct pt_regs *regs)
  1845. {
  1846. extern int speround_handler(struct pt_regs *regs);
  1847. int err;
  1848. /* We restore the interrupt state now */
  1849. if (!arch_irq_disabled_regs(regs))
  1850. local_irq_enable();
  1851. preempt_disable();
  1852. if (regs->msr & MSR_SPE)
  1853. giveup_spe(current);
  1854. preempt_enable();
  1855. regs->nip -= 4;
  1856. err = speround_handler(regs);
  1857. if (err == 0) {
  1858. regs->nip += 4; /* skip emulated instruction */
  1859. emulate_single_step(regs);
  1860. return;
  1861. }
  1862. if (err == -EFAULT) {
  1863. /* got an error reading the instruction */
  1864. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1865. } else if (err == -EINVAL) {
  1866. /* didn't recognize the instruction */
  1867. printk(KERN_ERR "unrecognized spe instruction "
  1868. "in %s at %lx\n", current->comm, regs->nip);
  1869. } else {
  1870. _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip);
  1871. return;
  1872. }
  1873. }
  1874. #endif
  1875. /*
  1876. * We enter here if we get an unrecoverable exception, that is, one
  1877. * that happened at a point where the RI (recoverable interrupt) bit
  1878. * in the MSR is 0. This indicates that SRR0/1 are live, and that
  1879. * we therefore lost state by taking this exception.
  1880. */
  1881. void unrecoverable_exception(struct pt_regs *regs)
  1882. {
  1883. pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
  1884. regs->trap, regs->nip, regs->msr);
  1885. die("Unrecoverable exception", regs, SIGABRT);
  1886. }
  1887. NOKPROBE_SYMBOL(unrecoverable_exception);
  1888. #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
  1889. /*
  1890. * Default handler for a Watchdog exception,
  1891. * spins until a reboot occurs
  1892. */
  1893. void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
  1894. {
  1895. /* Generic WatchdogHandler, implement your own */
  1896. mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
  1897. return;
  1898. }
  1899. void WatchdogException(struct pt_regs *regs)
  1900. {
  1901. printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
  1902. WatchdogHandler(regs);
  1903. }
  1904. #endif
  1905. /*
  1906. * We enter here if we discover during exception entry that we are
  1907. * running in supervisor mode with a userspace value in the stack pointer.
  1908. */
  1909. void kernel_bad_stack(struct pt_regs *regs)
  1910. {
  1911. printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
  1912. regs->gpr[1], regs->nip);
  1913. die("Bad kernel stack pointer", regs, SIGABRT);
  1914. }
  1915. NOKPROBE_SYMBOL(kernel_bad_stack);
  1916. void __init trap_init(void)
  1917. {
  1918. }
  1919. #ifdef CONFIG_PPC_EMULATED_STATS
  1920. #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
  1921. struct ppc_emulated ppc_emulated = {
  1922. #ifdef CONFIG_ALTIVEC
  1923. WARN_EMULATED_SETUP(altivec),
  1924. #endif
  1925. WARN_EMULATED_SETUP(dcba),
  1926. WARN_EMULATED_SETUP(dcbz),
  1927. WARN_EMULATED_SETUP(fp_pair),
  1928. WARN_EMULATED_SETUP(isel),
  1929. WARN_EMULATED_SETUP(mcrxr),
  1930. WARN_EMULATED_SETUP(mfpvr),
  1931. WARN_EMULATED_SETUP(multiple),
  1932. WARN_EMULATED_SETUP(popcntb),
  1933. WARN_EMULATED_SETUP(spe),
  1934. WARN_EMULATED_SETUP(string),
  1935. WARN_EMULATED_SETUP(sync),
  1936. WARN_EMULATED_SETUP(unaligned),
  1937. #ifdef CONFIG_MATH_EMULATION
  1938. WARN_EMULATED_SETUP(math),
  1939. #endif
  1940. #ifdef CONFIG_VSX
  1941. WARN_EMULATED_SETUP(vsx),
  1942. #endif
  1943. #ifdef CONFIG_PPC64
  1944. WARN_EMULATED_SETUP(mfdscr),
  1945. WARN_EMULATED_SETUP(mtdscr),
  1946. WARN_EMULATED_SETUP(lq_stq),
  1947. WARN_EMULATED_SETUP(lxvw4x),
  1948. WARN_EMULATED_SETUP(lxvh8x),
  1949. WARN_EMULATED_SETUP(lxvd2x),
  1950. WARN_EMULATED_SETUP(lxvb16x),
  1951. #endif
  1952. };
  1953. u32 ppc_warn_emulated;
  1954. void ppc_warn_emulated_print(const char *type)
  1955. {
  1956. pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
  1957. type);
  1958. }
  1959. static int __init ppc_warn_emulated_init(void)
  1960. {
  1961. struct dentry *dir;
  1962. unsigned int i;
  1963. struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
  1964. dir = debugfs_create_dir("emulated_instructions",
  1965. powerpc_debugfs_root);
  1966. debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated);
  1967. for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++)
  1968. debugfs_create_u32(entries[i].name, 0644, dir,
  1969. (u32 *)&entries[i].val.counter);
  1970. return 0;
  1971. }
  1972. device_initcall(ppc_warn_emulated_init);
  1973. #endif /* CONFIG_PPC_EMULATED_STATS */