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/arch/powerpc/platforms/cell/spufs/switch.c

http://github.com/mirrors/linux
C | 2208 lines | 1303 code | 258 blank | 647 comment | 101 complexity | 0fec13d5cc42dc5d04d2956943f74a4f MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * spu_switch.c
  4. *
  5. * (C) Copyright IBM Corp. 2005
  6. *
  7. * Author: Mark Nutter <mnutter@us.ibm.com>
  8. *
  9. * Host-side part of SPU context switch sequence outlined in
  10. * Synergistic Processor Element, Book IV.
  11. *
  12. * A fully premptive switch of an SPE is very expensive in terms
  13. * of time and system resources. SPE Book IV indicates that SPE
  14. * allocation should follow a "serially reusable device" model,
  15. * in which the SPE is assigned a task until it completes. When
  16. * this is not possible, this sequence may be used to premptively
  17. * save, and then later (optionally) restore the context of a
  18. * program executing on an SPE.
  19. */
  20. #include <linux/export.h>
  21. #include <linux/errno.h>
  22. #include <linux/hardirq.h>
  23. #include <linux/sched.h>
  24. #include <linux/kernel.h>
  25. #include <linux/mm.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/smp.h>
  28. #include <linux/stddef.h>
  29. #include <linux/unistd.h>
  30. #include <asm/io.h>
  31. #include <asm/spu.h>
  32. #include <asm/spu_priv1.h>
  33. #include <asm/spu_csa.h>
  34. #include <asm/mmu_context.h>
  35. #include "spufs.h"
  36. #include "spu_save_dump.h"
  37. #include "spu_restore_dump.h"
  38. #if 0
  39. #define POLL_WHILE_TRUE(_c) { \
  40. do { \
  41. } while (_c); \
  42. }
  43. #else
  44. #define RELAX_SPIN_COUNT 1000
  45. #define POLL_WHILE_TRUE(_c) { \
  46. do { \
  47. int _i; \
  48. for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  49. cpu_relax(); \
  50. } \
  51. if (unlikely(_c)) yield(); \
  52. else break; \
  53. } while (_c); \
  54. }
  55. #endif /* debug */
  56. #define POLL_WHILE_FALSE(_c) POLL_WHILE_TRUE(!(_c))
  57. static inline void acquire_spu_lock(struct spu *spu)
  58. {
  59. /* Save, Step 1:
  60. * Restore, Step 1:
  61. * Acquire SPU-specific mutual exclusion lock.
  62. * TBD.
  63. */
  64. }
  65. static inline void release_spu_lock(struct spu *spu)
  66. {
  67. /* Restore, Step 76:
  68. * Release SPU-specific mutual exclusion lock.
  69. * TBD.
  70. */
  71. }
  72. static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  73. {
  74. struct spu_problem __iomem *prob = spu->problem;
  75. u32 isolate_state;
  76. /* Save, Step 2:
  77. * Save, Step 6:
  78. * If SPU_Status[E,L,IS] any field is '1', this
  79. * SPU is in isolate state and cannot be context
  80. * saved at this time.
  81. */
  82. isolate_state = SPU_STATUS_ISOLATED_STATE |
  83. SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
  84. return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
  85. }
  86. static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
  87. {
  88. /* Save, Step 3:
  89. * Restore, Step 2:
  90. * Save INT_Mask_class0 in CSA.
  91. * Write INT_MASK_class0 with value of 0.
  92. * Save INT_Mask_class1 in CSA.
  93. * Write INT_MASK_class1 with value of 0.
  94. * Save INT_Mask_class2 in CSA.
  95. * Write INT_MASK_class2 with value of 0.
  96. * Synchronize all three interrupts to be sure
  97. * we no longer execute a handler on another CPU.
  98. */
  99. spin_lock_irq(&spu->register_lock);
  100. if (csa) {
  101. csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
  102. csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
  103. csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
  104. }
  105. spu_int_mask_set(spu, 0, 0ul);
  106. spu_int_mask_set(spu, 1, 0ul);
  107. spu_int_mask_set(spu, 2, 0ul);
  108. eieio();
  109. spin_unlock_irq(&spu->register_lock);
  110. /*
  111. * This flag needs to be set before calling synchronize_irq so
  112. * that the update will be visible to the relevant handlers
  113. * via a simple load.
  114. */
  115. set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
  116. clear_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);
  117. synchronize_irq(spu->irqs[0]);
  118. synchronize_irq(spu->irqs[1]);
  119. synchronize_irq(spu->irqs[2]);
  120. }
  121. static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
  122. {
  123. /* Save, Step 4:
  124. * Restore, Step 25.
  125. * Set a software watchdog timer, which specifies the
  126. * maximum allowable time for a context save sequence.
  127. *
  128. * For present, this implementation will not set a global
  129. * watchdog timer, as virtualization & variable system load
  130. * may cause unpredictable execution times.
  131. */
  132. }
  133. static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
  134. {
  135. /* Save, Step 5:
  136. * Restore, Step 3:
  137. * Inhibit user-space access (if provided) to this
  138. * SPU by unmapping the virtual pages assigned to
  139. * the SPU memory-mapped I/O (MMIO) for problem
  140. * state. TBD.
  141. */
  142. }
  143. static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
  144. {
  145. /* Save, Step 7:
  146. * Restore, Step 5:
  147. * Set a software context switch pending flag.
  148. * Done above in Step 3 - disable_interrupts().
  149. */
  150. }
  151. static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
  152. {
  153. struct spu_priv2 __iomem *priv2 = spu->priv2;
  154. /* Save, Step 8:
  155. * Suspend DMA and save MFC_CNTL.
  156. */
  157. switch (in_be64(&priv2->mfc_control_RW) &
  158. MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
  159. case MFC_CNTL_SUSPEND_IN_PROGRESS:
  160. POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
  161. MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
  162. MFC_CNTL_SUSPEND_COMPLETE);
  163. fallthrough;
  164. case MFC_CNTL_SUSPEND_COMPLETE:
  165. if (csa)
  166. csa->priv2.mfc_control_RW =
  167. in_be64(&priv2->mfc_control_RW) |
  168. MFC_CNTL_SUSPEND_DMA_QUEUE;
  169. break;
  170. case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
  171. out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
  172. POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
  173. MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
  174. MFC_CNTL_SUSPEND_COMPLETE);
  175. if (csa)
  176. csa->priv2.mfc_control_RW =
  177. in_be64(&priv2->mfc_control_RW) &
  178. ~MFC_CNTL_SUSPEND_DMA_QUEUE &
  179. ~MFC_CNTL_SUSPEND_MASK;
  180. break;
  181. }
  182. }
  183. static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
  184. {
  185. struct spu_problem __iomem *prob = spu->problem;
  186. /* Save, Step 9:
  187. * Save SPU_Runcntl in the CSA. This value contains
  188. * the "Application Desired State".
  189. */
  190. csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
  191. }
  192. static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
  193. {
  194. /* Save, Step 10:
  195. * Save MFC_SR1 in the CSA.
  196. */
  197. csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
  198. }
  199. static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
  200. {
  201. struct spu_problem __iomem *prob = spu->problem;
  202. /* Save, Step 11:
  203. * Read SPU_Status[R], and save to CSA.
  204. */
  205. if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
  206. csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
  207. } else {
  208. u32 stopped;
  209. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
  210. eieio();
  211. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  212. SPU_STATUS_RUNNING);
  213. stopped =
  214. SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
  215. SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
  216. if ((in_be32(&prob->spu_status_R) & stopped) == 0)
  217. csa->prob.spu_status_R = SPU_STATUS_RUNNING;
  218. else
  219. csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
  220. }
  221. }
  222. static inline void save_mfc_stopped_status(struct spu_state *csa,
  223. struct spu *spu)
  224. {
  225. struct spu_priv2 __iomem *priv2 = spu->priv2;
  226. const u64 mask = MFC_CNTL_DECREMENTER_RUNNING |
  227. MFC_CNTL_DMA_QUEUES_EMPTY;
  228. /* Save, Step 12:
  229. * Read MFC_CNTL[Ds]. Update saved copy of
  230. * CSA.MFC_CNTL[Ds].
  231. *
  232. * update: do the same with MFC_CNTL[Q].
  233. */
  234. csa->priv2.mfc_control_RW &= ~mask;
  235. csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
  236. }
  237. static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
  238. {
  239. struct spu_priv2 __iomem *priv2 = spu->priv2;
  240. /* Save, Step 13:
  241. * Write MFC_CNTL[Dh] set to a '1' to halt
  242. * the decrementer.
  243. */
  244. out_be64(&priv2->mfc_control_RW,
  245. MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
  246. eieio();
  247. }
  248. static inline void save_timebase(struct spu_state *csa, struct spu *spu)
  249. {
  250. /* Save, Step 14:
  251. * Read PPE Timebase High and Timebase low registers
  252. * and save in CSA. TBD.
  253. */
  254. csa->suspend_time = get_cycles();
  255. }
  256. static inline void remove_other_spu_access(struct spu_state *csa,
  257. struct spu *spu)
  258. {
  259. /* Save, Step 15:
  260. * Remove other SPU access to this SPU by unmapping
  261. * this SPU's pages from their address space. TBD.
  262. */
  263. }
  264. static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
  265. {
  266. struct spu_problem __iomem *prob = spu->problem;
  267. /* Save, Step 16:
  268. * Restore, Step 11.
  269. * Write SPU_MSSync register. Poll SPU_MSSync[P]
  270. * for a value of 0.
  271. */
  272. out_be64(&prob->spc_mssync_RW, 1UL);
  273. POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
  274. }
  275. static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
  276. {
  277. /* Save, Step 17:
  278. * Restore, Step 12.
  279. * Restore, Step 48.
  280. * Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
  281. * Then issue a PPE sync instruction.
  282. */
  283. spu_tlb_invalidate(spu);
  284. mb();
  285. }
  286. static inline void handle_pending_interrupts(struct spu_state *csa,
  287. struct spu *spu)
  288. {
  289. /* Save, Step 18:
  290. * Handle any pending interrupts from this SPU
  291. * here. This is OS or hypervisor specific. One
  292. * option is to re-enable interrupts to handle any
  293. * pending interrupts, with the interrupt handlers
  294. * recognizing the software Context Switch Pending
  295. * flag, to ensure the SPU execution or MFC command
  296. * queue is not restarted. TBD.
  297. */
  298. }
  299. static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
  300. {
  301. struct spu_priv2 __iomem *priv2 = spu->priv2;
  302. int i;
  303. /* Save, Step 19:
  304. * If MFC_Cntl[Se]=0 then save
  305. * MFC command queues.
  306. */
  307. if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
  308. for (i = 0; i < 8; i++) {
  309. csa->priv2.puq[i].mfc_cq_data0_RW =
  310. in_be64(&priv2->puq[i].mfc_cq_data0_RW);
  311. csa->priv2.puq[i].mfc_cq_data1_RW =
  312. in_be64(&priv2->puq[i].mfc_cq_data1_RW);
  313. csa->priv2.puq[i].mfc_cq_data2_RW =
  314. in_be64(&priv2->puq[i].mfc_cq_data2_RW);
  315. csa->priv2.puq[i].mfc_cq_data3_RW =
  316. in_be64(&priv2->puq[i].mfc_cq_data3_RW);
  317. }
  318. for (i = 0; i < 16; i++) {
  319. csa->priv2.spuq[i].mfc_cq_data0_RW =
  320. in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
  321. csa->priv2.spuq[i].mfc_cq_data1_RW =
  322. in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
  323. csa->priv2.spuq[i].mfc_cq_data2_RW =
  324. in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
  325. csa->priv2.spuq[i].mfc_cq_data3_RW =
  326. in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
  327. }
  328. }
  329. }
  330. static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
  331. {
  332. struct spu_problem __iomem *prob = spu->problem;
  333. /* Save, Step 20:
  334. * Save the PPU_QueryMask register
  335. * in the CSA.
  336. */
  337. csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
  338. }
  339. static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
  340. {
  341. struct spu_problem __iomem *prob = spu->problem;
  342. /* Save, Step 21:
  343. * Save the PPU_QueryType register
  344. * in the CSA.
  345. */
  346. csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
  347. }
  348. static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
  349. {
  350. struct spu_problem __iomem *prob = spu->problem;
  351. /* Save the Prxy_TagStatus register in the CSA.
  352. *
  353. * It is unnecessary to restore dma_tagstatus_R, however,
  354. * dma_tagstatus_R in the CSA is accessed via backing_ops, so
  355. * we must save it.
  356. */
  357. csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
  358. }
  359. static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
  360. {
  361. struct spu_priv2 __iomem *priv2 = spu->priv2;
  362. /* Save, Step 22:
  363. * Save the MFC_CSR_TSQ register
  364. * in the LSCSA.
  365. */
  366. csa->priv2.spu_tag_status_query_RW =
  367. in_be64(&priv2->spu_tag_status_query_RW);
  368. }
  369. static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
  370. {
  371. struct spu_priv2 __iomem *priv2 = spu->priv2;
  372. /* Save, Step 23:
  373. * Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
  374. * registers in the CSA.
  375. */
  376. csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
  377. csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
  378. }
  379. static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
  380. {
  381. struct spu_priv2 __iomem *priv2 = spu->priv2;
  382. /* Save, Step 24:
  383. * Save the MFC_CSR_ATO register in
  384. * the CSA.
  385. */
  386. csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
  387. }
  388. static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
  389. {
  390. /* Save, Step 25:
  391. * Save the MFC_TCLASS_ID register in
  392. * the CSA.
  393. */
  394. csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
  395. }
  396. static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
  397. {
  398. /* Save, Step 26:
  399. * Restore, Step 23.
  400. * Write the MFC_TCLASS_ID register with
  401. * the value 0x10000000.
  402. */
  403. spu_mfc_tclass_id_set(spu, 0x10000000);
  404. eieio();
  405. }
  406. static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
  407. {
  408. struct spu_priv2 __iomem *priv2 = spu->priv2;
  409. /* Save, Step 27:
  410. * Restore, Step 14.
  411. * Write MFC_CNTL[Pc]=1 (purge queue).
  412. */
  413. out_be64(&priv2->mfc_control_RW,
  414. MFC_CNTL_PURGE_DMA_REQUEST |
  415. MFC_CNTL_SUSPEND_MASK);
  416. eieio();
  417. }
  418. static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
  419. {
  420. struct spu_priv2 __iomem *priv2 = spu->priv2;
  421. /* Save, Step 28:
  422. * Poll MFC_CNTL[Ps] until value '11' is read
  423. * (purge complete).
  424. */
  425. POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
  426. MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
  427. MFC_CNTL_PURGE_DMA_COMPLETE);
  428. }
  429. static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
  430. {
  431. /* Save, Step 30:
  432. * Restore, Step 18:
  433. * Write MFC_SR1 with MFC_SR1[D=0,S=1] and
  434. * MFC_SR1[TL,R,Pr,T] set correctly for the
  435. * OS specific environment.
  436. *
  437. * Implementation note: The SPU-side code
  438. * for save/restore is privileged, so the
  439. * MFC_SR1[Pr] bit is not set.
  440. *
  441. */
  442. spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
  443. MFC_STATE1_RELOCATE_MASK |
  444. MFC_STATE1_BUS_TLBIE_MASK));
  445. }
  446. static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
  447. {
  448. struct spu_problem __iomem *prob = spu->problem;
  449. /* Save, Step 31:
  450. * Save SPU_NPC in the CSA.
  451. */
  452. csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
  453. }
  454. static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
  455. {
  456. struct spu_priv2 __iomem *priv2 = spu->priv2;
  457. /* Save, Step 32:
  458. * Save SPU_PrivCntl in the CSA.
  459. */
  460. csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
  461. }
  462. static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
  463. {
  464. struct spu_priv2 __iomem *priv2 = spu->priv2;
  465. /* Save, Step 33:
  466. * Restore, Step 16:
  467. * Write SPU_PrivCntl[S,Le,A] fields reset to 0.
  468. */
  469. out_be64(&priv2->spu_privcntl_RW, 0UL);
  470. eieio();
  471. }
  472. static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
  473. {
  474. struct spu_priv2 __iomem *priv2 = spu->priv2;
  475. /* Save, Step 34:
  476. * Save SPU_LSLR in the CSA.
  477. */
  478. csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
  479. }
  480. static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
  481. {
  482. struct spu_priv2 __iomem *priv2 = spu->priv2;
  483. /* Save, Step 35:
  484. * Restore, Step 17.
  485. * Reset SPU_LSLR.
  486. */
  487. out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
  488. eieio();
  489. }
  490. static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
  491. {
  492. struct spu_priv2 __iomem *priv2 = spu->priv2;
  493. /* Save, Step 36:
  494. * Save SPU_Cfg in the CSA.
  495. */
  496. csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
  497. }
  498. static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
  499. {
  500. /* Save, Step 37:
  501. * Save PM_Trace_Tag_Wait_Mask in the CSA.
  502. * Not performed by this implementation.
  503. */
  504. }
  505. static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
  506. {
  507. /* Save, Step 38:
  508. * Save RA_GROUP_ID register and the
  509. * RA_ENABLE reigster in the CSA.
  510. */
  511. csa->priv1.resource_allocation_groupID_RW =
  512. spu_resource_allocation_groupID_get(spu);
  513. csa->priv1.resource_allocation_enable_RW =
  514. spu_resource_allocation_enable_get(spu);
  515. }
  516. static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
  517. {
  518. struct spu_problem __iomem *prob = spu->problem;
  519. /* Save, Step 39:
  520. * Save MB_Stat register in the CSA.
  521. */
  522. csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
  523. }
  524. static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
  525. {
  526. struct spu_problem __iomem *prob = spu->problem;
  527. /* Save, Step 40:
  528. * Save the PPU_MB register in the CSA.
  529. */
  530. csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
  531. }
  532. static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
  533. {
  534. struct spu_priv2 __iomem *priv2 = spu->priv2;
  535. /* Save, Step 41:
  536. * Save the PPUINT_MB register in the CSA.
  537. */
  538. csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
  539. }
  540. static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
  541. {
  542. struct spu_priv2 __iomem *priv2 = spu->priv2;
  543. u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
  544. int i;
  545. /* Save, Step 42:
  546. */
  547. /* Save CH 1, without channel count */
  548. out_be64(&priv2->spu_chnlcntptr_RW, 1);
  549. csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
  550. /* Save the following CH: [0,3,4,24,25,27] */
  551. for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
  552. idx = ch_indices[i];
  553. out_be64(&priv2->spu_chnlcntptr_RW, idx);
  554. eieio();
  555. csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
  556. csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
  557. out_be64(&priv2->spu_chnldata_RW, 0UL);
  558. out_be64(&priv2->spu_chnlcnt_RW, 0UL);
  559. eieio();
  560. }
  561. }
  562. static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
  563. {
  564. struct spu_priv2 __iomem *priv2 = spu->priv2;
  565. int i;
  566. /* Save, Step 43:
  567. * Save SPU Read Mailbox Channel.
  568. */
  569. out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
  570. eieio();
  571. csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
  572. for (i = 0; i < 4; i++) {
  573. csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
  574. }
  575. out_be64(&priv2->spu_chnlcnt_RW, 0UL);
  576. eieio();
  577. }
  578. static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
  579. {
  580. struct spu_priv2 __iomem *priv2 = spu->priv2;
  581. /* Save, Step 44:
  582. * Save MFC_CMD Channel.
  583. */
  584. out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
  585. eieio();
  586. csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
  587. eieio();
  588. }
  589. static inline void reset_ch(struct spu_state *csa, struct spu *spu)
  590. {
  591. struct spu_priv2 __iomem *priv2 = spu->priv2;
  592. u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
  593. u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
  594. u64 idx;
  595. int i;
  596. /* Save, Step 45:
  597. * Reset the following CH: [21, 23, 28, 30]
  598. */
  599. for (i = 0; i < 4; i++) {
  600. idx = ch_indices[i];
  601. out_be64(&priv2->spu_chnlcntptr_RW, idx);
  602. eieio();
  603. out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
  604. eieio();
  605. }
  606. }
  607. static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
  608. {
  609. struct spu_priv2 __iomem *priv2 = spu->priv2;
  610. /* Save, Step 46:
  611. * Restore, Step 25.
  612. * Write MFC_CNTL[Sc]=0 (resume queue processing).
  613. */
  614. out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
  615. }
  616. static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,
  617. unsigned int *code, int code_size)
  618. {
  619. /* Save, Step 47:
  620. * Restore, Step 30.
  621. * If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
  622. * register, then initialize SLB_VSID and SLB_ESID
  623. * to provide access to SPU context save code and
  624. * LSCSA.
  625. *
  626. * This implementation places both the context
  627. * switch code and LSCSA in kernel address space.
  628. *
  629. * Further this implementation assumes that the
  630. * MFC_SR1[R]=1 (in other words, assume that
  631. * translation is desired by OS environment).
  632. */
  633. spu_invalidate_slbs(spu);
  634. spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);
  635. }
  636. static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
  637. {
  638. /* Save, Step 48:
  639. * Restore, Step 23.
  640. * Change the software context switch pending flag
  641. * to context switch active. This implementation does
  642. * not uses a switch active flag.
  643. *
  644. * Now that we have saved the mfc in the csa, we can add in the
  645. * restart command if an exception occurred.
  646. */
  647. if (test_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags))
  648. csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
  649. clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
  650. mb();
  651. }
  652. static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
  653. {
  654. unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
  655. CLASS1_ENABLE_STORAGE_FAULT_INTR;
  656. /* Save, Step 49:
  657. * Restore, Step 22:
  658. * Reset and then enable interrupts, as
  659. * needed by OS.
  660. *
  661. * This implementation enables only class1
  662. * (translation) interrupts.
  663. */
  664. spin_lock_irq(&spu->register_lock);
  665. spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
  666. spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
  667. spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
  668. spu_int_mask_set(spu, 0, 0ul);
  669. spu_int_mask_set(spu, 1, class1_mask);
  670. spu_int_mask_set(spu, 2, 0ul);
  671. spin_unlock_irq(&spu->register_lock);
  672. }
  673. static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
  674. unsigned int ls_offset, unsigned int size,
  675. unsigned int tag, unsigned int rclass,
  676. unsigned int cmd)
  677. {
  678. struct spu_problem __iomem *prob = spu->problem;
  679. union mfc_tag_size_class_cmd command;
  680. unsigned int transfer_size;
  681. volatile unsigned int status = 0x0;
  682. while (size > 0) {
  683. transfer_size =
  684. (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
  685. command.u.mfc_size = transfer_size;
  686. command.u.mfc_tag = tag;
  687. command.u.mfc_rclassid = rclass;
  688. command.u.mfc_cmd = cmd;
  689. do {
  690. out_be32(&prob->mfc_lsa_W, ls_offset);
  691. out_be64(&prob->mfc_ea_W, ea);
  692. out_be64(&prob->mfc_union_W.all64, command.all64);
  693. status =
  694. in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
  695. if (unlikely(status & 0x2)) {
  696. cpu_relax();
  697. }
  698. } while (status & 0x3);
  699. size -= transfer_size;
  700. ea += transfer_size;
  701. ls_offset += transfer_size;
  702. }
  703. return 0;
  704. }
  705. static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
  706. {
  707. unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
  708. unsigned int ls_offset = 0x0;
  709. unsigned int size = 16384;
  710. unsigned int tag = 0;
  711. unsigned int rclass = 0;
  712. unsigned int cmd = MFC_PUT_CMD;
  713. /* Save, Step 50:
  714. * Issue a DMA command to copy the first 16K bytes
  715. * of local storage to the CSA.
  716. */
  717. send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
  718. }
  719. static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
  720. {
  721. struct spu_problem __iomem *prob = spu->problem;
  722. /* Save, Step 51:
  723. * Restore, Step 31.
  724. * Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
  725. * point address of context save code in local
  726. * storage.
  727. *
  728. * This implementation uses SPU-side save/restore
  729. * programs with entry points at LSA of 0.
  730. */
  731. out_be32(&prob->spu_npc_RW, 0);
  732. eieio();
  733. }
  734. static inline void set_signot1(struct spu_state *csa, struct spu *spu)
  735. {
  736. struct spu_problem __iomem *prob = spu->problem;
  737. union {
  738. u64 ull;
  739. u32 ui[2];
  740. } addr64;
  741. /* Save, Step 52:
  742. * Restore, Step 32:
  743. * Write SPU_Sig_Notify_1 register with upper 32-bits
  744. * of the CSA.LSCSA effective address.
  745. */
  746. addr64.ull = (u64) csa->lscsa;
  747. out_be32(&prob->signal_notify1, addr64.ui[0]);
  748. eieio();
  749. }
  750. static inline void set_signot2(struct spu_state *csa, struct spu *spu)
  751. {
  752. struct spu_problem __iomem *prob = spu->problem;
  753. union {
  754. u64 ull;
  755. u32 ui[2];
  756. } addr64;
  757. /* Save, Step 53:
  758. * Restore, Step 33:
  759. * Write SPU_Sig_Notify_2 register with lower 32-bits
  760. * of the CSA.LSCSA effective address.
  761. */
  762. addr64.ull = (u64) csa->lscsa;
  763. out_be32(&prob->signal_notify2, addr64.ui[1]);
  764. eieio();
  765. }
  766. static inline void send_save_code(struct spu_state *csa, struct spu *spu)
  767. {
  768. unsigned long addr = (unsigned long)&spu_save_code[0];
  769. unsigned int ls_offset = 0x0;
  770. unsigned int size = sizeof(spu_save_code);
  771. unsigned int tag = 0;
  772. unsigned int rclass = 0;
  773. unsigned int cmd = MFC_GETFS_CMD;
  774. /* Save, Step 54:
  775. * Issue a DMA command to copy context save code
  776. * to local storage and start SPU.
  777. */
  778. send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
  779. }
  780. static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
  781. {
  782. struct spu_problem __iomem *prob = spu->problem;
  783. /* Save, Step 55:
  784. * Restore, Step 38.
  785. * Write PPU_QueryMask=1 (enable Tag Group 0)
  786. * and issue eieio instruction.
  787. */
  788. out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
  789. eieio();
  790. }
  791. static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
  792. {
  793. struct spu_problem __iomem *prob = spu->problem;
  794. u32 mask = MFC_TAGID_TO_TAGMASK(0);
  795. unsigned long flags;
  796. /* Save, Step 56:
  797. * Restore, Step 39.
  798. * Restore, Step 39.
  799. * Restore, Step 46.
  800. * Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
  801. * or write PPU_QueryType[TS]=01 and wait for Tag Group
  802. * Complete Interrupt. Write INT_Stat_Class0 or
  803. * INT_Stat_Class2 with value of 'handled'.
  804. */
  805. POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
  806. local_irq_save(flags);
  807. spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
  808. spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
  809. local_irq_restore(flags);
  810. }
  811. static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
  812. {
  813. struct spu_problem __iomem *prob = spu->problem;
  814. unsigned long flags;
  815. /* Save, Step 57:
  816. * Restore, Step 40.
  817. * Poll until SPU_Status[R]=0 or wait for SPU Class 0
  818. * or SPU Class 2 interrupt. Write INT_Stat_class0
  819. * or INT_Stat_class2 with value of handled.
  820. */
  821. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
  822. local_irq_save(flags);
  823. spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
  824. spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
  825. local_irq_restore(flags);
  826. }
  827. static inline int check_save_status(struct spu_state *csa, struct spu *spu)
  828. {
  829. struct spu_problem __iomem *prob = spu->problem;
  830. u32 complete;
  831. /* Save, Step 54:
  832. * If SPU_Status[P]=1 and SPU_Status[SC] = "success",
  833. * context save succeeded, otherwise context save
  834. * failed.
  835. */
  836. complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
  837. SPU_STATUS_STOPPED_BY_STOP);
  838. return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
  839. }
  840. static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
  841. {
  842. /* Restore, Step 4:
  843. * If required, notify the "using application" that
  844. * the SPU task has been terminated. TBD.
  845. */
  846. }
  847. static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
  848. struct spu *spu)
  849. {
  850. struct spu_priv2 __iomem *priv2 = spu->priv2;
  851. /* Restore, Step 7:
  852. * Write MFC_Cntl[Dh,Sc,Sm]='1','1','0' to suspend
  853. * the queue and halt the decrementer.
  854. */
  855. out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
  856. MFC_CNTL_DECREMENTER_HALTED);
  857. eieio();
  858. }
  859. static inline void wait_suspend_mfc_complete(struct spu_state *csa,
  860. struct spu *spu)
  861. {
  862. struct spu_priv2 __iomem *priv2 = spu->priv2;
  863. /* Restore, Step 8:
  864. * Restore, Step 47.
  865. * Poll MFC_CNTL[Ss] until 11 is returned.
  866. */
  867. POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
  868. MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
  869. MFC_CNTL_SUSPEND_COMPLETE);
  870. }
  871. static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
  872. {
  873. struct spu_problem __iomem *prob = spu->problem;
  874. /* Restore, Step 9:
  875. * If SPU_Status[R]=1, stop SPU execution
  876. * and wait for stop to complete.
  877. *
  878. * Returns 1 if SPU_Status[R]=1 on entry.
  879. * 0 otherwise
  880. */
  881. if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
  882. if (in_be32(&prob->spu_status_R) &
  883. SPU_STATUS_ISOLATED_EXIT_STATUS) {
  884. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  885. SPU_STATUS_RUNNING);
  886. }
  887. if ((in_be32(&prob->spu_status_R) &
  888. SPU_STATUS_ISOLATED_LOAD_STATUS)
  889. || (in_be32(&prob->spu_status_R) &
  890. SPU_STATUS_ISOLATED_STATE)) {
  891. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
  892. eieio();
  893. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  894. SPU_STATUS_RUNNING);
  895. out_be32(&prob->spu_runcntl_RW, 0x2);
  896. eieio();
  897. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  898. SPU_STATUS_RUNNING);
  899. }
  900. if (in_be32(&prob->spu_status_R) &
  901. SPU_STATUS_WAITING_FOR_CHANNEL) {
  902. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
  903. eieio();
  904. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  905. SPU_STATUS_RUNNING);
  906. }
  907. return 1;
  908. }
  909. return 0;
  910. }
  911. static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
  912. {
  913. struct spu_problem __iomem *prob = spu->problem;
  914. /* Restore, Step 10:
  915. * If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
  916. * release SPU from isolate state.
  917. */
  918. if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
  919. if (in_be32(&prob->spu_status_R) &
  920. SPU_STATUS_ISOLATED_EXIT_STATUS) {
  921. spu_mfc_sr1_set(spu,
  922. MFC_STATE1_MASTER_RUN_CONTROL_MASK);
  923. eieio();
  924. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
  925. eieio();
  926. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  927. SPU_STATUS_RUNNING);
  928. }
  929. if ((in_be32(&prob->spu_status_R) &
  930. SPU_STATUS_ISOLATED_LOAD_STATUS)
  931. || (in_be32(&prob->spu_status_R) &
  932. SPU_STATUS_ISOLATED_STATE)) {
  933. spu_mfc_sr1_set(spu,
  934. MFC_STATE1_MASTER_RUN_CONTROL_MASK);
  935. eieio();
  936. out_be32(&prob->spu_runcntl_RW, 0x2);
  937. eieio();
  938. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  939. SPU_STATUS_RUNNING);
  940. }
  941. }
  942. }
  943. static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
  944. {
  945. struct spu_priv2 __iomem *priv2 = spu->priv2;
  946. u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
  947. u64 idx;
  948. int i;
  949. /* Restore, Step 20:
  950. */
  951. /* Reset CH 1 */
  952. out_be64(&priv2->spu_chnlcntptr_RW, 1);
  953. out_be64(&priv2->spu_chnldata_RW, 0UL);
  954. /* Reset the following CH: [0,3,4,24,25,27] */
  955. for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
  956. idx = ch_indices[i];
  957. out_be64(&priv2->spu_chnlcntptr_RW, idx);
  958. eieio();
  959. out_be64(&priv2->spu_chnldata_RW, 0UL);
  960. out_be64(&priv2->spu_chnlcnt_RW, 0UL);
  961. eieio();
  962. }
  963. }
  964. static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
  965. {
  966. struct spu_priv2 __iomem *priv2 = spu->priv2;
  967. u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
  968. u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
  969. u64 idx;
  970. int i;
  971. /* Restore, Step 21:
  972. * Reset the following CH: [21, 23, 28, 29, 30]
  973. */
  974. for (i = 0; i < 5; i++) {
  975. idx = ch_indices[i];
  976. out_be64(&priv2->spu_chnlcntptr_RW, idx);
  977. eieio();
  978. out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
  979. eieio();
  980. }
  981. }
  982. static inline void setup_spu_status_part1(struct spu_state *csa,
  983. struct spu *spu)
  984. {
  985. u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
  986. u32 status_I = SPU_STATUS_INVALID_INSTR;
  987. u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
  988. u32 status_S = SPU_STATUS_SINGLE_STEP;
  989. u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
  990. u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
  991. u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
  992. u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
  993. u32 status_code;
  994. /* Restore, Step 27:
  995. * If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
  996. * instruction sequence to the end of the SPU based restore
  997. * code (after the "context restored" stop and signal) to
  998. * restore the correct SPU status.
  999. *
  1000. * NOTE: Rather than modifying the SPU executable, we
  1001. * instead add a new 'stopped_status' field to the
  1002. * LSCSA. The SPU-side restore reads this field and
  1003. * takes the appropriate action when exiting.
  1004. */
  1005. status_code =
  1006. (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
  1007. if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
  1008. /* SPU_Status[P,I]=1 - Illegal Instruction followed
  1009. * by Stop and Signal instruction, followed by 'br -4'.
  1010. *
  1011. */
  1012. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
  1013. csa->lscsa->stopped_status.slot[1] = status_code;
  1014. } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
  1015. /* SPU_Status[P,H]=1 - Halt Conditional, followed
  1016. * by Stop and Signal instruction, followed by
  1017. * 'br -4'.
  1018. */
  1019. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
  1020. csa->lscsa->stopped_status.slot[1] = status_code;
  1021. } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
  1022. /* SPU_Status[S,P]=1 - Stop and Signal instruction
  1023. * followed by 'br -4'.
  1024. */
  1025. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
  1026. csa->lscsa->stopped_status.slot[1] = status_code;
  1027. } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
  1028. /* SPU_Status[S,I]=1 - Illegal instruction followed
  1029. * by 'br -4'.
  1030. */
  1031. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
  1032. csa->lscsa->stopped_status.slot[1] = status_code;
  1033. } else if ((csa->prob.spu_status_R & status_P) == status_P) {
  1034. /* SPU_Status[P]=1 - Stop and Signal instruction
  1035. * followed by 'br -4'.
  1036. */
  1037. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
  1038. csa->lscsa->stopped_status.slot[1] = status_code;
  1039. } else if ((csa->prob.spu_status_R & status_H) == status_H) {
  1040. /* SPU_Status[H]=1 - Halt Conditional, followed
  1041. * by 'br -4'.
  1042. */
  1043. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
  1044. } else if ((csa->prob.spu_status_R & status_S) == status_S) {
  1045. /* SPU_Status[S]=1 - Two nop instructions.
  1046. */
  1047. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
  1048. } else if ((csa->prob.spu_status_R & status_I) == status_I) {
  1049. /* SPU_Status[I]=1 - Illegal instruction followed
  1050. * by 'br -4'.
  1051. */
  1052. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
  1053. }
  1054. }
  1055. static inline void setup_spu_status_part2(struct spu_state *csa,
  1056. struct spu *spu)
  1057. {
  1058. u32 mask;
  1059. /* Restore, Step 28:
  1060. * If the CSA.SPU_Status[I,S,H,P,R]=0 then
  1061. * add a 'br *' instruction to the end of
  1062. * the SPU based restore code.
  1063. *
  1064. * NOTE: Rather than modifying the SPU executable, we
  1065. * instead add a new 'stopped_status' field to the
  1066. * LSCSA. The SPU-side restore reads this field and
  1067. * takes the appropriate action when exiting.
  1068. */
  1069. mask = SPU_STATUS_INVALID_INSTR |
  1070. SPU_STATUS_SINGLE_STEP |
  1071. SPU_STATUS_STOPPED_BY_HALT |
  1072. SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
  1073. if (!(csa->prob.spu_status_R & mask)) {
  1074. csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
  1075. }
  1076. }
  1077. static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
  1078. {
  1079. /* Restore, Step 29:
  1080. * Restore RA_GROUP_ID register and the
  1081. * RA_ENABLE reigster from the CSA.
  1082. */
  1083. spu_resource_allocation_groupID_set(spu,
  1084. csa->priv1.resource_allocation_groupID_RW);
  1085. spu_resource_allocation_enable_set(spu,
  1086. csa->priv1.resource_allocation_enable_RW);
  1087. }
  1088. static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
  1089. {
  1090. unsigned long addr = (unsigned long)&spu_restore_code[0];
  1091. unsigned int ls_offset = 0x0;
  1092. unsigned int size = sizeof(spu_restore_code);
  1093. unsigned int tag = 0;
  1094. unsigned int rclass = 0;
  1095. unsigned int cmd = MFC_GETFS_CMD;
  1096. /* Restore, Step 37:
  1097. * Issue MFC DMA command to copy context
  1098. * restore code to local storage.
  1099. */
  1100. send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
  1101. }
  1102. static inline void setup_decr(struct spu_state *csa, struct spu *spu)
  1103. {
  1104. /* Restore, Step 34:
  1105. * If CSA.MFC_CNTL[Ds]=1 (decrementer was
  1106. * running) then adjust decrementer, set
  1107. * decrementer running status in LSCSA,
  1108. * and set decrementer "wrapped" status
  1109. * in LSCSA.
  1110. */
  1111. if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
  1112. cycles_t resume_time = get_cycles();
  1113. cycles_t delta_time = resume_time - csa->suspend_time;
  1114. csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
  1115. if (csa->lscsa->decr.slot[0] < delta_time) {
  1116. csa->lscsa->decr_status.slot[0] |=
  1117. SPU_DECR_STATUS_WRAPPED;
  1118. }
  1119. csa->lscsa->decr.slot[0] -= delta_time;
  1120. } else {
  1121. csa->lscsa->decr_status.slot[0] = 0;
  1122. }
  1123. }
  1124. static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
  1125. {
  1126. /* Restore, Step 35:
  1127. * Copy the CSA.PU_MB data into the LSCSA.
  1128. */
  1129. csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
  1130. }
  1131. static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
  1132. {
  1133. /* Restore, Step 36:
  1134. * Copy the CSA.PUINT_MB data into the LSCSA.
  1135. */
  1136. csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
  1137. }
  1138. static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
  1139. {
  1140. struct spu_problem __iomem *prob = spu->problem;
  1141. u32 complete;
  1142. /* Restore, Step 40:
  1143. * If SPU_Status[P]=1 and SPU_Status[SC] = "success",
  1144. * context restore succeeded, otherwise context restore
  1145. * failed.
  1146. */
  1147. complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
  1148. SPU_STATUS_STOPPED_BY_STOP);
  1149. return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
  1150. }
  1151. static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
  1152. {
  1153. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1154. /* Restore, Step 41:
  1155. * Restore SPU_PrivCntl from the CSA.
  1156. */
  1157. out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
  1158. eieio();
  1159. }
  1160. static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
  1161. {
  1162. struct spu_problem __iomem *prob = spu->problem;
  1163. u32 mask;
  1164. /* Restore, Step 42:
  1165. * If any CSA.SPU_Status[I,S,H,P]=1, then
  1166. * restore the error or single step state.
  1167. */
  1168. mask = SPU_STATUS_INVALID_INSTR |
  1169. SPU_STATUS_SINGLE_STEP |
  1170. SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
  1171. if (csa->prob.spu_status_R & mask) {
  1172. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
  1173. eieio();
  1174. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  1175. SPU_STATUS_RUNNING);
  1176. }
  1177. }
  1178. static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
  1179. {
  1180. struct spu_problem __iomem *prob = spu->problem;
  1181. u32 mask;
  1182. /* Restore, Step 43:
  1183. * If all CSA.SPU_Status[I,S,H,P,R]=0 then write
  1184. * SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
  1185. * then write '00' to SPU_RunCntl[R0R1] and wait
  1186. * for SPU_Status[R]=0.
  1187. */
  1188. mask = SPU_STATUS_INVALID_INSTR |
  1189. SPU_STATUS_SINGLE_STEP |
  1190. SPU_STATUS_STOPPED_BY_HALT |
  1191. SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
  1192. if (!(csa->prob.spu_status_R & mask)) {
  1193. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
  1194. eieio();
  1195. POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
  1196. SPU_STATUS_RUNNING);
  1197. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
  1198. eieio();
  1199. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
  1200. SPU_STATUS_RUNNING);
  1201. }
  1202. }
  1203. static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
  1204. {
  1205. unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
  1206. unsigned int ls_offset = 0x0;
  1207. unsigned int size = 16384;
  1208. unsigned int tag = 0;
  1209. unsigned int rclass = 0;
  1210. unsigned int cmd = MFC_GET_CMD;
  1211. /* Restore, Step 44:
  1212. * Issue a DMA command to restore the first
  1213. * 16kb of local storage from CSA.
  1214. */
  1215. send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
  1216. }
  1217. static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
  1218. {
  1219. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1220. /* Restore, Step 47.
  1221. * Write MFC_Cntl[Sc,Sm]='1','0' to suspend
  1222. * the queue.
  1223. */
  1224. out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
  1225. eieio();
  1226. }
  1227. static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
  1228. {
  1229. /* Restore, Step 49:
  1230. * Write INT_MASK_class0 with value of 0.
  1231. * Write INT_MASK_class1 with value of 0.
  1232. * Write INT_MASK_class2 with value of 0.
  1233. * Write INT_STAT_class0 with value of -1.
  1234. * Write INT_STAT_class1 with value of -1.
  1235. * Write INT_STAT_class2 with value of -1.
  1236. */
  1237. spin_lock_irq(&spu->register_lock);
  1238. spu_int_mask_set(spu, 0, 0ul);
  1239. spu_int_mask_set(spu, 1, 0ul);
  1240. spu_int_mask_set(spu, 2, 0ul);
  1241. spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
  1242. spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
  1243. spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
  1244. spin_unlock_irq(&spu->register_lock);
  1245. }
  1246. static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
  1247. {
  1248. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1249. int i;
  1250. /* Restore, Step 50:
  1251. * If MFC_Cntl[Se]!=0 then restore
  1252. * MFC command queues.
  1253. */
  1254. if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
  1255. for (i = 0; i < 8; i++) {
  1256. out_be64(&priv2->puq[i].mfc_cq_data0_RW,
  1257. csa->priv2.puq[i].mfc_cq_data0_RW);
  1258. out_be64(&priv2->puq[i].mfc_cq_data1_RW,
  1259. csa->priv2.puq[i].mfc_cq_data1_RW);
  1260. out_be64(&priv2->puq[i].mfc_cq_data2_RW,
  1261. csa->priv2.puq[i].mfc_cq_data2_RW);
  1262. out_be64(&priv2->puq[i].mfc_cq_data3_RW,
  1263. csa->priv2.puq[i].mfc_cq_data3_RW);
  1264. }
  1265. for (i = 0; i < 16; i++) {
  1266. out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
  1267. csa->priv2.spuq[i].mfc_cq_data0_RW);
  1268. out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
  1269. csa->priv2.spuq[i].mfc_cq_data1_RW);
  1270. out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
  1271. csa->priv2.spuq[i].mfc_cq_data2_RW);
  1272. out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
  1273. csa->priv2.spuq[i].mfc_cq_data3_RW);
  1274. }
  1275. }
  1276. eieio();
  1277. }
  1278. static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
  1279. {
  1280. struct spu_problem __iomem *prob = spu->problem;
  1281. /* Restore, Step 51:
  1282. * Restore the PPU_QueryMask register from CSA.
  1283. */
  1284. out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
  1285. eieio();
  1286. }
  1287. static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
  1288. {
  1289. struct spu_problem __iomem *prob = spu->problem;
  1290. /* Restore, Step 52:
  1291. * Restore the PPU_QueryType register from CSA.
  1292. */
  1293. out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
  1294. eieio();
  1295. }
  1296. static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
  1297. {
  1298. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1299. /* Restore, Step 53:
  1300. * Restore the MFC_CSR_TSQ register from CSA.
  1301. */
  1302. out_be64(&priv2->spu_tag_status_query_RW,
  1303. csa->priv2.spu_tag_status_query_RW);
  1304. eieio();
  1305. }
  1306. static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
  1307. {
  1308. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1309. /* Restore, Step 54:
  1310. * Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
  1311. * registers from CSA.
  1312. */
  1313. out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
  1314. out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
  1315. eieio();
  1316. }
  1317. static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
  1318. {
  1319. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1320. /* Restore, Step 55:
  1321. * Restore the MFC_CSR_ATO register from CSA.
  1322. */
  1323. out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
  1324. }
  1325. static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
  1326. {
  1327. /* Restore, Step 56:
  1328. * Restore the MFC_TCLASS_ID register from CSA.
  1329. */
  1330. spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
  1331. eieio();
  1332. }
  1333. static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
  1334. {
  1335. u64 ch0_cnt, ch0_data;
  1336. u64 ch1_data;
  1337. /* Restore, Step 57:
  1338. * Set the Lock Line Reservation Lost Event by:
  1339. * 1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
  1340. * 2. If CSA.SPU_Channel_0_Count=0 and
  1341. * CSA.SPU_Wr_Event_Mask[Lr]=1 and
  1342. * CSA.SPU_Event_Status[Lr]=0 then set
  1343. * CSA.SPU_Event_Status_Count=1.
  1344. */
  1345. ch0_cnt = csa->spu_chnlcnt_RW[0];
  1346. ch0_data = csa->spu_chnldata_RW[0];
  1347. ch1_data = csa->spu_chnldata_RW[1];
  1348. csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
  1349. if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
  1350. (ch1_data & MFC_LLR_LOST_EVENT)) {
  1351. csa->spu_chnlcnt_RW[0] = 1;
  1352. }
  1353. }
  1354. static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
  1355. {
  1356. /* Restore, Step 58:
  1357. * If the status of the CSA software decrementer
  1358. * "wrapped" flag is set, OR in a '1' to
  1359. * CSA.SPU_Event_Status[Tm].
  1360. */
  1361. if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
  1362. return;
  1363. if ((csa->spu_chnlcnt_RW[0] == 0) &&
  1364. (csa->spu_chnldata_RW[1] & 0x20) &&
  1365. !(csa->spu_chnldata_RW[0] & 0x20))
  1366. csa->spu_chnlcnt_RW[0] = 1;
  1367. csa->spu_chnldata_RW[0] |= 0x20;
  1368. }
  1369. static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
  1370. {
  1371. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1372. u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
  1373. int i;
  1374. /* Restore, Step 59:
  1375. * Restore the following CH: [0,3,4,24,25,27]
  1376. */
  1377. for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
  1378. idx = ch_indices[i];
  1379. out_be64(&priv2->spu_chnlcntptr_RW, idx);
  1380. eieio();
  1381. out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
  1382. out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
  1383. eieio();
  1384. }
  1385. }
  1386. static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
  1387. {
  1388. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1389. u64 ch_indices[3] = { 9UL, 21UL, 23UL };
  1390. u64 ch_counts[3] = { 1UL, 16UL, 1UL };
  1391. u64 idx;
  1392. int i;
  1393. /* Restore, Step 60:
  1394. * Restore the following CH: [9,21,23].
  1395. */
  1396. ch_counts[0] = 1UL;
  1397. ch_counts[1] = csa->spu_chnlcnt_RW[21];
  1398. ch_counts[2] = 1UL;
  1399. for (i = 0; i < 3; i++) {
  1400. idx = ch_indices[i];
  1401. out_be64(&priv2->spu_chnlcntptr_RW, idx);
  1402. eieio();
  1403. out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
  1404. eieio();
  1405. }
  1406. }
  1407. static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
  1408. {
  1409. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1410. /* Restore, Step 61:
  1411. * Restore the SPU_LSLR register from CSA.
  1412. */
  1413. out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
  1414. eieio();
  1415. }
  1416. static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
  1417. {
  1418. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1419. /* Restore, Step 62:
  1420. * Restore the SPU_Cfg register from CSA.
  1421. */
  1422. out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
  1423. eieio();
  1424. }
  1425. static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
  1426. {
  1427. /* Restore, Step 63:
  1428. * Restore PM_Trace_Tag_Wait_Mask from CSA.
  1429. * Not performed by this implementation.
  1430. */
  1431. }
  1432. static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
  1433. {
  1434. struct spu_problem __iomem *prob = spu->problem;
  1435. /* Restore, Step 64:
  1436. * Restore SPU_NPC from CSA.
  1437. */
  1438. out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
  1439. eieio();
  1440. }
  1441. static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
  1442. {
  1443. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1444. int i;
  1445. /* Restore, Step 65:
  1446. * Restore MFC_RdSPU_MB from CSA.
  1447. */
  1448. out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
  1449. eieio();
  1450. out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
  1451. for (i = 0; i < 4; i++) {
  1452. out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
  1453. }
  1454. eieio();
  1455. }
  1456. static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
  1457. {
  1458. struct spu_problem __iomem *prob = spu->problem;
  1459. u32 dummy = 0;
  1460. /* Restore, Step 66:
  1461. * If CSA.MB_Stat[P]=0 (mailbox empty) then
  1462. * read from the PPU_MB register.
  1463. */
  1464. if ((csa->prob.mb_stat_R & 0xFF) == 0) {
  1465. dummy = in_be32(&prob->pu_mb_R);
  1466. eieio();
  1467. }
  1468. }
  1469. static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
  1470. {
  1471. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1472. u64 dummy = 0UL;
  1473. /* Restore, Step 66:
  1474. * If CSA.MB_Stat[I]=0 (mailbox empty) then
  1475. * read from the PPUINT_MB register.
  1476. */
  1477. if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
  1478. dummy = in_be64(&priv2->puint_mb_R);
  1479. eieio();
  1480. spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
  1481. eieio();
  1482. }
  1483. }
  1484. static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
  1485. {
  1486. /* Restore, Step 69:
  1487. * Restore the MFC_SR1 register from CSA.
  1488. */
  1489. spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
  1490. eieio();
  1491. }
  1492. static inline void set_int_route(struct spu_state *csa, struct spu *spu)
  1493. {
  1494. struct spu_context *ctx = spu->ctx;
  1495. spu_cpu_affinity_set(spu, ctx->last_ran);
  1496. }
  1497. static inline void restore_other_spu_access(struct spu_state *csa,
  1498. struct spu *spu)
  1499. {
  1500. /* Restore, Step 70:
  1501. * Restore other SPU mappings to this SPU. TBD.
  1502. */
  1503. }
  1504. static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
  1505. {
  1506. struct spu_problem __iomem *prob = spu->problem;
  1507. /* Restore, Step 71:
  1508. * If CSA.SPU_Status[R]=1 then write
  1509. * SPU_RunCntl[R0R1]='01'.
  1510. */
  1511. if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
  1512. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
  1513. eieio();
  1514. }
  1515. }
  1516. static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
  1517. {
  1518. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1519. /* Restore, Step 72:
  1520. * Restore the MFC_CNTL register for the CSA.
  1521. */
  1522. out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
  1523. eieio();
  1524. /*
  1525. * The queue is put back into the same state that was evident prior to
  1526. * the context switch. The suspend flag is added to the saved state in
  1527. * the csa, if the operational state was suspending or suspended. In
  1528. * this case, the code that suspended the mfc is responsible for
  1529. * continuing it. Note that SPE faults do not change the operational
  1530. * state of the spu.
  1531. */
  1532. }
  1533. static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
  1534. {
  1535. /* Restore, Step 73:
  1536. * Enable user-space access (if provided) to this
  1537. * SPU by mapping the virtual pages assigned to
  1538. * the SPU memory-mapped I/O (MMIO) for problem
  1539. * state. TBD.
  1540. */
  1541. }
  1542. static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
  1543. {
  1544. /* Restore, Step 74:
  1545. * Reset the "context switch active" flag.
  1546. * Not performed by this implementation.
  1547. */
  1548. }
  1549. static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
  1550. {
  1551. /* Restore, Step 75:
  1552. * Re-enable SPU interrupts.
  1553. */
  1554. spin_lock_irq(&spu->register_lock);
  1555. spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
  1556. spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
  1557. spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
  1558. spin_unlock_irq(&spu->register_lock);
  1559. }
  1560. static int quiece_spu(struct spu_state *prev, struct spu *spu)
  1561. {
  1562. /*
  1563. * Combined steps 2-18 of SPU context save sequence, which
  1564. * quiesce the SPU state (disable SPU execution, MFC command
  1565. * queues, decrementer, SPU interrupts, etc.).
  1566. *
  1567. * Returns 0 on success.
  1568. * 2 if failed step 2.
  1569. * 6 if failed step 6.
  1570. */
  1571. if (check_spu_isolate(prev, spu)) { /* Step 2. */
  1572. return 2;
  1573. }
  1574. disable_interrupts(prev, spu); /* Step 3. */
  1575. set_watchdog_timer(prev, spu); /* Step 4. */
  1576. inhibit_user_access(prev, spu); /* Step 5. */
  1577. if (check_spu_isolate(prev, spu)) { /* Step 6. */
  1578. return 6;
  1579. }
  1580. set_switch_pending(prev, spu); /* Step 7. */
  1581. save_mfc_cntl(prev, spu); /* Step 8. */
  1582. save_spu_runcntl(prev, spu); /* Step 9. */
  1583. save_mfc_sr1(prev, spu); /* Step 10. */
  1584. save_spu_status(prev, spu); /* Step 11. */
  1585. save_mfc_stopped_status(prev, spu); /* Step 12. */
  1586. halt_mfc_decr(prev, spu); /* Step 13. */
  1587. save_timebase(prev, spu); /* Step 14. */
  1588. remove_other_spu_access(prev, spu); /* Step 15. */
  1589. do_mfc_mssync(prev, spu); /* Step 16. */
  1590. issue_mfc_tlbie(prev, spu); /* Step 17. */
  1591. handle_pending_interrupts(prev, spu); /* Step 18. */
  1592. return 0;
  1593. }
  1594. static void save_csa(struct spu_state *prev, struct spu *spu)
  1595. {
  1596. /*
  1597. * Combine steps 19-44 of SPU context save sequence, which
  1598. * save regions of the privileged & problem state areas.
  1599. */
  1600. save_mfc_queues(prev, spu); /* Step 19. */
  1601. save_ppu_querymask(prev, spu); /* Step 20. */
  1602. save_ppu_querytype(prev, spu); /* Step 21. */
  1603. save_ppu_tagstatus(prev, spu); /* NEW. */
  1604. save_mfc_csr_tsq(prev, spu); /* Step 22. */
  1605. save_mfc_csr_cmd(prev, spu); /* Step 23. */
  1606. save_mfc_csr_ato(prev, spu); /* Step 24. */
  1607. save_mfc_tclass_id(prev, spu); /* Step 25. */
  1608. set_mfc_tclass_id(prev, spu); /* Step 26. */
  1609. save_mfc_cmd(prev, spu); /* Step 26a - moved from 44. */
  1610. purge_mfc_queue(prev, spu); /* Step 27. */
  1611. wait_purge_complete(prev, spu); /* Step 28. */
  1612. setup_mfc_sr1(prev, spu); /* Step 30. */
  1613. save_spu_npc(prev, spu); /* Step 31. */
  1614. save_spu_privcntl(prev, spu); /* Step 32. */
  1615. reset_spu_privcntl(prev, spu); /* Step 33. */
  1616. save_spu_lslr(prev, spu); /* Step 34. */
  1617. reset_spu_lslr(prev, spu); /* Step 35. */
  1618. save_spu_cfg(prev, spu); /* Step 36. */
  1619. save_pm_trace(prev, spu); /* Step 37. */
  1620. save_mfc_rag(prev, spu); /* Step 38. */
  1621. save_ppu_mb_stat(prev, spu); /* Step 39. */
  1622. save_ppu_mb(prev, spu); /* Step 40. */
  1623. save_ppuint_mb(prev, spu); /* Step 41. */
  1624. save_ch_part1(prev, spu); /* Step 42. */
  1625. save_spu_mb(prev, spu); /* Step 43. */
  1626. reset_ch(prev, spu); /* Step 45. */
  1627. }
  1628. static void save_lscsa(struct spu_state *prev, struct spu *spu)
  1629. {
  1630. /*
  1631. * Perform steps 46-57 of SPU context save sequence,
  1632. * which save regions of the local store and register
  1633. * file.
  1634. */
  1635. resume_mfc_queue(prev, spu); /* Step 46. */
  1636. /* Step 47. */
  1637. setup_mfc_slbs(prev, spu, spu_save_code, sizeof(spu_save_code));
  1638. set_switch_active(prev, spu); /* Step 48. */
  1639. enable_interrupts(prev, spu); /* Step 49. */
  1640. save_ls_16kb(prev, spu); /* Step 50. */
  1641. set_spu_npc(prev, spu); /* Step 51. */
  1642. set_signot1(prev, spu); /* Step 52. */
  1643. set_signot2(prev, spu); /* Step 53. */
  1644. send_save_code(prev, spu); /* Step 54. */
  1645. set_ppu_querymask(prev, spu); /* Step 55. */
  1646. wait_tag_complete(prev, spu); /* Step 56. */
  1647. wait_spu_stopped(prev, spu); /* Step 57. */
  1648. }
  1649. static void force_spu_isolate_exit(struct spu *spu)
  1650. {
  1651. struct spu_problem __iomem *prob = spu->problem;
  1652. struct spu_priv2 __iomem *priv2 = spu->priv2;
  1653. /* Stop SPE execution and wait for completion. */
  1654. out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
  1655. iobarrier_rw();
  1656. POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
  1657. /* Restart SPE master runcntl. */
  1658. spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
  1659. iobarrier_w();
  1660. /* Initiate isolate exit request and wait for completion. */
  1661. out_be64(&priv2->spu_privcntl_RW, 4LL);
  1662. iobarrier_w();
  1663. out_be32(&prob->spu_runcntl_RW, 2);
  1664. iobarrier_rw();
  1665. POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
  1666. & SPU_STATUS_STOPPED_BY_STOP));
  1667. /* Reset load request to normal. */
  1668. out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
  1669. iobarrier_w();
  1670. }
  1671. /**
  1672. * stop_spu_isolate
  1673. * Check SPU run-control state and force isolated
  1674. * exit function as necessary.
  1675. */
  1676. static void stop_spu_isolate(struct spu *spu)
  1677. {
  1678. struct spu_problem __iomem *prob = spu->problem;
  1679. if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
  1680. /* The SPU is in isolated state; the only way
  1681. * to get it out is to perform an isolated
  1682. * exit (clean) operation.
  1683. */
  1684. force_spu_isolate_exit(spu);
  1685. }
  1686. }
  1687. static void harvest(struct spu_state *prev, struct spu *spu)
  1688. {
  1689. /*
  1690. * Perform steps 2-25 of SPU context restore sequence,
  1691. * which resets an SPU either after a failed save, or
  1692. * when using SPU for first time.
  1693. */
  1694. disable_interrupts(prev, spu); /* Step 2. */
  1695. inhibit_user_access(prev, spu); /* Step 3. */
  1696. terminate_spu_app(prev, spu); /* Step 4. */
  1697. set_switch_pending(prev, spu); /* Step 5. */
  1698. stop_spu_isolate(spu); /* NEW. */
  1699. remove_other_spu_access(prev, spu); /* Step 6. */
  1700. suspend_mfc_and_halt_decr(prev, spu); /* Step 7. */
  1701. wait_suspend_mfc_complete(prev, spu); /* Step 8. */
  1702. if (!suspend_spe(prev, spu)) /* Step 9. */
  1703. clear_spu_status(prev, spu); /* Step 10. */
  1704. do_mfc_mssync(prev, spu); /* Step 11. */
  1705. issue_mfc_tlbie(prev, spu); /* Step 12. */
  1706. handle_pending_interrupts(prev, spu); /* Step 13. */
  1707. purge_mfc_queue(prev, spu); /* Step 14. */
  1708. wait_purge_complete(prev, spu); /* Step 15. */
  1709. reset_spu_privcntl(prev, spu); /* Step 16. */
  1710. reset_spu_lslr(prev, spu); /* Step 17. */
  1711. setup_mfc_sr1(prev, spu); /* Step 18. */
  1712. spu_invalidate_slbs(spu); /* Step 19. */
  1713. reset_ch_part1(prev, spu); /* Step 20. */
  1714. reset_ch_part2(prev, spu); /* Step 21. */
  1715. enable_interrupts(prev, spu); /* Step 22. */
  1716. set_switch_active(prev, spu); /* Step 23. */
  1717. set_mfc_tclass_id(prev, spu); /* Step 24. */
  1718. resume_mfc_queue(prev, spu); /* Step 25. */
  1719. }
  1720. static void restore_lscsa(struct spu_state *next, struct spu *spu)
  1721. {
  1722. /*
  1723. * Perform steps 26-40 of SPU context restore sequence,
  1724. * which restores regions of the local store and register
  1725. * file.
  1726. */
  1727. set_watchdog_timer(next, spu); /* Step 26. */
  1728. setup_spu_status_part1(next, spu); /* Step 27. */
  1729. setup_spu_status_part2(next, spu); /* Step 28. */
  1730. restore_mfc_rag(next, spu); /* Step 29. */
  1731. /* Step 30. */
  1732. setup_mfc_slbs(next, spu, spu_restore_code, sizeof(spu_restore_code));
  1733. set_spu_npc(next, spu); /* Step 31. */
  1734. set_signot1(next, spu); /* Step 32. */
  1735. set_signot2(next, spu); /* Step 33. */
  1736. setup_decr(next, spu); /* Step 34. */
  1737. setup_ppu_mb(next, spu); /* Step 35. */
  1738. setup_ppuint_mb(next, spu); /* Step 36. */
  1739. send_restore_code(next, spu); /* Step 37. */
  1740. set_ppu_querymask(next, spu); /* Step 38. */
  1741. wait_tag_complete(next, spu); /* Step 39. */
  1742. wait_spu_stopped(next, spu); /* Step 40. */
  1743. }
  1744. static void restore_csa(struct spu_state *next, struct spu *spu)
  1745. {
  1746. /*
  1747. * Combine steps 41-76 of SPU context restore sequence, which
  1748. * restore regions of the privileged & problem state areas.
  1749. */
  1750. restore_spu_privcntl(next, spu); /* Step 41. */
  1751. restore_status_part1(next, spu); /* Step 42. */
  1752. restore_status_part2(next, spu); /* Step 43. */
  1753. restore_ls_16kb(next, spu); /* Step 44. */
  1754. wait_tag_complete(next, spu); /* Step 45. */
  1755. suspend_mfc(next, spu); /* Step 46. */
  1756. wait_suspend_mfc_complete(next, spu); /* Step 47. */
  1757. issue_mfc_tlbie(next, spu); /* Step 48. */
  1758. clear_interrupts(next, spu); /* Step 49. */
  1759. restore_mfc_queues(next, spu); /* Step 50. */
  1760. restore_ppu_querymask(next, spu); /* Step 51. */
  1761. restore_ppu_querytype(next, spu); /* Step 52. */
  1762. restore_mfc_csr_tsq(next, spu); /* Step 53. */
  1763. restore_mfc_csr_cmd(next, spu); /* Step 54. */
  1764. restore_mfc_csr_ato(next, spu); /* Step 55. */
  1765. restore_mfc_tclass_id(next, spu); /* Step 56. */
  1766. set_llr_event(next, spu); /* Step 57. */
  1767. restore_decr_wrapped(next, spu); /* Step 58. */
  1768. restore_ch_part1(next, spu); /* Step 59. */
  1769. restore_ch_part2(next, spu); /* Step 60. */
  1770. restore_spu_lslr(next, spu); /* Step 61. */
  1771. restore_spu_cfg(next, spu); /* Step 62. */
  1772. restore_pm_trace(next, spu); /* Step 63. */
  1773. restore_spu_npc(next, spu); /* Step 64. */
  1774. restore_spu_mb(next, spu); /* Step 65. */
  1775. check_ppu_mb_stat(next, spu); /* Step 66. */
  1776. check_ppuint_mb_stat(next, spu); /* Step 67. */
  1777. spu_invalidate_slbs(spu); /* Modified Step 68. */
  1778. restore_mfc_sr1(next, spu); /* Step 69. */
  1779. set_int_route(next, spu); /* NEW */
  1780. restore_other_spu_access(next, spu); /* Step 70. */
  1781. restore_spu_runcntl(next, spu); /* Step 71. */
  1782. restore_mfc_cntl(next, spu); /* Step 72. */
  1783. enable_user_access(next, spu); /* Step 73. */
  1784. reset_switch_active(next, spu); /* Step 74. */
  1785. reenable_interrupts(next, spu); /* Step 75. */
  1786. }
  1787. static int __do_spu_save(struct spu_state *prev, struct spu *spu)
  1788. {
  1789. int rc;
  1790. /*
  1791. * SPU context save can be broken into three phases:
  1792. *
  1793. * (a) quiesce [steps 2-16].
  1794. * (b) save of CSA, performed by PPE [steps 17-42]
  1795. * (c) save of LSCSA, mostly performed by SPU [steps 43-52].
  1796. *
  1797. * Returns 0 on success.
  1798. * 2,6 if failed to quiece SPU
  1799. * 53 if SPU-side of save failed.
  1800. */
  1801. rc = quiece_spu(prev, spu); /* Steps 2-16. */
  1802. switch (rc) {
  1803. default:
  1804. case 2:
  1805. case 6:
  1806. harvest(prev, spu);
  1807. return rc;
  1808. break;
  1809. case 0:
  1810. break;
  1811. }
  1812. save_csa(prev, spu); /* Steps 17-43. */
  1813. save_lscsa(prev, spu); /* Steps 44-53. */
  1814. return check_save_status(prev, spu); /* Step 54. */
  1815. }
  1816. static int __do_spu_restore(struct spu_state *next, struct spu *spu)
  1817. {
  1818. int rc;
  1819. /*
  1820. * SPU context restore can be broken into three phases:
  1821. *
  1822. * (a) harvest (or reset) SPU [steps 2-24].
  1823. * (b) restore LSCSA [steps 25-40], mostly performed by SPU.
  1824. * (c) restore CSA [steps 41-76], performed by PPE.
  1825. *
  1826. * The 'harvest' step is not performed here, but rather
  1827. * as needed below.
  1828. */
  1829. restore_lscsa(next, spu); /* Steps 24-39. */
  1830. rc = check_restore_status(next, spu); /* Step 40. */
  1831. switch (rc) {
  1832. default:
  1833. /* Failed. Return now. */
  1834. return rc;
  1835. break;
  1836. case 0:
  1837. /* Fall through to next step. */
  1838. break;
  1839. }
  1840. restore_csa(next, spu);
  1841. return 0;
  1842. }
  1843. /**
  1844. * spu_save - SPU context save, with locking.
  1845. * @prev: pointer to SPU context save area, to be saved.
  1846. * @spu: pointer to SPU iomem structure.
  1847. *
  1848. * Acquire locks, perform the save operation then return.
  1849. */
  1850. int spu_save(struct spu_state *prev, struct spu *spu)
  1851. {
  1852. int rc;
  1853. acquire_spu_lock(spu); /* Step 1. */
  1854. rc = __do_spu_save(prev, spu); /* Steps 2-53. */
  1855. release_spu_lock(spu);
  1856. if (rc != 0 && rc != 2 && rc != 6) {
  1857. panic("%s failed on SPU[%d], rc=%d.\n",
  1858. __func__, spu->number, rc);
  1859. }
  1860. return 0;
  1861. }
  1862. EXPORT_SYMBOL_GPL(spu_save);
  1863. /**
  1864. * spu_restore - SPU context restore, with harvest and locking.
  1865. * @new: pointer to SPU context save area, to be restored.
  1866. * @spu: pointer to SPU iomem structure.
  1867. *
  1868. * Perform harvest + restore, as we may not be coming
  1869. * from a previous successful save operation, and the
  1870. * hardware state is unknown.
  1871. */
  1872. int spu_restore(struct spu_state *new, struct spu *spu)
  1873. {
  1874. int rc;
  1875. acquire_spu_lock(spu);
  1876. harvest(NULL, spu);
  1877. spu->slb_replace = 0;
  1878. rc = __do_spu_restore(new, spu);
  1879. release_spu_lock(spu);
  1880. if (rc) {
  1881. panic("%s failed on SPU[%d] rc=%d.\n",
  1882. __func__, spu->number, rc);
  1883. }
  1884. return rc;
  1885. }
  1886. EXPORT_SYMBOL_GPL(spu_restore);
  1887. static void init_prob(struct spu_state *csa)
  1888. {
  1889. csa->spu_chnlcnt_RW[9] = 1;
  1890. csa->spu_chnlcnt_RW[21] = 16;
  1891. csa->spu_chnlcnt_RW[23] = 1;
  1892. csa->spu_chnlcnt_RW[28] = 1;
  1893. csa->spu_chnlcnt_RW[30] = 1;
  1894. csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
  1895. csa->prob.mb_stat_R = 0x000400;
  1896. }
  1897. static void init_priv1(struct spu_state *csa)
  1898. {
  1899. /* Enable decode, relocate, tlbie response, master runcntl. */
  1900. csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
  1901. MFC_STATE1_MASTER_RUN_CONTROL_MASK |
  1902. MFC_STATE1_PROBLEM_STATE_MASK |
  1903. MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
  1904. /* Enable OS-specific set of interrupts. */
  1905. csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
  1906. CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
  1907. CLASS0_ENABLE_SPU_ERROR_INTR;
  1908. csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
  1909. CLASS1_ENABLE_STORAGE_FAULT_INTR;
  1910. csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
  1911. CLASS2_ENABLE_SPU_HALT_INTR |
  1912. CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
  1913. }
  1914. static void init_priv2(struct spu_state *csa)
  1915. {
  1916. csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
  1917. csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
  1918. MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
  1919. MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
  1920. }
  1921. /**
  1922. * spu_alloc_csa - allocate and initialize an SPU context save area.
  1923. *
  1924. * Allocate and initialize the contents of an SPU context save area.
  1925. * This includes enabling address translation, interrupt masks, etc.,
  1926. * as appropriate for the given OS environment.
  1927. *
  1928. * Note that storage for the 'lscsa' is allocated separately,
  1929. * as it is by far the largest of the context save regions,
  1930. * and may need to be pinned or otherwise specially aligned.
  1931. */
  1932. int spu_init_csa(struct spu_state *csa)
  1933. {
  1934. int rc;
  1935. if (!csa)
  1936. return -EINVAL;
  1937. memset(csa, 0, sizeof(struct spu_state));
  1938. rc = spu_alloc_lscsa(csa);
  1939. if (rc)
  1940. return rc;
  1941. spin_lock_init(&csa->register_lock);
  1942. init_prob(csa);
  1943. init_priv1(csa);
  1944. init_priv2(csa);
  1945. return 0;
  1946. }
  1947. void spu_fini_csa(struct spu_state *csa)
  1948. {
  1949. spu_free_lscsa(csa);
  1950. }