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/drivers/scsi/qla2xxx/qla_os.c

http://github.com/mirrors/linux
C | 7956 lines | 6323 code | 1033 blank | 600 comment | 1011 complexity | 69290e65b10cef3fe76a68cfae7f6121 MD5 | raw file
   1/*
   2 * QLogic Fibre Channel HBA Driver
   3 * Copyright (c)  2003-2014 QLogic Corporation
   4 *
   5 * See LICENSE.qla2xxx for copyright and licensing details.
   6 */
   7#include "qla_def.h"
   8
   9#include <linux/moduleparam.h>
  10#include <linux/vmalloc.h>
  11#include <linux/delay.h>
  12#include <linux/kthread.h>
  13#include <linux/mutex.h>
  14#include <linux/kobject.h>
  15#include <linux/slab.h>
  16#include <linux/blk-mq-pci.h>
  17#include <linux/refcount.h>
  18
  19#include <scsi/scsi_tcq.h>
  20#include <scsi/scsicam.h>
  21#include <scsi/scsi_transport.h>
  22#include <scsi/scsi_transport_fc.h>
  23
  24#include "qla_target.h"
  25
  26/*
  27 * Driver version
  28 */
  29char qla2x00_version_str[40];
  30
  31static int apidev_major;
  32
  33/*
  34 * SRB allocation cache
  35 */
  36struct kmem_cache *srb_cachep;
  37
  38/*
  39 * CT6 CTX allocation cache
  40 */
  41static struct kmem_cache *ctx_cachep;
  42/*
  43 * error level for logging
  44 */
  45uint ql_errlev = 0x8001;
  46
  47static int ql2xenableclass2;
  48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
  49MODULE_PARM_DESC(ql2xenableclass2,
  50		"Specify if Class 2 operations are supported from the very "
  51		"beginning. Default is 0 - class 2 not supported.");
  52
  53
  54int ql2xlogintimeout = 20;
  55module_param(ql2xlogintimeout, int, S_IRUGO);
  56MODULE_PARM_DESC(ql2xlogintimeout,
  57		"Login timeout value in seconds.");
  58
  59int qlport_down_retry;
  60module_param(qlport_down_retry, int, S_IRUGO);
  61MODULE_PARM_DESC(qlport_down_retry,
  62		"Maximum number of command retries to a port that returns "
  63		"a PORT-DOWN status.");
  64
  65int ql2xplogiabsentdevice;
  66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  67MODULE_PARM_DESC(ql2xplogiabsentdevice,
  68		"Option to enable PLOGI to devices that are not present after "
  69		"a Fabric scan.  This is needed for several broken switches. "
  70		"Default is 0 - no PLOGI. 1 - perform PLOGI.");
  71
  72int ql2xloginretrycount;
  73module_param(ql2xloginretrycount, int, S_IRUGO);
  74MODULE_PARM_DESC(ql2xloginretrycount,
  75		"Specify an alternate value for the NVRAM login retry count.");
  76
  77int ql2xallocfwdump = 1;
  78module_param(ql2xallocfwdump, int, S_IRUGO);
  79MODULE_PARM_DESC(ql2xallocfwdump,
  80		"Option to enable allocation of memory for a firmware dump "
  81		"during HBA initialization.  Memory allocation requirements "
  82		"vary by ISP type.  Default is 1 - allocate memory.");
  83
  84int ql2xextended_error_logging;
  85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  87MODULE_PARM_DESC(ql2xextended_error_logging,
  88		"Option to enable extended error logging,\n"
  89		"\t\tDefault is 0 - no logging.  0x40000000 - Module Init & Probe.\n"
  90		"\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
  91		"\t\t0x08000000 - IO tracing.    0x04000000 - DPC Thread.\n"
  92		"\t\t0x02000000 - Async events.  0x01000000 - Timer routines.\n"
  93		"\t\t0x00800000 - User space.    0x00400000 - Task Management.\n"
  94		"\t\t0x00200000 - AER/EEH.       0x00100000 - Multi Q.\n"
  95		"\t\t0x00080000 - P3P Specific.  0x00040000 - Virtual Port.\n"
  96		"\t\t0x00020000 - Buffer Dump.   0x00010000 - Misc.\n"
  97		"\t\t0x00008000 - Verbose.       0x00004000 - Target.\n"
  98		"\t\t0x00002000 - Target Mgmt.   0x00001000 - Target TMF.\n"
  99		"\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
 100		"\t\t0x1e400000 - Preferred value for capturing essential "
 101		"debug information (equivalent to old "
 102		"ql2xextended_error_logging=1).\n"
 103		"\t\tDo LOGICAL OR of the value to enable more than one level");
 104
 105int ql2xshiftctondsd = 6;
 106module_param(ql2xshiftctondsd, int, S_IRUGO);
 107MODULE_PARM_DESC(ql2xshiftctondsd,
 108		"Set to control shifting of command type processing "
 109		"based on total number of SG elements.");
 110
 111int ql2xfdmienable = 1;
 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
 114MODULE_PARM_DESC(ql2xfdmienable,
 115		"Enables FDMI registrations. "
 116		"0 - no FDMI registrations. "
 117		"1 - provide FDMI registrations (default).");
 118
 119#define MAX_Q_DEPTH	64
 120static int ql2xmaxqdepth = MAX_Q_DEPTH;
 121module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
 122MODULE_PARM_DESC(ql2xmaxqdepth,
 123		"Maximum queue depth to set for each LUN. "
 124		"Default is 64.");
 125
 126int ql2xenabledif = 2;
 127module_param(ql2xenabledif, int, S_IRUGO);
 128MODULE_PARM_DESC(ql2xenabledif,
 129		" Enable T10-CRC-DIF:\n"
 130		" Default is 2.\n"
 131		"  0 -- No DIF Support\n"
 132		"  1 -- Enable DIF for all types\n"
 133		"  2 -- Enable DIF for all types, except Type 0.\n");
 134
 135#if (IS_ENABLED(CONFIG_NVME_FC))
 136int ql2xnvmeenable = 1;
 137#else
 138int ql2xnvmeenable;
 139#endif
 140module_param(ql2xnvmeenable, int, 0644);
 141MODULE_PARM_DESC(ql2xnvmeenable,
 142    "Enables NVME support. "
 143    "0 - no NVMe.  Default is Y");
 144
 145int ql2xenablehba_err_chk = 2;
 146module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
 147MODULE_PARM_DESC(ql2xenablehba_err_chk,
 148		" Enable T10-CRC-DIF Error isolation by HBA:\n"
 149		" Default is 2.\n"
 150		"  0 -- Error isolation disabled\n"
 151		"  1 -- Error isolation enabled only for DIX Type 0\n"
 152		"  2 -- Error isolation enabled for all Types\n");
 153
 154int ql2xiidmaenable = 1;
 155module_param(ql2xiidmaenable, int, S_IRUGO);
 156MODULE_PARM_DESC(ql2xiidmaenable,
 157		"Enables iIDMA settings "
 158		"Default is 1 - perform iIDMA. 0 - no iIDMA.");
 159
 160int ql2xmqsupport = 1;
 161module_param(ql2xmqsupport, int, S_IRUGO);
 162MODULE_PARM_DESC(ql2xmqsupport,
 163		"Enable on demand multiple queue pairs support "
 164		"Default is 1 for supported. "
 165		"Set it to 0 to turn off mq qpair support.");
 166
 167int ql2xfwloadbin;
 168module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
 169module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
 170MODULE_PARM_DESC(ql2xfwloadbin,
 171		"Option to specify location from which to load ISP firmware:.\n"
 172		" 2 -- load firmware via the request_firmware() (hotplug).\n"
 173		"      interface.\n"
 174		" 1 -- load firmware from flash.\n"
 175		" 0 -- use default semantics.\n");
 176
 177int ql2xetsenable;
 178module_param(ql2xetsenable, int, S_IRUGO);
 179MODULE_PARM_DESC(ql2xetsenable,
 180		"Enables firmware ETS burst."
 181		"Default is 0 - skip ETS enablement.");
 182
 183int ql2xdbwr = 1;
 184module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
 185MODULE_PARM_DESC(ql2xdbwr,
 186		"Option to specify scheme for request queue posting.\n"
 187		" 0 -- Regular doorbell.\n"
 188		" 1 -- CAMRAM doorbell (faster).\n");
 189
 190int ql2xtargetreset = 1;
 191module_param(ql2xtargetreset, int, S_IRUGO);
 192MODULE_PARM_DESC(ql2xtargetreset,
 193		 "Enable target reset."
 194		 "Default is 1 - use hw defaults.");
 195
 196int ql2xgffidenable;
 197module_param(ql2xgffidenable, int, S_IRUGO);
 198MODULE_PARM_DESC(ql2xgffidenable,
 199		"Enables GFF_ID checks of port type. "
 200		"Default is 0 - Do not use GFF_ID information.");
 201
 202int ql2xasynctmfenable = 1;
 203module_param(ql2xasynctmfenable, int, S_IRUGO);
 204MODULE_PARM_DESC(ql2xasynctmfenable,
 205		"Enables issue of TM IOCBs asynchronously via IOCB mechanism"
 206		"Default is 1 - Issue TM IOCBs via mailbox mechanism.");
 207
 208int ql2xdontresethba;
 209module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
 210MODULE_PARM_DESC(ql2xdontresethba,
 211		"Option to specify reset behaviour.\n"
 212		" 0 (Default) -- Reset on failure.\n"
 213		" 1 -- Do not reset on failure.\n");
 214
 215uint64_t ql2xmaxlun = MAX_LUNS;
 216module_param(ql2xmaxlun, ullong, S_IRUGO);
 217MODULE_PARM_DESC(ql2xmaxlun,
 218		"Defines the maximum LU number to register with the SCSI "
 219		"midlayer. Default is 65535.");
 220
 221int ql2xmdcapmask = 0x1F;
 222module_param(ql2xmdcapmask, int, S_IRUGO);
 223MODULE_PARM_DESC(ql2xmdcapmask,
 224		"Set the Minidump driver capture mask level. "
 225		"Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
 226
 227int ql2xmdenable = 1;
 228module_param(ql2xmdenable, int, S_IRUGO);
 229MODULE_PARM_DESC(ql2xmdenable,
 230		"Enable/disable MiniDump. "
 231		"0 - MiniDump disabled. "
 232		"1 (Default) - MiniDump enabled.");
 233
 234int ql2xexlogins;
 235module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
 236MODULE_PARM_DESC(ql2xexlogins,
 237		 "Number of extended Logins. "
 238		 "0 (Default)- Disabled.");
 239
 240int ql2xexchoffld = 1024;
 241module_param(ql2xexchoffld, uint, 0644);
 242MODULE_PARM_DESC(ql2xexchoffld,
 243	"Number of target exchanges.");
 244
 245int ql2xiniexchg = 1024;
 246module_param(ql2xiniexchg, uint, 0644);
 247MODULE_PARM_DESC(ql2xiniexchg,
 248	"Number of initiator exchanges.");
 249
 250int ql2xfwholdabts;
 251module_param(ql2xfwholdabts, int, S_IRUGO);
 252MODULE_PARM_DESC(ql2xfwholdabts,
 253		"Allow FW to hold status IOCB until ABTS rsp received. "
 254		"0 (Default) Do not set fw option. "
 255		"1 - Set fw option to hold ABTS.");
 256
 257int ql2xmvasynctoatio = 1;
 258module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
 259MODULE_PARM_DESC(ql2xmvasynctoatio,
 260		"Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
 261		"0 (Default). Do not move IOCBs"
 262		"1 - Move IOCBs.");
 263
 264int ql2xautodetectsfp = 1;
 265module_param(ql2xautodetectsfp, int, 0444);
 266MODULE_PARM_DESC(ql2xautodetectsfp,
 267		 "Detect SFP range and set appropriate distance.\n"
 268		 "1 (Default): Enable\n");
 269
 270int ql2xenablemsix = 1;
 271module_param(ql2xenablemsix, int, 0444);
 272MODULE_PARM_DESC(ql2xenablemsix,
 273		 "Set to enable MSI or MSI-X interrupt mechanism.\n"
 274		 " Default is 1, enable MSI-X interrupt mechanism.\n"
 275		 " 0 -- enable traditional pin-based mechanism.\n"
 276		 " 1 -- enable MSI-X interrupt mechanism.\n"
 277		 " 2 -- enable MSI interrupt mechanism.\n");
 278
 279int qla2xuseresexchforels;
 280module_param(qla2xuseresexchforels, int, 0444);
 281MODULE_PARM_DESC(qla2xuseresexchforels,
 282		 "Reserve 1/2 of emergency exchanges for ELS.\n"
 283		 " 0 (default): disabled");
 284
 285static int ql2xprotmask;
 286module_param(ql2xprotmask, int, 0644);
 287MODULE_PARM_DESC(ql2xprotmask,
 288		 "Override DIF/DIX protection capabilities mask\n"
 289		 "Default is 0 which sets protection mask based on "
 290		 "capabilities reported by HBA firmware.\n");
 291
 292static int ql2xprotguard;
 293module_param(ql2xprotguard, int, 0644);
 294MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
 295		 "  0 -- Let HBA firmware decide\n"
 296		 "  1 -- Force T10 CRC\n"
 297		 "  2 -- Force IP checksum\n");
 298
 299int ql2xdifbundlinginternalbuffers;
 300module_param(ql2xdifbundlinginternalbuffers, int, 0644);
 301MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
 302    "Force using internal buffers for DIF information\n"
 303    "0 (Default). Based on check.\n"
 304    "1 Force using internal buffers\n");
 305
 306int ql2xsmartsan;
 307module_param(ql2xsmartsan, int, 0444);
 308module_param_named(smartsan, ql2xsmartsan, int, 0444);
 309MODULE_PARM_DESC(ql2xsmartsan,
 310		"Send SmartSAN Management Attributes for FDMI Registration."
 311		" Default is 0 - No SmartSAN registration,"
 312		" 1 - Register SmartSAN Management Attributes.");
 313
 314int ql2xrdpenable;
 315module_param(ql2xrdpenable, int, 0444);
 316module_param_named(rdpenable, ql2xrdpenable, int, 0444);
 317MODULE_PARM_DESC(ql2xrdpenable,
 318		"Enables RDP responses. "
 319		"0 - no RDP responses (default). "
 320		"1 - provide RDP responses.");
 321
 322static void qla2x00_clear_drv_active(struct qla_hw_data *);
 323static void qla2x00_free_device(scsi_qla_host_t *);
 324static int qla2xxx_map_queues(struct Scsi_Host *shost);
 325static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
 326
 327
 328static struct scsi_transport_template *qla2xxx_transport_template = NULL;
 329struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
 330
 331/* TODO Convert to inlines
 332 *
 333 * Timer routines
 334 */
 335
 336__inline__ void
 337qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
 338{
 339	timer_setup(&vha->timer, qla2x00_timer, 0);
 340	vha->timer.expires = jiffies + interval * HZ;
 341	add_timer(&vha->timer);
 342	vha->timer_active = 1;
 343}
 344
 345static inline void
 346qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
 347{
 348	/* Currently used for 82XX only. */
 349	if (vha->device_flags & DFLG_DEV_FAILED) {
 350		ql_dbg(ql_dbg_timer, vha, 0x600d,
 351		    "Device in a failed state, returning.\n");
 352		return;
 353	}
 354
 355	mod_timer(&vha->timer, jiffies + interval * HZ);
 356}
 357
 358static __inline__ void
 359qla2x00_stop_timer(scsi_qla_host_t *vha)
 360{
 361	del_timer_sync(&vha->timer);
 362	vha->timer_active = 0;
 363}
 364
 365static int qla2x00_do_dpc(void *data);
 366
 367static void qla2x00_rst_aen(scsi_qla_host_t *);
 368
 369static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
 370	struct req_que **, struct rsp_que **);
 371static void qla2x00_free_fw_dump(struct qla_hw_data *);
 372static void qla2x00_mem_free(struct qla_hw_data *);
 373int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
 374	struct qla_qpair *qpair);
 375
 376/* -------------------------------------------------------------------------- */
 377static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
 378    struct rsp_que *rsp)
 379{
 380	struct qla_hw_data *ha = vha->hw;
 381
 382	rsp->qpair = ha->base_qpair;
 383	rsp->req = req;
 384	ha->base_qpair->hw = ha;
 385	ha->base_qpair->req = req;
 386	ha->base_qpair->rsp = rsp;
 387	ha->base_qpair->vha = vha;
 388	ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
 389	ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
 390	ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
 391	ha->base_qpair->srb_mempool = ha->srb_mempool;
 392	INIT_LIST_HEAD(&ha->base_qpair->hints_list);
 393	ha->base_qpair->enable_class_2 = ql2xenableclass2;
 394	/* init qpair to this cpu. Will adjust at run time. */
 395	qla_cpu_update(rsp->qpair, raw_smp_processor_id());
 396	ha->base_qpair->pdev = ha->pdev;
 397
 398	if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
 399		ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
 400}
 401
 402static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
 403				struct rsp_que *rsp)
 404{
 405	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 406
 407	ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
 408				GFP_KERNEL);
 409	if (!ha->req_q_map) {
 410		ql_log(ql_log_fatal, vha, 0x003b,
 411		    "Unable to allocate memory for request queue ptrs.\n");
 412		goto fail_req_map;
 413	}
 414
 415	ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
 416				GFP_KERNEL);
 417	if (!ha->rsp_q_map) {
 418		ql_log(ql_log_fatal, vha, 0x003c,
 419		    "Unable to allocate memory for response queue ptrs.\n");
 420		goto fail_rsp_map;
 421	}
 422
 423	ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
 424	if (ha->base_qpair == NULL) {
 425		ql_log(ql_log_warn, vha, 0x00e0,
 426		    "Failed to allocate base queue pair memory.\n");
 427		goto fail_base_qpair;
 428	}
 429
 430	qla_init_base_qpair(vha, req, rsp);
 431
 432	if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
 433		ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
 434			GFP_KERNEL);
 435		if (!ha->queue_pair_map) {
 436			ql_log(ql_log_fatal, vha, 0x0180,
 437			    "Unable to allocate memory for queue pair ptrs.\n");
 438			goto fail_qpair_map;
 439		}
 440	}
 441
 442	/*
 443	 * Make sure we record at least the request and response queue zero in
 444	 * case we need to free them if part of the probe fails.
 445	 */
 446	ha->rsp_q_map[0] = rsp;
 447	ha->req_q_map[0] = req;
 448	set_bit(0, ha->rsp_qid_map);
 449	set_bit(0, ha->req_qid_map);
 450	return 0;
 451
 452fail_qpair_map:
 453	kfree(ha->base_qpair);
 454	ha->base_qpair = NULL;
 455fail_base_qpair:
 456	kfree(ha->rsp_q_map);
 457	ha->rsp_q_map = NULL;
 458fail_rsp_map:
 459	kfree(ha->req_q_map);
 460	ha->req_q_map = NULL;
 461fail_req_map:
 462	return -ENOMEM;
 463}
 464
 465static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
 466{
 467	if (IS_QLAFX00(ha)) {
 468		if (req && req->ring_fx00)
 469			dma_free_coherent(&ha->pdev->dev,
 470			    (req->length_fx00 + 1) * sizeof(request_t),
 471			    req->ring_fx00, req->dma_fx00);
 472	} else if (req && req->ring)
 473		dma_free_coherent(&ha->pdev->dev,
 474		(req->length + 1) * sizeof(request_t),
 475		req->ring, req->dma);
 476
 477	if (req)
 478		kfree(req->outstanding_cmds);
 479
 480	kfree(req);
 481}
 482
 483static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
 484{
 485	if (IS_QLAFX00(ha)) {
 486		if (rsp && rsp->ring_fx00)
 487			dma_free_coherent(&ha->pdev->dev,
 488			    (rsp->length_fx00 + 1) * sizeof(request_t),
 489			    rsp->ring_fx00, rsp->dma_fx00);
 490	} else if (rsp && rsp->ring) {
 491		dma_free_coherent(&ha->pdev->dev,
 492		(rsp->length + 1) * sizeof(response_t),
 493		rsp->ring, rsp->dma);
 494	}
 495	kfree(rsp);
 496}
 497
 498static void qla2x00_free_queues(struct qla_hw_data *ha)
 499{
 500	struct req_que *req;
 501	struct rsp_que *rsp;
 502	int cnt;
 503	unsigned long flags;
 504
 505	if (ha->queue_pair_map) {
 506		kfree(ha->queue_pair_map);
 507		ha->queue_pair_map = NULL;
 508	}
 509	if (ha->base_qpair) {
 510		kfree(ha->base_qpair);
 511		ha->base_qpair = NULL;
 512	}
 513
 514	spin_lock_irqsave(&ha->hardware_lock, flags);
 515	for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
 516		if (!test_bit(cnt, ha->req_qid_map))
 517			continue;
 518
 519		req = ha->req_q_map[cnt];
 520		clear_bit(cnt, ha->req_qid_map);
 521		ha->req_q_map[cnt] = NULL;
 522
 523		spin_unlock_irqrestore(&ha->hardware_lock, flags);
 524		qla2x00_free_req_que(ha, req);
 525		spin_lock_irqsave(&ha->hardware_lock, flags);
 526	}
 527	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 528
 529	kfree(ha->req_q_map);
 530	ha->req_q_map = NULL;
 531
 532
 533	spin_lock_irqsave(&ha->hardware_lock, flags);
 534	for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
 535		if (!test_bit(cnt, ha->rsp_qid_map))
 536			continue;
 537
 538		rsp = ha->rsp_q_map[cnt];
 539		clear_bit(cnt, ha->rsp_qid_map);
 540		ha->rsp_q_map[cnt] =  NULL;
 541		spin_unlock_irqrestore(&ha->hardware_lock, flags);
 542		qla2x00_free_rsp_que(ha, rsp);
 543		spin_lock_irqsave(&ha->hardware_lock, flags);
 544	}
 545	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 546
 547	kfree(ha->rsp_q_map);
 548	ha->rsp_q_map = NULL;
 549}
 550
 551static char *
 552qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
 553{
 554	struct qla_hw_data *ha = vha->hw;
 555	static const char *const pci_bus_modes[] = {
 556		"33", "66", "100", "133",
 557	};
 558	uint16_t pci_bus;
 559
 560	pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
 561	if (pci_bus) {
 562		snprintf(str, str_len, "PCI-X (%s MHz)",
 563			 pci_bus_modes[pci_bus]);
 564	} else {
 565		pci_bus = (ha->pci_attr & BIT_8) >> 8;
 566		snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
 567	}
 568
 569	return str;
 570}
 571
 572static char *
 573qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
 574{
 575	static const char *const pci_bus_modes[] = {
 576		"33", "66", "100", "133",
 577	};
 578	struct qla_hw_data *ha = vha->hw;
 579	uint32_t pci_bus;
 580
 581	if (pci_is_pcie(ha->pdev)) {
 582		uint32_t lstat, lspeed, lwidth;
 583		const char *speed_str;
 584
 585		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
 586		lspeed = lstat & PCI_EXP_LNKCAP_SLS;
 587		lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
 588
 589		switch (lspeed) {
 590		case 1:
 591			speed_str = "2.5GT/s";
 592			break;
 593		case 2:
 594			speed_str = "5.0GT/s";
 595			break;
 596		case 3:
 597			speed_str = "8.0GT/s";
 598			break;
 599		case 4:
 600			speed_str = "16.0GT/s";
 601			break;
 602		default:
 603			speed_str = "<unknown>";
 604			break;
 605		}
 606		snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
 607
 608		return str;
 609	}
 610
 611	pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
 612	if (pci_bus == 0 || pci_bus == 8)
 613		snprintf(str, str_len, "PCI (%s MHz)",
 614			 pci_bus_modes[pci_bus >> 3]);
 615	else
 616		snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
 617			 pci_bus & 4 ? 2 : 1,
 618			 pci_bus_modes[pci_bus & 3]);
 619
 620	return str;
 621}
 622
 623static char *
 624qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
 625{
 626	char un_str[10];
 627	struct qla_hw_data *ha = vha->hw;
 628
 629	snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
 630	    ha->fw_minor_version, ha->fw_subminor_version);
 631
 632	if (ha->fw_attributes & BIT_9) {
 633		strcat(str, "FLX");
 634		return (str);
 635	}
 636
 637	switch (ha->fw_attributes & 0xFF) {
 638	case 0x7:
 639		strcat(str, "EF");
 640		break;
 641	case 0x17:
 642		strcat(str, "TP");
 643		break;
 644	case 0x37:
 645		strcat(str, "IP");
 646		break;
 647	case 0x77:
 648		strcat(str, "VI");
 649		break;
 650	default:
 651		sprintf(un_str, "(%x)", ha->fw_attributes);
 652		strcat(str, un_str);
 653		break;
 654	}
 655	if (ha->fw_attributes & 0x100)
 656		strcat(str, "X");
 657
 658	return (str);
 659}
 660
 661static char *
 662qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
 663{
 664	struct qla_hw_data *ha = vha->hw;
 665
 666	snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
 667	    ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
 668	return str;
 669}
 670
 671void qla2x00_sp_free_dma(srb_t *sp)
 672{
 673	struct qla_hw_data *ha = sp->vha->hw;
 674	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 675
 676	if (sp->flags & SRB_DMA_VALID) {
 677		scsi_dma_unmap(cmd);
 678		sp->flags &= ~SRB_DMA_VALID;
 679	}
 680
 681	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
 682		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
 683		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
 684		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
 685	}
 686
 687	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
 688		/* List assured to be having elements */
 689		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
 690		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
 691	}
 692
 693	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
 694		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
 695
 696		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
 697		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
 698	}
 699
 700	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
 701		struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
 702
 703		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
 704		    ctx1->fcp_cmnd_dma);
 705		list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
 706		ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
 707		ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
 708		mempool_free(ctx1, ha->ctx_mempool);
 709	}
 710}
 711
 712void qla2x00_sp_compl(srb_t *sp, int res)
 713{
 714	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 715	struct completion *comp = sp->comp;
 716
 717	sp->free(sp);
 718	cmd->result = res;
 719	CMD_SP(cmd) = NULL;
 720	cmd->scsi_done(cmd);
 721	if (comp)
 722		complete(comp);
 723}
 724
 725void qla2xxx_qpair_sp_free_dma(srb_t *sp)
 726{
 727	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 728	struct qla_hw_data *ha = sp->fcport->vha->hw;
 729
 730	if (sp->flags & SRB_DMA_VALID) {
 731		scsi_dma_unmap(cmd);
 732		sp->flags &= ~SRB_DMA_VALID;
 733	}
 734
 735	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
 736		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
 737		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
 738		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
 739	}
 740
 741	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
 742		/* List assured to be having elements */
 743		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
 744		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
 745	}
 746
 747	if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
 748		struct crc_context *difctx = sp->u.scmd.crc_ctx;
 749		struct dsd_dma *dif_dsd, *nxt_dsd;
 750
 751		list_for_each_entry_safe(dif_dsd, nxt_dsd,
 752		    &difctx->ldif_dma_hndl_list, list) {
 753			list_del(&dif_dsd->list);
 754			dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
 755			    dif_dsd->dsd_list_dma);
 756			kfree(dif_dsd);
 757			difctx->no_dif_bundl--;
 758		}
 759
 760		list_for_each_entry_safe(dif_dsd, nxt_dsd,
 761		    &difctx->ldif_dsd_list, list) {
 762			list_del(&dif_dsd->list);
 763			dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
 764			    dif_dsd->dsd_list_dma);
 765			kfree(dif_dsd);
 766			difctx->no_ldif_dsd--;
 767		}
 768
 769		if (difctx->no_ldif_dsd) {
 770			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
 771			    "%s: difctx->no_ldif_dsd=%x\n",
 772			    __func__, difctx->no_ldif_dsd);
 773		}
 774
 775		if (difctx->no_dif_bundl) {
 776			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
 777			    "%s: difctx->no_dif_bundl=%x\n",
 778			    __func__, difctx->no_dif_bundl);
 779		}
 780		sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
 781	}
 782
 783	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
 784		struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
 785
 786		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
 787		    ctx1->fcp_cmnd_dma);
 788		list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
 789		ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
 790		ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
 791		mempool_free(ctx1, ha->ctx_mempool);
 792		sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
 793	}
 794
 795	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
 796		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
 797
 798		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
 799		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
 800	}
 801}
 802
 803void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
 804{
 805	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 806	struct completion *comp = sp->comp;
 807
 808	sp->free(sp);
 809	cmd->result = res;
 810	CMD_SP(cmd) = NULL;
 811	cmd->scsi_done(cmd);
 812	if (comp)
 813		complete(comp);
 814}
 815
 816static int
 817qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
 818{
 819	scsi_qla_host_t *vha = shost_priv(host);
 820	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
 821	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
 822	struct qla_hw_data *ha = vha->hw;
 823	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
 824	srb_t *sp;
 825	int rval;
 826
 827	if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
 828	    WARN_ON_ONCE(!rport)) {
 829		cmd->result = DID_NO_CONNECT << 16;
 830		goto qc24_fail_command;
 831	}
 832
 833	if (ha->mqenable) {
 834		uint32_t tag;
 835		uint16_t hwq;
 836		struct qla_qpair *qpair = NULL;
 837
 838		tag = blk_mq_unique_tag(cmd->request);
 839		hwq = blk_mq_unique_tag_to_hwq(tag);
 840		qpair = ha->queue_pair_map[hwq];
 841
 842		if (qpair)
 843			return qla2xxx_mqueuecommand(host, cmd, qpair);
 844	}
 845
 846	if (ha->flags.eeh_busy) {
 847		if (ha->flags.pci_channel_io_perm_failure) {
 848			ql_dbg(ql_dbg_aer, vha, 0x9010,
 849			    "PCI Channel IO permanent failure, exiting "
 850			    "cmd=%p.\n", cmd);
 851			cmd->result = DID_NO_CONNECT << 16;
 852		} else {
 853			ql_dbg(ql_dbg_aer, vha, 0x9011,
 854			    "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
 855			cmd->result = DID_REQUEUE << 16;
 856		}
 857		goto qc24_fail_command;
 858	}
 859
 860	rval = fc_remote_port_chkready(rport);
 861	if (rval) {
 862		cmd->result = rval;
 863		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
 864		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
 865		    cmd, rval);
 866		goto qc24_fail_command;
 867	}
 868
 869	if (!vha->flags.difdix_supported &&
 870		scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
 871			ql_dbg(ql_dbg_io, vha, 0x3004,
 872			    "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
 873			    cmd);
 874			cmd->result = DID_NO_CONNECT << 16;
 875			goto qc24_fail_command;
 876	}
 877
 878	if (!fcport) {
 879		cmd->result = DID_NO_CONNECT << 16;
 880		goto qc24_fail_command;
 881	}
 882
 883	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
 884		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
 885			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
 886			ql_dbg(ql_dbg_io, vha, 0x3005,
 887			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
 888			    atomic_read(&fcport->state),
 889			    atomic_read(&base_vha->loop_state));
 890			cmd->result = DID_NO_CONNECT << 16;
 891			goto qc24_fail_command;
 892		}
 893		goto qc24_target_busy;
 894	}
 895
 896	/*
 897	 * Return target busy if we've received a non-zero retry_delay_timer
 898	 * in a FCP_RSP.
 899	 */
 900	if (fcport->retry_delay_timestamp == 0) {
 901		/* retry delay not set */
 902	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
 903		fcport->retry_delay_timestamp = 0;
 904	else
 905		goto qc24_target_busy;
 906
 907	sp = scsi_cmd_priv(cmd);
 908	qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
 909
 910	sp->u.scmd.cmd = cmd;
 911	sp->type = SRB_SCSI_CMD;
 912
 913	CMD_SP(cmd) = (void *)sp;
 914	sp->free = qla2x00_sp_free_dma;
 915	sp->done = qla2x00_sp_compl;
 916
 917	rval = ha->isp_ops->start_scsi(sp);
 918	if (rval != QLA_SUCCESS) {
 919		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
 920		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
 921		goto qc24_host_busy_free_sp;
 922	}
 923
 924	return 0;
 925
 926qc24_host_busy_free_sp:
 927	sp->free(sp);
 928
 929qc24_target_busy:
 930	return SCSI_MLQUEUE_TARGET_BUSY;
 931
 932qc24_fail_command:
 933	cmd->scsi_done(cmd);
 934
 935	return 0;
 936}
 937
 938/* For MQ supported I/O */
 939int
 940qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
 941    struct qla_qpair *qpair)
 942{
 943	scsi_qla_host_t *vha = shost_priv(host);
 944	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
 945	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
 946	struct qla_hw_data *ha = vha->hw;
 947	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
 948	srb_t *sp;
 949	int rval;
 950
 951	rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
 952	if (rval) {
 953		cmd->result = rval;
 954		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
 955		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
 956		    cmd, rval);
 957		goto qc24_fail_command;
 958	}
 959
 960	if (!fcport) {
 961		cmd->result = DID_NO_CONNECT << 16;
 962		goto qc24_fail_command;
 963	}
 964
 965	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
 966		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
 967			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
 968			ql_dbg(ql_dbg_io, vha, 0x3077,
 969			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
 970			    atomic_read(&fcport->state),
 971			    atomic_read(&base_vha->loop_state));
 972			cmd->result = DID_NO_CONNECT << 16;
 973			goto qc24_fail_command;
 974		}
 975		goto qc24_target_busy;
 976	}
 977
 978	/*
 979	 * Return target busy if we've received a non-zero retry_delay_timer
 980	 * in a FCP_RSP.
 981	 */
 982	if (fcport->retry_delay_timestamp == 0) {
 983		/* retry delay not set */
 984	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
 985		fcport->retry_delay_timestamp = 0;
 986	else
 987		goto qc24_target_busy;
 988
 989	sp = scsi_cmd_priv(cmd);
 990	qla2xxx_init_sp(sp, vha, qpair, fcport);
 991
 992	sp->u.scmd.cmd = cmd;
 993	sp->type = SRB_SCSI_CMD;
 994	CMD_SP(cmd) = (void *)sp;
 995	sp->free = qla2xxx_qpair_sp_free_dma;
 996	sp->done = qla2xxx_qpair_sp_compl;
 997
 998	rval = ha->isp_ops->start_scsi_mq(sp);
 999	if (rval != QLA_SUCCESS) {
1000		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1001		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1002		if (rval == QLA_INTERFACE_ERROR)
1003			goto qc24_free_sp_fail_command;
1004		goto qc24_host_busy_free_sp;
1005	}
1006
1007	return 0;
1008
1009qc24_host_busy_free_sp:
1010	sp->free(sp);
1011
1012qc24_target_busy:
1013	return SCSI_MLQUEUE_TARGET_BUSY;
1014
1015qc24_free_sp_fail_command:
1016	sp->free(sp);
1017	CMD_SP(cmd) = NULL;
1018	qla2xxx_rel_qpair_sp(sp->qpair, sp);
1019
1020qc24_fail_command:
1021	cmd->scsi_done(cmd);
1022
1023	return 0;
1024}
1025
1026/*
1027 * qla2x00_eh_wait_on_command
1028 *    Waits for the command to be returned by the Firmware for some
1029 *    max time.
1030 *
1031 * Input:
1032 *    cmd = Scsi Command to wait on.
1033 *
1034 * Return:
1035 *    Completed in time : QLA_SUCCESS
1036 *    Did not complete in time : QLA_FUNCTION_FAILED
1037 */
1038static int
1039qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1040{
1041#define ABORT_POLLING_PERIOD	1000
1042#define ABORT_WAIT_ITER		((2 * 1000) / (ABORT_POLLING_PERIOD))
1043	unsigned long wait_iter = ABORT_WAIT_ITER;
1044	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1045	struct qla_hw_data *ha = vha->hw;
1046	int ret = QLA_SUCCESS;
1047
1048	if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1049		ql_dbg(ql_dbg_taskm, vha, 0x8005,
1050		    "Return:eh_wait.\n");
1051		return ret;
1052	}
1053
1054	while (CMD_SP(cmd) && wait_iter--) {
1055		msleep(ABORT_POLLING_PERIOD);
1056	}
1057	if (CMD_SP(cmd))
1058		ret = QLA_FUNCTION_FAILED;
1059
1060	return ret;
1061}
1062
1063/*
1064 * qla2x00_wait_for_hba_online
1065 *    Wait till the HBA is online after going through
1066 *    <= MAX_RETRIES_OF_ISP_ABORT  or
1067 *    finally HBA is disabled ie marked offline
1068 *
1069 * Input:
1070 *     ha - pointer to host adapter structure
1071 *
1072 * Note:
1073 *    Does context switching-Release SPIN_LOCK
1074 *    (if any) before calling this routine.
1075 *
1076 * Return:
1077 *    Success (Adapter is online) : 0
1078 *    Failed  (Adapter is offline/disabled) : 1
1079 */
1080int
1081qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1082{
1083	int		return_status;
1084	unsigned long	wait_online;
1085	struct qla_hw_data *ha = vha->hw;
1086	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1087
1088	wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1089	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1090	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1091	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1092	    ha->dpc_active) && time_before(jiffies, wait_online)) {
1093
1094		msleep(1000);
1095	}
1096	if (base_vha->flags.online)
1097		return_status = QLA_SUCCESS;
1098	else
1099		return_status = QLA_FUNCTION_FAILED;
1100
1101	return (return_status);
1102}
1103
1104static inline int test_fcport_count(scsi_qla_host_t *vha)
1105{
1106	struct qla_hw_data *ha = vha->hw;
1107	unsigned long flags;
1108	int res;
1109
1110	spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1111	ql_dbg(ql_dbg_init, vha, 0x00ec,
1112	    "tgt %p, fcport_count=%d\n",
1113	    vha, vha->fcport_count);
1114	res = (vha->fcport_count == 0);
1115	spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1116
1117	return res;
1118}
1119
1120/*
1121 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1122 * it has dependency on UNLOADING flag to stop device discovery
1123 */
1124void
1125qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1126{
1127	u8 i;
1128
1129	qla2x00_mark_all_devices_lost(vha);
1130
1131	for (i = 0; i < 10; i++) {
1132		if (wait_event_timeout(vha->fcport_waitQ,
1133		    test_fcport_count(vha), HZ) > 0)
1134			break;
1135	}
1136
1137	flush_workqueue(vha->hw->wq);
1138}
1139
1140/*
1141 * qla2x00_wait_for_hba_ready
1142 * Wait till the HBA is ready before doing driver unload
1143 *
1144 * Input:
1145 *     ha - pointer to host adapter structure
1146 *
1147 * Note:
1148 *    Does context switching-Release SPIN_LOCK
1149 *    (if any) before calling this routine.
1150 *
1151 */
1152static void
1153qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1154{
1155	struct qla_hw_data *ha = vha->hw;
1156	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1157
1158	while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1159		ha->flags.mbox_busy) ||
1160	       test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1161	       test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1162		if (test_bit(UNLOADING, &base_vha->dpc_flags))
1163			break;
1164		msleep(1000);
1165	}
1166}
1167
1168int
1169qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1170{
1171	int		return_status;
1172	unsigned long	wait_reset;
1173	struct qla_hw_data *ha = vha->hw;
1174	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1175
1176	wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1177	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1178	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1179	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1180	    ha->dpc_active) && time_before(jiffies, wait_reset)) {
1181
1182		msleep(1000);
1183
1184		if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1185		    ha->flags.chip_reset_done)
1186			break;
1187	}
1188	if (ha->flags.chip_reset_done)
1189		return_status = QLA_SUCCESS;
1190	else
1191		return_status = QLA_FUNCTION_FAILED;
1192
1193	return return_status;
1194}
1195
1196#define ISP_REG_DISCONNECT 0xffffffffU
1197/**************************************************************************
1198* qla2x00_isp_reg_stat
1199*
1200* Description:
1201*	Read the host status register of ISP before aborting the command.
1202*
1203* Input:
1204*	ha = pointer to host adapter structure.
1205*
1206*
1207* Returns:
1208*	Either true or false.
1209*
1210* Note:	Return true if there is register disconnect.
1211**************************************************************************/
1212static inline
1213uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1214{
1215	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1216	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1217
1218	if (IS_P3P_TYPE(ha))
1219		return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1220	else
1221		return ((RD_REG_DWORD(&reg->host_status)) ==
1222			ISP_REG_DISCONNECT);
1223}
1224
1225/**************************************************************************
1226* qla2xxx_eh_abort
1227*
1228* Description:
1229*    The abort function will abort the specified command.
1230*
1231* Input:
1232*    cmd = Linux SCSI command packet to be aborted.
1233*
1234* Returns:
1235*    Either SUCCESS or FAILED.
1236*
1237* Note:
1238*    Only return FAILED if command not returned by firmware.
1239**************************************************************************/
1240static int
1241qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1242{
1243	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1244	DECLARE_COMPLETION_ONSTACK(comp);
1245	srb_t *sp;
1246	int ret;
1247	unsigned int id;
1248	uint64_t lun;
1249	int rval;
1250	struct qla_hw_data *ha = vha->hw;
1251	uint32_t ratov_j;
1252	struct qla_qpair *qpair;
1253	unsigned long flags;
1254
1255	if (qla2x00_isp_reg_stat(ha)) {
1256		ql_log(ql_log_info, vha, 0x8042,
1257		    "PCI/Register disconnect, exiting.\n");
1258		return FAILED;
1259	}
1260
1261	ret = fc_block_scsi_eh(cmd);
1262	if (ret != 0)
1263		return ret;
1264
1265	sp = scsi_cmd_priv(cmd);
1266	qpair = sp->qpair;
1267
1268	if ((sp->fcport && sp->fcport->deleted) || !qpair)
1269		return SUCCESS;
1270
1271	spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1272	sp->comp = &comp;
1273	spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1274
1275
1276	id = cmd->device->id;
1277	lun = cmd->device->lun;
1278
1279	ql_dbg(ql_dbg_taskm, vha, 0x8002,
1280	    "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1281	    vha->host_no, id, lun, sp, cmd, sp->handle);
1282
1283	/*
1284	 * Abort will release the original Command/sp from FW. Let the
1285	 * original command call scsi_done. In return, he will wakeup
1286	 * this sleeping thread.
1287	 */
1288	rval = ha->isp_ops->abort_command(sp);
1289
1290	ql_dbg(ql_dbg_taskm, vha, 0x8003,
1291	       "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1292
1293	/* Wait for the command completion. */
1294	ratov_j = ha->r_a_tov/10 * 4 * 1000;
1295	ratov_j = msecs_to_jiffies(ratov_j);
1296	switch (rval) {
1297	case QLA_SUCCESS:
1298		if (!wait_for_completion_timeout(&comp, ratov_j)) {
1299			ql_dbg(ql_dbg_taskm, vha, 0xffff,
1300			    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1301			    __func__, ha->r_a_tov/10);
1302			ret = FAILED;
1303		} else {
1304			ret = SUCCESS;
1305		}
1306		break;
1307	default:
1308		ret = FAILED;
1309		break;
1310	}
1311
1312	sp->comp = NULL;
1313
1314	ql_log(ql_log_info, vha, 0x801c,
1315	    "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1316	    vha->host_no, id, lun, ret);
1317
1318	return ret;
1319}
1320
1321/*
1322 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1323 */
1324int
1325qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1326	uint64_t l, enum nexus_wait_type type)
1327{
1328	int cnt, match, status;
1329	unsigned long flags;
1330	struct qla_hw_data *ha = vha->hw;
1331	struct req_que *req;
1332	srb_t *sp;
1333	struct scsi_cmnd *cmd;
1334
1335	status = QLA_SUCCESS;
1336
1337	spin_lock_irqsave(&ha->hardware_lock, flags);
1338	req = vha->req;
1339	for (cnt = 1; status == QLA_SUCCESS &&
1340		cnt < req->num_outstanding_cmds; cnt++) {
1341		sp = req->outstanding_cmds[cnt];
1342		if (!sp)
1343			continue;
1344		if (sp->type != SRB_SCSI_CMD)
1345			continue;
1346		if (vha->vp_idx != sp->vha->vp_idx)
1347			continue;
1348		match = 0;
1349		cmd = GET_CMD_SP(sp);
1350		switch (type) {
1351		case WAIT_HOST:
1352			match = 1;
1353			break;
1354		case WAIT_TARGET:
1355			match = cmd->device->id == t;
1356			break;
1357		case WAIT_LUN:
1358			match = (cmd->device->id == t &&
1359				cmd->device->lun == l);
1360			break;
1361		}
1362		if (!match)
1363			continue;
1364
1365		spin_unlock_irqrestore(&ha->hardware_lock, flags);
1366		status = qla2x00_eh_wait_on_command(cmd);
1367		spin_lock_irqsave(&ha->hardware_lock, flags);
1368	}
1369	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1370
1371	return status;
1372}
1373
1374static char *reset_errors[] = {
1375	"HBA not online",
1376	"HBA not ready",
1377	"Task management failed",
1378	"Waiting for command completions",
1379};
1380
1381static int
1382__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1383    struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1384{
1385	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1386	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1387	int err;
1388
1389	if (!fcport) {
1390		return FAILED;
1391	}
1392
1393	err = fc_block_scsi_eh(cmd);
1394	if (err != 0)
1395		return err;
1396
1397	if (fcport->deleted)
1398		return SUCCESS;
1399
1400	ql_log(ql_log_info, vha, 0x8009,
1401	    "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1402	    cmd->device->id, cmd->device->lun, cmd);
1403
1404	err = 0;
1405	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1406		ql_log(ql_log_warn, vha, 0x800a,
1407		    "Wait for hba online failed for cmd=%p.\n", cmd);
1408		goto eh_reset_failed;
1409	}
1410	err = 2;
1411	if (do_reset(fcport, cmd->device->lun, 1)
1412		!= QLA_SUCCESS) {
1413		ql_log(ql_log_warn, vha, 0x800c,
1414		    "do_reset failed for cmd=%p.\n", cmd);
1415		goto eh_reset_failed;
1416	}
1417	err = 3;
1418	if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1419	    cmd->device->lun, type) != QLA_SUCCESS) {
1420		ql_log(ql_log_warn, vha, 0x800d,
1421		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1422		goto eh_reset_failed;
1423	}
1424
1425	ql_log(ql_log_info, vha, 0x800e,
1426	    "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1427	    vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1428
1429	return SUCCESS;
1430
1431eh_reset_failed:
1432	ql_log(ql_log_info, vha, 0x800f,
1433	    "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1434	    reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1435	    cmd);
1436	return FAILED;
1437}
1438
1439static int
1440qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1441{
1442	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1443	struct qla_hw_data *ha = vha->hw;
1444
1445	if (qla2x00_isp_reg_stat(ha)) {
1446		ql_log(ql_log_info, vha, 0x803e,
1447		    "PCI/Register disconnect, exiting.\n");
1448		return FAILED;
1449	}
1450
1451	return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1452	    ha->isp_ops->lun_reset);
1453}
1454
1455static int
1456qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1457{
1458	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1459	struct qla_hw_data *ha = vha->hw;
1460
1461	if (qla2x00_isp_reg_stat(ha)) {
1462		ql_log(ql_log_info, vha, 0x803f,
1463		    "PCI/Register disconnect, exiting.\n");
1464		return FAILED;
1465	}
1466
1467	return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1468	    ha->isp_ops->target_reset);
1469}
1470
1471/**************************************************************************
1472* qla2xxx_eh_bus_reset
1473*
1474* Description:
1475*    The bus reset function will reset the bus and abort any executing
1476*    commands.
1477*
1478* Input:
1479*    cmd = Linux SCSI command packet of the command that cause the
1480*          bus reset.
1481*
1482* Returns:
1483*    SUCCESS/FAILURE (defined as macro in scsi.h).
1484*
1485**************************************************************************/
1486static int
1487qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1488{
1489	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1490	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1491	int ret = FAILED;
1492	unsigned int id;
1493	uint64_t lun;
1494	struct qla_hw_data *ha = vha->hw;
1495
1496	if (qla2x00_isp_reg_stat(ha)) {
1497		ql_log(ql_log_info, vha, 0x8040,
1498		    "PCI/Register disconnect, exiting.\n");
1499		return FAILED;
1500	}
1501
1502	id = cmd->device->id;
1503	lun = cmd->device->lun;
1504
1505	if (!fcport) {
1506		return ret;
1507	}
1508
1509	ret = fc_block_scsi_eh(cmd);
1510	if (ret != 0)
1511		return ret;
1512	ret = FAILED;
1513
1514	if (qla2x00_chip_is_down(vha))
1515		return ret;
1516
1517	ql_log(ql_log_info, vha, 0x8012,
1518	    "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1519
1520	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1521		ql_log(ql_log_fatal, vha, 0x8013,
1522		    "Wait for hba online failed board disabled.\n");
1523		goto eh_bus_reset_done;
1524	}
1525
1526	if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1527		ret = SUCCESS;
1528
1529	if (ret == FAILED)
1530		goto eh_bus_reset_done;
1531
1532	/* Flush outstanding commands. */
1533	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1534	    QLA_SUCCESS) {
1535		ql_log(ql_log_warn, vha, 0x8014,
1536		    "Wait for pending commands failed.\n");
1537		ret = FAILED;
1538	}
1539
1540eh_bus_reset_done:
1541	ql_log(ql_log_warn, vha, 0x802b,
1542	    "BUS RESET %s nexus=%ld:%d:%llu.\n",
1543	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1544
1545	return ret;
1546}
1547
1548/**************************************************************************
1549* qla2xxx_eh_host_reset
1550*
1551* Description:
1552*    The reset function will reset the Adapter.
1553*
1554* Input:
1555*      cmd = Linux SCSI command packet of the command that cause the
1556*            adapter reset.
1557*
1558* Returns:
1559*      Either SUCCESS or FAILED.
1560*
1561* Note:
1562**************************************************************************/
1563static int
1564qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1565{
1566	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1567	struct qla_hw_data *ha = vha->hw;
1568	int ret = FAILED;
1569	unsigned int id;
1570	uint64_t lun;
1571	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1572
1573	if (qla2x00_isp_reg_stat(ha)) {
1574		ql_log(ql_log_info, vha, 0x8041,
1575		    "PCI/Register disconnect, exiting.\n");
1576		schedule_work(&ha->board_disable);
1577		return SUCCESS;
1578	}
1579
1580	id = cmd->device->id;
1581	lun = cmd->device->lun;
1582
1583	ql_log(ql_log_info, vha, 0x8018,
1584	    "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1585
1586	/*
1587	 * No point in issuing another reset if one is active.  Also do not
1588	 * attempt a reset if we are updating flash.
1589	 */
1590	if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1591		goto eh_host_reset_lock;
1592
1593	if (vha != base_vha) {
1594		if (qla2x00_vp_abort_isp(vha))
1595			goto eh_host_reset_lock;
1596	} else {
1597		if (IS_P3P_TYPE(vha->hw)) {
1598			if (!qla82xx_fcoe_ctx_reset(vha)) {
1599				/* Ctx reset success */
1600				ret = SUCCESS;
1601				goto eh_host_reset_lock;
1602			}
1603			/* fall thru if ctx reset failed */
1604		}
1605		if (ha->wq)
1606			flush_workqueue(ha->wq);
1607
1608		set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1609		if (ha->isp_ops->abort_isp(base_vha)) {
1610			clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1611			/* failed. schedule dpc to try */
1612			set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1613
1614			if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1615				ql_log(ql_log_warn, vha, 0x802a,
1616				    "wait for hba online failed.\n");
1617				goto eh_host_reset_lock;
1618			}
1619		}
1620		clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1621	}
1622
1623	/* Waiting for command to be returned to OS.*/
1624	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1625		QLA_SUCCESS)
1626		ret = SUCCESS;
1627
1628eh_host_reset_lock:
1629	ql_log(ql_log_info, vha, 0x8017,
1630	    "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1631	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1632
1633	return ret;
1634}
1635
1636/*
1637* qla2x00_loop_reset
1638*      Issue loop reset.
1639*
1640* Input:
1641*      ha = adapter block pointer.
1642*
1643* Returns:
1644*      0 = success
1645*/
1646int
1647qla2x00_loop_reset(scsi_qla_host_t *vha)
1648{
1649	int ret;
1650	struct fc_port *fcport;
1651	struct qla_hw_data *ha = vha->hw;
1652
1653	if (IS_QLAFX00(ha)) {
1654		return qlafx00_loop_reset(vha);
1655	}
1656
1657	if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1658		list_for_each_entry(fcport, &vha->vp_fcports, list) {
1659			if (fcport->port_type != FCT_TARGET)
1660				continue;
1661
1662			ret = ha->isp_ops->target_reset(fcport, 0, 0);
1663			if (ret != QLA_SUCCESS) {
1664				ql_dbg(ql_dbg_taskm, vha, 0x802c,
1665				    "Bus Reset failed: Reset=%d "
1666				    "d_id=%x.\n", ret, fcport->d_id.b24);
1667			}
1668		}
1669	}
1670
1671
1672	if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1673		atomic_set(&vha->loop_state, LOOP_DOWN);
1674		atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1675		qla2x00_mark_all_devices_lost(vha);
1676		ret = qla2x00_full_login_lip(vha);
1677		if (ret != QLA_SUCCESS) {
1678			ql_dbg(ql_dbg_taskm, vha, 0x802d,
1679			    "full_login_lip=%d.\n", ret);
1680		}
1681	}
1682
1683	if (ha->flags.enable_lip_reset) {
1684		ret = qla2x00_lip_reset(vha);
1685		if (ret != QLA_SUCCESS)
1686			ql_dbg(ql_dbg_taskm, vha, 0x802e,
1687			    "lip_reset failed (%d).\n", ret);
1688	}
1689
1690	/* Issue marker command only when we are going to start the I/O */
1691	vha->marker_needed = 1;
1692
1693	return QLA_SUCCESS;
1694}
1695
1696/*
1697 * The caller must ensure that no completion interrupts will happen
1698 * while this function is in progress.
1699 */
1700static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1701			      unsigned long *flags)
1702	__releases(qp->qp_lock_ptr)
1703	__acquires(qp->qp_lock_ptr)
1704{
1705	DECLARE_COMPLETION_ONSTACK(comp);
1706	scsi_qla_host_t *vha = qp->vha;
1707	struct qla_hw_data *ha = vha->hw;
1708	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1709	int rval;
1710	bool ret_cmd;
1711	uint32_t ratov_j;
1712
1713	lockdep_assert_held(qp->qp_lock_ptr);
1714
1715	if (qla2x00_chip_is_down(vha)) {
1716		sp->done(sp, res);
1717		return;
1718	}
1719
1720	if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1721	    (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1722	     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1723	     !qla2x00_isp_reg_stat(ha))) {
1724		if (sp->comp) {
1725			sp->done(sp, res);
1726			return;
1727		}
1728
1729		sp->comp = &comp;
1730		spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1731
1732		rval = ha->isp_ops->abort_command(sp);
1733		/* Wait for command completion. */
1734		ret_cmd = false;
1735		ratov_j = ha->r_a_tov/10 * 4 * 1000;
1736		ratov_j = msecs_to_jiffies(ratov_j);
1737		switch (rval) {
1738		case QLA_SUCCESS:
1739			if (wait_for_completion_timeout(&comp, ratov_j)) {
1740				ql_dbg(ql_dbg_taskm, vha, 0xffff,
1741				    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1742				    __func__, ha->r_a_tov/10);
1743				ret_cmd = true;
1744			}
1745			/* else FW return SP to driver */
1746			break;
1747		default:
1748			ret_cmd = true;
1749			break;
1750		}
1751
1752		spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1753		if (ret_cmd && blk_mq_request_started(cmd->request))
1754			sp->done(sp, res);
1755	} else {
1756		sp->done(sp, res);
1757	}
1758}
1759
1760/*
1761 * The caller must ensure that no completion interrupts will happen
1762 * while this function is in progress.
1763 */
1764static void
1765__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1766{
1767	int cnt;
1768	unsigned long flags;
1769	srb_t *sp;
1770	scsi_qla_host_t *vha = qp->vha;
1771	struct qla_hw_data *ha = vha->hw;
1772	struct req_que *req;
1773	struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1774	struct qla_tgt_cmd *cmd;
1775
1776	if (!ha->req_q_map)
1777		return;
1778	spin_lock_irqsave(qp->qp_lock_ptr, flags);
1779	req = qp->req;
1780	for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1781		sp = req->outstanding_cmds[cnt];
1782		if (sp) {
1783			switch (sp->cmd_type) {
1784			case TYPE_SRB:
1785				qla2x00_abort_srb(qp, sp, res, &flags);
1786				break;
1787			case TYPE_TGT_CMD:
1788				if (!vha->hw->tgt.tgt_ops || !tgt ||
1789				    qla_ini_mode_enabled(vha)) {
1790					ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1791					    "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1792					    vha->dpc_flags);
1793					continue;
1794				}
1795				cmd = (struct qla_tgt_cmd *)sp;
1796				cmd->aborted = 1;
1797				break;
1798			case TYPE_TGT_TMCMD:
1799				/* Skip task management functions. */
1800				break;
1801			default:
1802				break;
1803			}
1804			req->outstanding_cmds[cnt] = NULL;
1805		}
1806	}
1807	spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1808}
1809
1810/*
1811 * The caller must ensure that no completion interrupts will happen
1812 * while this function is in progress.
1813 */
1814void
1815qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1816{
1817	int que;
1818	struct qla_hw_data *ha = vha->hw;
1819
1820	/* Continue only if initialization complete. */
1821	if (!ha->base_qpair)
1822		return;
1823	__qla2x00_abort_all_cmds(ha->base_qpair, res);
1824
1825	if (!ha->queue_pair_map)
1826		return;
1827	for (que = 0; que < ha->max_qpairs; que++) {
1828		if (!ha->queue_pair_map[que])
1829			continue;
1830
1831		__qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1832	}
1833}
1834
1835static int
1836qla2xxx_slave_alloc(struct scsi_device *sdev)
1837{
1838	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1839
1840	if (!rport || fc_remote_port_chkready(rport))
1841		return -ENXIO;
1842
1843	sdev->hostdata = *(fc_port_t **)rport->dd_data;
1844
1845	return 0;
1846}
1847
1848static int
1849qla2xxx_slave_configure(struct scsi_device *sdev)
1850{
1851	scsi_qla_host_t *vha = shost_priv(sdev->host);
1852	struct req_que *req = vha->req;
1853
1854	if (IS_T10_PI_CAPABLE(vha->hw))
1855		blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1856
1857	scsi_change_queue_depth(sdev, req->max_q_depth);
1858	return 0;
1859}
1860
1861static void
1862qla2xxx_slave_destroy(struct scsi_device *sdev)
1863{
1864	sdev->hostdata = NULL;
1865}
1866
1867/**
1868 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1869 * @ha: HA context
1870 *
1871 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1872 * supported addressing method.
1873 */
1874static void
1875qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1876{
1877	/* Assume a 32bit DMA mask. */
1878	ha->flags.enable_64bit_addressing = 0;
1879
1880	if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1881		/* Any upper-dword bits set? */
1882		if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1883		    !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1884			/* Ok, a 64bit DMA mask is applicable. */
1885			ha->flags.enable_64bit_addressing = 1;
1886			ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1887			ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1888			return;
1889		}
1890	}
1891
1892	dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1893	pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1894}
1895
1896static void
1897qla2x00_enable_intrs(struct qla_hw_data *ha)
1898{
1899	unsigned long flags = 0;
1900	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1901
1902	spin_lock_irqsave(&ha->hardware_lock, flags);
1903	ha->interrupts_on = 1;
1904	/* enable risc and host interrupts */
1905	WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1906	RD_REG_WORD(&reg->ictrl);
1907	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1908
1909}
1910
1911static void
1912qla2x00_disable_intrs(struct qla_hw_data *ha)
1913{
1914	unsigned long flags = 0;
1915	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1916
1917	spin_lock_irqsave(&ha->hardware_lock, flags);
1918	ha->interrupts_on = 0;
1919	/* disable risc and host interrupts */
1920	WRT_REG_WORD(&reg->ictrl, 0);
1921	RD_REG_WORD(&reg->ictrl);
1922	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1923}
1924
1925static void
1926qla24xx_enable_intrs(struct qla_hw_data *ha)
1927{
1928	unsigned long flags = 0;
1929	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1930
1931	spin_lock_irqsave(&ha->hardware_lock, flags);
1932	ha->interrupts_on = 1;
1933	WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1934	RD_REG_DWORD(&reg->ictrl);
1935	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1936}
1937
1938static void
1939qla24xx_disable_intrs(struct qla_hw_data *ha)
1940{
1941	unsigned long flags = 0;
1942	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1943
1944	if (IS_NOPOLLING_TYPE(ha))
1945		return;
1946	spin_lock_irqsave(&ha->hardware_lock, flags);
1947	ha->interrupts_on = 0;
1948	WRT_REG_DWORD(&reg->ictrl, 0);
1949	RD_REG_DWORD(&reg->ictrl);
1950	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1951}
1952
1953static int
1954qla2x00_iospace_config(struct qla_hw_data *ha)
1955{
1956	resource_size_t pio;
1957	uint16_t msix;
1958
1959	if (pci_request_selected_regions(ha->pdev, ha->bars,
1960	    QLA2XXX_DRIVER_NAME)) {
1961		ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1962		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1963		    pci_name(ha->pdev));
1964		goto iospace_error_exit;
1965	}
1966	if (!(ha->bars & 1))
1967		goto skip_pio;
1968
1969	/* We only need PIO for Flash operations on ISP2312 v2 chips. */
1970	pio = pci_resource_start(ha->pdev, 0);
1971	if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1972		if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1973			ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1974			    "Invalid pci I/O region size (%s).\n",
1975			    pci_name(ha->pdev));
1976			pio = 0;
1977		}
1978	} else {
1979		ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1980		    "Region #0 no a PIO resource (%s).\n",
1981		    pci_name(ha->pdev));
1982		pio = 0;
1983	}
1984	ha->pio_address = pio;
1985	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1986	    "PIO address=%llu.\n",
1987	    (unsigned long long)ha->pio_address);
1988
1989skip_pio:
1990	/* Use MMIO operations for all accesses. */
1991	if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1992		ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1993		    "Region #1 not an MMIO resource (%s), aborting.\n",
1994		    pci_name(ha->pdev));
1995		goto iospace_error_exit;
1996	}
1997	if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1998		ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1999		    "Invalid PCI mem region size (%s), aborting.\n",
2000		    pci_name(ha->pdev));
2001		goto iospace_error_exit;
2002	}
2003
2004	ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2005	if (!ha->iobase) {
2006		ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2007		    "Cannot remap MMIO (%s), aborting.\n",
2008		    pci_name(ha->pdev));
2009		goto iospace_error_exit;
2010	}
2011
2012	/* Determine queue resources */
2013	ha->max_req_queues = ha->max_rsp_queues = 1;
2014	ha->msix_count = QLA_BASE_VECTORS;
2015	if (!ql2xmqsupport || !ql2xnvmeenable ||
2016	    (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2017		goto mqiobase_exit;
2018
2019	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2020			pci_resource_len(ha->pdev, 3));
2021	if (ha->mqiobase) {
2022		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2023		    "MQIO Base=%p.\n", ha->mqiobase);
2024		/* Read MSIX vector size of the board */
2025		pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2026		ha->msix_count = msix + 1;
2027		/* Max queues are bounded by available msix vectors */
2028		/* MB interrupt uses 1 vector */
2029		ha->max_req_queues = ha->msix_count - 1;
2030		ha->max_rsp_queues = ha->max_req_queues;
2031		/* Queue pairs is the max value minus the base queue pair */
2032		ha->max_qpairs = ha->max_rsp_queues - 1;
2033		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2034		    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2035
2036		ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2037		    "MSI-X vector count: %d.\n", ha->msix_count);
2038	} else
2039		ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2040		    "BAR 3 not enabled.\n");
2041
2042mqiobase_exit:
2043	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2044	    "MSIX Count: %d.\n", ha->msix_count);
2045	return (0);
2046
2047iospace_error_exit:
2048	return (-ENOMEM);
2049}
2050
2051
2052static int
2053qla83xx_iospace_config(struct qla_hw_data *ha)
2054{
2055	uint16_t msix;
2056
2057	if (pci_request_selected_regions(ha->pdev, ha->bars,
2058	    QLA2XXX_DRIVER_NAME)) {
2059		ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2060		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2061		    pci_name(ha->pdev));
2062
2063		goto iospace_error_exit;
2064	}
2065
2066	/* Use MMIO operations for all accesses. */
2067	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2068		ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2069		    "Invalid pci I/O region size (%s).\n",
2070		    pci_name(ha->pdev));
2071		goto iospace_error_exit;
2072	}
2073	if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2074		ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2075		    "Invalid PCI mem region size (%s), aborting\n",
2076			pci_name(ha->pdev));
2077		goto iospace_error_exit;
2078	}
2079
2080	ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2081	if (!ha->iobase) {
2082		ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2083		    "Cannot remap MMIO (%s), aborting.\n",
2084		    pci_name(ha->pdev));
2085		goto iospace_error_exit;
2086	}
2087
2088	/* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2089	/* 83XX 26XX always use MQ type access for queues
2090	 * - mbar 2, a.k.a region 4 */
2091	ha->max_req_queues = ha->max_rsp_queues = 1;
2092	ha->msix_count = QLA_BASE_VECTORS;
2093	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2094			pci_resource_len(ha->pdev, 4));
2095
2096	if (!ha->mqiobase) {
2097		ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2098		    "BAR2/region4 not enabled\n");
2099		goto mqiobase_exit;
2100	}
2101
2102	ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2103			pci_resource_len(ha->pdev, 2));
2104	if (ha->msixbase) {
2105		/* Read MSIX vector size of the board */
2106		pci_read_config_word(ha->pdev,
2107		    QLA_83XX_PCI_MSIX_CONTROL, &msix);
2108		ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE)  + 1;
2109		/*
2110		 * By default, driver uses at least two msix vectors
2111		 * (default & rspq)
2112		 */
2113		if (ql2xmqsupport || ql2xnvmeenable) {
2114			/* MB interrupt uses 1 vector */
2115			ha->max_req_queues = ha->msix_count - 1;
2116
2117			/* ATIOQ needs 1 vector. That's 1 less QPair */
2118			if (QLA_TGT_MODE_ENABLED())
2119				ha->max_req_queues--;
2120
2121			ha->max_rsp_queues = ha->max_req_queues;
2122
2123			/* Queue pairs is the max value minus
2124			 * the base queue pair */
2125			ha->max_qpairs = ha->max_req_queues - 1;
2126			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2127			    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2128		}
2129		ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2130		    "MSI-X vector count: %d.\n", ha->msix_count);
2131	} else
2132		ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2133		    "BAR 1 not enabled.\n");
2134
2135mqiobase_exit:
2136	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2137	    "MSIX Count: %d.\n", ha->msix_count);
2138	return 0;
2139
2140iospace_error_exit:
2141	return -ENOMEM;
2142}
2143
2144static struct isp_operations qla2100_isp_ops = {
2145	.pci_config		= qla2100_pci_config,
2146	.reset_chip		= qla2x00_reset_chip,
2147	.chip_diag		= qla2x00_chip_diag,
2148	.config_rings		= qla2x00_config_rings,
2149	.reset_adapter		= qla2x00_reset_adapter,
2150	.nvram_config		= qla2x00_nvram_config,
2151	.update_fw_options	= qla2x00_update_fw_options,
2152	.load_risc		= qla2x00_load_risc,
2153	.pci_info_str		= qla2x00_pci_info_str,
2154	.fw_version_str		= qla2x00_fw_version_str,
2155	.intr_handler		= qla2100_intr_handler,
2156	.enable_intrs		= qla2x00_enable_intrs,
2157	.disable_intrs		= qla2x00_disable_intrs,
2158	.abort_command		= qla2x00_abort_command,
2159	.target_reset		= qla2x00_abort_target,
2160	.lun_reset		= qla2x00_lun_reset,
2161	.fabric_login		= qla2x00_login_fabric,
2162	.fabric_logout		= qla2x00_fabric_logout,
2163	.calc_req_entries	= qla2x00_calc_iocbs_32,
2164	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2165	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2166	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2167	.read_nvram		= qla2x00_read_nvram_data,
2168	.write_nvram		= qla2x00_write_nvram_data,
2169	.fw_dump		= qla2100_fw_dump,
2170	.beacon_on		= NULL,
2171	.beacon_off		= NULL,
2172	.beacon_blink		= NULL,
2173	.read_optrom		= qla2x00_read_optrom_data,
2174	.write_optrom		= qla2x00_write_optrom_data,
2175	.get_flash_version	= qla2x00_get_flash_version,
2176	.start_scsi		= qla2x00_start_scsi,
2177	.start_scsi_mq          = NULL,
2178	.abort_isp		= qla2x00_abort_isp,
2179	.iospace_config     	= qla2x00_iospace_config,
2180	.initialize_adapter	= qla2x00_initialize_adapter,
2181};
2182
2183static struct isp_operations qla2300_isp_ops = {
2184	.pci_config		= qla2300_pci_config,
2185	.reset_chip		= qla2x00_reset_chip,
2186	.chip_diag		= qla2x00_chip_diag,
2187	.config_rings		= qla2x00_config_rings,
2188	.reset_adapter		= qla2x00_reset_adapter,
2189	.nvram_config		= qla2x00_nvram_config,
2190	.update_fw_options	= qla2x00_update_fw_options,
2191	.load_risc		= qla2x00_load_risc,
2192	.pci_info_str		= qla2x00_pci_info_str,
2193	.fw_version_str		= qla2x00_fw_version_str,
2194	.intr_handler		= qla2300_intr_handler,
2195	.enable_intrs		= qla2x00_enable_intrs,
2196	.disable_intrs		= qla2x00_disable_intrs,
2197	.abort_command		= qla2x00_abort_command,
2198	.target_reset		= qla2x00_abort_target,
2199	.lun_reset		= qla2x00_lun_reset,
2200	.fabric_login		= qla2x00_login_fabric,
2201	.fabric_logout		= qla2x00_fabric_logout,
2202	.calc_req_entries	= qla2x00_calc_iocbs_32,
2203	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2204	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2205	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2206	.read_nvram		= qla2x00_read_nvram_data,
2207	.write_nvram		= qla2x00_write_nvram_data,
2208	.fw_dump		= qla2300_fw_dump,
2209	.beacon_on		= qla2x00_beacon_on,
2210	.beacon_off		= qla2x00_beacon_off,
2211	.beacon_blink		= qla2x00_beacon_blink,
2212	.read_optrom		= qla2x00_read_optrom_data,
2213	.write_optrom		= qla2x00_write_optrom_data,
2214	.get_flash_version	= qla2x00_get_flash_version,
2215	.start_scsi		= qla2x00_start_scsi,
2216	.start_scsi_mq          = NULL,
2217	.abort_isp		= qla2x00_abort_isp,
2218	.iospace_config		= qla2x00_iospace_config,
2219	.initialize_adapter	= qla2x00_initialize_adapter,
2220};
2221
2222static struct isp_operations qla24xx_isp_ops = {
2223	.pci_config		= qla24xx_pci_config,
2224	.reset_chip		= qla24xx_reset_chip,
2225	.chip_diag		= qla24xx_chip_diag,
2226	.config_rings		= qla24xx_config_rings,
2227	.reset_adapter		= qla24xx_reset_adapter,
2228	.nvram_config		= qla24xx_nvram_config,
2229	.update_fw_options	= qla24xx_update_fw_options,
2230	.load_risc		= qla24xx_load_risc,
2231	.pci_info_str		= qla24xx_pci_info_str,
2232	.fw_version_str		= qla24xx_fw_version_str,
2233	.intr_handler		= qla24xx_intr_handler,
2234	.enable_intrs		= qla24xx_enable_intrs,
2235	.disable_intrs		= qla24xx_disable_intrs,
2236	.abort_command		= qla24xx_abort_command,
2237	.target_reset		= qla24xx_abort_target,
2238	.lun_reset		= qla24xx_lun_reset,
2239	.fabric_login		= qla24xx_login_fabric,
2240	.fabric_logout		= qla24xx_fabric_logout,
2241	.calc_req_entries	= NULL,
2242	.build_iocbs		= NULL,
2243	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2244	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2245	.read_nvram		= qla24xx_read_nvram_data,
2246	.write_nvram		= qla24xx_write_nvram_data,
2247	.fw_dump		= qla24xx_fw_dump,
2248	.beacon_on		= qla24xx_beacon_on,
2249	.beacon_off		= qla24xx_beacon_off,
2250	.beacon_blink		= qla24xx_beacon_blink,
2251	.read_optrom		= qla24xx_read_optrom_data,
2252	.write_optrom		= qla24xx_write_optrom_data,
2253	.get_flash_version	= qla24xx_get_flash_version,
2254	.start_scsi		= qla24xx_start_scsi,
2255	.start_scsi_mq          = NULL,
2256	.abort_isp		= qla2x00_abort_isp,
2257	.iospace_config		= qla2x00_iospace_config,
2258	.initialize_adapter	= qla2x00_initialize_adapter,
2259};
2260
2261static struct isp_operations qla25xx_isp_ops = {
2262	.pci_config		= qla25xx_pci_config,
2263	.reset_chip		= qla24xx_reset_chip,
2264	.chip_diag		= qla24xx_chip_diag,
2265	.config_rings		= qla24xx_config_rings,
2266	.reset_adapter		= qla24xx_reset_adapter,
2267	.nvram_config		= qla24xx_nvram_config,
2268	.update_fw_options	= qla24xx_update_fw_options,
2269	.load_risc		= qla24xx_load_risc,
2270	.pci_info_str		= qla24xx_pci_info_str,
2271	.fw_version_str		= qla24xx_fw_version_str,
2272	.intr_handler		= qla24xx_intr_handler,
2273	.enable_intrs		= qla24xx_enable_intrs,
2274	.disable_intrs		= qla24xx_disable_intrs,
2275	.abort_command		= qla24xx_abort_command,
2276	.target_reset		= qla24xx_abort_target,
2277	.lun_reset		= qla24xx_lun_reset,
2278	.fabric_login		= qla24xx_login_fabric,
2279	.fabric_logout		= qla24xx_fabric_logout,
2280	.calc_req_entries	= NULL,
2281	.build_iocbs		= NULL,
2282	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2283	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2284	.read_nvram		= qla25xx_read_nvram_data,
2285	.write_nvram		= qla25xx_write_nvram_data,
2286	.fw_dump		= qla25xx_fw_dump,
2287	.beacon_on		= qla24xx_beacon_on,
2288	.beacon_off		= qla24xx_beacon_off,
2289	.beacon_blink		= qla24xx_beacon_blink,
2290	.read_optrom		= qla25xx_read_optrom_data,
2291	.write_optrom		= qla24xx_write_optrom_data,
2292	.get_flash_version	= qla24xx_get_flash_version,
2293	.start_scsi		= qla24xx_dif_start_scsi,
2294	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2295	.abort_isp		= qla2x00_abort_isp,
2296	.iospace_config		= qla2x00_iospace_config,
2297	.initialize_adapter	= qla2x00_initialize_adapter,
2298};
2299
2300static struct isp_operations qla81xx_isp_ops = {
2301	.pci_config		= qla25xx_pci_config,
2302	.reset_chip		= qla24xx_reset_chip,
2303	.chip_diag		= qla24xx_chip_diag,
2304	.config_rings		= qla24xx_config_rings,
2305	.reset_adapter		= qla24xx_reset_adapter,
2306	.nvram_config		= qla81xx_nvram_config,
2307	.update_fw_options	= qla24xx_update_fw_options,
2308	.load_risc		= qla81xx_load_risc,
2309	.pci_info_str		= qla24xx_pci_info_str,
2310	.fw_version_str		= qla24xx_fw_version_str,
2311	.intr_handler		= qla24xx_intr_handler,
2312	.enable_intrs		= qla24xx_enable_intrs,
2313	.disable_intrs		= qla24xx_disable_intrs,
2314	.abort_command		= qla24xx_abort_command,
2315	.target_reset		= qla24xx_abort_target,
2316	.lun_reset		= qla24xx_lun_reset,
2317	.fabric_login		= qla24xx_login_fabric,
2318	.fabric_logout		= qla24xx_fabric_logout,
2319	.calc_req_entries	= NULL,
2320	.build_iocbs		= NULL,
2321	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2322	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2323	.read_nvram		= NULL,
2324	.write_nvram		= NULL,
2325	.fw_dump		= qla81xx_fw_dump,
2326	.beacon_on		= qla24xx_beacon_on,
2327	.beacon_off		= qla24xx_beacon_off,
2328	.beacon_blink		= qla83xx_beacon_blink,
2329	.read_optrom		= qla25xx_read_optrom_data,
2330	.write_optrom		= qla24xx_write_optrom_data,
2331	.get_flash_version	= qla24xx_get_flash_version,
2332	.start_scsi		= qla24xx_dif_start_scsi,
2333	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2334	.abort_isp		= qla2x00_abort_isp,
2335	.iospace_config		= qla2x00_iospace_config,
2336	.initialize_adapter	= qla2x00_initialize_adapter,
2337};
2338
2339static struct isp_operations qla82xx_isp_ops = {
2340	.pci_config		= qla82xx_pci_config,
2341	.reset_chip		= qla82xx_reset_chip,
2342	.chip_diag		= qla24xx_chip_diag,
2343	.config_rings		= qla82xx_config_rings,
2344	.reset_adapter		= qla24xx_reset_adapter,
2345	.nvram_config		= qla81xx_nvram_config,
2346	.update_fw_options	= qla24xx_update_fw_options,
2347	.load_risc		= qla82xx_load_risc,
2348	.pci_info_str		= qla24xx_pci_info_str,
2349	.fw_version_str		= qla24xx_fw_version_str,
2350	.intr_handler		= qla82xx_intr_handler,
2351	.enable_intrs		= qla82xx_enable_intrs,
2352	.disable_intrs		= qla82xx_disable_intrs,
2353	.abort_command		= qla24xx_abort_command,
2354	.target_reset		= qla24xx_abort_target,
2355	.lun_reset		= qla24xx_lun_reset,
2356	.fabric_login		= qla24xx_login_fabric,
2357	.fabric_logout		= qla24xx_fabric_logout,
2358	.calc_req_entries	= NULL,
2359	.build_iocbs		= NULL,
2360	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2361	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2362	.read_nvram		= qla24xx_read_nvram_data,
2363	.write_nvram		= qla24xx_write_nvram_data,
2364	.fw_dump		= qla82xx_fw_dump,
2365	.beacon_on		= qla82xx_beacon_on,
2366	.beacon_off		= qla82xx_beacon_off,
2367	.beacon_blink		= NULL,
2368	.read_optrom		= qla82xx_read_optrom_data,
2369	.write_optrom		= qla82xx_write_optrom_data,
2370	.get_flash_version	= qla82xx_get_flash_version,
2371	.start_scsi             = qla82xx_start_scsi,
2372	.start_scsi_mq          = NULL,
2373	.abort_isp		= qla82xx_abort_isp,
2374	.iospace_config     	= qla82xx_iospace_config,
2375	.initialize_adapter	= qla2x00_initialize_adapter,
2376};
2377
2378static struct isp_operations qla8044_isp_ops = {
2379	.pci_config		= qla82xx_pci_config,
2380	.reset_chip		= qla82xx_reset_chip,
2381	.chip_diag		= qla24xx_chip_diag,
2382	.config_rings		= qla82xx_config_rings,
2383	.reset_adapter		= qla24xx_reset_adapter,
2384	.nvram_config		= qla81xx_nvram_config,
2385	.update_fw_options	= qla24xx_update_fw_options,
2386	.load_risc		= qla82xx_load_risc,
2387	.pci_info_str		= qla24xx_pci_info_str,
2388	.fw_version_str		= qla24xx_fw_version_str,
2389	.intr_handler		= qla8044_intr_handler,
2390	.enable_intrs		= qla82xx_enable_intrs,
2391	.disable_intrs		= qla82xx_disable_intrs,
2392	.abort_command		= qla24xx_abort_command,
2393	.target_reset		= qla24xx_abort_target,
2394	.lun_reset		= qla24xx_lun_reset,
2395	.fabric_login		= qla24xx_login_fabric,
2396	.fabric_logout		= qla24xx_fabric_logout,
2397	.calc_req_entries	= NULL,
2398	.build_iocbs		= NULL,
2399	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2400	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2401	.read_nvram		= NULL,
2402	.write_nvram		= NULL,
2403	.fw_dump		= qla8044_fw_dump,
2404	.beacon_on		= qla82xx_beacon_on,
2405	.beacon_off		= qla82xx_beacon_off,
2406	.beacon_blink		= NULL,
2407	.read_optrom		= qla8044_read_optrom_data,
2408	.write_optrom		= qla8044_write_optrom_data,
2409	.get_flash_version	= qla82xx_get_flash_version,
2410	.start_scsi             = qla82xx_start_scsi,
2411	.start_scsi_mq          = NULL,
2412	.abort_isp		= qla8044_abort_isp,
2413	.iospace_config		= qla82xx_iospace_config,
2414	.initialize_adapter	= qla2x00_initialize_adapter,
2415};
2416
2417static struct isp_operations qla83xx_isp_ops = {
2418	.pci_config		= qla25xx_pci_config,
2419	.reset_chip		= qla24xx_reset_chip,
2420	.chip_diag		= qla24xx_chip_diag,
2421	.config_rings		= qla24xx_config_rings,
2422	.reset_adapter		= qla24xx_reset_adapter,
2423	.nvram_config		= qla81xx_nvram_config,
2424	.update_fw_options	= qla24xx_update_fw_options,
2425	.load_risc		= qla81xx_load_risc,
2426	.pci_info_str		= qla24xx_pci_info_str,
2427	.fw_version_str		= qla24xx_fw_version_str,
2428	.intr_handler		= qla24xx_intr_handler,
2429	.enable_intrs		= qla24xx_enable_intrs,
2430	.disable_intrs		= qla24xx_disable_intrs,
2431	.abort_command		= qla24xx_abort_command,
2432	.target_reset		= qla24xx_abort_target,
2433	.lun_reset		= qla24xx_lun_reset,
2434	.fabric_login		= qla24xx_login_fabric,
2435	.fabric_logout		= qla24xx_fabric_logout,
2436	.calc_req_entries	= NULL,
2437	.build_iocbs		= NULL,
2438	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2439	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2440	.read_nvram		= NULL,
2441	.write_nvram		= NULL,
2442	.fw_dump		= qla83xx_fw_dump,
2443	.beacon_on		= qla24xx_beacon_on,
2444	.beacon_off		= qla24xx_beacon_off,
2445	.beacon_blink		= qla83xx_beacon_blink,
2446	.read_optrom		= qla25xx_read_optrom_data,
2447	.write_optrom		= qla24xx_write_optrom_data,
2448	.get_flash_version	= qla24xx_get_flash_version,
2449	.start_scsi		= qla24xx_dif_start_scsi,
2450	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2451	.abort_isp		= qla2x00_abort_isp,
2452	.iospace_config		= qla83xx_iospace_config,
2453	.initialize_adapter	= qla2x00_initialize_adapter,
2454};
2455
2456static struct isp_operations qlafx00_isp_ops = {
2457	.pci_config		= qlafx00_pci_config,
2458	.reset_chip		= qlafx00_soft_reset,
2459	.chip_diag		= qlafx00_chip_diag,
2460	.config_rings		= qlafx00_config_rings,
2461	.reset_adapter		= qlafx00_soft_reset,
2462	.nvram_config		= NULL,
2463	.update_fw_options	= NULL,
2464	.load_risc		= NULL,
2465	.pci_info_str		= qlafx00_pci_info_str,
2466	.fw_version_str		= qlafx00_fw_version_str,
2467	.intr_handler		= qlafx00_intr_handler,
2468	.enable_intrs		= qlafx00_enable_intrs,
2469	.disable_intrs		= qlafx00_disable_intrs,
2470	.abort_command		= qla24xx_async_abort_command,
2471	.target_reset		= qlafx00_abort_target,
2472	.lun_reset		= qlafx00_lun_reset,
2473	.fabric_login		= NULL,
2474	.fabric_logout		= NULL,
2475	.calc_req_entries	= NULL,
2476	.build_iocbs		= NULL,
2477	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2478	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2479	.read_nvram		= qla24xx_read_nvram_data,
2480	.write_nvram		= qla24xx_write_nvram_data,
2481	.fw_dump		= NULL,
2482	.beacon_on		= qla24xx_beacon_on,
2483	.beacon_off		= qla24xx_beacon_off,
2484	.beacon_blink		= NULL,
2485	.read_optrom		= qla24xx_read_optrom_data,
2486	.write_optrom		= qla24xx_write_optrom_data,
2487	.get_flash_version	= qla24xx_get_flash_version,
2488	.start_scsi		= qlafx00_start_scsi,
2489	.start_scsi_mq          = NULL,
2490	.abort_isp		= qlafx00_abort_isp,
2491	.iospace_config		= qlafx00_iospace_config,
2492	.initialize_adapter	= qlafx00_initialize_adapter,
2493};
2494
2495static struct isp_operations qla27xx_isp_ops = {
2496	.pci_config		= qla25xx_pci_config,
2497	.reset_chip		= qla24xx_reset_chip,
2498	.chip_diag		= qla24xx_chip_diag,
2499	.config_rings		= qla24xx_config_rings,
2500	.reset_adapter		= qla24xx_reset_adapter,
2501	.nvram_config		= qla81xx_nvram_config,
2502	.update_fw_options	= qla24xx_update_fw_options,
2503	.load_risc		= qla81xx_load_risc,
2504	.pci_info_str		= qla24xx_pci_info_str,
2505	.fw_version_str		= qla24xx_fw_version_str,
2506	.intr_handler		= qla24xx_intr_handler,
2507	.enable_intrs		= qla24xx_enable_intrs,
2508	.disable_intrs		= qla24xx_disable_intrs,
2509	.abort_command		= qla24xx_abort_command,
2510	.target_reset		= qla24xx_abort_target,
2511	.lun_reset		= qla24xx_lun_reset,
2512	.fabric_login		= qla24xx_login_fabric,
2513	.fabric_logout		= qla24xx_fabric_logout,
2514	.calc_req_entries	= NULL,
2515	.build_iocbs		= NULL,
2516	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2517	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2518	.read_nvram		= NULL,
2519	.write_nvram		= NULL,
2520	.fw_dump		= qla27xx_fwdump,
2521	.beacon_on		= qla24xx_beacon_on,
2522	.beacon_off		= qla24xx_beacon_off,
2523	.beacon_blink		= qla83xx_beacon_blink,
2524	.read_optrom		= qla25xx_read_optrom_data,
2525	.write_optrom		= qla24xx_write_optrom_data,
2526	.get_flash_version	= qla24xx_get_flash_version,
2527	.start_scsi		= qla24xx_dif_start_scsi,
2528	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2529	.abort_isp		= qla2x00_abort_isp,
2530	.iospace_config		= qla83xx_iospace_config,
2531	.initialize_adapter	= qla2x00_initialize_adapter,
2532};
2533
2534static inline void
2535qla2x00_set_isp_flags(struct qla_hw_data *ha)
2536{
2537	ha->device_type = DT_EXTENDED_IDS;
2538	switch (ha->pdev->device) {
2539	case PCI_DEVICE_ID_QLOGIC_ISP2100:
2540		ha->isp_type |= DT_ISP2100;
2541		ha->device_type &= ~DT_EXTENDED_IDS;
2542		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2543		break;
2544	case PCI_DEVICE_ID_QLOGIC_ISP2200:
2545		ha->isp_type |= DT_ISP2200;
2546		ha->device_type &= ~DT_EXTENDED_IDS;
2547		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2548		break;
2549	case PCI_DEVICE_ID_QLOGIC_ISP2300:
2550		ha->isp_type |= DT_ISP2300;
2551		ha->device_type |= DT_ZIO_SUPPORTED;
2552		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2553		break;
2554	case PCI_DEVICE_ID_QLOGIC_ISP2312:
2555		ha->isp_type |= DT_ISP2312;
2556		ha->device_type |= DT_ZIO_SUPPORTED;
2557		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2558		break;
2559	case PCI_DEVICE_ID_QLOGIC_ISP2322:
2560		ha->isp_type |= DT_ISP2322;
2561		ha->device_type |= DT_ZIO_SUPPORTED;
2562		if (ha->pdev->subsystem_vendor == 0x1028 &&
2563		    ha->pdev->subsystem_device == 0x0170)
2564			ha->device_type |= DT_OEM_001;
2565		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2566		break;
2567	case PCI_DEVICE_ID_QLOGIC_ISP6312:
2568		ha->isp_type |= DT_ISP6312;
2569		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2570		break;
2571	case PCI_DEVICE_ID_QLOGIC_ISP6322:
2572		ha->isp_type |= DT_ISP6322;
2573		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2574		break;
2575	case PCI_DEVICE_ID_QLOGIC_ISP2422:
2576		ha->isp_type |= DT_ISP2422;
2577		ha->device_type |= DT_ZIO_SUPPORTED;
2578		ha->device_type |= DT_FWI2;
2579		ha->device_type |= DT_IIDMA;
2580		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2581		break;
2582	case PCI_DEVICE_ID_QLOGIC_ISP2432:
2583		ha->isp_type |= DT_ISP2432;
2584		ha->device_type |= DT_ZIO_SUPPORTED;
2585		ha->device_type |= DT_FWI2;
2586		ha->device_type |= DT_IIDMA;
2587		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2588		break;
2589	case PCI_DEVICE_ID_QLOGIC_ISP8432:
2590		ha->isp_type |= DT_ISP8432;
2591		ha->device_type |= DT_ZIO_SUPPORTED;
2592		ha->device_type |= DT_FWI2;
2593		ha->device_type |= DT_IIDMA;
2594		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2595		break;
2596	case PCI_DEVICE_ID_QLOGIC_ISP5422:
2597		ha->isp_type |= DT_ISP5422;
2598		ha->device_type |= DT_FWI2;
2599		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2600		break;
2601	case PCI_DEVICE_ID_QLOGIC_ISP5432:
2602		ha->isp_type |= DT_ISP5432;
2603		ha->device_type |= DT_FWI2;
2604		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2605		break;
2606	case PCI_DEVICE_ID_QLOGIC_ISP2532:
2607		ha->isp_type |= DT_ISP2532;
2608		ha->device_type |= DT_ZIO_SUPPORTED;
2609		ha->device_type |= DT_FWI2;
2610		ha->device_type |= DT_IIDMA;
2611		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2612		break;
2613	case PCI_DEVICE_ID_QLOGIC_ISP8001:
2614		ha->isp_type |= DT_ISP8001;
2615		ha->device_type |= DT_ZIO_SUPPORTED;
2616		ha->device_type |= DT_FWI2;
2617		ha->device_type |= DT_IIDMA;
2618		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2619		break;
2620	case PCI_DEVICE_ID_QLOGIC_ISP8021:
2621		ha->isp_type |= DT_ISP8021;
2622		ha->device_type |= DT_ZIO_SUPPORTED;
2623		ha->device_type |= DT_FWI2;
2624		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2625		/* Initialize 82XX ISP flags */
2626		qla82xx_init_flags(ha);
2627		break;
2628	 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2629		ha->isp_type |= DT_ISP8044;
2630		ha->device_type |= DT_ZIO_SUPPORTED;
2631		ha->device_type |= DT_FWI2;
2632		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2633		/* Initialize 82XX ISP flags */
2634		qla82xx_init_flags(ha);
2635		break;
2636	case PCI_DEVICE_ID_QLOGIC_ISP2031:
2637		ha->isp_type |= DT_ISP2031;
2638		ha->device_type |= DT_ZIO_SUPPORTED;
2639		ha->device_type |= DT_FWI2;
2640		ha->device_type |= DT_IIDMA;
2641		ha->device_type |= DT_T10_PI;
2642		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2643		break;
2644	case PCI_DEVICE_ID_QLOGIC_ISP8031:
2645		ha->isp_type |= DT_ISP8031;
2646		ha->device_type |= DT_ZIO_SUPPORTED;
2647		ha->device_type |= DT_FWI2;
2648		ha->device_type |= DT_IIDMA;
2649		ha->device_type |= DT_T10_PI;
2650		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2651		break;
2652	case PCI_DEVICE_ID_QLOGIC_ISPF001:
2653		ha->isp_type |= DT_ISPFX00;
2654		break;
2655	case PCI_DEVICE_ID_QLOGIC_ISP2071:
2656		ha->isp_type |= DT_ISP2071;
2657		ha->device_type |= DT_ZIO_SUPPORTED;
2658		ha->device_type |= DT_FWI2;
2659		ha->device_type |= DT_IIDMA;
2660		ha->device_type |= DT_T10_PI;
2661		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2662		break;
2663	case PCI_DEVICE_ID_QLOGIC_ISP2271:
2664		ha->isp_type |= DT_ISP2271;
2665		ha->device_type |= DT_ZIO_SUPPORTED;
2666		ha->device_type |= DT_FWI2;
2667		ha->device_type |= DT_IIDMA;
2668		ha->device_type |= DT_T10_PI;
2669		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2670		break;
2671	case PCI_DEVICE_ID_QLOGIC_ISP2261:
2672		ha->isp_type |= DT_ISP2261;
2673		ha->device_type |= DT_ZIO_SUPPORTED;
2674		ha->device_type |= DT_FWI2;
2675		ha->device_type |= DT_IIDMA;
2676		ha->device_type |= DT_T10_PI;
2677		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2678		break;
2679	case PCI_DEVICE_ID_QLOGIC_ISP2081:
2680	case PCI_DEVICE_ID_QLOGIC_ISP2089:
2681		ha->isp_type |= DT_ISP2081;
2682		ha->device_type |= DT_ZIO_SUPPORTED;
2683		ha->device_type |= DT_FWI2;
2684		ha->device_type |= DT_IIDMA;
2685		ha->device_type |= DT_T10_PI;
2686		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2687		break;
2688	case PCI_DEVICE_ID_QLOGIC_ISP2281:
2689	case PCI_DEVICE_ID_QLOGIC_ISP2289:
2690		ha->isp_type |= DT_ISP2281;
2691		ha->device_type |= DT_ZIO_SUPPORTED;
2692		ha->device_type |= DT_FWI2;
2693		ha->device_type |= DT_IIDMA;
2694		ha->device_type |= DT_T10_PI;
2695		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2696		break;
2697	}
2698
2699	if (IS_QLA82XX(ha))
2700		ha->port_no = ha->portnum & 1;
2701	else {
2702		/* Get adapter physical port no from interrupt pin register. */
2703		pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2704		if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2705		    IS_QLA27XX(ha) || IS_QLA28XX(ha))
2706			ha->port_no--;
2707		else
2708			ha->port_no = !(ha->port_no & 1);
2709	}
2710
2711	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2712	    "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2713	    ha->device_type, ha->port_no, ha->fw_srisc_address);
2714}
2715
2716static void
2717qla2xxx_scan_start(struct Scsi_Host *shost)
2718{
2719	scsi_qla_host_t *vha = shost_priv(shost);
2720
2721	if (vha->hw->flags.running_gold_fw)
2722		return;
2723
2724	set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2725	set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2726	set_bit(RSCN_UPDATE, &vha->dpc_flags);
2727	set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2728}
2729
2730static int
2731qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2732{
2733	scsi_qla_host_t *vha = shost_priv(shost);
2734
2735	if (test_bit(UNLOADING, &vha->dpc_flags))
2736		return 1;
2737	if (!vha->host)
2738		return 1;
2739	if (time > vha->hw->loop_reset_delay * HZ)
2740		return 1;
2741
2742	return atomic_read(&vha->loop_state) == LOOP_READY;
2743}
2744
2745static void qla2x00_iocb_work_fn(struct work_struct *work)
2746{
2747	struct scsi_qla_host *vha = container_of(work,
2748		struct scsi_qla_host, iocb_work);
2749	struct qla_hw_data *ha = vha->hw;
2750	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2751	int i = 2;
2752	unsigned long flags;
2753
2754	if (test_bit(UNLOADING, &base_vha->dpc_flags))
2755		return;
2756
2757	while (!list_empty(&vha->work_list) && i > 0) {
2758		qla2x00_do_work(vha);
2759		i--;
2760	}
2761
2762	spin_lock_irqsave(&vha->work_lock, flags);
2763	clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2764	spin_unlock_irqrestore(&vha->work_lock, flags);
2765}
2766
2767/*
2768 * PCI driver interface
2769 */
2770static int
2771qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2772{
2773	int	ret = -ENODEV;
2774	struct Scsi_Host *host;
2775	scsi_qla_host_t *base_vha = NULL;
2776	struct qla_hw_data *ha;
2777	char pci_info[30];
2778	char fw_str[30], wq_name[30];
2779	struct scsi_host_template *sht;
2780	int bars, mem_only = 0;
2781	uint16_t req_length = 0, rsp_length = 0;
2782	struct req_que *req = NULL;
2783	struct rsp_que *rsp = NULL;
2784	int i;
2785
2786	bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2787	sht = &qla2xxx_driver_template;
2788	if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2789	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2790	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2791	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2792	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2793	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2794	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2795	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2796	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2797	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2798	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2799	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2800	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2801	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2802	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2803	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2804	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2805	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2806	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2807		bars = pci_select_bars(pdev, IORESOURCE_MEM);
2808		mem_only = 1;
2809		ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2810		    "Mem only adapter.\n");
2811	}
2812	ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2813	    "Bars=%d.\n", bars);
2814
2815	if (mem_only) {
2816		if (pci_enable_device_mem(pdev))
2817			return ret;
2818	} else {
2819		if (pci_enable_device(pdev))
2820			return ret;
2821	}
2822
2823	/* This may fail but that's ok */
2824	pci_enable_pcie_error_reporting(pdev);
2825
2826	/* Turn off T10-DIF when FC-NVMe is enabled */
2827	if (ql2xnvmeenable)
2828		ql2xenabledif = 0;
2829
2830	ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2831	if (!ha) {
2832		ql_log_pci(ql_log_fatal, pdev, 0x0009,
2833		    "Unable to allocate memory for ha.\n");
2834		goto disable_device;
2835	}
2836	ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2837	    "Memory allocated for ha=%p.\n", ha);
2838	ha->pdev = pdev;
2839	INIT_LIST_HEAD(&ha->tgt.q_full_list);
2840	spin_lock_init(&ha->tgt.q_full_lock);
2841	spin_lock_init(&ha->tgt.sess_lock);
2842	spin_lock_init(&ha->tgt.atio_lock);
2843
2844	atomic_set(&ha->nvme_active_aen_cnt, 0);
2845
2846	/* Clear our data area */
2847	ha->bars = bars;
2848	ha->mem_only = mem_only;
2849	spin_lock_init(&ha->hardware_lock);
2850	spin_lock_init(&ha->vport_slock);
2851	mutex_init(&ha->selflogin_lock);
2852	mutex_init(&ha->optrom_mutex);
2853
2854	/* Set ISP-type information. */
2855	qla2x00_set_isp_flags(ha);
2856
2857	/* Set EEH reset type to fundamental if required by hba */
2858	if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2859	    IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
2860		pdev->needs_freset = 1;
2861
2862	ha->prev_topology = 0;
2863	ha->init_cb_size = sizeof(init_cb_t);
2864	ha->link_data_rate = PORT_SPEED_UNKNOWN;
2865	ha->optrom_size = OPTROM_SIZE_2300;
2866	ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2867	atomic_set(&ha->num_pend_mbx_stage1, 0);
2868	atomic_set(&ha->num_pend_mbx_stage2, 0);
2869	atomic_set(&ha->num_pend_mbx_stage3, 0);
2870	atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2871	ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2872
2873	/* Assign ISP specific operations. */
2874	if (IS_QLA2100(ha)) {
2875		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2876		ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2877		req_length = REQUEST_ENTRY_CNT_2100;
2878		rsp_length = RESPONSE_ENTRY_CNT_2100;
2879		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2880		ha->gid_list_info_size = 4;
2881		ha->flash_conf_off = ~0;
2882		ha->flash_data_off = ~0;
2883		ha->nvram_conf_off = ~0;
2884		ha->nvram_data_off = ~0;
2885		ha->isp_ops = &qla2100_isp_ops;
2886	} else if (IS_QLA2200(ha)) {
2887		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2888		ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2889		req_length = REQUEST_ENTRY_CNT_2200;
2890		rsp_length = RESPONSE_ENTRY_CNT_2100;
2891		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2892		ha->gid_list_info_size = 4;
2893		ha->flash_conf_off = ~0;
2894		ha->flash_data_off = ~0;
2895		ha->nvram_conf_off = ~0;
2896		ha->nvram_data_off = ~0;
2897		ha->isp_ops = &qla2100_isp_ops;
2898	} else if (IS_QLA23XX(ha)) {
2899		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2900		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2901		req_length = REQUEST_ENTRY_CNT_2200;
2902		rsp_length = RESPONSE_ENTRY_CNT_2300;
2903		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2904		ha->gid_list_info_size = 6;
2905		if (IS_QLA2322(ha) || IS_QLA6322(ha))
2906			ha->optrom_size = OPTROM_SIZE_2322;
2907		ha->flash_conf_off = ~0;
2908		ha->flash_data_off = ~0;
2909		ha->nvram_conf_off = ~0;
2910		ha->nvram_data_off = ~0;
2911		ha->isp_ops = &qla2300_isp_ops;
2912	} else if (IS_QLA24XX_TYPE(ha)) {
2913		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2914		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2915		req_length = REQUEST_ENTRY_CNT_24XX;
2916		rsp_length = RESPONSE_ENTRY_CNT_2300;
2917		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2918		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2919		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2920		ha->gid_list_info_size = 8;
2921		ha->optrom_size = OPTROM_SIZE_24XX;
2922		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2923		ha->isp_ops = &qla24xx_isp_ops;
2924		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2925		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2926		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2927		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2928	} else if (IS_QLA25XX(ha)) {
2929		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2930		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2931		req_length = REQUEST_ENTRY_CNT_24XX;
2932		rsp_length = RESPONSE_ENTRY_CNT_2300;
2933		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2934		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2935		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2936		ha->gid_list_info_size = 8;
2937		ha->optrom_size = OPTROM_SIZE_25XX;
2938		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2939		ha->isp_ops = &qla25xx_isp_ops;
2940		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2941		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2942		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2943		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2944	} else if (IS_QLA81XX(ha)) {
2945		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2946		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2947		req_length = REQUEST_ENTRY_CNT_24XX;
2948		rsp_length = RESPONSE_ENTRY_CNT_2300;
2949		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2950		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2951		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2952		ha->gid_list_info_size = 8;
2953		ha->optrom_size = OPTROM_SIZE_81XX;
2954		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2955		ha->isp_ops = &qla81xx_isp_ops;
2956		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2957		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2958		ha->nvram_conf_off = ~0;
2959		ha->nvram_data_off = ~0;
2960	} else if (IS_QLA82XX(ha)) {
2961		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2962		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2963		req_length = REQUEST_ENTRY_CNT_82XX;
2964		rsp_length = RESPONSE_ENTRY_CNT_82XX;
2965		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2966		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2967		ha->gid_list_info_size = 8;
2968		ha->optrom_size = OPTROM_SIZE_82XX;
2969		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2970		ha->isp_ops = &qla82xx_isp_ops;
2971		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2972		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2973		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2974		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2975	} else if (IS_QLA8044(ha)) {
2976		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2977		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2978		req_length = REQUEST_ENTRY_CNT_82XX;
2979		rsp_length = RESPONSE_ENTRY_CNT_82XX;
2980		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2981		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2982		ha->gid_list_info_size = 8;
2983		ha->optrom_size = OPTROM_SIZE_83XX;
2984		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2985		ha->isp_ops = &qla8044_isp_ops;
2986		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2987		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2988		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2989		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2990	} else if (IS_QLA83XX(ha)) {
2991		ha->portnum = PCI_FUNC(ha->pdev->devfn);
2992		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2993		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2994		req_length = REQUEST_ENTRY_CNT_83XX;
2995		rsp_length = RESPONSE_ENTRY_CNT_83XX;
2996		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2997		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2998		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2999		ha->gid_list_info_size = 8;
3000		ha->optrom_size = OPTROM_SIZE_83XX;
3001		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3002		ha->isp_ops = &qla83xx_isp_ops;
3003		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3004		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3005		ha->nvram_conf_off = ~0;
3006		ha->nvram_data_off = ~0;
3007	}  else if (IS_QLAFX00(ha)) {
3008		ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3009		ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3010		ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3011		req_length = REQUEST_ENTRY_CNT_FX00;
3012		rsp_length = RESPONSE_ENTRY_CNT_FX00;
3013		ha->isp_ops = &qlafx00_isp_ops;
3014		ha->port_down_retry_count = 30; /* default value */
3015		ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3016		ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3017		ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3018		ha->mr.fw_hbt_en = 1;
3019		ha->mr.host_info_resend = false;
3020		ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3021	} else if (IS_QLA27XX(ha)) {
3022		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3023		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3024		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3025		req_length = REQUEST_ENTRY_CNT_83XX;
3026		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3027		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3028		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3029		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3030		ha->gid_list_info_size = 8;
3031		ha->optrom_size = OPTROM_SIZE_83XX;
3032		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3033		ha->isp_ops = &qla27xx_isp_ops;
3034		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3035		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3036		ha->nvram_conf_off = ~0;
3037		ha->nvram_data_off = ~0;
3038	} else if (IS_QLA28XX(ha)) {
3039		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3040		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3041		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3042		req_length = REQUEST_ENTRY_CNT_24XX;
3043		rsp_length = RESPONSE_ENTRY_CNT_2300;
3044		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3045		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3046		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3047		ha->gid_list_info_size = 8;
3048		ha->optrom_size = OPTROM_SIZE_28XX;
3049		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3050		ha->isp_ops = &qla27xx_isp_ops;
3051		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3052		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3053		ha->nvram_conf_off = ~0;
3054		ha->nvram_data_off = ~0;
3055	}
3056
3057	ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3058	    "mbx_count=%d, req_length=%d, "
3059	    "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3060	    "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3061	    "max_fibre_devices=%d.\n",
3062	    ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3063	    ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3064	    ha->nvram_npiv_size, ha->max_fibre_devices);
3065	ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3066	    "isp_ops=%p, flash_conf_off=%d, "
3067	    "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3068	    ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3069	    ha->nvram_conf_off, ha->nvram_data_off);
3070
3071	/* Configure PCI I/O space */
3072	ret = ha->isp_ops->iospace_config(ha);
3073	if (ret)
3074		goto iospace_config_failed;
3075
3076	ql_log_pci(ql_log_info, pdev, 0x001d,
3077	    "Found an ISP%04X irq %d iobase 0x%p.\n",
3078	    pdev->device, pdev->irq, ha->iobase);
3079	mutex_init(&ha->vport_lock);
3080	mutex_init(&ha->mq_lock);
3081	init_completion(&ha->mbx_cmd_comp);
3082	complete(&ha->mbx_cmd_comp);
3083	init_completion(&ha->mbx_intr_comp);
3084	init_completion(&ha->dcbx_comp);
3085	init_completion(&ha->lb_portup_comp);
3086
3087	set_bit(0, (unsigned long *) ha->vp_idx_map);
3088
3089	qla2x00_config_dma_addressing(ha);
3090	ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3091	    "64 Bit addressing is %s.\n",
3092	    ha->flags.enable_64bit_addressing ? "enable" :
3093	    "disable");
3094	ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3095	if (ret) {
3096		ql_log_pci(ql_log_fatal, pdev, 0x0031,
3097		    "Failed to allocate memory for adapter, aborting.\n");
3098
3099		goto probe_hw_failed;
3100	}
3101
3102	req->max_q_depth = MAX_Q_DEPTH;
3103	if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3104		req->max_q_depth = ql2xmaxqdepth;
3105
3106
3107	base_vha = qla2x00_create_host(sht, ha);
3108	if (!base_vha) {
3109		ret = -ENOMEM;
3110		goto probe_hw_failed;
3111	}
3112
3113	pci_set_drvdata(pdev, base_vha);
3114	set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3115
3116	host = base_vha->host;
3117	base_vha->req = req;
3118	if (IS_QLA2XXX_MIDTYPE(ha))
3119		base_vha->mgmt_svr_loop_id =
3120			qla2x00_reserve_mgmt_server_loop_id(base_vha);
3121	else
3122		base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3123						base_vha->vp_idx;
3124
3125	/* Setup fcport template structure. */
3126	ha->mr.fcport.vha = base_vha;
3127	ha->mr.fcport.port_type = FCT_UNKNOWN;
3128	ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3129	qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3130	ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3131	ha->mr.fcport.scan_state = 1;
3132
3133	/* Set the SG table size based on ISP type */
3134	if (!IS_FWI2_CAPABLE(ha)) {
3135		if (IS_QLA2100(ha))
3136			host->sg_tablesize = 32;
3137	} else {
3138		if (!IS_QLA82XX(ha))
3139			host->sg_tablesize = QLA_SG_ALL;
3140	}
3141	host->max_id = ha->max_fibre_devices;
3142	host->cmd_per_lun = 3;
3143	host->unique_id = host->host_no;
3144	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3145		host->max_cmd_len = 32;
3146	else
3147		host->max_cmd_len = MAX_CMDSZ;
3148	host->max_channel = MAX_BUSES - 1;
3149	/* Older HBAs support only 16-bit LUNs */
3150	if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3151	    ql2xmaxlun > 0xffff)
3152		host->max_lun = 0xffff;
3153	else
3154		host->max_lun = ql2xmaxlun;
3155	host->transportt = qla2xxx_transport_template;
3156	sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3157
3158	ql_dbg(ql_dbg_init, base_vha, 0x0033,
3159	    "max_id=%d this_id=%d "
3160	    "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3161	    "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3162	    host->this_id, host->cmd_per_lun, host->unique_id,
3163	    host->max_cmd_len, host->max_channel, host->max_lun,
3164	    host->transportt, sht->vendor_id);
3165
3166	INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3167
3168	/* Set up the irqs */
3169	ret = qla2x00_request_irqs(ha, rsp);
3170	if (ret)
3171		goto probe_failed;
3172
3173	/* Alloc arrays of request and response ring ptrs */
3174	ret = qla2x00_alloc_queues(ha, req, rsp);
3175	if (ret) {
3176		ql_log(ql_log_fatal, base_vha, 0x003d,
3177		    "Failed to allocate memory for queue pointers..."
3178		    "aborting.\n");
3179		ret = -ENODEV;
3180		goto probe_failed;
3181	}
3182
3183	if (ha->mqenable) {
3184		/* number of hardware queues supported by blk/scsi-mq*/
3185		host->nr_hw_queues = ha->max_qpairs;
3186
3187		ql_dbg(ql_dbg_init, base_vha, 0x0192,
3188			"blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3189	} else {
3190		if (ql2xnvmeenable) {
3191			host->nr_hw_queues = ha->max_qpairs;
3192			ql_dbg(ql_dbg_init, base_vha, 0x0194,
3193			    "FC-NVMe support is enabled, HW queues=%d\n",
3194			    host->nr_hw_queues);
3195		} else {
3196			ql_dbg(ql_dbg_init, base_vha, 0x0193,
3197			    "blk/scsi-mq disabled.\n");
3198		}
3199	}
3200
3201	qlt_probe_one_stage1(base_vha, ha);
3202
3203	pci_save_state(pdev);
3204
3205	/* Assign back pointers */
3206	rsp->req = req;
3207	req->rsp = rsp;
3208
3209	if (IS_QLAFX00(ha)) {
3210		ha->rsp_q_map[0] = rsp;
3211		ha->req_q_map[0] = req;
3212		set_bit(0, ha->req_qid_map);
3213		set_bit(0, ha->rsp_qid_map);
3214	}
3215
3216	/* FWI2-capable only. */
3217	req->req_q_in = &ha->iobase->isp24.req_q_in;
3218	req->req_q_out = &ha->iobase->isp24.req_q_out;
3219	rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3220	rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3221	if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3222	    IS_QLA28XX(ha)) {
3223		req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3224		req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3225		rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3226		rsp->rsp_q_out =  &ha->mqiobase->isp25mq.rsp_q_out;
3227	}
3228
3229	if (IS_QLAFX00(ha)) {
3230		req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3231		req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3232		rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3233		rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3234	}
3235
3236	if (IS_P3P_TYPE(ha)) {
3237		req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3238		rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3239		rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3240	}
3241
3242	ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3243	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3244	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3245	ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3246	    "req->req_q_in=%p req->req_q_out=%p "
3247	    "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3248	    req->req_q_in, req->req_q_out,
3249	    rsp->rsp_q_in, rsp->rsp_q_out);
3250	ql_dbg(ql_dbg_init, base_vha, 0x003e,
3251	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3252	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3253	ql_dbg(ql_dbg_init, base_vha, 0x003f,
3254	    "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3255	    req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3256
3257	ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3258	if (unlikely(!ha->wq)) {
3259		ret = -ENOMEM;
3260		goto probe_failed;
3261	}
3262
3263	if (ha->isp_ops->initialize_adapter(base_vha)) {
3264		ql_log(ql_log_fatal, base_vha, 0x00d6,
3265		    "Failed to initialize adapter - Adapter flags %x.\n",
3266		    base_vha->device_flags);
3267
3268		if (IS_QLA82XX(ha)) {
3269			qla82xx_idc_lock(ha);
3270			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3271				QLA8XXX_DEV_FAILED);
3272			qla82xx_idc_unlock(ha);
3273			ql_log(ql_log_fatal, base_vha, 0x00d7,
3274			    "HW State: FAILED.\n");
3275		} else if (IS_QLA8044(ha)) {
3276			qla8044_idc_lock(ha);
3277			qla8044_wr_direct(base_vha,
3278				QLA8044_CRB_DEV_STATE_INDEX,
3279				QLA8XXX_DEV_FAILED);
3280			qla8044_idc_unlock(ha);
3281			ql_log(ql_log_fatal, base_vha, 0x0150,
3282			    "HW State: FAILED.\n");
3283		}
3284
3285		ret = -ENODEV;
3286		goto probe_failed;
3287	}
3288
3289	if (IS_QLAFX00(ha))
3290		host->can_queue = QLAFX00_MAX_CANQUEUE;
3291	else
3292		host->can_queue = req->num_outstanding_cmds - 10;
3293
3294	ql_dbg(ql_dbg_init, base_vha, 0x0032,
3295	    "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3296	    host->can_queue, base_vha->req,
3297	    base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3298
3299	if (ha->mqenable) {
3300		bool startit = false;
3301
3302		if (QLA_TGT_MODE_ENABLED())
3303			startit = false;
3304
3305		if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3306			startit = true;
3307
3308		/* Create start of day qpairs for Block MQ */
3309		for (i = 0; i < ha->max_qpairs; i++)
3310			qla2xxx_create_qpair(base_vha, 5, 0, startit);
3311	}
3312
3313	if (ha->flags.running_gold_fw)
3314		goto skip_dpc;
3315
3316	/*
3317	 * Startup the kernel thread for this host adapter
3318	 */
3319	ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3320	    "%s_dpc", base_vha->host_str);
3321	if (IS_ERR(ha->dpc_thread)) {
3322		ql_log(ql_log_fatal, base_vha, 0x00ed,
3323		    "Failed to start DPC thread.\n");
3324		ret = PTR_ERR(ha->dpc_thread);
3325		ha->dpc_thread = NULL;
3326		goto probe_failed;
3327	}
3328	ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3329	    "DPC thread started successfully.\n");
3330
3331	/*
3332	 * If we're not coming up in initiator mode, we might sit for
3333	 * a while without waking up the dpc thread, which leads to a
3334	 * stuck process warning.  So just kick the dpc once here and
3335	 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3336	 */
3337	qla2xxx_wake_dpc(base_vha);
3338
3339	INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3340
3341	if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3342		sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3343		ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3344		INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3345
3346		sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3347		ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3348		INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3349		INIT_WORK(&ha->idc_state_handler,
3350		    qla83xx_idc_state_handler_work);
3351		INIT_WORK(&ha->nic_core_unrecoverable,
3352		    qla83xx_nic_core_unrecoverable_work);
3353	}
3354
3355skip_dpc:
3356	list_add_tail(&base_vha->list, &ha->vp_list);
3357	base_vha->host->irq = ha->pdev->irq;
3358
3359	/* Initialized the timer */
3360	qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3361	ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3362	    "Started qla2x00_timer with "
3363	    "interval=%d.\n", WATCH_INTERVAL);
3364	ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3365	    "Detected hba at address=%p.\n",
3366	    ha);
3367
3368	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3369		if (ha->fw_attributes & BIT_4) {
3370			int prot = 0, guard;
3371
3372			base_vha->flags.difdix_supported = 1;
3373			ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3374			    "Registering for DIF/DIX type 1 and 3 protection.\n");
3375			if (ql2xenabledif == 1)
3376				prot = SHOST_DIX_TYPE0_PROTECTION;
3377			if (ql2xprotmask)
3378				scsi_host_set_prot(host, ql2xprotmask);
3379			else
3380				scsi_host_set_prot(host,
3381				    prot | SHOST_DIF_TYPE1_PROTECTION
3382				    | SHOST_DIF_TYPE2_PROTECTION
3383				    | SHOST_DIF_TYPE3_PROTECTION
3384				    | SHOST_DIX_TYPE1_PROTECTION
3385				    | SHOST_DIX_TYPE2_PROTECTION
3386				    | SHOST_DIX_TYPE3_PROTECTION);
3387
3388			guard = SHOST_DIX_GUARD_CRC;
3389
3390			if (IS_PI_IPGUARD_CAPABLE(ha) &&
3391			    (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3392				guard |= SHOST_DIX_GUARD_IP;
3393
3394			if (ql2xprotguard)
3395				scsi_host_set_guard(host, ql2xprotguard);
3396			else
3397				scsi_host_set_guard(host, guard);
3398		} else
3399			base_vha->flags.difdix_supported = 0;
3400	}
3401
3402	ha->isp_ops->enable_intrs(ha);
3403
3404	if (IS_QLAFX00(ha)) {
3405		ret = qlafx00_fx_disc(base_vha,
3406			&base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3407		host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3408		    QLA_SG_ALL : 128;
3409	}
3410
3411	ret = scsi_add_host(host, &pdev->dev);
3412	if (ret)
3413		goto probe_failed;
3414
3415	base_vha->flags.init_done = 1;
3416	base_vha->flags.online = 1;
3417	ha->prev_minidump_failed = 0;
3418
3419	ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3420	    "Init done and hba is online.\n");
3421
3422	if (qla_ini_mode_enabled(base_vha) ||
3423		qla_dual_mode_enabled(base_vha))
3424		scsi_scan_host(host);
3425	else
3426		ql_dbg(ql_dbg_init, base_vha, 0x0122,
3427			"skipping scsi_scan_host() for non-initiator port\n");
3428
3429	qla2x00_alloc_sysfs_attr(base_vha);
3430
3431	if (IS_QLAFX00(ha)) {
3432		ret = qlafx00_fx_disc(base_vha,
3433			&base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3434
3435		/* Register system information */
3436		ret =  qlafx00_fx_disc(base_vha,
3437			&base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3438	}
3439
3440	qla2x00_init_host_attr(base_vha);
3441
3442	qla2x00_dfs_setup(base_vha);
3443
3444	ql_log(ql_log_info, base_vha, 0x00fb,
3445	    "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3446	ql_log(ql_log_info, base_vha, 0x00fc,
3447	    "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3448	    pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3449						       sizeof(pci_info)),
3450	    pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3451	    base_vha->host_no,
3452	    ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3453
3454	qlt_add_target(ha, base_vha);
3455
3456	clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3457
3458	if (test_bit(UNLOADING, &base_vha->dpc_flags))
3459		return -ENODEV;
3460
3461	return 0;
3462
3463probe_failed:
3464	if (base_vha->gnl.l) {
3465		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3466				base_vha->gnl.l, base_vha->gnl.ldma);
3467		base_vha->gnl.l = NULL;
3468	}
3469
3470	if (base_vha->timer_active)
3471		qla2x00_stop_timer(base_vha);
3472	base_vha->flags.online = 0;
3473	if (ha->dpc_thread) {
3474		struct task_struct *t = ha->dpc_thread;
3475
3476		ha->dpc_thread = NULL;
3477		kthread_stop(t);
3478	}
3479
3480	qla2x00_free_device(base_vha);
3481	scsi_host_put(base_vha->host);
3482	/*
3483	 * Need to NULL out local req/rsp after
3484	 * qla2x00_free_device => qla2x00_free_queues frees
3485	 * what these are pointing to. Or else we'll
3486	 * fall over below in qla2x00_free_req/rsp_que.
3487	 */
3488	req = NULL;
3489	rsp = NULL;
3490
3491probe_hw_failed:
3492	qla2x00_mem_free(ha);
3493	qla2x00_free_req_que(ha, req);
3494	qla2x00_free_rsp_que(ha, rsp);
3495	qla2x00_clear_drv_active(ha);
3496
3497iospace_config_failed:
3498	if (IS_P3P_TYPE(ha)) {
3499		if (!ha->nx_pcibase)
3500			iounmap((device_reg_t *)ha->nx_pcibase);
3501		if (!ql2xdbwr)
3502			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3503	} else {
3504		if (ha->iobase)
3505			iounmap(ha->iobase);
3506		if (ha->cregbase)
3507			iounmap(ha->cregbase);
3508	}
3509	pci_release_selected_regions(ha->pdev, ha->bars);
3510	kfree(ha);
3511
3512disable_device:
3513	pci_disable_device(pdev);
3514	return ret;
3515}
3516
3517static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3518{
3519	scsi_qla_host_t *vp;
3520	unsigned long flags;
3521	struct qla_hw_data *ha;
3522
3523	if (!base_vha)
3524		return;
3525
3526	ha = base_vha->hw;
3527
3528	spin_lock_irqsave(&ha->vport_slock, flags);
3529	list_for_each_entry(vp, &ha->vp_list, list)
3530		set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3531
3532	/*
3533	 * Indicate device removal to prevent future board_disable
3534	 * and wait until any pending board_disable has completed.
3535	 */
3536	set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3537	spin_unlock_irqrestore(&ha->vport_slock, flags);
3538}
3539
3540static void
3541qla2x00_shutdown(struct pci_dev *pdev)
3542{
3543	scsi_qla_host_t *vha;
3544	struct qla_hw_data  *ha;
3545
3546	vha = pci_get_drvdata(pdev);
3547	ha = vha->hw;
3548
3549	ql_log(ql_log_info, vha, 0xfffa,
3550		"Adapter shutdown\n");
3551
3552	/*
3553	 * Prevent future board_disable and wait
3554	 * until any pending board_disable has completed.
3555	 */
3556	__qla_set_remove_flag(vha);
3557	cancel_work_sync(&ha->board_disable);
3558
3559	if (!atomic_read(&pdev->enable_cnt))
3560		return;
3561
3562	/* Notify ISPFX00 firmware */
3563	if (IS_QLAFX00(ha))
3564		qlafx00_driver_shutdown(vha, 20);
3565
3566	/* Turn-off FCE trace */
3567	if (ha->flags.fce_enabled) {
3568		qla2x00_disable_fce_trace(vha, NULL, NULL);
3569		ha->flags.fce_enabled = 0;
3570	}
3571
3572	/* Turn-off EFT trace */
3573	if (ha->eft)
3574		qla2x00_disable_eft_trace(vha);
3575
3576	if (IS_QLA25XX(ha) ||  IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3577	    IS_QLA28XX(ha)) {
3578		if (ha->flags.fw_started)
3579			qla2x00_abort_isp_cleanup(vha);
3580	} else {
3581		/* Stop currently executing firmware. */
3582		qla2x00_try_to_stop_firmware(vha);
3583	}
3584
3585	/* Disable timer */
3586	if (vha->timer_active)
3587		qla2x00_stop_timer(vha);
3588
3589	/* Turn adapter off line */
3590	vha->flags.online = 0;
3591
3592	/* turn-off interrupts on the card */
3593	if (ha->interrupts_on) {
3594		vha->flags.init_done = 0;
3595		ha->isp_ops->disable_intrs(ha);
3596	}
3597
3598	qla2x00_free_irqs(vha);
3599
3600	qla2x00_free_fw_dump(ha);
3601
3602	pci_disable_device(pdev);
3603	ql_log(ql_log_info, vha, 0xfffe,
3604		"Adapter shutdown successfully.\n");
3605}
3606
3607/* Deletes all the virtual ports for a given ha */
3608static void
3609qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3610{
3611	scsi_qla_host_t *vha;
3612	unsigned long flags;
3613
3614	mutex_lock(&ha->vport_lock);
3615	while (ha->cur_vport_count) {
3616		spin_lock_irqsave(&ha->vport_slock, flags);
3617
3618		BUG_ON(base_vha->list.next == &ha->vp_list);
3619		/* This assumes first entry in ha->vp_list is always base vha */
3620		vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3621		scsi_host_get(vha->host);
3622
3623		spin_unlock_irqrestore(&ha->vport_slock, flags);
3624		mutex_unlock(&ha->vport_lock);
3625
3626		qla_nvme_delete(vha);
3627
3628		fc_vport_terminate(vha->fc_vport);
3629		scsi_host_put(vha->host);
3630
3631		mutex_lock(&ha->vport_lock);
3632	}
3633	mutex_unlock(&ha->vport_lock);
3634}
3635
3636/* Stops all deferred work threads */
3637static void
3638qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3639{
3640	/* Cancel all work and destroy DPC workqueues */
3641	if (ha->dpc_lp_wq) {
3642		cancel_work_sync(&ha->idc_aen);
3643		destroy_workqueue(ha->dpc_lp_wq);
3644		ha->dpc_lp_wq = NULL;
3645	}
3646
3647	if (ha->dpc_hp_wq) {
3648		cancel_work_sync(&ha->nic_core_reset);
3649		cancel_work_sync(&ha->idc_state_handler);
3650		cancel_work_sync(&ha->nic_core_unrecoverable);
3651		destroy_workqueue(ha->dpc_hp_wq);
3652		ha->dpc_hp_wq = NULL;
3653	}
3654
3655	/* Kill the kernel thread for this host */
3656	if (ha->dpc_thread) {
3657		struct task_struct *t = ha->dpc_thread;
3658
3659		/*
3660		 * qla2xxx_wake_dpc checks for ->dpc_thread
3661		 * so we need to zero it out.
3662		 */
3663		ha->dpc_thread = NULL;
3664		kthread_stop(t);
3665	}
3666}
3667
3668static void
3669qla2x00_unmap_iobases(struct qla_hw_data *ha)
3670{
3671	if (IS_QLA82XX(ha)) {
3672
3673		iounmap((device_reg_t *)ha->nx_pcibase);
3674		if (!ql2xdbwr)
3675			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3676	} else {
3677		if (ha->iobase)
3678			iounmap(ha->iobase);
3679
3680		if (ha->cregbase)
3681			iounmap(ha->cregbase);
3682
3683		if (ha->mqiobase)
3684			iounmap(ha->mqiobase);
3685
3686		if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3687		    ha->msixbase)
3688			iounmap(ha->msixbase);
3689	}
3690}
3691
3692static void
3693qla2x00_clear_drv_active(struct qla_hw_data *ha)
3694{
3695	if (IS_QLA8044(ha)) {
3696		qla8044_idc_lock(ha);
3697		qla8044_clear_drv_active(ha);
3698		qla8044_idc_unlock(ha);
3699	} else if (IS_QLA82XX(ha)) {
3700		qla82xx_idc_lock(ha);
3701		qla82xx_clear_drv_active(ha);
3702		qla82xx_idc_unlock(ha);
3703	}
3704}
3705
3706static void
3707qla2x00_remove_one(struct pci_dev *pdev)
3708{
3709	scsi_qla_host_t *base_vha;
3710	struct qla_hw_data  *ha;
3711
3712	base_vha = pci_get_drvdata(pdev);
3713	ha = base_vha->hw;
3714	ql_log(ql_log_info, base_vha, 0xb079,
3715	    "Removing driver\n");
3716	__qla_set_remove_flag(base_vha);
3717	cancel_work_sync(&ha->board_disable);
3718
3719	/*
3720	 * If the PCI device is disabled then there was a PCI-disconnect and
3721	 * qla2x00_disable_board_on_pci_error has taken care of most of the
3722	 * resources.
3723	 */
3724	if (!atomic_read(&pdev->enable_cnt)) {
3725		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3726		    base_vha->gnl.l, base_vha->gnl.ldma);
3727		base_vha->gnl.l = NULL;
3728		scsi_host_put(base_vha->host);
3729		kfree(ha);
3730		pci_set_drvdata(pdev, NULL);
3731		return;
3732	}
3733	qla2x00_wait_for_hba_ready(base_vha);
3734
3735	/*
3736	 * if UNLOADING flag is already set, then continue unload,
3737	 * where it was set first.
3738	 */
3739	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3740		return;
3741
3742	if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3743	    IS_QLA28XX(ha)) {
3744		if (ha->flags.fw_started)
3745			qla2x00_abort_isp_cleanup(base_vha);
3746	} else if (!IS_QLAFX00(ha)) {
3747		if (IS_QLA8031(ha)) {
3748			ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3749			    "Clearing fcoe driver presence.\n");
3750			if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3751				ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3752				    "Error while clearing DRV-Presence.\n");
3753		}
3754
3755		qla2x00_try_to_stop_firmware(base_vha);
3756	}
3757
3758	qla2x00_wait_for_sess_deletion(base_vha);
3759
3760	qla_nvme_delete(base_vha);
3761
3762	dma_free_coherent(&ha->pdev->dev,
3763		base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3764
3765	base_vha->gnl.l = NULL;
3766
3767	vfree(base_vha->scan.l);
3768
3769	if (IS_QLAFX00(ha))
3770		qlafx00_driver_shutdown(base_vha, 20);
3771
3772	qla2x00_delete_all_vps(ha, base_vha);
3773
3774	qla2x00_dfs_remove(base_vha);
3775
3776	qla84xx_put_chip(base_vha);
3777
3778	/* Disable timer */
3779	if (base_vha->timer_active)
3780		qla2x00_stop_timer(base_vha);
3781
3782	base_vha->flags.online = 0;
3783
3784	/* free DMA memory */
3785	if (ha->exlogin_buf)
3786		qla2x00_free_exlogin_buffer(ha);
3787
3788	/* free DMA memory */
3789	if (ha->exchoffld_buf)
3790		qla2x00_free_exchoffld_buffer(ha);
3791
3792	qla2x00_destroy_deferred_work(ha);
3793
3794	qlt_remove_target(ha, base_vha);
3795
3796	qla2x00_free_sysfs_attr(base_vha, true);
3797
3798	fc_remove_host(base_vha->host);
3799	qlt_remove_target_resources(ha);
3800
3801	scsi_remove_host(base_vha->host);
3802
3803	qla2x00_free_device(base_vha);
3804
3805	qla2x00_clear_drv_active(ha);
3806
3807	scsi_host_put(base_vha->host);
3808
3809	qla2x00_unmap_iobases(ha);
3810
3811	pci_release_selected_regions(ha->pdev, ha->bars);
3812	kfree(ha);
3813
3814	pci_disable_pcie_error_reporting(pdev);
3815
3816	pci_disable_device(pdev);
3817}
3818
3819static inline void
3820qla24xx_free_purex_list(struct purex_list *list)
3821{
3822	struct list_head *item, *next;
3823	ulong flags;
3824
3825	spin_lock_irqsave(&list->lock, flags);
3826	list_for_each_safe(item, next, &list->head) {
3827		list_del(item);
3828		kfree(list_entry(item, struct purex_item, list));
3829	}
3830	spin_unlock_irqrestore(&list->lock, flags);
3831}
3832
3833static void
3834qla2x00_free_device(scsi_qla_host_t *vha)
3835{
3836	struct qla_hw_data *ha = vha->hw;
3837
3838	qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3839
3840	/* Disable timer */
3841	if (vha->timer_active)
3842		qla2x00_stop_timer(vha);
3843
3844	qla25xx_delete_queues(vha);
3845	vha->flags.online = 0;
3846
3847	/* turn-off interrupts on the card */
3848	if (ha->interrupts_on) {
3849		vha->flags.init_done = 0;
3850		ha->isp_ops->disable_intrs(ha);
3851	}
3852
3853	qla2x00_free_fcports(vha);
3854
3855	qla2x00_free_irqs(vha);
3856
3857	/* Flush the work queue and remove it */
3858	if (ha->wq) {
3859		flush_workqueue(ha->wq);
3860		destroy_workqueue(ha->wq);
3861		ha->wq = NULL;
3862	}
3863
3864
3865	qla24xx_free_purex_list(&vha->purex_list);
3866
3867	qla2x00_mem_free(ha);
3868
3869	qla82xx_md_free(vha);
3870
3871	qla2x00_free_queues(ha);
3872}
3873
3874void qla2x00_free_fcports(struct scsi_qla_host *vha)
3875{
3876	fc_port_t *fcport, *tfcport;
3877
3878	list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3879		qla2x00_free_fcport(fcport);
3880}
3881
3882static inline void
3883qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
3884{
3885	int now;
3886
3887	if (!fcport->rport)
3888		return;
3889
3890	if (fcport->rport) {
3891		ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3892		    "%s %8phN. rport %p roles %x\n",
3893		    __func__, fcport->port_name, fcport->rport,
3894		    fcport->rport->roles);
3895		fc_remote_port_delete(fcport->rport);
3896	}
3897	qlt_do_generation_tick(vha, &now);
3898}
3899
3900/*
3901 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3902 *
3903 * Input: ha = adapter block pointer.  fcport = port structure pointer.
3904 *
3905 * Return: None.
3906 *
3907 * Context:
3908 */
3909void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3910    int do_login)
3911{
3912	if (IS_QLAFX00(vha->hw)) {
3913		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3914		qla2x00_schedule_rport_del(vha, fcport);
3915		return;
3916	}
3917
3918	if (atomic_read(&fcport->state) == FCS_ONLINE &&
3919	    vha->vp_idx == fcport->vha->vp_idx) {
3920		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3921		qla2x00_schedule_rport_del(vha, fcport);
3922	}
3923	/*
3924	 * We may need to retry the login, so don't change the state of the
3925	 * port but do the retries.
3926	 */
3927	if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3928		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3929
3930	if (!do_login)
3931		return;
3932
3933	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3934}
3935
3936void
3937qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
3938{
3939	fc_port_t *fcport;
3940
3941	ql_dbg(ql_dbg_disc, vha, 0x20f1,
3942	    "Mark all dev lost\n");
3943
3944	list_for_each_entry(fcport, &vha->vp_fcports, list) {
3945		fcport->scan_state = 0;
3946		qlt_schedule_sess_for_deletion(fcport);
3947	}
3948}
3949
3950static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3951{
3952	int i;
3953
3954	if (IS_FWI2_CAPABLE(ha))
3955		return;
3956
3957	for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3958		set_bit(i, ha->loop_id_map);
3959	set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3960	set_bit(BROADCAST, ha->loop_id_map);
3961}
3962
3963/*
3964* qla2x00_mem_alloc
3965*      Allocates adapter memory.
3966*
3967* Returns:
3968*      0  = success.
3969*      !0  = failure.
3970*/
3971static int
3972qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3973	struct req_que **req, struct rsp_que **rsp)
3974{
3975	char	name[16];
3976
3977	ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3978		&ha->init_cb_dma, GFP_KERNEL);
3979	if (!ha->init_cb)
3980		goto fail;
3981
3982	if (qlt_mem_alloc(ha) < 0)
3983		goto fail_free_init_cb;
3984
3985	ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3986		qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3987	if (!ha->gid_list)
3988		goto fail_free_tgt_mem;
3989
3990	ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3991	if (!ha->srb_mempool)
3992		goto fail_free_gid_list;
3993
3994	if (IS_P3P_TYPE(ha)) {
3995		/* Allocate cache for CT6 Ctx. */
3996		if (!ctx_cachep) {
3997			ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3998				sizeof(struct ct6_dsd), 0,
3999				SLAB_HWCACHE_ALIGN, NULL);
4000			if (!ctx_cachep)
4001				goto fail_free_srb_mempool;
4002		}
4003		ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4004			ctx_cachep);
4005		if (!ha->ctx_mempool)
4006			goto fail_free_srb_mempool;
4007		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4008		    "ctx_cachep=%p ctx_mempool=%p.\n",
4009		    ctx_cachep, ha->ctx_mempool);
4010	}
4011
4012	/* Get memory for cached NVRAM */
4013	ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4014	if (!ha->nvram)
4015		goto fail_free_ctx_mempool;
4016
4017	snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4018		ha->pdev->device);
4019	ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4020		DMA_POOL_SIZE, 8, 0);
4021	if (!ha->s_dma_pool)
4022		goto fail_free_nvram;
4023
4024	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4025	    "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4026	    ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4027
4028	if (IS_P3P_TYPE(ha) || ql2xenabledif) {
4029		ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4030			DSD_LIST_DMA_POOL_SIZE, 8, 0);
4031		if (!ha->dl_dma_pool) {
4032			ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4033			    "Failed to allocate memory for dl_dma_pool.\n");
4034			goto fail_s_dma_pool;
4035		}
4036
4037		ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4038			FCP_CMND_DMA_POOL_SIZE, 8, 0);
4039		if (!ha->fcp_cmnd_dma_pool) {
4040			ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4041			    "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4042			goto fail_dl_dma_pool;
4043		}
4044
4045		if (ql2xenabledif) {
4046			u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4047			struct dsd_dma *dsd, *nxt;
4048			uint i;
4049			/* Creata a DMA pool of buffers for DIF bundling */
4050			ha->dif_bundl_pool = dma_pool_create(name,
4051			    &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4052			if (!ha->dif_bundl_pool) {
4053				ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4054				    "%s: failed create dif_bundl_pool\n",
4055				    __func__);
4056				goto fail_dif_bundl_dma_pool;
4057			}
4058
4059			INIT_LIST_HEAD(&ha->pool.good.head);
4060			INIT_LIST_HEAD(&ha->pool.unusable.head);
4061			ha->pool.good.count = 0;
4062			ha->pool.unusable.count = 0;
4063			for (i = 0; i < 128; i++) {
4064				dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4065				if (!dsd) {
4066					ql_dbg_pci(ql_dbg_init, ha->pdev,
4067					    0xe0ee, "%s: failed alloc dsd\n",
4068					    __func__);
4069					return 1;
4070				}
4071				ha->dif_bundle_kallocs++;
4072
4073				dsd->dsd_addr = dma_pool_alloc(
4074				    ha->dif_bundl_pool, GFP_ATOMIC,
4075				    &dsd->dsd_list_dma);
4076				if (!dsd->dsd_addr) {
4077					ql_dbg_pci(ql_dbg_init, ha->pdev,
4078					    0xe0ee,
4079					    "%s: failed alloc ->dsd_addr\n",
4080					    __func__);
4081					kfree(dsd);
4082					ha->dif_bundle_kallocs--;
4083					continue;
4084				}
4085				ha->dif_bundle_dma_allocs++;
4086
4087				/*
4088				 * if DMA buffer crosses 4G boundary,
4089				 * put it on bad list
4090				 */
4091				if (MSD(dsd->dsd_list_dma) ^
4092				    MSD(dsd->dsd_list_dma + bufsize)) {
4093					list_add_tail(&dsd->list,
4094					    &ha->pool.unusable.head);
4095					ha->pool.unusable.count++;
4096				} else {
4097					list_add_tail(&dsd->list,
4098					    &ha->pool.good.head);
4099					ha->pool.good.count++;
4100				}
4101			}
4102
4103			/* return the good ones back to the pool */
4104			list_for_each_entry_safe(dsd, nxt,
4105			    &ha->pool.good.head, list) {
4106				list_del(&dsd->list);
4107				dma_pool_free(ha->dif_bundl_pool,
4108				    dsd->dsd_addr, dsd->dsd_list_dma);
4109				ha->dif_bundle_dma_allocs--;
4110				kfree(dsd);
4111				ha->dif_bundle_kallocs--;
4112			}
4113
4114			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4115			    "%s: dif dma pool (good=%u unusable=%u)\n",
4116			    __func__, ha->pool.good.count,
4117			    ha->pool.unusable.count);
4118		}
4119
4120		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4121		    "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4122		    ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4123		    ha->dif_bundl_pool);
4124	}
4125
4126	/* Allocate memory for SNS commands */
4127	if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4128	/* Get consistent memory allocated for SNS commands */
4129		ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4130		sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4131		if (!ha->sns_cmd)
4132			goto fail_dma_pool;
4133		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4134		    "sns_cmd: %p.\n", ha->sns_cmd);
4135	} else {
4136	/* Get consistent memory allocated for MS IOCB */
4137		ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4138			&ha->ms_iocb_dma);
4139		if (!ha->ms_iocb)
4140			goto fail_dma_pool;
4141	/* Get consistent memory allocated for CT SNS commands */
4142		ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4143			sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4144		if (!ha->ct_sns)
4145			goto fail_free_ms_iocb;
4146		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4147		    "ms_iocb=%p ct_sns=%p.\n",
4148		    ha->ms_iocb, ha->ct_sns);
4149	}
4150
4151	/* Allocate memory for request ring */
4152	*req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4153	if (!*req) {
4154		ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4155		    "Failed to allocate memory for req.\n");
4156		goto fail_req;
4157	}
4158	(*req)->length = req_len;
4159	(*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4160		((*req)->length + 1) * sizeof(request_t),
4161		&(*req)->dma, GFP_KERNEL);
4162	if (!(*req)->ring) {
4163		ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4164		    "Failed to allocate memory for req_ring.\n");
4165		goto fail_req_ring;
4166	}
4167	/* Allocate memory for response ring */
4168	*rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4169	if (!*rsp) {
4170		ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4171		    "Failed to allocate memory for rsp.\n");
4172		goto fail_rsp;
4173	}
4174	(*rsp)->hw = ha;
4175	(*rsp)->length = rsp_len;
4176	(*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4177		((*rsp)->length + 1) * sizeof(response_t),
4178		&(*rsp)->dma, GFP_KERNEL);
4179	if (!(*rsp)->ring) {
4180		ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4181		    "Failed to allocate memory for rsp_ring.\n");
4182		goto fail_rsp_ring;
4183	}
4184	(*req)->rsp = *rsp;
4185	(*rsp)->req = *req;
4186	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4187	    "req=%p req->length=%d req->ring=%p rsp=%p "
4188	    "rsp->length=%d rsp->ring=%p.\n",
4189	    *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4190	    (*rsp)->ring);
4191	/* Allocate memory for NVRAM data for vports */
4192	if (ha->nvram_npiv_size) {
4193		ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4194					sizeof(struct qla_npiv_entry),
4195					GFP_KERNEL);
4196		if (!ha->npiv_info) {
4197			ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4198			    "Failed to allocate memory for npiv_info.\n");
4199			goto fail_npiv_info;
4200		}
4201	} else
4202		ha->npiv_info = NULL;
4203
4204	/* Get consistent memory allocated for EX-INIT-CB. */
4205	if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4206	    IS_QLA28XX(ha)) {
4207		ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4208		    &ha->ex_init_cb_dma);
4209		if (!ha->ex_init_cb)
4210			goto fail_ex_init_cb;
4211		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4212		    "ex_init_cb=%p.\n", ha->ex_init_cb);
4213	}
4214
4215	INIT_LIST_HEAD(&ha->gbl_dsd_list);
4216
4217	/* Get consistent memory allocated for Async Port-Database. */
4218	if (!IS_FWI2_CAPABLE(ha)) {
4219		ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4220			&ha->async_pd_dma);
4221		if (!ha->async_pd)
4222			goto fail_async_pd;
4223		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4224		    "async_pd=%p.\n", ha->async_pd);
4225	}
4226
4227	INIT_LIST_HEAD(&ha->vp_list);
4228
4229	/* Allocate memory for our loop_id bitmap */
4230	ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4231				  sizeof(long),
4232				  GFP_KERNEL);
4233	if (!ha->loop_id_map)
4234		goto fail_loop_id_map;
4235	else {
4236		qla2x00_set_reserved_loop_ids(ha);
4237		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4238		    "loop_id_map=%p.\n", ha->loop_id_map);
4239	}
4240
4241	ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4242	    SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4243	if (!ha->sfp_data) {
4244		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4245		    "Unable to allocate memory for SFP read-data.\n");
4246		goto fail_sfp_data;
4247	}
4248
4249	ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4250	    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4251	    GFP_KERNEL);
4252	if (!ha->flt) {
4253		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4254		    "Unable to allocate memory for FLT.\n");
4255		goto fail_flt_buffer;
4256	}
4257
4258	return 0;
4259
4260fail_flt_buffer:
4261	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4262	    ha->sfp_data, ha->sfp_data_dma);
4263fail_sfp_data:
4264	kfree(ha->loop_id_map);
4265fail_loop_id_map:
4266	dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4267fail_async_pd:
4268	dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4269fail_ex_init_cb:
4270	kfree(ha->npiv_info);
4271fail_npiv_info:
4272	dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4273		sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4274	(*rsp)->ring = NULL;
4275	(*rsp)->dma = 0;
4276fail_rsp_ring:
4277	kfree(*rsp);
4278	*rsp = NULL;
4279fail_rsp:
4280	dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4281		sizeof(request_t), (*req)->ring, (*req)->dma);
4282	(*req)->ring = NULL;
4283	(*req)->dma = 0;
4284fail_req_ring:
4285	kfree(*req);
4286	*req = NULL;
4287fail_req:
4288	dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4289		ha->ct_sns, ha->ct_sns_dma);
4290	ha->ct_sns = NULL;
4291	ha->ct_sns_dma = 0;
4292fail_free_ms_iocb:
4293	dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4294	ha->ms_iocb = NULL;
4295	ha->ms_iocb_dma = 0;
4296
4297	if (ha->sns_cmd)
4298		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4299		    ha->sns_cmd, ha->sns_cmd_dma);
4300fail_dma_pool:
4301	if (ql2xenabledif) {
4302		struct dsd_dma *dsd, *nxt;
4303
4304		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4305		    list) {
4306			list_del(&dsd->list);
4307			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4308			    dsd->dsd_list_dma);
4309			ha->dif_bundle_dma_allocs--;
4310			kfree(dsd);
4311			ha->dif_bundle_kallocs--;
4312			ha->pool.unusable.count--;
4313		}
4314		dma_pool_destroy(ha->dif_bundl_pool);
4315		ha->dif_bundl_pool = NULL;
4316	}
4317
4318fail_dif_bundl_dma_pool:
4319	if (IS_QLA82XX(ha) || ql2xenabledif) {
4320		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4321		ha->fcp_cmnd_dma_pool = NULL;
4322	}
4323fail_dl_dma_pool:
4324	if (IS_QLA82XX(ha) || ql2xenabledif) {
4325		dma_pool_destroy(ha->dl_dma_pool);
4326		ha->dl_dma_pool = NULL;
4327	}
4328fail_s_dma_pool:
4329	dma_pool_destroy(ha->s_dma_pool);
4330	ha->s_dma_pool = NULL;
4331fail_free_nvram:
4332	kfree(ha->nvram);
4333	ha->nvram = NULL;
4334fail_free_ctx_mempool:
4335	mempool_destroy(ha->ctx_mempool);
4336	ha->ctx_mempool = NULL;
4337fail_free_srb_mempool:
4338	mempool_destroy(ha->srb_mempool);
4339	ha->srb_mempool = NULL;
4340fail_free_gid_list:
4341	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4342	ha->gid_list,
4343	ha->gid_list_dma);
4344	ha->gid_list = NULL;
4345	ha->gid_list_dma = 0;
4346fail_free_tgt_mem:
4347	qlt_mem_free(ha);
4348fail_free_init_cb:
4349	dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4350	ha->init_cb_dma);
4351	ha->init_cb = NULL;
4352	ha->init_cb_dma = 0;
4353fail:
4354	ql_log(ql_log_fatal, NULL, 0x0030,
4355	    "Memory allocation failure.\n");
4356	return -ENOMEM;
4357}
4358
4359int
4360qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4361{
4362	int rval;
4363	uint16_t	size, max_cnt, temp;
4364	struct qla_hw_data *ha = vha->hw;
4365
4366	/* Return if we don't need to alloacate any extended logins */
4367	if (!ql2xexlogins)
4368		return QLA_SUCCESS;
4369
4370	if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4371		return QLA_SUCCESS;
4372
4373	ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4374	max_cnt = 0;
4375	rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4376	if (rval != QLA_SUCCESS) {
4377		ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4378		    "Failed to get exlogin status.\n");
4379		return rval;
4380	}
4381
4382	temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4383	temp *= size;
4384
4385	if (temp != ha->exlogin_size) {
4386		qla2x00_free_exlogin_buffer(ha);
4387		ha->exlogin_size = temp;
4388
4389		ql_log(ql_log_info, vha, 0xd024,
4390		    "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4391		    max_cnt, size, temp);
4392
4393		ql_log(ql_log_info, vha, 0xd025,
4394		    "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4395
4396		/* Get consistent memory for extended logins */
4397		ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4398			ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4399		if (!ha->exlogin_buf) {
4400			ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4401		    "Failed to allocate memory for exlogin_buf_dma.\n");
4402			return -ENOMEM;
4403		}
4404	}
4405
4406	/* Now configure the dma buffer */
4407	rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4408	if (rval) {
4409		ql_log(ql_log_fatal, vha, 0xd033,
4410		    "Setup extended login buffer  ****FAILED****.\n");
4411		qla2x00_free_exlogin_buffer(ha);
4412	}
4413
4414	return rval;
4415}
4416
4417/*
4418* qla2x00_free_exlogin_buffer
4419*
4420* Input:
4421*	ha = adapter block pointer
4422*/
4423void
4424qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4425{
4426	if (ha->exlogin_buf) {
4427		dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4428		    ha->exlogin_buf, ha->exlogin_buf_dma);
4429		ha->exlogin_buf = NULL;
4430		ha->exlogin_size = 0;
4431	}
4432}
4433
4434static void
4435qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4436{
4437	u32 temp;
4438	struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4439	*ret_cnt = FW_DEF_EXCHANGES_CNT;
4440
4441	if (max_cnt > vha->hw->max_exchg)
4442		max_cnt = vha->hw->max_exchg;
4443
4444	if (qla_ini_mode_enabled(vha)) {
4445		if (vha->ql2xiniexchg > max_cnt)
4446			vha->ql2xiniexchg = max_cnt;
4447
4448		if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4449			*ret_cnt = vha->ql2xiniexchg;
4450
4451	} else if (qla_tgt_mode_enabled(vha)) {
4452		if (vha->ql2xexchoffld > max_cnt) {
4453			vha->ql2xexchoffld = max_cnt;
4454			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4455		}
4456
4457		if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4458			*ret_cnt = vha->ql2xexchoffld;
4459	} else if (qla_dual_mode_enabled(vha)) {
4460		temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4461		if (temp > max_cnt) {
4462			vha->ql2xiniexchg -= (temp - max_cnt)/2;
4463			vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4464			temp = max_cnt;
4465			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4466		}
4467
4468		if (temp > FW_DEF_EXCHANGES_CNT)
4469			*ret_cnt = temp;
4470	}
4471}
4472
4473int
4474qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4475{
4476	int rval;
4477	u16	size, max_cnt;
4478	u32 actual_cnt, totsz;
4479	struct qla_hw_data *ha = vha->hw;
4480
4481	if (!ha->flags.exchoffld_enabled)
4482		return QLA_SUCCESS;
4483
4484	if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4485		return QLA_SUCCESS;
4486
4487	max_cnt = 0;
4488	rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4489	if (rval != QLA_SUCCESS) {
4490		ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4491		    "Failed to get exlogin status.\n");
4492		return rval;
4493	}
4494
4495	qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4496	ql_log(ql_log_info, vha, 0xd014,
4497	    "Actual exchange offload count: %d.\n", actual_cnt);
4498
4499	totsz = actual_cnt * size;
4500
4501	if (totsz != ha->exchoffld_size) {
4502		qla2x00_free_exchoffld_buffer(ha);
4503		if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4504			ha->exchoffld_size = 0;
4505			ha->flags.exchoffld_enabled = 0;
4506			return QLA_SUCCESS;
4507		}
4508
4509		ha->exchoffld_size = totsz;
4510
4511		ql_log(ql_log_info, vha, 0xd016,
4512		    "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4513		    max_cnt, actual_cnt, size, totsz);
4514
4515		ql_log(ql_log_info, vha, 0xd017,
4516		    "Exchange Buffers requested size = 0x%x\n",
4517		    ha->exchoffld_size);
4518
4519		/* Get consistent memory for extended logins */
4520		ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4521			ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4522		if (!ha->exchoffld_buf) {
4523			ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4524			"Failed to allocate memory for Exchange Offload.\n");
4525
4526			if (ha->max_exchg >
4527			    (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4528				ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4529			} else if (ha->max_exchg >
4530			    (FW_DEF_EXCHANGES_CNT + 512)) {
4531				ha->max_exchg -= 512;
4532			} else {
4533				ha->flags.exchoffld_enabled = 0;
4534				ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4535				    "Disabling Exchange offload due to lack of memory\n");
4536			}
4537			ha->exchoffld_size = 0;
4538
4539			return -ENOMEM;
4540		}
4541	} else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4542		/* pathological case */
4543		qla2x00_free_exchoffld_buffer(ha);
4544		ha->exchoffld_size = 0;
4545		ha->flags.exchoffld_enabled = 0;
4546		ql_log(ql_log_info, vha, 0xd016,
4547		    "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4548		    ha->exchoffld_size, actual_cnt, size, totsz);
4549		return 0;
4550	}
4551
4552	/* Now configure the dma buffer */
4553	rval = qla_set_exchoffld_mem_cfg(vha);
4554	if (rval) {
4555		ql_log(ql_log_fatal, vha, 0xd02e,
4556		    "Setup exchange offload buffer ****FAILED****.\n");
4557		qla2x00_free_exchoffld_buffer(ha);
4558	} else {
4559		/* re-adjust number of target exchange */
4560		struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4561
4562		if (qla_ini_mode_enabled(vha))
4563			icb->exchange_count = 0;
4564		else
4565			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4566	}
4567
4568	return rval;
4569}
4570
4571/*
4572* qla2x00_free_exchoffld_buffer
4573*
4574* Input:
4575*	ha = adapter block pointer
4576*/
4577void
4578qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4579{
4580	if (ha->exchoffld_buf) {
4581		dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4582		    ha->exchoffld_buf, ha->exchoffld_buf_dma);
4583		ha->exchoffld_buf = NULL;
4584		ha->exchoffld_size = 0;
4585	}
4586}
4587
4588/*
4589* qla2x00_free_fw_dump
4590*	Frees fw dump stuff.
4591*
4592* Input:
4593*	ha = adapter block pointer
4594*/
4595static void
4596qla2x00_free_fw_dump(struct qla_hw_data *ha)
4597{
4598	struct fwdt *fwdt = ha->fwdt;
4599	uint j;
4600
4601	if (ha->fce)
4602		dma_free_coherent(&ha->pdev->dev,
4603		    FCE_SIZE, ha->fce, ha->fce_dma);
4604
4605	if (ha->eft)
4606		dma_free_coherent(&ha->pdev->dev,
4607		    EFT_SIZE, ha->eft, ha->eft_dma);
4608
4609	if (ha->fw_dump)
4610		vfree(ha->fw_dump);
4611
4612	ha->fce = NULL;
4613	ha->fce_dma = 0;
4614	ha->flags.fce_enabled = 0;
4615	ha->eft = NULL;
4616	ha->eft_dma = 0;
4617	ha->fw_dumped = 0;
4618	ha->fw_dump_cap_flags = 0;
4619	ha->fw_dump_reading = 0;
4620	ha->fw_dump = NULL;
4621	ha->fw_dump_len = 0;
4622
4623	for (j = 0; j < 2; j++, fwdt++) {
4624		if (fwdt->template)
4625			vfree(fwdt->template);
4626		fwdt->template = NULL;
4627		fwdt->length = 0;
4628	}
4629}
4630
4631/*
4632* qla2x00_mem_free
4633*      Frees all adapter allocated memory.
4634*
4635* Input:
4636*      ha = adapter block pointer.
4637*/
4638static void
4639qla2x00_mem_free(struct qla_hw_data *ha)
4640{
4641	qla2x00_free_fw_dump(ha);
4642
4643	if (ha->mctp_dump)
4644		dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4645		    ha->mctp_dump_dma);
4646	ha->mctp_dump = NULL;
4647
4648	mempool_destroy(ha->srb_mempool);
4649	ha->srb_mempool = NULL;
4650
4651	if (ha->dcbx_tlv)
4652		dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4653		    ha->dcbx_tlv, ha->dcbx_tlv_dma);
4654	ha->dcbx_tlv = NULL;
4655
4656	if (ha->xgmac_data)
4657		dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4658		    ha->xgmac_data, ha->xgmac_data_dma);
4659	ha->xgmac_data = NULL;
4660
4661	if (ha->sns_cmd)
4662		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4663		ha->sns_cmd, ha->sns_cmd_dma);
4664	ha->sns_cmd = NULL;
4665	ha->sns_cmd_dma = 0;
4666
4667	if (ha->ct_sns)
4668		dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4669		ha->ct_sns, ha->ct_sns_dma);
4670	ha->ct_sns = NULL;
4671	ha->ct_sns_dma = 0;
4672
4673	if (ha->sfp_data)
4674		dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4675		    ha->sfp_data_dma);
4676	ha->sfp_data = NULL;
4677
4678	if (ha->flt)
4679		dma_free_coherent(&ha->pdev->dev,
4680		    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4681		    ha->flt, ha->flt_dma);
4682	ha->flt = NULL;
4683	ha->flt_dma = 0;
4684
4685	if (ha->ms_iocb)
4686		dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4687	ha->ms_iocb = NULL;
4688	ha->ms_iocb_dma = 0;
4689
4690	if (ha->ex_init_cb)
4691		dma_pool_free(ha->s_dma_pool,
4692			ha->ex_init_cb, ha->ex_init_cb_dma);
4693	ha->ex_init_cb = NULL;
4694	ha->ex_init_cb_dma = 0;
4695
4696	if (ha->async_pd)
4697		dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4698	ha->async_pd = NULL;
4699	ha->async_pd_dma = 0;
4700
4701	dma_pool_destroy(ha->s_dma_pool);
4702	ha->s_dma_pool = NULL;
4703
4704	if (ha->gid_list)
4705		dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4706		ha->gid_list, ha->gid_list_dma);
4707	ha->gid_list = NULL;
4708	ha->gid_list_dma = 0;
4709
4710	if (IS_QLA82XX(ha)) {
4711		if (!list_empty(&ha->gbl_dsd_list)) {
4712			struct dsd_dma *dsd_ptr, *tdsd_ptr;
4713
4714			/* clean up allocated prev pool */
4715			list_for_each_entry_safe(dsd_ptr,
4716				tdsd_ptr, &ha->gbl_dsd_list, list) {
4717				dma_pool_free(ha->dl_dma_pool,
4718				dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4719				list_del(&dsd_ptr->list);
4720				kfree(dsd_ptr);
4721			}
4722		}
4723	}
4724
4725	dma_pool_destroy(ha->dl_dma_pool);
4726	ha->dl_dma_pool = NULL;
4727
4728	dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4729	ha->fcp_cmnd_dma_pool = NULL;
4730
4731	mempool_destroy(ha->ctx_mempool);
4732	ha->ctx_mempool = NULL;
4733
4734	if (ql2xenabledif && ha->dif_bundl_pool) {
4735		struct dsd_dma *dsd, *nxt;
4736
4737		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4738					 list) {
4739			list_del(&dsd->list);
4740			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4741				      dsd->dsd_list_dma);
4742			ha->dif_bundle_dma_allocs--;
4743			kfree(dsd);
4744			ha->dif_bundle_kallocs--;
4745			ha->pool.unusable.count--;
4746		}
4747		list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4748			list_del(&dsd->list);
4749			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4750				      dsd->dsd_list_dma);
4751			ha->dif_bundle_dma_allocs--;
4752			kfree(dsd);
4753			ha->dif_bundle_kallocs--;
4754		}
4755	}
4756
4757	dma_pool_destroy(ha->dif_bundl_pool);
4758	ha->dif_bundl_pool = NULL;
4759
4760	qlt_mem_free(ha);
4761
4762	if (ha->init_cb)
4763		dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4764			ha->init_cb, ha->init_cb_dma);
4765	ha->init_cb = NULL;
4766	ha->init_cb_dma = 0;
4767
4768	vfree(ha->optrom_buffer);
4769	ha->optrom_buffer = NULL;
4770	kfree(ha->nvram);
4771	ha->nvram = NULL;
4772	kfree(ha->npiv_info);
4773	ha->npiv_info = NULL;
4774	kfree(ha->swl);
4775	ha->swl = NULL;
4776	kfree(ha->loop_id_map);
4777	ha->loop_id_map = NULL;
4778}
4779
4780struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4781						struct qla_hw_data *ha)
4782{
4783	struct Scsi_Host *host;
4784	struct scsi_qla_host *vha = NULL;
4785
4786	host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4787	if (!host) {
4788		ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4789		    "Failed to allocate host from the scsi layer, aborting.\n");
4790		return NULL;
4791	}
4792
4793	/* Clear our data area */
4794	vha = shost_priv(host);
4795	memset(vha, 0, sizeof(scsi_qla_host_t));
4796
4797	vha->host = host;
4798	vha->host_no = host->host_no;
4799	vha->hw = ha;
4800
4801	vha->qlini_mode = ql2x_ini_mode;
4802	vha->ql2xexchoffld = ql2xexchoffld;
4803	vha->ql2xiniexchg = ql2xiniexchg;
4804
4805	INIT_LIST_HEAD(&vha->vp_fcports);
4806	INIT_LIST_HEAD(&vha->work_list);
4807	INIT_LIST_HEAD(&vha->list);
4808	INIT_LIST_HEAD(&vha->qla_cmd_list);
4809	INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4810	INIT_LIST_HEAD(&vha->logo_list);
4811	INIT_LIST_HEAD(&vha->plogi_ack_list);
4812	INIT_LIST_HEAD(&vha->qp_list);
4813	INIT_LIST_HEAD(&vha->gnl.fcports);
4814	INIT_LIST_HEAD(&vha->gpnid_list);
4815	INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
4816
4817	INIT_LIST_HEAD(&vha->purex_list.head);
4818	spin_lock_init(&vha->purex_list.lock);
4819
4820	spin_lock_init(&vha->work_lock);
4821	spin_lock_init(&vha->cmd_list_lock);
4822	init_waitqueue_head(&vha->fcport_waitQ);
4823	init_waitqueue_head(&vha->vref_waitq);
4824
4825	vha->gnl.size = sizeof(struct get_name_list_extended) *
4826			(ha->max_loop_id + 1);
4827	vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4828	    vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4829	if (!vha->gnl.l) {
4830		ql_log(ql_log_fatal, vha, 0xd04a,
4831		    "Alloc failed for name list.\n");
4832		scsi_host_put(vha->host);
4833		return NULL;
4834	}
4835
4836	/* todo: what about ext login? */
4837	vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4838	vha->scan.l = vmalloc(vha->scan.size);
4839	if (!vha->scan.l) {
4840		ql_log(ql_log_fatal, vha, 0xd04a,
4841		    "Alloc failed for scan database.\n");
4842		dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4843		    vha->gnl.l, vha->gnl.ldma);
4844		vha->gnl.l = NULL;
4845		scsi_host_put(vha->host);
4846		return NULL;
4847	}
4848	INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
4849
4850	sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
4851	ql_dbg(ql_dbg_init, vha, 0x0041,
4852	    "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4853	    vha->host, vha->hw, vha,
4854	    dev_name(&(ha->pdev->dev)));
4855
4856	return vha;
4857}
4858
4859struct qla_work_evt *
4860qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4861{
4862	struct qla_work_evt *e;
4863	uint8_t bail;
4864
4865	if (test_bit(UNLOADING, &vha->dpc_flags))
4866		return NULL;
4867
4868	QLA_VHA_MARK_BUSY(vha, bail);
4869	if (bail)
4870		return NULL;
4871
4872	e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4873	if (!e) {
4874		QLA_VHA_MARK_NOT_BUSY(vha);
4875		return NULL;
4876	}
4877
4878	INIT_LIST_HEAD(&e->list);
4879	e->type = type;
4880	e->flags = QLA_EVT_FLAG_FREE;
4881	return e;
4882}
4883
4884int
4885qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4886{
4887	unsigned long flags;
4888	bool q = false;
4889
4890	spin_lock_irqsave(&vha->work_lock, flags);
4891	list_add_tail(&e->list, &vha->work_list);
4892
4893	if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4894		q = true;
4895
4896	spin_unlock_irqrestore(&vha->work_lock, flags);
4897
4898	if (q)
4899		queue_work(vha->hw->wq, &vha->iocb_work);
4900
4901	return QLA_SUCCESS;
4902}
4903
4904int
4905qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4906    u32 data)
4907{
4908	struct qla_work_evt *e;
4909
4910	e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4911	if (!e)
4912		return QLA_FUNCTION_FAILED;
4913
4914	e->u.aen.code = code;
4915	e->u.aen.data = data;
4916	return qla2x00_post_work(vha, e);
4917}
4918
4919int
4920qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4921{
4922	struct qla_work_evt *e;
4923
4924	e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4925	if (!e)
4926		return QLA_FUNCTION_FAILED;
4927
4928	memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4929	return qla2x00_post_work(vha, e);
4930}
4931
4932#define qla2x00_post_async_work(name, type)	\
4933int qla2x00_post_async_##name##_work(		\
4934    struct scsi_qla_host *vha,			\
4935    fc_port_t *fcport, uint16_t *data)		\
4936{						\
4937	struct qla_work_evt *e;			\
4938						\
4939	e = qla2x00_alloc_work(vha, type);	\
4940	if (!e)					\
4941		return QLA_FUNCTION_FAILED;	\
4942						\
4943	e->u.logio.fcport = fcport;		\
4944	if (data) {				\
4945		e->u.logio.data[0] = data[0];	\
4946		e->u.logio.data[1] = data[1];	\
4947	}					\
4948	fcport->flags |= FCF_ASYNC_ACTIVE;	\
4949	return qla2x00_post_work(vha, e);	\
4950}
4951
4952qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4953qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4954qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4955qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4956qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
4957
4958int
4959qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4960{
4961	struct qla_work_evt *e;
4962
4963	e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4964	if (!e)
4965		return QLA_FUNCTION_FAILED;
4966
4967	e->u.uevent.code = code;
4968	return qla2x00_post_work(vha, e);
4969}
4970
4971static void
4972qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4973{
4974	char event_string[40];
4975	char *envp[] = { event_string, NULL };
4976
4977	switch (code) {
4978	case QLA_UEVENT_CODE_FW_DUMP:
4979		snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4980		    vha->host_no);
4981		break;
4982	default:
4983		/* do nothing */
4984		break;
4985	}
4986	kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4987}
4988
4989int
4990qlafx00_post_aenfx_work(struct scsi_qla_host *vha,  uint32_t evtcode,
4991			uint32_t *data, int cnt)
4992{
4993	struct qla_work_evt *e;
4994
4995	e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4996	if (!e)
4997		return QLA_FUNCTION_FAILED;
4998
4999	e->u.aenfx.evtcode = evtcode;
5000	e->u.aenfx.count = cnt;
5001	memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5002	return qla2x00_post_work(vha, e);
5003}
5004
5005void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5006{
5007	unsigned long flags;
5008
5009	if (IS_SW_RESV_ADDR(fcport->d_id))
5010		return;
5011
5012	spin_lock_irqsave(&fcport->vha->work_lock, flags);
5013	if (fcport->disc_state == DSC_UPD_FCPORT) {
5014		spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5015		return;
5016	}
5017	fcport->jiffies_at_registration = jiffies;
5018	fcport->sec_since_registration = 0;
5019	fcport->next_disc_state = DSC_DELETED;
5020	qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5021	spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5022
5023	queue_work(system_unbound_wq, &fcport->reg_work);
5024}
5025
5026static
5027void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5028{
5029	unsigned long flags;
5030	fc_port_t *fcport =  NULL, *tfcp;
5031	struct qlt_plogi_ack_t *pla =
5032	    (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5033	uint8_t free_fcport = 0;
5034
5035	ql_dbg(ql_dbg_disc, vha, 0xffff,
5036	    "%s %d %8phC enter\n",
5037	    __func__, __LINE__, e->u.new_sess.port_name);
5038
5039	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5040	fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5041	if (fcport) {
5042		fcport->d_id = e->u.new_sess.id;
5043		if (pla) {
5044			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5045			memcpy(fcport->node_name,
5046			    pla->iocb.u.isp24.u.plogi.node_name,
5047			    WWN_SIZE);
5048			qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5049			/* we took an extra ref_count to prevent PLOGI ACK when
5050			 * fcport/sess has not been created.
5051			 */
5052			pla->ref_count--;
5053		}
5054	} else {
5055		spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5056		fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5057		if (fcport) {
5058			fcport->d_id = e->u.new_sess.id;
5059			fcport->flags |= FCF_FABRIC_DEVICE;
5060			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5061
5062			memcpy(fcport->port_name, e->u.new_sess.port_name,
5063			    WWN_SIZE);
5064
5065			fcport->fc4_type = e->u.new_sess.fc4_type;
5066			if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5067				fcport->fc4_type = FS_FC4TYPE_FCP;
5068				fcport->n2n_flag = 1;
5069				if (vha->flags.nvme_enabled)
5070					fcport->fc4_type |= FS_FC4TYPE_NVME;
5071			}
5072
5073		} else {
5074			ql_dbg(ql_dbg_disc, vha, 0xffff,
5075				   "%s %8phC mem alloc fail.\n",
5076				   __func__, e->u.new_sess.port_name);
5077
5078			if (pla) {
5079				list_del(&pla->list);
5080				kmem_cache_free(qla_tgt_plogi_cachep, pla);
5081			}
5082			return;
5083		}
5084
5085		spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5086		/* search again to make sure no one else got ahead */
5087		tfcp = qla2x00_find_fcport_by_wwpn(vha,
5088		    e->u.new_sess.port_name, 1);
5089		if (tfcp) {
5090			/* should rarily happen */
5091			ql_dbg(ql_dbg_disc, vha, 0xffff,
5092			    "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5093			    __func__, tfcp->port_name, tfcp->disc_state,
5094			    tfcp->fw_login_state);
5095
5096			free_fcport = 1;
5097		} else {
5098			list_add_tail(&fcport->list, &vha->vp_fcports);
5099
5100		}
5101		if (pla) {
5102			qlt_plogi_ack_link(vha, pla, fcport,
5103			    QLT_PLOGI_LINK_SAME_WWN);
5104			pla->ref_count--;
5105		}
5106	}
5107	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5108
5109	if (fcport) {
5110		fcport->id_changed = 1;
5111		fcport->scan_state = QLA_FCPORT_FOUND;
5112		fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5113		memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5114
5115		if (pla) {
5116			if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5117				u16 wd3_lo;
5118
5119				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5120				fcport->local = 0;
5121				fcport->loop_id =
5122					le16_to_cpu(
5123					    pla->iocb.u.isp24.nport_handle);
5124				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5125				wd3_lo =
5126				    le16_to_cpu(
5127					pla->iocb.u.isp24.u.prli.wd3_lo);
5128
5129				if (wd3_lo & BIT_7)
5130					fcport->conf_compl_supported = 1;
5131
5132				if ((wd3_lo & BIT_4) == 0)
5133					fcport->port_type = FCT_INITIATOR;
5134				else
5135					fcport->port_type = FCT_TARGET;
5136			}
5137			qlt_plogi_ack_unref(vha, pla);
5138		} else {
5139			fc_port_t *dfcp = NULL;
5140
5141			spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5142			tfcp = qla2x00_find_fcport_by_nportid(vha,
5143			    &e->u.new_sess.id, 1);
5144			if (tfcp && (tfcp != fcport)) {
5145				/*
5146				 * We have a conflict fcport with same NportID.
5147				 */
5148				ql_dbg(ql_dbg_disc, vha, 0xffff,
5149				    "%s %8phC found conflict b4 add. DS %d LS %d\n",
5150				    __func__, tfcp->port_name, tfcp->disc_state,
5151				    tfcp->fw_login_state);
5152
5153				switch (tfcp->disc_state) {
5154				case DSC_DELETED:
5155					break;
5156				case DSC_DELETE_PEND:
5157					fcport->login_pause = 1;
5158					tfcp->conflict = fcport;
5159					break;
5160				default:
5161					fcport->login_pause = 1;
5162					tfcp->conflict = fcport;
5163					dfcp = tfcp;
5164					break;
5165				}
5166			}
5167			spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5168			if (dfcp)
5169				qlt_schedule_sess_for_deletion(tfcp);
5170
5171			if (N2N_TOPO(vha->hw)) {
5172				fcport->flags &= ~FCF_FABRIC_DEVICE;
5173				fcport->keep_nport_handle = 1;
5174				if (vha->flags.nvme_enabled) {
5175					fcport->fc4_type =
5176					    (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5177					fcport->n2n_flag = 1;
5178				}
5179				fcport->fw_login_state = 0;
5180
5181				schedule_delayed_work(&vha->scan.scan_work, 5);
5182			} else {
5183				qla24xx_fcport_handle_login(vha, fcport);
5184			}
5185		}
5186	}
5187
5188	if (free_fcport) {
5189		qla2x00_free_fcport(fcport);
5190		if (pla) {
5191			list_del(&pla->list);
5192			kmem_cache_free(qla_tgt_plogi_cachep, pla);
5193		}
5194	}
5195}
5196
5197static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5198{
5199	struct srb *sp = e->u.iosb.sp;
5200	int rval;
5201
5202	rval = qla2x00_start_sp(sp);
5203	if (rval != QLA_SUCCESS) {
5204		ql_dbg(ql_dbg_disc, vha, 0x2043,
5205		    "%s: %s: Re-issue IOCB failed (%d).\n",
5206		    __func__, sp->name, rval);
5207		qla24xx_sp_unmap(vha, sp);
5208	}
5209}
5210
5211void
5212qla2x00_do_work(struct scsi_qla_host *vha)
5213{
5214	struct qla_work_evt *e, *tmp;
5215	unsigned long flags;
5216	LIST_HEAD(work);
5217	int rc;
5218
5219	spin_lock_irqsave(&vha->work_lock, flags);
5220	list_splice_init(&vha->work_list, &work);
5221	spin_unlock_irqrestore(&vha->work_lock, flags);
5222
5223	list_for_each_entry_safe(e, tmp, &work, list) {
5224		rc = QLA_SUCCESS;
5225		switch (e->type) {
5226		case QLA_EVT_AEN:
5227			fc_host_post_event(vha->host, fc_get_event_number(),
5228			    e->u.aen.code, e->u.aen.data);
5229			break;
5230		case QLA_EVT_IDC_ACK:
5231			qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5232			break;
5233		case QLA_EVT_ASYNC_LOGIN:
5234			qla2x00_async_login(vha, e->u.logio.fcport,
5235			    e->u.logio.data);
5236			break;
5237		case QLA_EVT_ASYNC_LOGOUT:
5238			rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5239			break;
5240		case QLA_EVT_ASYNC_ADISC:
5241			qla2x00_async_adisc(vha, e->u.logio.fcport,
5242			    e->u.logio.data);
5243			break;
5244		case QLA_EVT_UEVENT:
5245			qla2x00_uevent_emit(vha, e->u.uevent.code);
5246			break;
5247		case QLA_EVT_AENFX:
5248			qlafx00_process_aen(vha, e);
5249			break;
5250		case QLA_EVT_GPNID:
5251			qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5252			break;
5253		case QLA_EVT_UNMAP:
5254			qla24xx_sp_unmap(vha, e->u.iosb.sp);
5255			break;
5256		case QLA_EVT_RELOGIN:
5257			qla2x00_relogin(vha);
5258			break;
5259		case QLA_EVT_NEW_SESS:
5260			qla24xx_create_new_sess(vha, e);
5261			break;
5262		case QLA_EVT_GPDB:
5263			qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5264			    e->u.fcport.opt);
5265			break;
5266		case QLA_EVT_PRLI:
5267			qla24xx_async_prli(vha, e->u.fcport.fcport);
5268			break;
5269		case QLA_EVT_GPSC:
5270			qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5271			break;
5272		case QLA_EVT_GNL:
5273			qla24xx_async_gnl(vha, e->u.fcport.fcport);
5274			break;
5275		case QLA_EVT_NACK:
5276			qla24xx_do_nack_work(vha, e);
5277			break;
5278		case QLA_EVT_ASYNC_PRLO:
5279			rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5280			break;
5281		case QLA_EVT_ASYNC_PRLO_DONE:
5282			qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5283			    e->u.logio.data);
5284			break;
5285		case QLA_EVT_GPNFT:
5286			qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5287			    e->u.gpnft.sp);
5288			break;
5289		case QLA_EVT_GPNFT_DONE:
5290			qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5291			break;
5292		case QLA_EVT_GNNFT_DONE:
5293			qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5294			break;
5295		case QLA_EVT_GNNID:
5296			qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5297			break;
5298		case QLA_EVT_GFPNID:
5299			qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5300			break;
5301		case QLA_EVT_SP_RETRY:
5302			qla_sp_retry(vha, e);
5303			break;
5304		case QLA_EVT_IIDMA:
5305			qla_do_iidma_work(vha, e->u.fcport.fcport);
5306			break;
5307		case QLA_EVT_ELS_PLOGI:
5308			qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5309			    e->u.fcport.fcport, false);
5310			break;
5311		}
5312
5313		if (rc == EAGAIN) {
5314			/* put 'work' at head of 'vha->work_list' */
5315			spin_lock_irqsave(&vha->work_lock, flags);
5316			list_splice(&work, &vha->work_list);
5317			spin_unlock_irqrestore(&vha->work_lock, flags);
5318			break;
5319		}
5320		list_del_init(&e->list);
5321		if (e->flags & QLA_EVT_FLAG_FREE)
5322			kfree(e);
5323
5324		/* For each work completed decrement vha ref count */
5325		QLA_VHA_MARK_NOT_BUSY(vha);
5326	}
5327}
5328
5329int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5330{
5331	struct qla_work_evt *e;
5332
5333	e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5334
5335	if (!e) {
5336		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5337		return QLA_FUNCTION_FAILED;
5338	}
5339
5340	return qla2x00_post_work(vha, e);
5341}
5342
5343/* Relogins all the fcports of a vport
5344 * Context: dpc thread
5345 */
5346void qla2x00_relogin(struct scsi_qla_host *vha)
5347{
5348	fc_port_t       *fcport;
5349	int status, relogin_needed = 0;
5350	struct event_arg ea;
5351
5352	list_for_each_entry(fcport, &vha->vp_fcports, list) {
5353		/*
5354		 * If the port is not ONLINE then try to login
5355		 * to it if we haven't run out of retries.
5356		 */
5357		if (atomic_read(&fcport->state) != FCS_ONLINE &&
5358		    fcport->login_retry) {
5359			if (fcport->scan_state != QLA_FCPORT_FOUND ||
5360			    fcport->disc_state == DSC_LOGIN_COMPLETE)
5361				continue;
5362
5363			if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5364				fcport->disc_state == DSC_DELETE_PEND) {
5365				relogin_needed = 1;
5366			} else {
5367				if (vha->hw->current_topology != ISP_CFG_NL) {
5368					memset(&ea, 0, sizeof(ea));
5369					ea.fcport = fcport;
5370					qla24xx_handle_relogin_event(vha, &ea);
5371				} else if (vha->hw->current_topology ==
5372				    ISP_CFG_NL) {
5373					fcport->login_retry--;
5374					status =
5375					    qla2x00_local_device_login(vha,
5376						fcport);
5377					if (status == QLA_SUCCESS) {
5378						fcport->old_loop_id =
5379						    fcport->loop_id;
5380						ql_dbg(ql_dbg_disc, vha, 0x2003,
5381						    "Port login OK: logged in ID 0x%x.\n",
5382						    fcport->loop_id);
5383						qla2x00_update_fcport
5384							(vha, fcport);
5385					} else if (status == 1) {
5386						set_bit(RELOGIN_NEEDED,
5387						    &vha->dpc_flags);
5388						/* retry the login again */
5389						ql_dbg(ql_dbg_disc, vha, 0x2007,
5390						    "Retrying %d login again loop_id 0x%x.\n",
5391						    fcport->login_retry,
5392						    fcport->loop_id);
5393					} else {
5394						fcport->login_retry = 0;
5395					}
5396
5397					if (fcport->login_retry == 0 &&
5398					    status != QLA_SUCCESS)
5399						qla2x00_clear_loop_id(fcport);
5400				}
5401			}
5402		}
5403		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5404			break;
5405	}
5406
5407	if (relogin_needed)
5408		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5409
5410	ql_dbg(ql_dbg_disc, vha, 0x400e,
5411	    "Relogin end.\n");
5412}
5413
5414/* Schedule work on any of the dpc-workqueues */
5415void
5416qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5417{
5418	struct qla_hw_data *ha = base_vha->hw;
5419
5420	switch (work_code) {
5421	case MBA_IDC_AEN: /* 0x8200 */
5422		if (ha->dpc_lp_wq)
5423			queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5424		break;
5425
5426	case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5427		if (!ha->flags.nic_core_reset_hdlr_active) {
5428			if (ha->dpc_hp_wq)
5429				queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5430		} else
5431			ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5432			    "NIC Core reset is already active. Skip "
5433			    "scheduling it again.\n");
5434		break;
5435	case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5436		if (ha->dpc_hp_wq)
5437			queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5438		break;
5439	case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5440		if (ha->dpc_hp_wq)
5441			queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5442		break;
5443	default:
5444		ql_log(ql_log_warn, base_vha, 0xb05f,
5445		    "Unknown work-code=0x%x.\n", work_code);
5446	}
5447
5448	return;
5449}
5450
5451/* Work: Perform NIC Core Unrecoverable state handling */
5452void
5453qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5454{
5455	struct qla_hw_data *ha =
5456		container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5457	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5458	uint32_t dev_state = 0;
5459
5460	qla83xx_idc_lock(base_vha, 0);
5461	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5462	qla83xx_reset_ownership(base_vha);
5463	if (ha->flags.nic_core_reset_owner) {
5464		ha->flags.nic_core_reset_owner = 0;
5465		qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5466		    QLA8XXX_DEV_FAILED);
5467		ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5468		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5469	}
5470	qla83xx_idc_unlock(base_vha, 0);
5471}
5472
5473/* Work: Execute IDC state handler */
5474void
5475qla83xx_idc_state_handler_work(struct work_struct *work)
5476{
5477	struct qla_hw_data *ha =
5478		container_of(work, struct qla_hw_data, idc_state_handler);
5479	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5480	uint32_t dev_state = 0;
5481
5482	qla83xx_idc_lock(base_vha, 0);
5483	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5484	if (dev_state == QLA8XXX_DEV_FAILED ||
5485			dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5486		qla83xx_idc_state_handler(base_vha);
5487	qla83xx_idc_unlock(base_vha, 0);
5488}
5489
5490static int
5491qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5492{
5493	int rval = QLA_SUCCESS;
5494	unsigned long heart_beat_wait = jiffies + (1 * HZ);
5495	uint32_t heart_beat_counter1, heart_beat_counter2;
5496
5497	do {
5498		if (time_after(jiffies, heart_beat_wait)) {
5499			ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5500			    "Nic Core f/w is not alive.\n");
5501			rval = QLA_FUNCTION_FAILED;
5502			break;
5503		}
5504
5505		qla83xx_idc_lock(base_vha, 0);
5506		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5507		    &heart_beat_counter1);
5508		qla83xx_idc_unlock(base_vha, 0);
5509		msleep(100);
5510		qla83xx_idc_lock(base_vha, 0);
5511		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5512		    &heart_beat_counter2);
5513		qla83xx_idc_unlock(base_vha, 0);
5514	} while (heart_beat_counter1 == heart_beat_counter2);
5515
5516	return rval;
5517}
5518
5519/* Work: Perform NIC Core Reset handling */
5520void
5521qla83xx_nic_core_reset_work(struct work_struct *work)
5522{
5523	struct qla_hw_data *ha =
5524		container_of(work, struct qla_hw_data, nic_core_reset);
5525	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5526	uint32_t dev_state = 0;
5527
5528	if (IS_QLA2031(ha)) {
5529		if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5530			ql_log(ql_log_warn, base_vha, 0xb081,
5531			    "Failed to dump mctp\n");
5532		return;
5533	}
5534
5535	if (!ha->flags.nic_core_reset_hdlr_active) {
5536		if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5537			qla83xx_idc_lock(base_vha, 0);
5538			qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5539			    &dev_state);
5540			qla83xx_idc_unlock(base_vha, 0);
5541			if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5542				ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5543				    "Nic Core f/w is alive.\n");
5544				return;
5545			}
5546		}
5547
5548		ha->flags.nic_core_reset_hdlr_active = 1;
5549		if (qla83xx_nic_core_reset(base_vha)) {
5550			/* NIC Core reset failed. */
5551			ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5552			    "NIC Core reset failed.\n");
5553		}
5554		ha->flags.nic_core_reset_hdlr_active = 0;
5555	}
5556}
5557
5558/* Work: Handle 8200 IDC aens */
5559void
5560qla83xx_service_idc_aen(struct work_struct *work)
5561{
5562	struct qla_hw_data *ha =
5563		container_of(work, struct qla_hw_data, idc_aen);
5564	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5565	uint32_t dev_state, idc_control;
5566
5567	qla83xx_idc_lock(base_vha, 0);
5568	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5569	qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5570	qla83xx_idc_unlock(base_vha, 0);
5571	if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5572		if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5573			ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5574			    "Application requested NIC Core Reset.\n");
5575			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5576		} else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5577		    QLA_SUCCESS) {
5578			ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5579			    "Other protocol driver requested NIC Core Reset.\n");
5580			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5581		}
5582	} else if (dev_state == QLA8XXX_DEV_FAILED ||
5583			dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5584		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5585	}
5586}
5587
5588static void
5589qla83xx_wait_logic(void)
5590{
5591	int i;
5592
5593	/* Yield CPU */
5594	if (!in_interrupt()) {
5595		/*
5596		 * Wait about 200ms before retrying again.
5597		 * This controls the number of retries for single
5598		 * lock operation.
5599		 */
5600		msleep(100);
5601		schedule();
5602	} else {
5603		for (i = 0; i < 20; i++)
5604			cpu_relax(); /* This a nop instr on i386 */
5605	}
5606}
5607
5608static int
5609qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5610{
5611	int rval;
5612	uint32_t data;
5613	uint32_t idc_lck_rcvry_stage_mask = 0x3;
5614	uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5615	struct qla_hw_data *ha = base_vha->hw;
5616
5617	ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5618	    "Trying force recovery of the IDC lock.\n");
5619
5620	rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5621	if (rval)
5622		return rval;
5623
5624	if ((data & idc_lck_rcvry_stage_mask) > 0) {
5625		return QLA_SUCCESS;
5626	} else {
5627		data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5628		rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5629		    data);
5630		if (rval)
5631			return rval;
5632
5633		msleep(200);
5634
5635		rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5636		    &data);
5637		if (rval)
5638			return rval;
5639
5640		if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5641			data &= (IDC_LOCK_RECOVERY_STAGE2