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/drivers/isdn/hisax/isar.c

http://github.com/mirrors/linux
C | 1911 lines | 1799 code | 76 blank | 36 comment | 442 complexity | 4751fb10c7e10d41699a10ff018803cd MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. /* $Id: isar.c,v 1.22.2.6 2004/02/11 13:21:34 keil Exp $
  2. *
  3. * isar.c ISAR (Siemens PSB 7110) specific routines
  4. *
  5. * Author Karsten Keil (keil@isdn4linux.de)
  6. *
  7. * This file is (c) under GNU General Public License
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include "hisax.h"
  12. #include "isar.h"
  13. #include "isdnl1.h"
  14. #include <linux/interrupt.h>
  15. #include <linux/slab.h>
  16. #define DBG_LOADFIRM 0
  17. #define DUMP_MBOXFRAME 2
  18. #define DLE 0x10
  19. #define ETX 0x03
  20. #define FAXMODCNT 13
  21. static const u_char faxmodulation[] = {3, 24, 48, 72, 73, 74, 96, 97, 98, 121, 122, 145, 146};
  22. static u_int modmask = 0x1fff;
  23. static int frm_extra_delay = 2;
  24. static int para_TOA = 6;
  25. static const u_char *FC1_CMD[] = {"FAE", "FTS", "FRS", "FTM", "FRM", "FTH", "FRH", "CTRL"};
  26. static void isar_setup(struct IsdnCardState *cs);
  27. static void isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para);
  28. static void ll_deliver_faxstat(struct BCState *bcs, u_char status);
  29. static inline int
  30. waitforHIA(struct IsdnCardState *cs, int timeout)
  31. {
  32. while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) {
  33. udelay(1);
  34. timeout--;
  35. }
  36. if (!timeout)
  37. printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
  38. return (timeout);
  39. }
  40. static int
  41. sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len,
  42. u_char *msg)
  43. {
  44. int i;
  45. if (!waitforHIA(cs, 4000))
  46. return (0);
  47. #if DUMP_MBOXFRAME
  48. if (cs->debug & L1_DEB_HSCX)
  49. debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
  50. #endif
  51. cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg);
  52. cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len);
  53. cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0);
  54. if (msg && len) {
  55. cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]);
  56. for (i = 1; i < len; i++)
  57. cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]);
  58. #if DUMP_MBOXFRAME > 1
  59. if (cs->debug & L1_DEB_HSCX_FIFO) {
  60. char tmp[256], *t;
  61. i = len;
  62. while (i > 0) {
  63. t = tmp;
  64. t += sprintf(t, "sendmbox cnt %d", len);
  65. QuickHex(t, &msg[len-i], (i > 64) ? 64 : i);
  66. debugl1(cs, "%s", tmp);
  67. i -= 64;
  68. }
  69. }
  70. #endif
  71. }
  72. cs->BC_Write_Reg(cs, 1, ISAR_HIS, his);
  73. waitforHIA(cs, 10000);
  74. return (1);
  75. }
  76. /* Call only with IRQ disabled !!! */
  77. static inline void
  78. rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
  79. {
  80. int i;
  81. cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0);
  82. if (msg && ireg->clsb) {
  83. msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX);
  84. for (i = 1; i < ireg->clsb; i++)
  85. msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX);
  86. #if DUMP_MBOXFRAME > 1
  87. if (cs->debug & L1_DEB_HSCX_FIFO) {
  88. char tmp[256], *t;
  89. i = ireg->clsb;
  90. while (i > 0) {
  91. t = tmp;
  92. t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
  93. QuickHex(t, &msg[ireg->clsb - i], (i > 64) ? 64 : i);
  94. debugl1(cs, "%s", tmp);
  95. i -= 64;
  96. }
  97. }
  98. #endif
  99. }
  100. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  101. }
  102. /* Call only with IRQ disabled !!! */
  103. static inline void
  104. get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
  105. {
  106. ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
  107. ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
  108. ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
  109. #if DUMP_MBOXFRAME
  110. if (cs->debug & L1_DEB_HSCX)
  111. debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
  112. ireg->clsb);
  113. #endif
  114. }
  115. static int
  116. waitrecmsg(struct IsdnCardState *cs, u_char *len,
  117. u_char *msg, int maxdelay)
  118. {
  119. int timeout = 0;
  120. struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
  121. while ((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
  122. (timeout++ < maxdelay))
  123. udelay(1);
  124. if (timeout > maxdelay) {
  125. printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
  126. return (0);
  127. }
  128. get_irq_infos(cs, ir);
  129. rcv_mbox(cs, ir, msg);
  130. *len = ir->clsb;
  131. return (1);
  132. }
  133. int
  134. ISARVersion(struct IsdnCardState *cs, char *s)
  135. {
  136. int ver;
  137. u_char msg[] = ISAR_MSG_HWVER;
  138. u_char tmp[64];
  139. u_char len;
  140. u_long flags;
  141. int debug;
  142. cs->cardmsg(cs, CARD_RESET, NULL);
  143. spin_lock_irqsave(&cs->lock, flags);
  144. /* disable ISAR IRQ */
  145. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  146. debug = cs->debug;
  147. cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
  148. if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) {
  149. spin_unlock_irqrestore(&cs->lock, flags);
  150. return (-1);
  151. }
  152. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  153. spin_unlock_irqrestore(&cs->lock, flags);
  154. return (-2);
  155. }
  156. cs->debug = debug;
  157. if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
  158. if (len == 1) {
  159. ver = tmp[0] & 0xf;
  160. printk(KERN_INFO "%s ISAR version %d\n", s, ver);
  161. } else
  162. ver = -3;
  163. } else
  164. ver = -4;
  165. spin_unlock_irqrestore(&cs->lock, flags);
  166. return (ver);
  167. }
  168. static int
  169. isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf)
  170. {
  171. int cfu_ret, ret, size, cnt, debug;
  172. u_char len, nom, noc;
  173. u_short sadr, left, *sp;
  174. u_char __user *p = buf;
  175. u_char *msg, *tmpmsg, *mp, tmp[64];
  176. u_long flags;
  177. struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
  178. struct {u_short sadr;
  179. u_short len;
  180. u_short d_key;
  181. } blk_head;
  182. #define BLK_HEAD_SIZE 6
  183. if (1 != (ret = ISARVersion(cs, "Testing"))) {
  184. printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
  185. return (1);
  186. }
  187. debug = cs->debug;
  188. #if DBG_LOADFIRM < 2
  189. cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
  190. #endif
  191. cfu_ret = copy_from_user(&size, p, sizeof(int));
  192. if (cfu_ret) {
  193. printk(KERN_ERR "isar_load_firmware copy_from_user ret %d\n", cfu_ret);
  194. return -EFAULT;
  195. }
  196. p += sizeof(int);
  197. printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
  198. cnt = 0;
  199. /* disable ISAR IRQ */
  200. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  201. if (!(msg = kmalloc(256, GFP_KERNEL))) {
  202. printk(KERN_ERR"isar_load_firmware no buffer\n");
  203. return (1);
  204. }
  205. if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
  206. printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
  207. kfree(msg);
  208. return (1);
  209. }
  210. spin_lock_irqsave(&cs->lock, flags);
  211. /* disable ISAR IRQ */
  212. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  213. spin_unlock_irqrestore(&cs->lock, flags);
  214. while (cnt < size) {
  215. if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
  216. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  217. goto reterror;
  218. }
  219. #ifdef __BIG_ENDIAN
  220. sadr = (blk_head.sadr & 0xff) * 256 + blk_head.sadr / 256;
  221. blk_head.sadr = sadr;
  222. sadr = (blk_head.len & 0xff) * 256 + blk_head.len / 256;
  223. blk_head.len = sadr;
  224. sadr = (blk_head.d_key & 0xff) * 256 + blk_head.d_key / 256;
  225. blk_head.d_key = sadr;
  226. #endif /* __BIG_ENDIAN */
  227. cnt += BLK_HEAD_SIZE;
  228. p += BLK_HEAD_SIZE;
  229. printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
  230. blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
  231. sadr = blk_head.sadr;
  232. left = blk_head.len;
  233. spin_lock_irqsave(&cs->lock, flags);
  234. if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
  235. printk(KERN_ERR"isar sendmsg dkey failed\n");
  236. ret = 1; goto reterr_unlock;
  237. }
  238. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  239. printk(KERN_ERR"isar waitrecmsg dkey failed\n");
  240. ret = 1; goto reterr_unlock;
  241. }
  242. if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
  243. printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
  244. ireg->iis, ireg->cmsb, len);
  245. ret = 1; goto reterr_unlock;
  246. }
  247. spin_unlock_irqrestore(&cs->lock, flags);
  248. while (left > 0) {
  249. if (left > 126)
  250. noc = 126;
  251. else
  252. noc = left;
  253. nom = 2 * noc;
  254. mp = msg;
  255. *mp++ = sadr / 256;
  256. *mp++ = sadr % 256;
  257. left -= noc;
  258. *mp++ = noc;
  259. if ((ret = copy_from_user(tmpmsg, p, nom))) {
  260. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  261. goto reterror;
  262. }
  263. p += nom;
  264. cnt += nom;
  265. nom += 3;
  266. sp = (u_short *)tmpmsg;
  267. #if DBG_LOADFIRM
  268. printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n",
  269. noc, sadr, left);
  270. #endif
  271. sadr += noc;
  272. while (noc) {
  273. #ifdef __BIG_ENDIAN
  274. *mp++ = *sp % 256;
  275. *mp++ = *sp / 256;
  276. #else
  277. *mp++ = *sp / 256;
  278. *mp++ = *sp % 256;
  279. #endif /* __BIG_ENDIAN */
  280. sp++;
  281. noc--;
  282. }
  283. spin_lock_irqsave(&cs->lock, flags);
  284. if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
  285. printk(KERN_ERR"isar sendmsg prog failed\n");
  286. ret = 1; goto reterr_unlock;
  287. }
  288. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  289. printk(KERN_ERR"isar waitrecmsg prog failed\n");
  290. ret = 1; goto reterr_unlock;
  291. }
  292. if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
  293. printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
  294. ireg->iis, ireg->cmsb, len);
  295. ret = 1; goto reterr_unlock;
  296. }
  297. spin_unlock_irqrestore(&cs->lock, flags);
  298. }
  299. printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
  300. blk_head.len);
  301. }
  302. /* 10ms delay */
  303. cnt = 10;
  304. while (cnt--)
  305. udelay(1000);
  306. msg[0] = 0xff;
  307. msg[1] = 0xfe;
  308. ireg->bstat = 0;
  309. spin_lock_irqsave(&cs->lock, flags);
  310. if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
  311. printk(KERN_ERR"isar sendmsg start dsp failed\n");
  312. ret = 1; goto reterr_unlock;
  313. }
  314. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  315. printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
  316. ret = 1; goto reterr_unlock;
  317. }
  318. if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
  319. printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
  320. ireg->iis, ireg->cmsb, len);
  321. ret = 1; goto reterr_unlock;
  322. } else
  323. printk(KERN_DEBUG"isar start dsp success\n");
  324. /* NORMAL mode entered */
  325. /* Enable IRQs of ISAR */
  326. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
  327. spin_unlock_irqrestore(&cs->lock, flags);
  328. cnt = 1000; /* max 1s */
  329. while ((!ireg->bstat) && cnt) {
  330. udelay(1000);
  331. cnt--;
  332. }
  333. if (!cnt) {
  334. printk(KERN_ERR"isar no general status event received\n");
  335. ret = 1; goto reterror;
  336. } else {
  337. printk(KERN_DEBUG"isar general status event %x\n",
  338. ireg->bstat);
  339. }
  340. /* 10ms delay */
  341. cnt = 10;
  342. while (cnt--)
  343. udelay(1000);
  344. spin_lock_irqsave(&cs->lock, flags);
  345. ireg->iis = 0;
  346. if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
  347. printk(KERN_ERR"isar sendmsg self tst failed\n");
  348. ret = 1; goto reterr_unlock;
  349. }
  350. cnt = 10000; /* max 100 ms */
  351. spin_unlock_irqrestore(&cs->lock, flags);
  352. while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
  353. udelay(10);
  354. cnt--;
  355. }
  356. udelay(1000);
  357. if (!cnt) {
  358. printk(KERN_ERR"isar no self tst response\n");
  359. ret = 1; goto reterror;
  360. }
  361. if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
  362. && (ireg->par[0] == 0)) {
  363. printk(KERN_DEBUG"isar selftest OK\n");
  364. } else {
  365. printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
  366. ireg->cmsb, ireg->clsb, ireg->par[0]);
  367. ret = 1; goto reterror;
  368. }
  369. spin_lock_irqsave(&cs->lock, flags);
  370. ireg->iis = 0;
  371. if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
  372. printk(KERN_ERR"isar RQST SVN failed\n");
  373. ret = 1; goto reterr_unlock;
  374. }
  375. spin_unlock_irqrestore(&cs->lock, flags);
  376. cnt = 30000; /* max 300 ms */
  377. while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
  378. udelay(10);
  379. cnt--;
  380. }
  381. udelay(1000);
  382. if (!cnt) {
  383. printk(KERN_ERR"isar no SVN response\n");
  384. ret = 1; goto reterror;
  385. } else {
  386. if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
  387. printk(KERN_DEBUG"isar software version %#x\n",
  388. ireg->par[0]);
  389. else {
  390. printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
  391. ireg->cmsb, ireg->clsb, cnt);
  392. ret = 1; goto reterror;
  393. }
  394. }
  395. spin_lock_irqsave(&cs->lock, flags);
  396. cs->debug = debug;
  397. isar_setup(cs);
  398. ret = 0;
  399. reterr_unlock:
  400. spin_unlock_irqrestore(&cs->lock, flags);
  401. reterror:
  402. cs->debug = debug;
  403. if (ret)
  404. /* disable ISAR IRQ */
  405. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  406. kfree(msg);
  407. kfree(tmpmsg);
  408. return (ret);
  409. }
  410. #define B_LL_NOCARRIER 8
  411. #define B_LL_CONNECT 9
  412. #define B_LL_OK 10
  413. static void
  414. isar_bh(struct work_struct *work)
  415. {
  416. struct BCState *bcs = container_of(work, struct BCState, tqueue);
  417. BChannel_bh(work);
  418. if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event))
  419. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR);
  420. if (test_and_clear_bit(B_LL_CONNECT, &bcs->event))
  421. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  422. if (test_and_clear_bit(B_LL_OK, &bcs->event))
  423. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK);
  424. }
  425. static void
  426. send_DLE_ETX(struct BCState *bcs)
  427. {
  428. u_char dleetx[2] = {DLE, ETX};
  429. struct sk_buff *skb;
  430. if ((skb = dev_alloc_skb(2))) {
  431. memcpy(skb_put(skb, 2), dleetx, 2);
  432. skb_queue_tail(&bcs->rqueue, skb);
  433. schedule_event(bcs, B_RCVBUFREADY);
  434. } else {
  435. printk(KERN_WARNING "HiSax: skb out of memory\n");
  436. }
  437. }
  438. static inline int
  439. dle_count(unsigned char *buf, int len)
  440. {
  441. int count = 0;
  442. while (len--)
  443. if (*buf++ == DLE)
  444. count++;
  445. return count;
  446. }
  447. static inline void
  448. insert_dle(unsigned char *dest, unsigned char *src, int count) {
  449. /* <DLE> in input stream have to be flagged as <DLE><DLE> */
  450. while (count--) {
  451. *dest++ = *src;
  452. if (*src++ == DLE)
  453. *dest++ = DLE;
  454. }
  455. }
  456. static void
  457. isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
  458. {
  459. u_char *ptr;
  460. struct sk_buff *skb;
  461. struct isar_reg *ireg = bcs->hw.isar.reg;
  462. if (!ireg->clsb) {
  463. debugl1(cs, "isar zero len frame");
  464. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  465. return;
  466. }
  467. switch (bcs->mode) {
  468. case L1_MODE_NULL:
  469. debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
  470. ireg->iis, ireg->cmsb, ireg->clsb);
  471. printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
  472. ireg->iis, ireg->cmsb, ireg->clsb);
  473. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  474. break;
  475. case L1_MODE_TRANS:
  476. case L1_MODE_V32:
  477. if ((skb = dev_alloc_skb(ireg->clsb))) {
  478. rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
  479. skb_queue_tail(&bcs->rqueue, skb);
  480. schedule_event(bcs, B_RCVBUFREADY);
  481. } else {
  482. printk(KERN_WARNING "HiSax: skb out of memory\n");
  483. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  484. }
  485. break;
  486. case L1_MODE_HDLC:
  487. if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
  488. if (cs->debug & L1_DEB_WARN)
  489. debugl1(cs, "isar_rcv_frame: incoming packet too large");
  490. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  491. bcs->hw.isar.rcvidx = 0;
  492. } else if (ireg->cmsb & HDLC_ERROR) {
  493. if (cs->debug & L1_DEB_WARN)
  494. debugl1(cs, "isar frame error %x len %d",
  495. ireg->cmsb, ireg->clsb);
  496. #ifdef ERROR_STATISTIC
  497. if (ireg->cmsb & HDLC_ERR_RER)
  498. bcs->err_inv++;
  499. if (ireg->cmsb & HDLC_ERR_CER)
  500. bcs->err_crc++;
  501. #endif
  502. bcs->hw.isar.rcvidx = 0;
  503. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  504. } else {
  505. if (ireg->cmsb & HDLC_FSD)
  506. bcs->hw.isar.rcvidx = 0;
  507. ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
  508. bcs->hw.isar.rcvidx += ireg->clsb;
  509. rcv_mbox(cs, ireg, ptr);
  510. if (ireg->cmsb & HDLC_FED) {
  511. if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
  512. if (cs->debug & L1_DEB_WARN)
  513. debugl1(cs, "isar frame to short %d",
  514. bcs->hw.isar.rcvidx);
  515. } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx - 2))) {
  516. printk(KERN_WARNING "ISAR: receive out of memory\n");
  517. } else {
  518. memcpy(skb_put(skb, bcs->hw.isar.rcvidx - 2),
  519. bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx - 2);
  520. skb_queue_tail(&bcs->rqueue, skb);
  521. schedule_event(bcs, B_RCVBUFREADY);
  522. }
  523. bcs->hw.isar.rcvidx = 0;
  524. }
  525. }
  526. break;
  527. case L1_MODE_FAX:
  528. if (bcs->hw.isar.state != STFAX_ACTIV) {
  529. if (cs->debug & L1_DEB_WARN)
  530. debugl1(cs, "isar_rcv_frame: not ACTIV");
  531. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  532. bcs->hw.isar.rcvidx = 0;
  533. break;
  534. }
  535. if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
  536. rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
  537. bcs->hw.isar.rcvidx = ireg->clsb +
  538. dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
  539. if (cs->debug & L1_DEB_HSCX)
  540. debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)",
  541. ireg->clsb, bcs->hw.isar.rcvidx);
  542. if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
  543. insert_dle((u_char *)skb_put(skb, bcs->hw.isar.rcvidx),
  544. bcs->hw.isar.rcvbuf, ireg->clsb);
  545. skb_queue_tail(&bcs->rqueue, skb);
  546. schedule_event(bcs, B_RCVBUFREADY);
  547. if (ireg->cmsb & SART_NMD) { /* ABORT */
  548. if (cs->debug & L1_DEB_WARN)
  549. debugl1(cs, "isar_rcv_frame: no more data");
  550. bcs->hw.isar.rcvidx = 0;
  551. send_DLE_ETX(bcs);
  552. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
  553. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
  554. 0, NULL);
  555. bcs->hw.isar.state = STFAX_ESCAPE;
  556. schedule_event(bcs, B_LL_NOCARRIER);
  557. }
  558. } else {
  559. printk(KERN_WARNING "HiSax: skb out of memory\n");
  560. }
  561. break;
  562. }
  563. if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) {
  564. if (cs->debug & L1_DEB_WARN)
  565. debugl1(cs, "isar_rcv_frame: unknown fax mode %x",
  566. bcs->hw.isar.cmd);
  567. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  568. bcs->hw.isar.rcvidx = 0;
  569. break;
  570. }
  571. /* PCTRL_CMD_FRH */
  572. if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
  573. if (cs->debug & L1_DEB_WARN)
  574. debugl1(cs, "isar_rcv_frame: incoming packet too large");
  575. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  576. bcs->hw.isar.rcvidx = 0;
  577. } else if (ireg->cmsb & HDLC_ERROR) {
  578. if (cs->debug & L1_DEB_WARN)
  579. debugl1(cs, "isar frame error %x len %d",
  580. ireg->cmsb, ireg->clsb);
  581. bcs->hw.isar.rcvidx = 0;
  582. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  583. } else {
  584. if (ireg->cmsb & HDLC_FSD) {
  585. bcs->hw.isar.rcvidx = 0;
  586. }
  587. ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
  588. bcs->hw.isar.rcvidx += ireg->clsb;
  589. rcv_mbox(cs, ireg, ptr);
  590. if (ireg->cmsb & HDLC_FED) {
  591. int len = bcs->hw.isar.rcvidx +
  592. dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx);
  593. if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
  594. if (cs->debug & L1_DEB_WARN)
  595. debugl1(cs, "isar frame to short %d",
  596. bcs->hw.isar.rcvidx);
  597. printk(KERN_WARNING "ISAR: frame to short %d\n",
  598. bcs->hw.isar.rcvidx);
  599. } else if (!(skb = dev_alloc_skb(len))) {
  600. printk(KERN_WARNING "ISAR: receive out of memory\n");
  601. } else {
  602. insert_dle((u_char *)skb_put(skb, len),
  603. bcs->hw.isar.rcvbuf,
  604. bcs->hw.isar.rcvidx);
  605. skb_queue_tail(&bcs->rqueue, skb);
  606. schedule_event(bcs, B_RCVBUFREADY);
  607. send_DLE_ETX(bcs);
  608. schedule_event(bcs, B_LL_OK);
  609. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  610. }
  611. bcs->hw.isar.rcvidx = 0;
  612. }
  613. }
  614. if (ireg->cmsb & SART_NMD) { /* ABORT */
  615. if (cs->debug & L1_DEB_WARN)
  616. debugl1(cs, "isar_rcv_frame: no more data");
  617. bcs->hw.isar.rcvidx = 0;
  618. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
  619. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
  620. bcs->hw.isar.state = STFAX_ESCAPE;
  621. if (test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag)) {
  622. send_DLE_ETX(bcs);
  623. schedule_event(bcs, B_LL_NOCARRIER);
  624. }
  625. }
  626. break;
  627. default:
  628. printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
  629. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  630. break;
  631. }
  632. }
  633. void
  634. isar_fill_fifo(struct BCState *bcs)
  635. {
  636. struct IsdnCardState *cs = bcs->cs;
  637. int count;
  638. u_char msb;
  639. u_char *ptr;
  640. if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
  641. debugl1(cs, "isar_fill_fifo");
  642. if (!bcs->tx_skb)
  643. return;
  644. if (bcs->tx_skb->len <= 0)
  645. return;
  646. if (!(bcs->hw.isar.reg->bstat &
  647. (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
  648. return;
  649. if (bcs->tx_skb->len > bcs->hw.isar.mml) {
  650. msb = 0;
  651. count = bcs->hw.isar.mml;
  652. } else {
  653. count = bcs->tx_skb->len;
  654. msb = HDLC_FED;
  655. }
  656. ptr = bcs->tx_skb->data;
  657. if (!bcs->hw.isar.txcnt) {
  658. msb |= HDLC_FST;
  659. if ((bcs->mode == L1_MODE_FAX) &&
  660. (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) {
  661. if (bcs->tx_skb->len > 1) {
  662. if ((ptr[0] == 0xff) && (ptr[1] == 0x13))
  663. /* last frame */
  664. test_and_set_bit(BC_FLG_LASTDATA,
  665. &bcs->Flag);
  666. }
  667. }
  668. }
  669. skb_pull(bcs->tx_skb, count);
  670. bcs->tx_cnt -= count;
  671. bcs->hw.isar.txcnt += count;
  672. switch (bcs->mode) {
  673. case L1_MODE_NULL:
  674. printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
  675. break;
  676. case L1_MODE_TRANS:
  677. case L1_MODE_V32:
  678. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  679. 0, count, ptr);
  680. break;
  681. case L1_MODE_HDLC:
  682. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  683. msb, count, ptr);
  684. break;
  685. case L1_MODE_FAX:
  686. if (bcs->hw.isar.state != STFAX_ACTIV) {
  687. if (cs->debug & L1_DEB_WARN)
  688. debugl1(cs, "isar_fill_fifo: not ACTIV");
  689. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  690. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  691. msb, count, ptr);
  692. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
  693. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  694. 0, count, ptr);
  695. } else {
  696. if (cs->debug & L1_DEB_WARN)
  697. debugl1(cs, "isar_fill_fifo: not FTH/FTM");
  698. }
  699. break;
  700. default:
  701. if (cs->debug)
  702. debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode);
  703. printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode);
  704. break;
  705. }
  706. }
  707. static inline
  708. struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath)
  709. {
  710. if ((!dpath) || (dpath == 3))
  711. return (NULL);
  712. if (cs->bcs[0].hw.isar.dpath == dpath)
  713. return (&cs->bcs[0]);
  714. if (cs->bcs[1].hw.isar.dpath == dpath)
  715. return (&cs->bcs[1]);
  716. return (NULL);
  717. }
  718. static void
  719. send_frames(struct BCState *bcs)
  720. {
  721. if (bcs->tx_skb) {
  722. if (bcs->tx_skb->len) {
  723. isar_fill_fifo(bcs);
  724. return;
  725. } else {
  726. if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
  727. (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
  728. u_long flags;
  729. spin_lock_irqsave(&bcs->aclock, flags);
  730. bcs->ackcnt += bcs->hw.isar.txcnt;
  731. spin_unlock_irqrestore(&bcs->aclock, flags);
  732. schedule_event(bcs, B_ACKPENDING);
  733. }
  734. if (bcs->mode == L1_MODE_FAX) {
  735. if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  736. if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
  737. test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
  738. }
  739. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
  740. if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) {
  741. test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag);
  742. test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
  743. }
  744. }
  745. }
  746. dev_kfree_skb_any(bcs->tx_skb);
  747. bcs->hw.isar.txcnt = 0;
  748. bcs->tx_skb = NULL;
  749. }
  750. }
  751. if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
  752. bcs->hw.isar.txcnt = 0;
  753. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  754. isar_fill_fifo(bcs);
  755. } else {
  756. if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) {
  757. if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
  758. if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) {
  759. u_char dummy = 0;
  760. sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) |
  761. ISAR_HIS_SDATA, 0x01, 1, &dummy);
  762. }
  763. test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag);
  764. } else {
  765. schedule_event(bcs, B_LL_CONNECT);
  766. }
  767. }
  768. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  769. schedule_event(bcs, B_XMTBUFREADY);
  770. }
  771. }
  772. static inline void
  773. check_send(struct IsdnCardState *cs, u_char rdm)
  774. {
  775. struct BCState *bcs;
  776. if (rdm & BSTAT_RDM1) {
  777. if ((bcs = sel_bcs_isar(cs, 1))) {
  778. if (bcs->mode) {
  779. send_frames(bcs);
  780. }
  781. }
  782. }
  783. if (rdm & BSTAT_RDM2) {
  784. if ((bcs = sel_bcs_isar(cs, 2))) {
  785. if (bcs->mode) {
  786. send_frames(bcs);
  787. }
  788. }
  789. }
  790. }
  791. static const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200",
  792. "NODEF4", "300", "600", "1200", "2400",
  793. "4800", "7200", "9600nt", "9600t", "12000",
  794. "14400", "WRONG"};
  795. static const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
  796. "Bell103", "V23", "Bell202", "V17", "V29",
  797. "V27ter"};
  798. static void
  799. isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
  800. struct IsdnCardState *cs = bcs->cs;
  801. u_char ril = ireg->par[0];
  802. u_char rim;
  803. if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
  804. return;
  805. if (ril > 14) {
  806. if (cs->debug & L1_DEB_WARN)
  807. debugl1(cs, "wrong pstrsp ril=%d", ril);
  808. ril = 15;
  809. }
  810. switch (ireg->par[1]) {
  811. case 0:
  812. rim = 0;
  813. break;
  814. case 0x20:
  815. rim = 2;
  816. break;
  817. case 0x40:
  818. rim = 3;
  819. break;
  820. case 0x41:
  821. rim = 4;
  822. break;
  823. case 0x51:
  824. rim = 5;
  825. break;
  826. case 0x61:
  827. rim = 6;
  828. break;
  829. case 0x71:
  830. rim = 7;
  831. break;
  832. case 0x82:
  833. rim = 8;
  834. break;
  835. case 0x92:
  836. rim = 9;
  837. break;
  838. case 0xa2:
  839. rim = 10;
  840. break;
  841. default:
  842. rim = 1;
  843. break;
  844. }
  845. sprintf(bcs->hw.isar.conmsg, "%s %s", dmril[ril], dmrim[rim]);
  846. bcs->conmsg = bcs->hw.isar.conmsg;
  847. if (cs->debug & L1_DEB_HSCX)
  848. debugl1(cs, "pump strsp %s", bcs->conmsg);
  849. }
  850. static void
  851. isar_pump_statev_modem(struct BCState *bcs, u_char devt) {
  852. struct IsdnCardState *cs = bcs->cs;
  853. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  854. switch (devt) {
  855. case PSEV_10MS_TIMER:
  856. if (cs->debug & L1_DEB_HSCX)
  857. debugl1(cs, "pump stev TIMER");
  858. break;
  859. case PSEV_CON_ON:
  860. if (cs->debug & L1_DEB_HSCX)
  861. debugl1(cs, "pump stev CONNECT");
  862. l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
  863. break;
  864. case PSEV_CON_OFF:
  865. if (cs->debug & L1_DEB_HSCX)
  866. debugl1(cs, "pump stev NO CONNECT");
  867. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  868. l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
  869. break;
  870. case PSEV_V24_OFF:
  871. if (cs->debug & L1_DEB_HSCX)
  872. debugl1(cs, "pump stev V24 OFF");
  873. break;
  874. case PSEV_CTS_ON:
  875. if (cs->debug & L1_DEB_HSCX)
  876. debugl1(cs, "pump stev CTS ON");
  877. break;
  878. case PSEV_CTS_OFF:
  879. if (cs->debug & L1_DEB_HSCX)
  880. debugl1(cs, "pump stev CTS OFF");
  881. break;
  882. case PSEV_DCD_ON:
  883. if (cs->debug & L1_DEB_HSCX)
  884. debugl1(cs, "pump stev CARRIER ON");
  885. test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
  886. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  887. break;
  888. case PSEV_DCD_OFF:
  889. if (cs->debug & L1_DEB_HSCX)
  890. debugl1(cs, "pump stev CARRIER OFF");
  891. break;
  892. case PSEV_DSR_ON:
  893. if (cs->debug & L1_DEB_HSCX)
  894. debugl1(cs, "pump stev DSR ON");
  895. break;
  896. case PSEV_DSR_OFF:
  897. if (cs->debug & L1_DEB_HSCX)
  898. debugl1(cs, "pump stev DSR_OFF");
  899. break;
  900. case PSEV_REM_RET:
  901. if (cs->debug & L1_DEB_HSCX)
  902. debugl1(cs, "pump stev REMOTE RETRAIN");
  903. break;
  904. case PSEV_REM_REN:
  905. if (cs->debug & L1_DEB_HSCX)
  906. debugl1(cs, "pump stev REMOTE RENEGOTIATE");
  907. break;
  908. case PSEV_GSTN_CLR:
  909. if (cs->debug & L1_DEB_HSCX)
  910. debugl1(cs, "pump stev GSTN CLEAR");
  911. break;
  912. default:
  913. if (cs->debug & L1_DEB_HSCX)
  914. debugl1(cs, "unknown pump stev %x", devt);
  915. break;
  916. }
  917. }
  918. static void
  919. ll_deliver_faxstat(struct BCState *bcs, u_char status)
  920. {
  921. isdn_ctrl ic;
  922. struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata;
  923. if (bcs->cs->debug & L1_DEB_HSCX)
  924. debugl1(bcs->cs, "HL->LL FAXIND %x", status);
  925. ic.driver = bcs->cs->myid;
  926. ic.command = ISDN_STAT_FAXIND;
  927. ic.arg = chanp->chan;
  928. ic.parm.aux.cmd = status;
  929. bcs->cs->iif.statcallb(&ic);
  930. }
  931. static void
  932. isar_pump_statev_fax(struct BCState *bcs, u_char devt) {
  933. struct IsdnCardState *cs = bcs->cs;
  934. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  935. u_char p1;
  936. switch (devt) {
  937. case PSEV_10MS_TIMER:
  938. if (cs->debug & L1_DEB_HSCX)
  939. debugl1(cs, "pump stev TIMER");
  940. break;
  941. case PSEV_RSP_READY:
  942. if (cs->debug & L1_DEB_HSCX)
  943. debugl1(cs, "pump stev RSP_READY");
  944. bcs->hw.isar.state = STFAX_READY;
  945. l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
  946. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  947. isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3);
  948. } else {
  949. isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3);
  950. }
  951. break;
  952. case PSEV_LINE_TX_H:
  953. if (bcs->hw.isar.state == STFAX_LINE) {
  954. if (cs->debug & L1_DEB_HSCX)
  955. debugl1(cs, "pump stev LINE_TX_H");
  956. bcs->hw.isar.state = STFAX_CONT;
  957. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  958. } else {
  959. if (cs->debug & L1_DEB_WARN)
  960. debugl1(cs, "pump stev LINE_TX_H wrong st %x",
  961. bcs->hw.isar.state);
  962. }
  963. break;
  964. case PSEV_LINE_RX_H:
  965. if (bcs->hw.isar.state == STFAX_LINE) {
  966. if (cs->debug & L1_DEB_HSCX)
  967. debugl1(cs, "pump stev LINE_RX_H");
  968. bcs->hw.isar.state = STFAX_CONT;
  969. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  970. } else {
  971. if (cs->debug & L1_DEB_WARN)
  972. debugl1(cs, "pump stev LINE_RX_H wrong st %x",
  973. bcs->hw.isar.state);
  974. }
  975. break;
  976. case PSEV_LINE_TX_B:
  977. if (bcs->hw.isar.state == STFAX_LINE) {
  978. if (cs->debug & L1_DEB_HSCX)
  979. debugl1(cs, "pump stev LINE_TX_B");
  980. bcs->hw.isar.state = STFAX_CONT;
  981. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  982. } else {
  983. if (cs->debug & L1_DEB_WARN)
  984. debugl1(cs, "pump stev LINE_TX_B wrong st %x",
  985. bcs->hw.isar.state);
  986. }
  987. break;
  988. case PSEV_LINE_RX_B:
  989. if (bcs->hw.isar.state == STFAX_LINE) {
  990. if (cs->debug & L1_DEB_HSCX)
  991. debugl1(cs, "pump stev LINE_RX_B");
  992. bcs->hw.isar.state = STFAX_CONT;
  993. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  994. } else {
  995. if (cs->debug & L1_DEB_WARN)
  996. debugl1(cs, "pump stev LINE_RX_B wrong st %x",
  997. bcs->hw.isar.state);
  998. }
  999. break;
  1000. case PSEV_RSP_CONN:
  1001. if (bcs->hw.isar.state == STFAX_CONT) {
  1002. if (cs->debug & L1_DEB_HSCX)
  1003. debugl1(cs, "pump stev RSP_CONN");
  1004. bcs->hw.isar.state = STFAX_ACTIV;
  1005. test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
  1006. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  1007. if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  1008. /* 1s Flags before data */
  1009. if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag))
  1010. del_timer(&bcs->hw.isar.ftimer);
  1011. /* 1000 ms */
  1012. bcs->hw.isar.ftimer.expires =
  1013. jiffies + ((1000 * HZ) / 1000);
  1014. test_and_set_bit(BC_FLG_LL_CONN,
  1015. &bcs->Flag);
  1016. add_timer(&bcs->hw.isar.ftimer);
  1017. } else {
  1018. schedule_event(bcs, B_LL_CONNECT);
  1019. }
  1020. } else {
  1021. if (cs->debug & L1_DEB_WARN)
  1022. debugl1(cs, "pump stev RSP_CONN wrong st %x",
  1023. bcs->hw.isar.state);
  1024. }
  1025. break;
  1026. case PSEV_FLAGS_DET:
  1027. if (cs->debug & L1_DEB_HSCX)
  1028. debugl1(cs, "pump stev FLAGS_DET");
  1029. break;
  1030. case PSEV_RSP_DISC:
  1031. if (cs->debug & L1_DEB_HSCX)
  1032. debugl1(cs, "pump stev RSP_DISC");
  1033. if (bcs->hw.isar.state == STFAX_ESCAPE) {
  1034. p1 = 5;
  1035. switch (bcs->hw.isar.newcmd) {
  1036. case 0:
  1037. bcs->hw.isar.state = STFAX_READY;
  1038. break;
  1039. case PCTRL_CMD_FTM:
  1040. p1 = 2;
  1041. case PCTRL_CMD_FTH:
  1042. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1043. PCTRL_CMD_SILON, 1, &p1);
  1044. bcs->hw.isar.state = STFAX_SILDET;
  1045. break;
  1046. case PCTRL_CMD_FRM:
  1047. if (frm_extra_delay)
  1048. mdelay(frm_extra_delay);
  1049. case PCTRL_CMD_FRH:
  1050. p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
  1051. bcs->hw.isar.newmod = 0;
  1052. bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
  1053. bcs->hw.isar.newcmd = 0;
  1054. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1055. bcs->hw.isar.cmd, 1, &p1);
  1056. bcs->hw.isar.state = STFAX_LINE;
  1057. bcs->hw.isar.try_mod = 3;
  1058. break;
  1059. default:
  1060. if (cs->debug & L1_DEB_HSCX)
  1061. debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd);
  1062. break;
  1063. }
  1064. } else if (bcs->hw.isar.state == STFAX_ACTIV) {
  1065. if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) {
  1066. schedule_event(bcs, B_LL_OK);
  1067. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
  1068. send_DLE_ETX(bcs);
  1069. schedule_event(bcs, B_LL_NOCARRIER);
  1070. } else {
  1071. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1072. }
  1073. bcs->hw.isar.state = STFAX_READY;
  1074. } else {
  1075. bcs->hw.isar.state = STFAX_READY;
  1076. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1077. }
  1078. break;
  1079. case PSEV_RSP_SILDET:
  1080. if (cs->debug & L1_DEB_HSCX)
  1081. debugl1(cs, "pump stev RSP_SILDET");
  1082. if (bcs->hw.isar.state == STFAX_SILDET) {
  1083. p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
  1084. bcs->hw.isar.newmod = 0;
  1085. bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
  1086. bcs->hw.isar.newcmd = 0;
  1087. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1088. bcs->hw.isar.cmd, 1, &p1);
  1089. bcs->hw.isar.state = STFAX_LINE;
  1090. bcs->hw.isar.try_mod = 3;
  1091. }
  1092. break;
  1093. case PSEV_RSP_SILOFF:
  1094. if (cs->debug & L1_DEB_HSCX)
  1095. debugl1(cs, "pump stev RSP_SILOFF");
  1096. break;
  1097. case PSEV_RSP_FCERR:
  1098. if (bcs->hw.isar.state == STFAX_LINE) {
  1099. if (cs->debug & L1_DEB_HSCX)
  1100. debugl1(cs, "pump stev RSP_FCERR try %d",
  1101. bcs->hw.isar.try_mod);
  1102. if (bcs->hw.isar.try_mod--) {
  1103. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1104. bcs->hw.isar.cmd, 1,
  1105. &bcs->hw.isar.mod);
  1106. break;
  1107. }
  1108. }
  1109. if (cs->debug & L1_DEB_HSCX)
  1110. debugl1(cs, "pump stev RSP_FCERR");
  1111. bcs->hw.isar.state = STFAX_ESCAPE;
  1112. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
  1113. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1114. break;
  1115. default:
  1116. break;
  1117. }
  1118. }
  1119. static char debbuf[128];
  1120. void
  1121. isar_int_main(struct IsdnCardState *cs)
  1122. {
  1123. struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
  1124. struct BCState *bcs;
  1125. get_irq_infos(cs, ireg);
  1126. switch (ireg->iis & ISAR_IIS_MSCMSD) {
  1127. case ISAR_IIS_RDATA:
  1128. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1129. isar_rcv_frame(cs, bcs);
  1130. } else {
  1131. debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
  1132. ireg->iis, ireg->cmsb, ireg->clsb);
  1133. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1134. }
  1135. break;
  1136. case ISAR_IIS_GSTEV:
  1137. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1138. ireg->bstat |= ireg->cmsb;
  1139. check_send(cs, ireg->cmsb);
  1140. break;
  1141. case ISAR_IIS_BSTEV:
  1142. #ifdef ERROR_STATISTIC
  1143. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1144. if (ireg->cmsb == BSTEV_TBO)
  1145. bcs->err_tx++;
  1146. if (ireg->cmsb == BSTEV_RBO)
  1147. bcs->err_rdo++;
  1148. }
  1149. #endif
  1150. if (cs->debug & L1_DEB_WARN)
  1151. debugl1(cs, "Buffer STEV dpath%d msb(%x)",
  1152. ireg->iis >> 6, ireg->cmsb);
  1153. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1154. break;
  1155. case ISAR_IIS_PSTEV:
  1156. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1157. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1158. if (bcs->mode == L1_MODE_V32) {
  1159. isar_pump_statev_modem(bcs, ireg->cmsb);
  1160. } else if (bcs->mode == L1_MODE_FAX) {
  1161. isar_pump_statev_fax(bcs, ireg->cmsb);
  1162. } else if (ireg->cmsb == PSEV_10MS_TIMER) {
  1163. if (cs->debug & L1_DEB_HSCX)
  1164. debugl1(cs, "pump stev TIMER");
  1165. } else {
  1166. if (cs->debug & L1_DEB_WARN)
  1167. debugl1(cs, "isar IIS_PSTEV pmode %d stat %x",
  1168. bcs->mode, ireg->cmsb);
  1169. }
  1170. } else {
  1171. debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
  1172. ireg->iis, ireg->cmsb, ireg->clsb);
  1173. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1174. }
  1175. break;
  1176. case ISAR_IIS_PSTRSP:
  1177. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1178. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1179. isar_pump_status_rsp(bcs, ireg);
  1180. } else {
  1181. debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
  1182. ireg->iis, ireg->cmsb, ireg->clsb);
  1183. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1184. }
  1185. break;
  1186. case ISAR_IIS_DIAG:
  1187. case ISAR_IIS_BSTRSP:
  1188. case ISAR_IIS_IOM2RSP:
  1189. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1190. if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
  1191. == L1_DEB_HSCX) {
  1192. u_char *tp = debbuf;
  1193. tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
  1194. ireg->iis, ireg->cmsb);
  1195. QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
  1196. debugl1(cs, "%s", debbuf);
  1197. }
  1198. break;
  1199. case ISAR_IIS_INVMSG:
  1200. rcv_mbox(cs, ireg, debbuf);
  1201. if (cs->debug & L1_DEB_WARN)
  1202. debugl1(cs, "invalid msg his:%x",
  1203. ireg->cmsb);
  1204. break;
  1205. default:
  1206. rcv_mbox(cs, ireg, debbuf);
  1207. if (cs->debug & L1_DEB_WARN)
  1208. debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
  1209. ireg->iis, ireg->cmsb, ireg->clsb);
  1210. break;
  1211. }
  1212. }
  1213. static void
  1214. ftimer_handler(struct BCState *bcs) {
  1215. if (bcs->cs->debug)
  1216. debugl1(bcs->cs, "ftimer flags %04lx",
  1217. bcs->Flag);
  1218. test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag);
  1219. if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) {
  1220. schedule_event(bcs, B_LL_CONNECT);
  1221. }
  1222. if (test_and_clear_bit(BC_FLG_FTI_FTS, &bcs->Flag)) {
  1223. schedule_event(bcs, B_LL_OK);
  1224. }
  1225. }
  1226. static void
  1227. setup_pump(struct BCState *bcs) {
  1228. struct IsdnCardState *cs = bcs->cs;
  1229. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1230. u_char ctrl, param[6];
  1231. switch (bcs->mode) {
  1232. case L1_MODE_NULL:
  1233. case L1_MODE_TRANS:
  1234. case L1_MODE_HDLC:
  1235. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
  1236. break;
  1237. case L1_MODE_V32:
  1238. ctrl = PMOD_DATAMODEM;
  1239. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  1240. ctrl |= PCTRL_ORIG;
  1241. param[5] = PV32P6_CTN;
  1242. } else {
  1243. param[5] = PV32P6_ATN;
  1244. }
  1245. param[0] = para_TOA; /* 6 db */
  1246. param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
  1247. PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
  1248. param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
  1249. param[3] = PV32P4_UT144;
  1250. param[4] = PV32P5_UT144;
  1251. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
  1252. break;
  1253. case L1_MODE_FAX:
  1254. ctrl = PMOD_FAX;
  1255. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  1256. ctrl |= PCTRL_ORIG;
  1257. param[1] = PFAXP2_CTN;
  1258. } else {
  1259. param[1] = PFAXP2_ATN;
  1260. }
  1261. param[0] = para_TOA; /* 6 db */
  1262. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
  1263. bcs->hw.isar.state = STFAX_NULL;
  1264. bcs->hw.isar.newcmd = 0;
  1265. bcs->hw.isar.newmod = 0;
  1266. test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag);
  1267. break;
  1268. }
  1269. udelay(1000);
  1270. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  1271. udelay(1000);
  1272. }
  1273. static void
  1274. setup_sart(struct BCState *bcs) {
  1275. struct IsdnCardState *cs = bcs->cs;
  1276. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1277. u_char ctrl, param[2];
  1278. switch (bcs->mode) {
  1279. case L1_MODE_NULL:
  1280. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0,
  1281. NULL);
  1282. break;
  1283. case L1_MODE_TRANS:
  1284. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2,
  1285. "\0\0");
  1286. break;
  1287. case L1_MODE_HDLC:
  1288. param[0] = 0;
  1289. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1,
  1290. param);
  1291. break;
  1292. case L1_MODE_V32:
  1293. ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
  1294. param[0] = S_P1_CHS_8;
  1295. param[1] = S_P2_BFT_DEF;
  1296. sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2,
  1297. param);
  1298. break;
  1299. case L1_MODE_FAX:
  1300. /* SART must not configured with FAX */
  1301. break;
  1302. }
  1303. udelay(1000);
  1304. sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
  1305. udelay(1000);
  1306. }
  1307. static void
  1308. setup_iom2(struct BCState *bcs) {
  1309. struct IsdnCardState *cs = bcs->cs;
  1310. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1311. u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD, 0, 0, 0, 0};
  1312. if (bcs->channel)
  1313. msg[1] = msg[3] = 1;
  1314. switch (bcs->mode) {
  1315. case L1_MODE_NULL:
  1316. cmsb = 0;
  1317. /* dummy slot */
  1318. msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
  1319. break;
  1320. case L1_MODE_TRANS:
  1321. case L1_MODE_HDLC:
  1322. break;
  1323. case L1_MODE_V32:
  1324. case L1_MODE_FAX:
  1325. cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
  1326. break;
  1327. }
  1328. sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
  1329. udelay(1000);
  1330. sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
  1331. udelay(1000);
  1332. }
  1333. static int
  1334. modeisar(struct BCState *bcs, int mode, int bc)
  1335. {
  1336. struct IsdnCardState *cs = bcs->cs;
  1337. /* Here we are selecting the best datapath for requested mode */
  1338. if (bcs->mode == L1_MODE_NULL) { /* New Setup */
  1339. bcs->channel = bc;
  1340. switch (mode) {
  1341. case L1_MODE_NULL: /* init */
  1342. if (!bcs->hw.isar.dpath)
  1343. /* no init for dpath 0 */
  1344. return (0);
  1345. break;
  1346. case L1_MODE_TRANS:
  1347. case L1_MODE_HDLC:
  1348. /* best is datapath 2 */
  1349. if (!test_and_set_bit(ISAR_DP2_USE,
  1350. &bcs->hw.isar.reg->Flags))
  1351. bcs->hw.isar.dpath = 2;
  1352. else if (!test_and_set_bit(ISAR_DP1_USE,
  1353. &bcs->hw.isar.reg->Flags))
  1354. bcs->hw.isar.dpath = 1;
  1355. else {
  1356. printk(KERN_WARNING"isar modeisar both paths in use\n");
  1357. return (1);
  1358. }
  1359. break;
  1360. case L1_MODE_V32:
  1361. case L1_MODE_FAX:
  1362. /* only datapath 1 */
  1363. if (!test_and_set_bit(ISAR_DP1_USE,
  1364. &bcs->hw.isar.reg->Flags))
  1365. bcs->hw.isar.dpath = 1;
  1366. else {
  1367. printk(KERN_WARNING"isar modeisar analog functions only with DP1\n");
  1368. debugl1(cs, "isar modeisar analog functions only with DP1");
  1369. return (1);
  1370. }
  1371. break;
  1372. }
  1373. }
  1374. if (cs->debug & L1_DEB_HSCX)
  1375. debugl1(cs, "isar dp%d mode %d->%d ichan %d",
  1376. bcs->hw.isar.dpath, bcs->mode, mode, bc);
  1377. bcs->mode = mode;
  1378. setup_pump(bcs);
  1379. setup_iom2(bcs);
  1380. setup_sart(bcs);
  1381. if (bcs->mode == L1_MODE_NULL) {
  1382. /* Clear resources */
  1383. if (bcs->hw.isar.dpath == 1)
  1384. test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
  1385. else if (bcs->hw.isar.dpath == 2)
  1386. test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
  1387. bcs->hw.isar.dpath = 0;
  1388. }
  1389. return (0);
  1390. }
  1391. static void
  1392. isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para)
  1393. {
  1394. struct IsdnCardState *cs = bcs->cs;
  1395. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1396. u_char ctrl = 0, nom = 0, p1 = 0;
  1397. switch (cmd) {
  1398. case ISDN_FAX_CLASS1_FTM:
  1399. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1400. if (bcs->hw.isar.state == STFAX_READY) {
  1401. p1 = para;
  1402. ctrl = PCTRL_CMD_FTM;
  1403. nom = 1;
  1404. bcs->hw.isar.state = STFAX_LINE;
  1405. bcs->hw.isar.cmd = ctrl;
  1406. bcs->hw.isar.mod = para;
  1407. bcs->hw.isar.newmod = 0;
  1408. bcs->hw.isar.newcmd = 0;
  1409. bcs->hw.isar.try_mod = 3;
  1410. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1411. (bcs->hw.isar.cmd == PCTRL_CMD_FTM) &&
  1412. (bcs->hw.isar.mod == para)) {
  1413. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1414. } else {
  1415. bcs->hw.isar.newmod = para;
  1416. bcs->hw.isar.newcmd = PCTRL_CMD_FTM;
  1417. nom = 0;
  1418. ctrl = PCTRL_CMD_ESC;
  1419. bcs->hw.isar.state = STFAX_ESCAPE;
  1420. }
  1421. break;
  1422. case ISDN_FAX_CLASS1_FTH:
  1423. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1424. if (bcs->hw.isar.state == STFAX_READY) {
  1425. p1 = para;
  1426. ctrl = PCTRL_CMD_FTH;
  1427. nom = 1;
  1428. bcs->hw.isar.state = STFAX_LINE;
  1429. bcs->hw.isar.cmd = ctrl;
  1430. bcs->hw.isar.mod = para;
  1431. bcs->hw.isar.newmod = 0;
  1432. bcs->hw.isar.newcmd = 0;
  1433. bcs->hw.isar.try_mod = 3;
  1434. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1435. (bcs->hw.isar.cmd == PCTRL_CMD_FTH) &&
  1436. (bcs->hw.isar.mod == para)) {
  1437. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1438. } else {
  1439. bcs->hw.isar.newmod = para;
  1440. bcs->hw.isar.newcmd = PCTRL_CMD_FTH;
  1441. nom = 0;
  1442. ctrl = PCTRL_CMD_ESC;
  1443. bcs->hw.isar.state = STFAX_ESCAPE;
  1444. }
  1445. break;
  1446. case ISDN_FAX_CLASS1_FRM:
  1447. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1448. if (bcs->hw.isar.state == STFAX_READY) {
  1449. p1 = para;
  1450. ctrl = PCTRL_CMD_FRM;
  1451. nom = 1;
  1452. bcs->hw.isar.state = STFAX_LINE;
  1453. bcs->hw.isar.cmd = ctrl;
  1454. bcs->hw.isar.mod = para;
  1455. bcs->hw.isar.newmod = 0;
  1456. bcs->hw.isar.newcmd = 0;
  1457. bcs->hw.isar.try_mod = 3;
  1458. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1459. (bcs->hw.isar.cmd == PCTRL_CMD_FRM) &&
  1460. (bcs->hw.isar.mod == para)) {
  1461. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1462. } else {
  1463. bcs->hw.isar.newmod = para;
  1464. bcs->hw.isar.newcmd = PCTRL_CMD_FRM;
  1465. nom = 0;
  1466. ctrl = PCTRL_CMD_ESC;
  1467. bcs->hw.isar.state = STFAX_ESCAPE;
  1468. }
  1469. break;
  1470. case ISDN_FAX_CLASS1_FRH:
  1471. test_and_set_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1472. if (bcs->hw.isar.state == STFAX_READY) {
  1473. p1 = para;
  1474. ctrl = PCTRL_CMD_FRH;
  1475. nom = 1;
  1476. bcs->hw.isar.state = STFAX_LINE;
  1477. bcs->hw.isar.cmd = ctrl;
  1478. bcs->hw.isar.mod = para;
  1479. bcs->hw.isar.newmod = 0;
  1480. bcs->hw.isar.newcmd = 0;
  1481. bcs->hw.isar.try_mod = 3;
  1482. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1483. (bcs->hw.isar.cmd == PCTRL_CMD_FRH) &&
  1484. (bcs->hw.isar.mod == para)) {
  1485. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1486. } else {
  1487. bcs->hw.isar.newmod = para;
  1488. bcs->hw.isar.newcmd = PCTRL_CMD_FRH;
  1489. nom = 0;
  1490. ctrl = PCTRL_CMD_ESC;
  1491. bcs->hw.isar.state = STFAX_ESCAPE;
  1492. }
  1493. break;
  1494. case ISDN_FAXPUMP_HALT:
  1495. bcs->hw.isar.state = STFAX_NULL;
  1496. nom = 0;
  1497. ctrl = PCTRL_CMD_HALT;
  1498. break;
  1499. }
  1500. if (ctrl)
  1501. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
  1502. }
  1503. static void
  1504. isar_setup(struct IsdnCardState *cs)
  1505. {
  1506. u_char msg;
  1507. int i;
  1508. /* Dpath 1, 2 */
  1509. msg = 61;
  1510. for (i = 0; i < 2; i++) {
  1511. /* Buffer Config */
  1512. sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
  1513. ISAR_HIS_P12CFG, 4, 1, &msg);
  1514. cs->bcs[i].hw.isar.mml = msg;
  1515. cs->bcs[i].mode = 0;
  1516. cs->bcs[i].hw.isar.dpath = i + 1;
  1517. modeisar(&cs->bcs[i], 0, 0);
  1518. INIT_WORK(&cs->bcs[i].tqueue, isar_bh);
  1519. }
  1520. }
  1521. static void
  1522. isar_l2l1(struct PStack *st, int pr, void *arg)
  1523. {
  1524. struct BCState *bcs = st->l1.bcs;
  1525. struct sk_buff *skb = arg;
  1526. int ret;
  1527. u_long flags;
  1528. switch (pr) {
  1529. case (PH_DATA | REQUEST):
  1530. spin_lock_irqsave(&bcs->cs->lock, flags);
  1531. if (bcs->tx_skb) {
  1532. skb_queue_tail(&bcs->squeue, skb);
  1533. } else {
  1534. bcs->tx_skb = skb;
  1535. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1536. if (bcs->cs->debug & L1_DEB_HSCX)
  1537. debugl1(bcs->cs, "DRQ set BC_FLG_BUSY");
  1538. bcs->hw.isar.txcnt = 0;
  1539. bcs->cs->BC_Send_Data(bcs);
  1540. }
  1541. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1542. break;
  1543. case (PH_PULL | INDICATION):
  1544. spin_lock_irqsave(&bcs->cs->lock, flags);
  1545. if (bcs->tx_skb) {
  1546. printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n");
  1547. } else {
  1548. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1549. if (bcs->cs->debug & L1_DEB_HSCX)
  1550. debugl1(bcs->cs, "PUI set BC_FLG_BUSY");
  1551. bcs->tx_skb = skb;
  1552. bcs->hw.isar.txcnt = 0;
  1553. bcs->cs->BC_Send_Data(bcs);
  1554. }
  1555. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1556. break;
  1557. case (PH_PULL | REQUEST):
  1558. if (!bcs->tx_skb) {
  1559. test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1560. st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
  1561. } else
  1562. test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1563. break;
  1564. case (PH_ACTIVATE | REQUEST):
  1565. spin_lock_irqsave(&bcs->cs->lock, flags);
  1566. test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
  1567. bcs->hw.isar.conmsg[0] = 0;
  1568. if (test_bit(FLG_ORIG, &st->l2.flag))
  1569. test_and_set_bit(BC_FLG_ORIG, &bcs->Flag);
  1570. else
  1571. test_and_clear_bit(BC_FLG_ORIG, &bcs->Flag);
  1572. switch (st->l1.mode) {
  1573. case L1_MODE_TRANS:
  1574. case L1_MODE_HDLC:
  1575. ret = modeisar(bcs, st->l1.mode, st->l1.bc);
  1576. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1577. if (ret)
  1578. l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
  1579. else
  1580. l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
  1581. break;
  1582. case L1_MODE_V32:
  1583. case L1_MODE_FAX:
  1584. ret = modeisar(bcs, st->l1.mode, st->l1.bc);
  1585. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1586. if (ret)
  1587. l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
  1588. break;
  1589. default:
  1590. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1591. break;
  1592. }
  1593. break;
  1594. case (PH_DEACTIVATE | REQUEST):
  1595. l1_msg_b(st, pr, arg);
  1596. break;
  1597. case (PH_DEACTIVATE | CONFIRM):
  1598. spin_lock_irqsave(&bcs->cs->lock, flags);
  1599. switch (st->l1.mode) {
  1600. case L1_MODE_TRANS:
  1601. case L1_MODE_HDLC:
  1602. case L1_MODE_V32:
  1603. break;
  1604. case L1_MODE_FAX:
  1605. isar_pump_cmd(bcs, ISDN_FAXPUMP_HALT, 0);
  1606. break;
  1607. }
  1608. test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
  1609. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1610. if (bcs->cs->debug & L1_DEB_HSCX)
  1611. debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY");
  1612. modeisar(bcs, 0, st->l1.bc);
  1613. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1614. st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
  1615. break;
  1616. }
  1617. }
  1618. static void
  1619. close_isarstate(struct BCState *bcs)
  1620. {
  1621. modeisar(bcs, 0, bcs->channel);
  1622. if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
  1623. kfree(bcs->hw.isar.rcvbuf);
  1624. bcs->hw.isar.rcvbuf = NULL;
  1625. skb_queue_purge(&bcs->rqueue);
  1626. skb_queue_purge(&bcs->squeue);
  1627. if (bcs->tx_skb) {
  1628. dev_kfree_skb_any(bcs->tx_skb);
  1629. bcs->tx_skb = NULL;
  1630. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1631. if (bcs->cs->debug & L1_DEB_HSCX)
  1632. debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
  1633. }
  1634. }
  1635. del_timer(&bcs->hw.isar.ftimer);
  1636. }
  1637. static int
  1638. open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
  1639. {
  1640. if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
  1641. if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
  1642. printk(KERN_WARNING
  1643. "HiSax: No memory for isar.rcvbuf\n");
  1644. return (1);
  1645. }
  1646. skb_queue_head_init(&bcs->rqueue);
  1647. skb_queue_head_init(&bcs->squeue);
  1648. }
  1649. bcs->tx_skb = NULL;
  1650. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1651. if (cs->debug & L1_DEB_HSCX)
  1652. debugl1(cs, "openisar clear BC_FLG_BUSY");
  1653. bcs->event = 0;
  1654. bcs->hw.isar.rcvidx = 0;
  1655. bcs->tx_cnt = 0;
  1656. return (0);
  1657. }
  1658. static int
  1659. setstack_isar(struct PStack *st, struct BCState *bcs)
  1660. {
  1661. bcs->channel = st->l1.bc;
  1662. if (open_isarstate(st->l1.hardware, bcs))
  1663. return (-1);
  1664. st->l1.bcs = bcs;
  1665. st->l2.l2l1 = isar_l2l1;
  1666. setstack_manager(st);
  1667. bcs->st = st;
  1668. setstack_l1_B(st);
  1669. return (0);
  1670. }
  1671. int
  1672. isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
  1673. u_long adr;
  1674. int features, i;
  1675. struct BCState *bcs;
  1676. if (cs->debug & L1_DEB_HSCX)
  1677. debugl1(cs, "isar_auxcmd cmd/ch %x/%ld", ic->command, ic->arg);
  1678. switch (ic->command) {
  1679. case (ISDN_CMD_FAXCMD):
  1680. bcs = cs->channel[ic->arg].bcs;
  1681. if (cs->debug & L1_DEB_HSCX)
  1682. debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d",
  1683. ic->parm.aux.cmd, ic->parm.aux.subcmd);
  1684. switch (ic->parm.aux.cmd) {
  1685. case ISDN_FAX_CLASS1_CTRL:
  1686. if (ic->parm.aux.subcmd == ETX)
  1687. test_and_set_bit(BC_FLG_DLEETX,
  1688. &bcs->Flag);
  1689. break;
  1690. case ISDN_FAX_CLASS1_FTS:
  1691. if (ic->parm.aux.subcmd == AT_QUERY) {
  1692. ic->command = ISDN_STAT_FAXIND;
  1693. ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
  1694. cs->iif.statcallb(ic);
  1695. return (0);
  1696. } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
  1697. strcpy(ic->parm.aux.para, "0-255");
  1698. ic->command = ISDN_STAT_FAXIND;
  1699. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1700. cs->iif.statcallb(ic);
  1701. return (0);
  1702. } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
  1703. if (cs->debug & L1_DEB_HSCX)
  1704. debugl1(cs, "isar_auxcmd %s=%d",
  1705. FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
  1706. if (bcs->hw.isar.state == STFAX_READY) {
  1707. if (!ic->parm.aux.para[0]) {
  1708. ic->command = ISDN_STAT_FAXIND;
  1709. ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
  1710. cs->iif.statcallb(ic);
  1711. return (0);
  1712. }
  1713. if (!test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) {
  1714. /* n*10 ms */
  1715. bcs->hw.isar.ftimer.expires =
  1716. jiffies + ((ic->parm.aux.para[0] * 10 * HZ) / 1000);
  1717. test_and_set_bit(BC_FLG_FTI_FTS, &bcs->Flag);
  1718. add_timer(&bcs->hw.isar.ftimer);
  1719. return (0);
  1720. } else {
  1721. if (cs->debug)
  1722. debugl1(cs, "isar FTS=%d and FTI busy",
  1723. ic->parm.aux.para[0]);
  1724. }
  1725. } else {
  1726. if (cs->debug)
  1727. debugl1(cs, "isar FTS=%d and isar.state not ready(%x)",
  1728. ic->parm.aux.para[0], bcs->hw.isar.state);
  1729. }
  1730. ic->command = ISDN_STAT_FAXIND;
  1731. ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
  1732. cs->iif.statcallb(ic);
  1733. }
  1734. break;
  1735. case ISDN_FAX_CLASS1_FRM:
  1736. case ISDN_FAX_CLASS1_FRH:
  1737. case ISDN_FAX_CLASS1_FTM:
  1738. case ISDN_FAX_CLASS1_FTH:
  1739. if (ic->parm.aux.subcmd == AT_QUERY) {
  1740. sprintf(ic->parm.aux.para,
  1741. "%d", bcs->hw.isar.mod);
  1742. ic->command = ISDN_STAT_FAXIND;
  1743. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1744. cs->iif.statcallb(ic);
  1745. return (0);
  1746. } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
  1747. char *p = ic->parm.aux.para;
  1748. for (i = 0; i < FAXMODCNT; i++)
  1749. if ((1 << i) & modmask)
  1750. p += sprintf(p, "%d,", faxmodulation[i]);
  1751. p--;
  1752. *p = 0;
  1753. ic->command = ISDN_STAT_FAXIND;
  1754. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1755. cs->iif.statcallb(ic);
  1756. return (0);
  1757. } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
  1758. if (cs->debug & L1_DEB_HSCX)
  1759. debugl1(cs, "isar_auxcmd %s=%d",
  1760. FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
  1761. for (i = 0; i < FAXMODCNT; i++)
  1762. if (faxmodulation[i] == ic->parm.aux.para[0])
  1763. break;
  1764. if ((i < FAXMODCNT) && ((1 << i) & modmask) &&
  1765. test_bit(BC_FLG_INIT, &bcs->Flag)) {
  1766. isar_pump_cmd(bcs,
  1767. ic->parm.aux.cmd,
  1768. ic->parm.aux.para[0]);
  1769. return (0);
  1770. }
  1771. }
  1772. /* wrong modulation or not activ */
  1773. /* fall through */
  1774. default:
  1775. ic->command = ISDN_STAT_FAXIND;
  1776. ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
  1777. cs->iif.statcallb(ic);
  1778. }
  1779. break;
  1780. case (ISDN_CMD_IOCTL):
  1781. switch (ic->arg) {
  1782. case 9: /* load firmware */
  1783. features = ISDN_FEATURE_L2_MODEM |
  1784. ISDN_FEATURE_L2_FAX |
  1785. ISDN_FEATURE_L3_FCLASS1;
  1786. memcpy(&adr, ic->parm.num, sizeof(ulong));
  1787. if (isar_load_firmware(cs, (u_char __user *)adr))
  1788. return (1);
  1789. else
  1790. ll_run(cs, features);
  1791. break;
  1792. case 20:
  1793. features = *(unsigned int *) ic->parm.num;
  1794. printk(KERN_DEBUG "HiSax: max modulation old(%04x) new(%04x)\n",
  1795. modmask, features);
  1796. modmask = features;
  1797. break;
  1798. case 21:
  1799. features = *(unsigned int *) ic->parm.num;
  1800. printk(KERN_DEBUG "HiSax: FRM extra delay old(%d) new(%d) ms\n",
  1801. frm_extra_delay, features);
  1802. if (features >= 0)
  1803. frm_extra_delay = features;
  1804. break;
  1805. case 22:
  1806. features = *(unsigned int *) ic->parm.num;
  1807. printk(KERN_DEBUG "HiSax: TOA old(%d) new(%d) db\n",
  1808. para_TOA, features);
  1809. if (features >= 0 && features < 32)
  1810. para_TOA = features;
  1811. break;
  1812. default:
  1813. printk(KERN_DEBUG "HiSax: invalid ioctl %d\n",
  1814. (int) ic->arg);
  1815. return (-EINVAL);
  1816. }
  1817. break;
  1818. default:
  1819. return (-EINVAL);
  1820. }
  1821. return (0);
  1822. }
  1823. void initisar(struct IsdnCardState *cs)
  1824. {
  1825. cs->bcs[0].BC_SetStack = setstack_isar;
  1826. cs->bcs[1].BC_SetStack = setstack_isar;
  1827. cs->bcs[0].BC_Close = close_isarstate;
  1828. cs->bcs[1].BC_Close = close_isarstate;
  1829. cs->bcs[0].hw.isar.ftimer.function = (void *) ftimer_handler;
  1830. cs->bcs[0].hw.isar.ftimer.data = (long) &cs->bcs[0];
  1831. init_timer(&cs->bcs[0].hw.isar.ftimer);
  1832. cs->bcs[1].hw.isar.ftimer.function = (void *) ftimer_handler;
  1833. cs->bcs[1].hw.isar.ftimer.data = (long) &cs->bcs[1];
  1834. init_timer(&cs->bcs[1].hw.isar.ftimer);
  1835. }