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/drivers/net/fddi/defxx.h

http://github.com/mirrors/linux
C Header | 1803 lines | 1305 code | 319 blank | 179 comment | 1 complexity | bafe07be59cacbbf9fa24c9c2e0fc97f MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. /*
  2. * File Name:
  3. * defxx.h
  4. *
  5. * Copyright Information:
  6. * Copyright Digital Equipment Corporation 1996.
  7. *
  8. * This software may be used and distributed according to the terms of
  9. * the GNU General Public License, incorporated herein by reference.
  10. *
  11. * Abstract:
  12. * Contains all definitions specified by port specification and required
  13. * by the defxx.c driver.
  14. *
  15. * The original author:
  16. * LVS Lawrence V. Stefani <lstefani@yahoo.com>
  17. *
  18. * Maintainers:
  19. * macro Maciej W. Rozycki <macro@linux-mips.org>
  20. *
  21. * Modification History:
  22. * Date Name Description
  23. * 16-Aug-96 LVS Created.
  24. * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O
  25. * macros to DEFXX.C.
  26. * 12-Sep-96 LVS Removed packet request header pointers.
  27. * 04 Aug 2003 macro Converted to the DMA API.
  28. * 23 Oct 2006 macro Big-endian host support.
  29. * 14 Dec 2006 macro TURBOchannel support.
  30. */
  31. #ifndef _DEFXX_H_
  32. #define _DEFXX_H_
  33. /* Define basic types for unsigned chars, shorts, longs */
  34. typedef u8 PI_UINT8;
  35. typedef u16 PI_UINT16;
  36. typedef u32 PI_UINT32;
  37. /* Define general structures */
  38. typedef struct /* 64-bit counter */
  39. {
  40. PI_UINT32 ms;
  41. PI_UINT32 ls;
  42. } PI_CNTR;
  43. typedef struct /* LAN address */
  44. {
  45. PI_UINT32 lwrd_0;
  46. PI_UINT32 lwrd_1;
  47. } PI_LAN_ADDR;
  48. typedef struct /* Station ID address */
  49. {
  50. PI_UINT32 octet_7_4;
  51. PI_UINT32 octet_3_0;
  52. } PI_STATION_ID;
  53. /* Define general constants */
  54. #define PI_ALIGN_K_DESC_BLK 8192 /* Descriptor block boundary */
  55. #define PI_ALIGN_K_CONS_BLK 64 /* Consumer block boundary */
  56. #define PI_ALIGN_K_CMD_REQ_BUFF 128 /* Xmt Command que buffer alignment */
  57. #define PI_ALIGN_K_CMD_RSP_BUFF 128 /* Rcv Command que buffer alignment */
  58. #define PI_ALIGN_K_UNSOL_BUFF 128 /* Unsol que buffer alignment */
  59. #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
  60. #define PI_ALIGN_K_RCV_DATA_BUFF 128 /* Rcv que buffer alignment */
  61. /* Define PHY index values */
  62. #define PI_PHY_K_S 0 /* Index to S phy */
  63. #define PI_PHY_K_A 0 /* Index to A phy */
  64. #define PI_PHY_K_B 1 /* Index to B phy */
  65. #define PI_PHY_K_MAX 2 /* Max number of phys */
  66. /* Define FMC descriptor fields */
  67. #define PI_FMC_DESCR_V_SOP 31
  68. #define PI_FMC_DESCR_V_EOP 30
  69. #define PI_FMC_DESCR_V_FSC 27
  70. #define PI_FMC_DESCR_V_FSB_ERROR 26
  71. #define PI_FMC_DESCR_V_FSB_ADDR_RECOG 25
  72. #define PI_FMC_DESCR_V_FSB_ADDR_COPIED 24
  73. #define PI_FMC_DESCR_V_FSB 22
  74. #define PI_FMC_DESCR_V_RCC_FLUSH 21
  75. #define PI_FMC_DESCR_V_RCC_CRC 20
  76. #define PI_FMC_DESCR_V_RCC_RRR 17
  77. #define PI_FMC_DESCR_V_RCC_DD 15
  78. #define PI_FMC_DESCR_V_RCC_SS 13
  79. #define PI_FMC_DESCR_V_RCC 13
  80. #define PI_FMC_DESCR_V_LEN 0
  81. #define PI_FMC_DESCR_M_SOP 0x80000000
  82. #define PI_FMC_DESCR_M_EOP 0x40000000
  83. #define PI_FMC_DESCR_M_FSC 0x38000000
  84. #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
  85. #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
  86. #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
  87. #define PI_FMC_DESCR_M_FSB 0x07C00000
  88. #define PI_FMC_DESCR_M_RCC_FLUSH 0x00200000
  89. #define PI_FMC_DESCR_M_RCC_CRC 0x00100000
  90. #define PI_FMC_DESCR_M_RCC_RRR 0x000E0000
  91. #define PI_FMC_DESCR_M_RCC_DD 0x00018000
  92. #define PI_FMC_DESCR_M_RCC_SS 0x00006000
  93. #define PI_FMC_DESCR_M_RCC 0x003FE000
  94. #define PI_FMC_DESCR_M_LEN 0x00001FFF
  95. #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR 0x01AA
  96. #define PI_FMC_DESCR_K_RRR_SUCCESS 0x00
  97. #define PI_FMC_DESCR_K_RRR_SA_MATCH 0x01
  98. #define PI_FMC_DESCR_K_RRR_DA_MATCH 0x02
  99. #define PI_FMC_DESCR_K_RRR_FMC_ABORT 0x03
  100. #define PI_FMC_DESCR_K_RRR_LENGTH_BAD 0x04
  101. #define PI_FMC_DESCR_K_RRR_FRAGMENT 0x05
  102. #define PI_FMC_DESCR_K_RRR_FORMAT_ERR 0x06
  103. #define PI_FMC_DESCR_K_RRR_MAC_RESET 0x07
  104. #define PI_FMC_DESCR_K_DD_NO_MATCH 0x0
  105. #define PI_FMC_DESCR_K_DD_PROMISCUOUS 0x1
  106. #define PI_FMC_DESCR_K_DD_CAM_MATCH 0x2
  107. #define PI_FMC_DESCR_K_DD_LOCAL_MATCH 0x3
  108. #define PI_FMC_DESCR_K_SS_NO_MATCH 0x0
  109. #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH 0x1
  110. #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE 0x2
  111. #define PI_FMC_DESCR_K_SS_LOCAL_MATCH 0x3
  112. /* Define some max buffer sizes */
  113. #define PI_CMD_REQ_K_SIZE_MAX 512
  114. #define PI_CMD_RSP_K_SIZE_MAX 512
  115. #define PI_UNSOL_K_SIZE_MAX 512
  116. #define PI_SMT_HOST_K_SIZE_MAX 4608 /* 4 1/2 K */
  117. #define PI_RCV_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
  118. #define PI_XMT_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
  119. /* Define adapter states */
  120. #define PI_STATE_K_RESET 0
  121. #define PI_STATE_K_UPGRADE 1
  122. #define PI_STATE_K_DMA_UNAVAIL 2
  123. #define PI_STATE_K_DMA_AVAIL 3
  124. #define PI_STATE_K_LINK_AVAIL 4
  125. #define PI_STATE_K_LINK_UNAVAIL 5
  126. #define PI_STATE_K_HALTED 6
  127. #define PI_STATE_K_RING_MEMBER 7
  128. #define PI_STATE_K_NUMBER 8
  129. /* Define codes for command type */
  130. #define PI_CMD_K_START 0x00
  131. #define PI_CMD_K_FILTERS_SET 0x01
  132. #define PI_CMD_K_FILTERS_GET 0x02
  133. #define PI_CMD_K_CHARS_SET 0x03
  134. #define PI_CMD_K_STATUS_CHARS_GET 0x04
  135. #define PI_CMD_K_CNTRS_GET 0x05
  136. #define PI_CMD_K_CNTRS_SET 0x06
  137. #define PI_CMD_K_ADDR_FILTER_SET 0x07
  138. #define PI_CMD_K_ADDR_FILTER_GET 0x08
  139. #define PI_CMD_K_ERROR_LOG_CLEAR 0x09
  140. #define PI_CMD_K_ERROR_LOG_GET 0x0A
  141. #define PI_CMD_K_FDDI_MIB_GET 0x0B
  142. #define PI_CMD_K_DEC_EXT_MIB_GET 0x0C
  143. #define PI_CMD_K_DEVICE_SPECIFIC_GET 0x0D
  144. #define PI_CMD_K_SNMP_SET 0x0E
  145. #define PI_CMD_K_UNSOL_TEST 0x0F
  146. #define PI_CMD_K_SMT_MIB_GET 0x10
  147. #define PI_CMD_K_SMT_MIB_SET 0x11
  148. #define PI_CMD_K_MAX 0x11 /* Must match last */
  149. /* Define item codes for Chars_Set and Filters_Set commands */
  150. #define PI_ITEM_K_EOL 0x00 /* End-of-Item list */
  151. #define PI_ITEM_K_T_REQ 0x01 /* DECnet T_REQ */
  152. #define PI_ITEM_K_TVX 0x02 /* DECnet TVX */
  153. #define PI_ITEM_K_RESTRICTED_TOKEN 0x03 /* DECnet Restricted Token */
  154. #define PI_ITEM_K_LEM_THRESHOLD 0x04 /* DECnet LEM Threshold */
  155. #define PI_ITEM_K_RING_PURGER 0x05 /* DECnet Ring Purger Enable */
  156. #define PI_ITEM_K_CNTR_INTERVAL 0x06 /* Chars_Set */
  157. #define PI_ITEM_K_IND_GROUP_PROM 0x07 /* Filters_Set */
  158. #define PI_ITEM_K_GROUP_PROM 0x08 /* Filters_Set */
  159. #define PI_ITEM_K_BROADCAST 0x09 /* Filters_Set */
  160. #define PI_ITEM_K_SMT_PROM 0x0A /* Filters_Set */
  161. #define PI_ITEM_K_SMT_USER 0x0B /* Filters_Set */
  162. #define PI_ITEM_K_RESERVED 0x0C /* Filters_Set */
  163. #define PI_ITEM_K_IMPLEMENTOR 0x0D /* Filters_Set */
  164. #define PI_ITEM_K_LOOPBACK_MODE 0x0E /* Chars_Set */
  165. #define PI_ITEM_K_CONFIG_POLICY 0x10 /* SMTConfigPolicy */
  166. #define PI_ITEM_K_CON_POLICY 0x11 /* SMTConnectionPolicy */
  167. #define PI_ITEM_K_T_NOTIFY 0x12 /* SMTTNotify */
  168. #define PI_ITEM_K_STATION_ACTION 0x13 /* SMTStationAction */
  169. #define PI_ITEM_K_MAC_PATHS_REQ 0x15 /* MACPathsRequested */
  170. #define PI_ITEM_K_MAC_ACTION 0x17 /* MACAction */
  171. #define PI_ITEM_K_CON_POLICIES 0x18 /* PORTConnectionPolicies */
  172. #define PI_ITEM_K_PORT_PATHS_REQ 0x19 /* PORTPathsRequested */
  173. #define PI_ITEM_K_MAC_LOOP_TIME 0x1A /* PORTMACLoopTime */
  174. #define PI_ITEM_K_TB_MAX 0x1B /* PORTTBMax */
  175. #define PI_ITEM_K_LER_CUTOFF 0x1C /* PORTLerCutoff */
  176. #define PI_ITEM_K_LER_ALARM 0x1D /* PORTLerAlarm */
  177. #define PI_ITEM_K_PORT_ACTION 0x1E /* PORTAction */
  178. #define PI_ITEM_K_FLUSH_TIME 0x20 /* Chars_Set */
  179. #define PI_ITEM_K_MAC_T_REQ 0x29 /* MACTReq */
  180. #define PI_ITEM_K_EMAC_RING_PURGER 0x2A /* eMACRingPurgerEnable */
  181. #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT 0x2B /* eMACRestrictedTokenTimeout */
  182. #define PI_ITEM_K_FDX_ENB_DIS 0x2C /* eFDXEnable */
  183. #define PI_ITEM_K_MAX 0x2C /* Must equal high item */
  184. /* Values for some of the items */
  185. #define PI_K_FALSE 0 /* Generic false */
  186. #define PI_K_TRUE 1 /* Generic true */
  187. #define PI_SNMP_K_TRUE 1 /* SNMP true/false values */
  188. #define PI_SNMP_K_FALSE 2
  189. #define PI_FSTATE_K_BLOCK 0 /* Filter State */
  190. #define PI_FSTATE_K_PASS 1
  191. /* Define command return codes */
  192. #define PI_RSP_K_SUCCESS 0x00
  193. #define PI_RSP_K_FAILURE 0x01
  194. #define PI_RSP_K_WARNING 0x02
  195. #define PI_RSP_K_LOOP_MODE_BAD 0x03
  196. #define PI_RSP_K_ITEM_CODE_BAD 0x04
  197. #define PI_RSP_K_TVX_BAD 0x05
  198. #define PI_RSP_K_TREQ_BAD 0x06
  199. #define PI_RSP_K_TOKEN_BAD 0x07
  200. #define PI_RSP_K_NO_EOL 0x0C
  201. #define PI_RSP_K_FILTER_STATE_BAD 0x0D
  202. #define PI_RSP_K_CMD_TYPE_BAD 0x0E
  203. #define PI_RSP_K_ADAPTER_STATE_BAD 0x0F
  204. #define PI_RSP_K_RING_PURGER_BAD 0x10
  205. #define PI_RSP_K_LEM_THRESHOLD_BAD 0x11
  206. #define PI_RSP_K_LOOP_NOT_SUPPORTED 0x12
  207. #define PI_RSP_K_FLUSH_TIME_BAD 0x13
  208. #define PI_RSP_K_NOT_IMPLEMENTED 0x14
  209. #define PI_RSP_K_CONFIG_POLICY_BAD 0x15
  210. #define PI_RSP_K_STATION_ACTION_BAD 0x16
  211. #define PI_RSP_K_MAC_ACTION_BAD 0x17
  212. #define PI_RSP_K_CON_POLICIES_BAD 0x18
  213. #define PI_RSP_K_MAC_LOOP_TIME_BAD 0x19
  214. #define PI_RSP_K_TB_MAX_BAD 0x1A
  215. #define PI_RSP_K_LER_CUTOFF_BAD 0x1B
  216. #define PI_RSP_K_LER_ALARM_BAD 0x1C
  217. #define PI_RSP_K_MAC_PATHS_REQ_BAD 0x1D
  218. #define PI_RSP_K_MAC_T_REQ_BAD 0x1E
  219. #define PI_RSP_K_EMAC_RING_PURGER_BAD 0x1F
  220. #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD 0x20
  221. #define PI_RSP_K_NO_SUCH_ENTRY 0x21
  222. #define PI_RSP_K_T_NOTIFY_BAD 0x22
  223. #define PI_RSP_K_TR_MAX_EXP_BAD 0x23
  224. #define PI_RSP_K_MAC_FRM_ERR_THR_BAD 0x24
  225. #define PI_RSP_K_MAX_T_REQ_BAD 0x25
  226. #define PI_RSP_K_FDX_ENB_DIS_BAD 0x26
  227. #define PI_RSP_K_ITEM_INDEX_BAD 0x27
  228. #define PI_RSP_K_PORT_ACTION_BAD 0x28
  229. /* Commonly used structures */
  230. typedef struct /* Item list */
  231. {
  232. PI_UINT32 item_code;
  233. PI_UINT32 value;
  234. } PI_ITEM_LIST;
  235. typedef struct /* Response header */
  236. {
  237. PI_UINT32 reserved;
  238. PI_UINT32 cmd_type;
  239. PI_UINT32 status;
  240. } PI_RSP_HEADER;
  241. /* Start Command */
  242. typedef struct
  243. {
  244. PI_UINT32 cmd_type;
  245. } PI_CMD_START_REQ;
  246. /* Start Response */
  247. typedef struct
  248. {
  249. PI_RSP_HEADER header;
  250. } PI_CMD_START_RSP;
  251. /* Filters_Set Request */
  252. #define PI_CMD_FILTERS_SET_K_ITEMS_MAX 63 /* Fits in a 512 byte buffer */
  253. typedef struct
  254. {
  255. PI_UINT32 cmd_type;
  256. PI_ITEM_LIST item[PI_CMD_FILTERS_SET_K_ITEMS_MAX];
  257. } PI_CMD_FILTERS_SET_REQ;
  258. /* Filters_Set Response */
  259. typedef struct
  260. {
  261. PI_RSP_HEADER header;
  262. } PI_CMD_FILTERS_SET_RSP;
  263. /* Filters_Get Request */
  264. typedef struct
  265. {
  266. PI_UINT32 cmd_type;
  267. } PI_CMD_FILTERS_GET_REQ;
  268. /* Filters_Get Response */
  269. typedef struct
  270. {
  271. PI_RSP_HEADER header;
  272. PI_UINT32 ind_group_prom;
  273. PI_UINT32 group_prom;
  274. PI_UINT32 broadcast_all;
  275. PI_UINT32 smt_all;
  276. PI_UINT32 smt_user;
  277. PI_UINT32 reserved_all;
  278. PI_UINT32 implementor_all;
  279. } PI_CMD_FILTERS_GET_RSP;
  280. /* Chars_Set Request */
  281. #define PI_CMD_CHARS_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
  282. typedef struct
  283. {
  284. PI_UINT32 cmd_type;
  285. struct /* Item list */
  286. {
  287. PI_UINT32 item_code;
  288. PI_UINT32 value;
  289. PI_UINT32 item_index;
  290. } item[PI_CMD_CHARS_SET_K_ITEMS_MAX];
  291. } PI_CMD_CHARS_SET_REQ;
  292. /* Chars_Set Response */
  293. typedef struct
  294. {
  295. PI_RSP_HEADER header;
  296. } PI_CMD_CHARS_SET_RSP;
  297. /* SNMP_Set Request */
  298. #define PI_CMD_SNMP_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
  299. typedef struct
  300. {
  301. PI_UINT32 cmd_type;
  302. struct /* Item list */
  303. {
  304. PI_UINT32 item_code;
  305. PI_UINT32 value;
  306. PI_UINT32 item_index;
  307. } item[PI_CMD_SNMP_SET_K_ITEMS_MAX];
  308. } PI_CMD_SNMP_SET_REQ;
  309. /* SNMP_Set Response */
  310. typedef struct
  311. {
  312. PI_RSP_HEADER header;
  313. } PI_CMD_SNMP_SET_RSP;
  314. /* SMT_MIB_Set Request */
  315. #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42 /* Max number of items */
  316. typedef struct
  317. {
  318. PI_UINT32 cmd_type;
  319. struct
  320. {
  321. PI_UINT32 item_code;
  322. PI_UINT32 value;
  323. PI_UINT32 item_index;
  324. } item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX];
  325. } PI_CMD_SMT_MIB_SET_REQ;
  326. /* SMT_MIB_Set Response */
  327. typedef struct
  328. {
  329. PI_RSP_HEADER header;
  330. } PI_CMD_SMT_MIB_SET_RSP;
  331. /* SMT_MIB_Get Request */
  332. typedef struct
  333. {
  334. PI_UINT32 cmd_type;
  335. } PI_CMD_SMT_MIB_GET_REQ;
  336. /* SMT_MIB_Get Response */
  337. typedef struct /* Refer to ANSI FDDI SMT Rev. 7.3 */
  338. {
  339. PI_RSP_HEADER header;
  340. /* SMT GROUP */
  341. PI_STATION_ID smt_station_id;
  342. PI_UINT32 smt_op_version_id;
  343. PI_UINT32 smt_hi_version_id;
  344. PI_UINT32 smt_lo_version_id;
  345. PI_UINT32 smt_user_data[8];
  346. PI_UINT32 smt_mib_version_id;
  347. PI_UINT32 smt_mac_ct;
  348. PI_UINT32 smt_non_master_ct;
  349. PI_UINT32 smt_master_ct;
  350. PI_UINT32 smt_available_paths;
  351. PI_UINT32 smt_config_capabilities;
  352. PI_UINT32 smt_config_policy;
  353. PI_UINT32 smt_connection_policy;
  354. PI_UINT32 smt_t_notify;
  355. PI_UINT32 smt_stat_rpt_policy;
  356. PI_UINT32 smt_trace_max_expiration;
  357. PI_UINT32 smt_bypass_present;
  358. PI_UINT32 smt_ecm_state;
  359. PI_UINT32 smt_cf_state;
  360. PI_UINT32 smt_remote_disconnect_flag;
  361. PI_UINT32 smt_station_status;
  362. PI_UINT32 smt_peer_wrap_flag;
  363. PI_CNTR smt_msg_time_stamp;
  364. PI_CNTR smt_transition_time_stamp;
  365. /* MAC GROUP */
  366. PI_UINT32 mac_frame_status_functions;
  367. PI_UINT32 mac_t_max_capability;
  368. PI_UINT32 mac_tvx_capability;
  369. PI_UINT32 mac_available_paths;
  370. PI_UINT32 mac_current_path;
  371. PI_LAN_ADDR mac_upstream_nbr;
  372. PI_LAN_ADDR mac_downstream_nbr;
  373. PI_LAN_ADDR mac_old_upstream_nbr;
  374. PI_LAN_ADDR mac_old_downstream_nbr;
  375. PI_UINT32 mac_dup_address_test;
  376. PI_UINT32 mac_requested_paths;
  377. PI_UINT32 mac_downstream_port_type;
  378. PI_LAN_ADDR mac_smt_address;
  379. PI_UINT32 mac_t_req;
  380. PI_UINT32 mac_t_neg;
  381. PI_UINT32 mac_t_max;
  382. PI_UINT32 mac_tvx_value;
  383. PI_UINT32 mac_frame_error_threshold;
  384. PI_UINT32 mac_frame_error_ratio;
  385. PI_UINT32 mac_rmt_state;
  386. PI_UINT32 mac_da_flag;
  387. PI_UINT32 mac_unda_flag;
  388. PI_UINT32 mac_frame_error_flag;
  389. PI_UINT32 mac_ma_unitdata_available;
  390. PI_UINT32 mac_hardware_present;
  391. PI_UINT32 mac_ma_unitdata_enable;
  392. /* PATH GROUP */
  393. PI_UINT32 path_configuration[8];
  394. PI_UINT32 path_tvx_lower_bound;
  395. PI_UINT32 path_t_max_lower_bound;
  396. PI_UINT32 path_max_t_req;
  397. /* PORT GROUP */
  398. PI_UINT32 port_my_type[PI_PHY_K_MAX];
  399. PI_UINT32 port_neighbor_type[PI_PHY_K_MAX];
  400. PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
  401. PI_UINT32 port_mac_indicated[PI_PHY_K_MAX];
  402. PI_UINT32 port_current_path[PI_PHY_K_MAX];
  403. PI_UINT32 port_requested_paths[PI_PHY_K_MAX];
  404. PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
  405. PI_UINT32 port_available_paths[PI_PHY_K_MAX];
  406. PI_UINT32 port_pmd_class[PI_PHY_K_MAX];
  407. PI_UINT32 port_connection_capabilities[PI_PHY_K_MAX];
  408. PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
  409. PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
  410. PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
  411. PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
  412. PI_UINT32 port_connect_state[PI_PHY_K_MAX];
  413. PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
  414. PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
  415. PI_UINT32 port_ler_flag[PI_PHY_K_MAX];
  416. PI_UINT32 port_hardware_present[PI_PHY_K_MAX];
  417. /* GROUP for things that were added later, so must be at the end. */
  418. PI_CNTR path_ring_latency;
  419. } PI_CMD_SMT_MIB_GET_RSP;
  420. /*
  421. * Item and group code definitions for SMT 7.3 mandatory objects. These
  422. * definitions are to be used as appropriate in SMT_MIB_SET commands and
  423. * certain host-sent SMT frames such as PMF Get and Set requests. The
  424. * codes have been taken from the MIB summary section of ANSI SMT 7.3.
  425. */
  426. #define PI_GRP_K_SMT_STATION_ID 0x100A
  427. #define PI_ITEM_K_SMT_STATION_ID 0x100B
  428. #define PI_ITEM_K_SMT_OP_VERS_ID 0x100D
  429. #define PI_ITEM_K_SMT_HI_VERS_ID 0x100E
  430. #define PI_ITEM_K_SMT_LO_VERS_ID 0x100F
  431. #define PI_ITEM_K_SMT_USER_DATA 0x1011
  432. #define PI_ITEM_K_SMT_MIB_VERS_ID 0x1012
  433. #define PI_GRP_K_SMT_STATION_CONFIG 0x1014
  434. #define PI_ITEM_K_SMT_MAC_CT 0x1015
  435. #define PI_ITEM_K_SMT_NON_MASTER_CT 0x1016
  436. #define PI_ITEM_K_SMT_MASTER_CT 0x1017
  437. #define PI_ITEM_K_SMT_AVAIL_PATHS 0x1018
  438. #define PI_ITEM_K_SMT_CONFIG_CAPS 0x1019
  439. #define PI_ITEM_K_SMT_CONFIG_POL 0x101A
  440. #define PI_ITEM_K_SMT_CONN_POL 0x101B
  441. #define PI_ITEM_K_SMT_T_NOTIFY 0x101D
  442. #define PI_ITEM_K_SMT_STAT_POL 0x101E
  443. #define PI_ITEM_K_SMT_TR_MAX_EXP 0x101F
  444. #define PI_ITEM_K_SMT_PORT_INDEXES 0x1020
  445. #define PI_ITEM_K_SMT_MAC_INDEXES 0x1021
  446. #define PI_ITEM_K_SMT_BYPASS_PRESENT 0x1022
  447. #define PI_GRP_K_SMT_STATUS 0x1028
  448. #define PI_ITEM_K_SMT_ECM_STATE 0x1029
  449. #define PI_ITEM_K_SMT_CF_STATE 0x102A
  450. #define PI_ITEM_K_SMT_REM_DISC_FLAG 0x102C
  451. #define PI_ITEM_K_SMT_STATION_STATUS 0x102D
  452. #define PI_ITEM_K_SMT_PEER_WRAP_FLAG 0x102E
  453. #define PI_GRP_K_SMT_MIB_OPERATION 0x1032
  454. #define PI_ITEM_K_SMT_MSG_TIME_STAMP 0x1033
  455. #define PI_ITEM_K_SMT_TRN_TIME_STAMP 0x1034
  456. #define PI_ITEM_K_SMT_STATION_ACT 0x103C
  457. #define PI_GRP_K_MAC_CAPABILITIES 0x200A
  458. #define PI_ITEM_K_MAC_FRM_STAT_FUNC 0x200B
  459. #define PI_ITEM_K_MAC_T_MAX_CAP 0x200D
  460. #define PI_ITEM_K_MAC_TVX_CAP 0x200E
  461. #define PI_GRP_K_MAC_CONFIG 0x2014
  462. #define PI_ITEM_K_MAC_AVAIL_PATHS 0x2016
  463. #define PI_ITEM_K_MAC_CURRENT_PATH 0x2017
  464. #define PI_ITEM_K_MAC_UP_NBR 0x2018
  465. #define PI_ITEM_K_MAC_DOWN_NBR 0x2019
  466. #define PI_ITEM_K_MAC_OLD_UP_NBR 0x201A
  467. #define PI_ITEM_K_MAC_OLD_DOWN_NBR 0x201B
  468. #define PI_ITEM_K_MAC_DUP_ADDR_TEST 0x201D
  469. #define PI_ITEM_K_MAC_REQ_PATHS 0x2020
  470. #define PI_ITEM_K_MAC_DOWN_PORT_TYPE 0x2021
  471. #define PI_ITEM_K_MAC_INDEX 0x2022
  472. #define PI_GRP_K_MAC_ADDRESS 0x2028
  473. #define PI_ITEM_K_MAC_SMT_ADDRESS 0x2029
  474. #define PI_GRP_K_MAC_OPERATION 0x2032
  475. #define PI_ITEM_K_MAC_TREQ 0x2033
  476. #define PI_ITEM_K_MAC_TNEG 0x2034
  477. #define PI_ITEM_K_MAC_TMAX 0x2035
  478. #define PI_ITEM_K_MAC_TVX_VALUE 0x2036
  479. #define PI_GRP_K_MAC_COUNTERS 0x2046
  480. #define PI_ITEM_K_MAC_FRAME_CT 0x2047
  481. #define PI_ITEM_K_MAC_COPIED_CT 0x2048
  482. #define PI_ITEM_K_MAC_TRANSMIT_CT 0x2049
  483. #define PI_ITEM_K_MAC_ERROR_CT 0x2051
  484. #define PI_ITEM_K_MAC_LOST_CT 0x2052
  485. #define PI_GRP_K_MAC_FRM_ERR_COND 0x205A
  486. #define PI_ITEM_K_MAC_FRM_ERR_THR 0x205F
  487. #define PI_ITEM_K_MAC_FRM_ERR_RAT 0x2060
  488. #define PI_GRP_K_MAC_STATUS 0x206E
  489. #define PI_ITEM_K_MAC_RMT_STATE 0x206F
  490. #define PI_ITEM_K_MAC_DA_FLAG 0x2070
  491. #define PI_ITEM_K_MAC_UNDA_FLAG 0x2071
  492. #define PI_ITEM_K_MAC_FRM_ERR_FLAG 0x2072
  493. #define PI_ITEM_K_MAC_MA_UNIT_AVAIL 0x2074
  494. #define PI_ITEM_K_MAC_HW_PRESENT 0x2075
  495. #define PI_ITEM_K_MAC_MA_UNIT_ENAB 0x2076
  496. #define PI_GRP_K_PATH_CONFIG 0x320A
  497. #define PI_ITEM_K_PATH_INDEX 0x320B
  498. #define PI_ITEM_K_PATH_CONFIGURATION 0x3212
  499. #define PI_ITEM_K_PATH_TVX_LB 0x3215
  500. #define PI_ITEM_K_PATH_T_MAX_LB 0x3216
  501. #define PI_ITEM_K_PATH_MAX_T_REQ 0x3217
  502. #define PI_GRP_K_PORT_CONFIG 0x400A
  503. #define PI_ITEM_K_PORT_MY_TYPE 0x400C
  504. #define PI_ITEM_K_PORT_NBR_TYPE 0x400D
  505. #define PI_ITEM_K_PORT_CONN_POLS 0x400E
  506. #define PI_ITEM_K_PORT_MAC_INDICATED 0x400F
  507. #define PI_ITEM_K_PORT_CURRENT_PATH 0x4010
  508. #define PI_ITEM_K_PORT_REQ_PATHS 0x4011
  509. #define PI_ITEM_K_PORT_MAC_PLACEMENT 0x4012
  510. #define PI_ITEM_K_PORT_AVAIL_PATHS 0x4013
  511. #define PI_ITEM_K_PORT_PMD_CLASS 0x4016
  512. #define PI_ITEM_K_PORT_CONN_CAPS 0x4017
  513. #define PI_ITEM_K_PORT_INDEX 0x401D
  514. #define PI_GRP_K_PORT_OPERATION 0x401E
  515. #define PI_ITEM_K_PORT_BS_FLAG 0x4021
  516. #define PI_GRP_K_PORT_ERR_CNTRS 0x4028
  517. #define PI_ITEM_K_PORT_LCT_FAIL_CT 0x402A
  518. #define PI_GRP_K_PORT_LER 0x4032
  519. #define PI_ITEM_K_PORT_LER_ESTIMATE 0x4033
  520. #define PI_ITEM_K_PORT_LEM_REJ_CT 0x4034
  521. #define PI_ITEM_K_PORT_LEM_CT 0x4035
  522. #define PI_ITEM_K_PORT_LER_CUTOFF 0x403A
  523. #define PI_ITEM_K_PORT_LER_ALARM 0x403B
  524. #define PI_GRP_K_PORT_STATUS 0x403C
  525. #define PI_ITEM_K_PORT_CONNECT_STATE 0x403D
  526. #define PI_ITEM_K_PORT_PCM_STATE 0x403E
  527. #define PI_ITEM_K_PORT_PC_WITHHOLD 0x403F
  528. #define PI_ITEM_K_PORT_LER_FLAG 0x4040
  529. #define PI_ITEM_K_PORT_HW_PRESENT 0x4041
  530. #define PI_ITEM_K_PORT_ACT 0x4046
  531. /* Addr_Filter_Set Request */
  532. #define PI_CMD_ADDR_FILTER_K_SIZE 62
  533. typedef struct
  534. {
  535. PI_UINT32 cmd_type;
  536. PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
  537. } PI_CMD_ADDR_FILTER_SET_REQ;
  538. /* Addr_Filter_Set Response */
  539. typedef struct
  540. {
  541. PI_RSP_HEADER header;
  542. } PI_CMD_ADDR_FILTER_SET_RSP;
  543. /* Addr_Filter_Get Request */
  544. typedef struct
  545. {
  546. PI_UINT32 cmd_type;
  547. } PI_CMD_ADDR_FILTER_GET_REQ;
  548. /* Addr_Filter_Get Response */
  549. typedef struct
  550. {
  551. PI_RSP_HEADER header;
  552. PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
  553. } PI_CMD_ADDR_FILTER_GET_RSP;
  554. /* Status_Chars_Get Request */
  555. typedef struct
  556. {
  557. PI_UINT32 cmd_type;
  558. } PI_CMD_STATUS_CHARS_GET_REQ;
  559. /* Status_Chars_Get Response */
  560. typedef struct
  561. {
  562. PI_RSP_HEADER header;
  563. PI_STATION_ID station_id; /* Station */
  564. PI_UINT32 station_type;
  565. PI_UINT32 smt_ver_id;
  566. PI_UINT32 smt_ver_id_max;
  567. PI_UINT32 smt_ver_id_min;
  568. PI_UINT32 station_state;
  569. PI_LAN_ADDR link_addr; /* Link */
  570. PI_UINT32 t_req;
  571. PI_UINT32 tvx;
  572. PI_UINT32 token_timeout;
  573. PI_UINT32 purger_enb;
  574. PI_UINT32 link_state;
  575. PI_UINT32 tneg;
  576. PI_UINT32 dup_addr_flag;
  577. PI_LAN_ADDR una;
  578. PI_LAN_ADDR una_old;
  579. PI_UINT32 un_dup_addr_flag;
  580. PI_LAN_ADDR dna;
  581. PI_LAN_ADDR dna_old;
  582. PI_UINT32 purger_state;
  583. PI_UINT32 fci_mode;
  584. PI_UINT32 error_reason;
  585. PI_UINT32 loopback;
  586. PI_UINT32 ring_latency;
  587. PI_LAN_ADDR last_dir_beacon_sa;
  588. PI_LAN_ADDR last_dir_beacon_una;
  589. PI_UINT32 phy_type[PI_PHY_K_MAX]; /* Phy */
  590. PI_UINT32 pmd_type[PI_PHY_K_MAX];
  591. PI_UINT32 lem_threshold[PI_PHY_K_MAX];
  592. PI_UINT32 phy_state[PI_PHY_K_MAX];
  593. PI_UINT32 nbor_phy_type[PI_PHY_K_MAX];
  594. PI_UINT32 link_error_est[PI_PHY_K_MAX];
  595. PI_UINT32 broken_reason[PI_PHY_K_MAX];
  596. PI_UINT32 reject_reason[PI_PHY_K_MAX];
  597. PI_UINT32 cntr_interval; /* Miscellaneous */
  598. PI_UINT32 module_rev;
  599. PI_UINT32 firmware_rev;
  600. PI_UINT32 mop_device_type;
  601. PI_UINT32 phy_led[PI_PHY_K_MAX];
  602. PI_UINT32 flush_time;
  603. } PI_CMD_STATUS_CHARS_GET_RSP;
  604. /* FDDI_MIB_Get Request */
  605. typedef struct
  606. {
  607. PI_UINT32 cmd_type;
  608. } PI_CMD_FDDI_MIB_GET_REQ;
  609. /* FDDI_MIB_Get Response */
  610. typedef struct
  611. {
  612. PI_RSP_HEADER header;
  613. /* SMT GROUP */
  614. PI_STATION_ID smt_station_id;
  615. PI_UINT32 smt_op_version_id;
  616. PI_UINT32 smt_hi_version_id;
  617. PI_UINT32 smt_lo_version_id;
  618. PI_UINT32 smt_mac_ct;
  619. PI_UINT32 smt_non_master_ct;
  620. PI_UINT32 smt_master_ct;
  621. PI_UINT32 smt_paths_available;
  622. PI_UINT32 smt_config_capabilities;
  623. PI_UINT32 smt_config_policy;
  624. PI_UINT32 smt_connection_policy;
  625. PI_UINT32 smt_t_notify;
  626. PI_UINT32 smt_status_reporting;
  627. PI_UINT32 smt_ecm_state;
  628. PI_UINT32 smt_cf_state;
  629. PI_UINT32 smt_hold_state;
  630. PI_UINT32 smt_remote_disconnect_flag;
  631. PI_UINT32 smt_station_action;
  632. /* MAC GROUP */
  633. PI_UINT32 mac_frame_status_capabilities;
  634. PI_UINT32 mac_t_max_greatest_lower_bound;
  635. PI_UINT32 mac_tvx_greatest_lower_bound;
  636. PI_UINT32 mac_paths_available;
  637. PI_UINT32 mac_current_path;
  638. PI_LAN_ADDR mac_upstream_nbr;
  639. PI_LAN_ADDR mac_old_upstream_nbr;
  640. PI_UINT32 mac_dup_addr_test;
  641. PI_UINT32 mac_paths_requested;
  642. PI_UINT32 mac_downstream_port_type;
  643. PI_LAN_ADDR mac_smt_address;
  644. PI_UINT32 mac_t_req;
  645. PI_UINT32 mac_t_neg;
  646. PI_UINT32 mac_t_max;
  647. PI_UINT32 mac_tvx_value;
  648. PI_UINT32 mac_t_min;
  649. PI_UINT32 mac_current_frame_status;
  650. /* mac_frame_cts */
  651. /* mac_error_cts */
  652. /* mac_lost_cts */
  653. PI_UINT32 mac_frame_error_threshold;
  654. PI_UINT32 mac_frame_error_ratio;
  655. PI_UINT32 mac_rmt_state;
  656. PI_UINT32 mac_da_flag;
  657. PI_UINT32 mac_una_da_flag;
  658. PI_UINT32 mac_frame_condition;
  659. PI_UINT32 mac_chip_set;
  660. PI_UINT32 mac_action;
  661. /* PATH GROUP => Does not need to be implemented */
  662. /* PORT GROUP */
  663. PI_UINT32 port_pc_type[PI_PHY_K_MAX];
  664. PI_UINT32 port_pc_neighbor[PI_PHY_K_MAX];
  665. PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
  666. PI_UINT32 port_remote_mac_indicated[PI_PHY_K_MAX];
  667. PI_UINT32 port_ce_state[PI_PHY_K_MAX];
  668. PI_UINT32 port_paths_requested[PI_PHY_K_MAX];
  669. PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
  670. PI_UINT32 port_available_paths[PI_PHY_K_MAX];
  671. PI_UINT32 port_mac_loop_time[PI_PHY_K_MAX];
  672. PI_UINT32 port_tb_max[PI_PHY_K_MAX];
  673. PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
  674. /* port_lct_fail_cts[PI_PHY_K_MAX]; */
  675. PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
  676. /* port_lem_reject_cts[PI_PHY_K_MAX]; */
  677. /* port_lem_cts[PI_PHY_K_MAX]; */
  678. PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
  679. PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
  680. PI_UINT32 port_connect_state[PI_PHY_K_MAX];
  681. PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
  682. PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
  683. PI_UINT32 port_ler_condition[PI_PHY_K_MAX];
  684. PI_UINT32 port_chip_set[PI_PHY_K_MAX];
  685. PI_UINT32 port_action[PI_PHY_K_MAX];
  686. /* ATTACHMENT GROUP */
  687. PI_UINT32 attachment_class;
  688. PI_UINT32 attachment_ob_present;
  689. PI_UINT32 attachment_imax_expiration;
  690. PI_UINT32 attachment_inserted_status;
  691. PI_UINT32 attachment_insert_policy;
  692. /* CHIP SET GROUP => Does not need to be implemented */
  693. } PI_CMD_FDDI_MIB_GET_RSP;
  694. /* DEC_Ext_MIB_Get Request */
  695. typedef struct
  696. {
  697. PI_UINT32 cmd_type;
  698. } PI_CMD_DEC_EXT_MIB_GET_REQ;
  699. /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */
  700. typedef struct
  701. {
  702. PI_RSP_HEADER header;
  703. /* SMT GROUP */
  704. PI_UINT32 esmt_station_type;
  705. /* MAC GROUP */
  706. PI_UINT32 emac_link_state;
  707. PI_UINT32 emac_ring_purger_state;
  708. PI_UINT32 emac_ring_purger_enable;
  709. PI_UINT32 emac_frame_strip_mode;
  710. PI_UINT32 emac_ring_error_reason;
  711. PI_UINT32 emac_up_nbr_dup_addr_flag;
  712. PI_UINT32 emac_restricted_token_timeout;
  713. /* PORT GROUP */
  714. PI_UINT32 eport_pmd_type[PI_PHY_K_MAX];
  715. PI_UINT32 eport_phy_state[PI_PHY_K_MAX];
  716. PI_UINT32 eport_reject_reason[PI_PHY_K_MAX];
  717. /* FDX (Full-Duplex) GROUP */
  718. PI_UINT32 efdx_enable; /* Valid only in SMT 7.3 */
  719. PI_UINT32 efdx_op; /* Valid only in SMT 7.3 */
  720. PI_UINT32 efdx_state; /* Valid only in SMT 7.3 */
  721. } PI_CMD_DEC_EXT_MIB_GET_RSP;
  722. typedef struct
  723. {
  724. PI_CNTR traces_rcvd; /* Station */
  725. PI_CNTR frame_cnt; /* Link */
  726. PI_CNTR error_cnt;
  727. PI_CNTR lost_cnt;
  728. PI_CNTR octets_rcvd;
  729. PI_CNTR octets_sent;
  730. PI_CNTR pdus_rcvd;
  731. PI_CNTR pdus_sent;
  732. PI_CNTR mcast_octets_rcvd;
  733. PI_CNTR mcast_octets_sent;
  734. PI_CNTR mcast_pdus_rcvd;
  735. PI_CNTR mcast_pdus_sent;
  736. PI_CNTR xmt_underruns;
  737. PI_CNTR xmt_failures;
  738. PI_CNTR block_check_errors;
  739. PI_CNTR frame_status_errors;
  740. PI_CNTR pdu_length_errors;
  741. PI_CNTR rcv_overruns;
  742. PI_CNTR user_buff_unavailable;
  743. PI_CNTR inits_initiated;
  744. PI_CNTR inits_rcvd;
  745. PI_CNTR beacons_initiated;
  746. PI_CNTR dup_addrs;
  747. PI_CNTR dup_tokens;
  748. PI_CNTR purge_errors;
  749. PI_CNTR fci_strip_errors;
  750. PI_CNTR traces_initiated;
  751. PI_CNTR directed_beacons_rcvd;
  752. PI_CNTR emac_frame_alignment_errors;
  753. PI_CNTR ebuff_errors[PI_PHY_K_MAX]; /* Phy */
  754. PI_CNTR lct_rejects[PI_PHY_K_MAX];
  755. PI_CNTR lem_rejects[PI_PHY_K_MAX];
  756. PI_CNTR link_errors[PI_PHY_K_MAX];
  757. PI_CNTR connections[PI_PHY_K_MAX];
  758. PI_CNTR copied_cnt; /* Valid only if using SMT 7.3 */
  759. PI_CNTR transmit_cnt; /* Valid only if using SMT 7.3 */
  760. PI_CNTR tokens;
  761. } PI_CNTR_BLK;
  762. /* Counters_Get Request */
  763. typedef struct
  764. {
  765. PI_UINT32 cmd_type;
  766. } PI_CMD_CNTRS_GET_REQ;
  767. /* Counters_Get Response */
  768. typedef struct
  769. {
  770. PI_RSP_HEADER header;
  771. PI_CNTR time_since_reset;
  772. PI_CNTR_BLK cntrs;
  773. } PI_CMD_CNTRS_GET_RSP;
  774. /* Counters_Set Request */
  775. typedef struct
  776. {
  777. PI_UINT32 cmd_type;
  778. PI_CNTR_BLK cntrs;
  779. } PI_CMD_CNTRS_SET_REQ;
  780. /* Counters_Set Response */
  781. typedef struct
  782. {
  783. PI_RSP_HEADER header;
  784. } PI_CMD_CNTRS_SET_RSP;
  785. /* Error_Log_Clear Request */
  786. typedef struct
  787. {
  788. PI_UINT32 cmd_type;
  789. } PI_CMD_ERROR_LOG_CLEAR_REQ;
  790. /* Error_Log_Clear Response */
  791. typedef struct
  792. {
  793. PI_RSP_HEADER header;
  794. } PI_CMD_ERROR_LOG_CLEAR_RSP;
  795. /* Error_Log_Get Request */
  796. #define PI_LOG_ENTRY_K_INDEX_MIN 0 /* Minimum index for entry */
  797. typedef struct
  798. {
  799. PI_UINT32 cmd_type;
  800. PI_UINT32 entry_index;
  801. } PI_CMD_ERROR_LOG_GET_REQ;
  802. /* Error_Log_Get Response */
  803. #define PI_K_LOG_FW_SIZE 111 /* Max number of fw longwords */
  804. #define PI_K_LOG_DIAG_SIZE 6 /* Max number of diag longwords */
  805. typedef struct
  806. {
  807. struct
  808. {
  809. PI_UINT32 fru_imp_mask;
  810. PI_UINT32 test_id;
  811. PI_UINT32 reserved[PI_K_LOG_DIAG_SIZE];
  812. } diag;
  813. PI_UINT32 fw[PI_K_LOG_FW_SIZE];
  814. } PI_LOG_ENTRY;
  815. typedef struct
  816. {
  817. PI_RSP_HEADER header;
  818. PI_UINT32 event_status;
  819. PI_UINT32 caller_id;
  820. PI_UINT32 timestamp_l;
  821. PI_UINT32 timestamp_h;
  822. PI_UINT32 write_count;
  823. PI_LOG_ENTRY entry_info;
  824. } PI_CMD_ERROR_LOG_GET_RSP;
  825. /* Define error log related constants and types. */
  826. /* Not all of the caller id's can occur. The only ones currently */
  827. /* implemented are: none, selftest, mfg, fw, console */
  828. #define PI_LOG_EVENT_STATUS_K_VALID 0 /* Valid Event Status */
  829. #define PI_LOG_EVENT_STATUS_K_INVALID 1 /* Invalid Event Status */
  830. #define PI_LOG_CALLER_ID_K_NONE 0 /* No caller */
  831. #define PI_LOG_CALLER_ID_K_SELFTEST 1 /* Normal power-up selftest */
  832. #define PI_LOG_CALLER_ID_K_MFG 2 /* Mfg power-up selftest */
  833. #define PI_LOG_CALLER_ID_K_ONLINE 3 /* On-line diagnostics */
  834. #define PI_LOG_CALLER_ID_K_HW 4 /* Hardware */
  835. #define PI_LOG_CALLER_ID_K_FW 5 /* Firmware */
  836. #define PI_LOG_CALLER_ID_K_CNS_HW 6 /* CNS firmware */
  837. #define PI_LOG_CALLER_ID_K_CNS_FW 7 /* CNS hardware */
  838. #define PI_LOG_CALLER_ID_K_CONSOLE 8 /* Console Caller Id */
  839. /*
  840. * Place all DMA commands in the following request and response structures
  841. * to simplify code.
  842. */
  843. typedef union
  844. {
  845. PI_UINT32 cmd_type;
  846. PI_CMD_START_REQ start;
  847. PI_CMD_FILTERS_SET_REQ filter_set;
  848. PI_CMD_FILTERS_GET_REQ filter_get;
  849. PI_CMD_CHARS_SET_REQ char_set;
  850. PI_CMD_ADDR_FILTER_SET_REQ addr_filter_set;
  851. PI_CMD_ADDR_FILTER_GET_REQ addr_filter_get;
  852. PI_CMD_STATUS_CHARS_GET_REQ stat_char_get;
  853. PI_CMD_CNTRS_GET_REQ cntrs_get;
  854. PI_CMD_CNTRS_SET_REQ cntrs_set;
  855. PI_CMD_ERROR_LOG_CLEAR_REQ error_log_clear;
  856. PI_CMD_ERROR_LOG_GET_REQ error_log_read;
  857. PI_CMD_SNMP_SET_REQ snmp_set;
  858. PI_CMD_FDDI_MIB_GET_REQ fddi_mib_get;
  859. PI_CMD_DEC_EXT_MIB_GET_REQ dec_mib_get;
  860. PI_CMD_SMT_MIB_SET_REQ smt_mib_set;
  861. PI_CMD_SMT_MIB_GET_REQ smt_mib_get;
  862. char pad[PI_CMD_REQ_K_SIZE_MAX];
  863. } PI_DMA_CMD_REQ;
  864. typedef union
  865. {
  866. PI_RSP_HEADER header;
  867. PI_CMD_START_RSP start;
  868. PI_CMD_FILTERS_SET_RSP filter_set;
  869. PI_CMD_FILTERS_GET_RSP filter_get;
  870. PI_CMD_CHARS_SET_RSP char_set;
  871. PI_CMD_ADDR_FILTER_SET_RSP addr_filter_set;
  872. PI_CMD_ADDR_FILTER_GET_RSP addr_filter_get;
  873. PI_CMD_STATUS_CHARS_GET_RSP stat_char_get;
  874. PI_CMD_CNTRS_GET_RSP cntrs_get;
  875. PI_CMD_CNTRS_SET_RSP cntrs_set;
  876. PI_CMD_ERROR_LOG_CLEAR_RSP error_log_clear;
  877. PI_CMD_ERROR_LOG_GET_RSP error_log_get;
  878. PI_CMD_SNMP_SET_RSP snmp_set;
  879. PI_CMD_FDDI_MIB_GET_RSP fddi_mib_get;
  880. PI_CMD_DEC_EXT_MIB_GET_RSP dec_mib_get;
  881. PI_CMD_SMT_MIB_SET_RSP smt_mib_set;
  882. PI_CMD_SMT_MIB_GET_RSP smt_mib_get;
  883. char pad[PI_CMD_RSP_K_SIZE_MAX];
  884. } PI_DMA_CMD_RSP;
  885. typedef union
  886. {
  887. PI_DMA_CMD_REQ request;
  888. PI_DMA_CMD_RSP response;
  889. } PI_DMA_CMD_BUFFER;
  890. /* Define format of Consumer Block (resident in host memory) */
  891. typedef struct
  892. {
  893. volatile PI_UINT32 xmt_rcv_data;
  894. volatile PI_UINT32 reserved_1;
  895. volatile PI_UINT32 smt_host;
  896. volatile PI_UINT32 reserved_2;
  897. volatile PI_UINT32 unsol;
  898. volatile PI_UINT32 reserved_3;
  899. volatile PI_UINT32 cmd_rsp;
  900. volatile PI_UINT32 reserved_4;
  901. volatile PI_UINT32 cmd_req;
  902. volatile PI_UINT32 reserved_5;
  903. } PI_CONSUMER_BLOCK;
  904. #define PI_CONS_M_RCV_INDEX 0x000000FF
  905. #define PI_CONS_M_XMT_INDEX 0x00FF0000
  906. #define PI_CONS_V_RCV_INDEX 0
  907. #define PI_CONS_V_XMT_INDEX 16
  908. /* Offsets into consumer block */
  909. #define PI_CONS_BLK_K_XMT_RCV 0x00
  910. #define PI_CONS_BLK_K_SMT_HOST 0x08
  911. #define PI_CONS_BLK_K_UNSOL 0x10
  912. #define PI_CONS_BLK_K_CMD_RSP 0x18
  913. #define PI_CONS_BLK_K_CMD_REQ 0x20
  914. /* Offsets into descriptor block */
  915. #define PI_DESCR_BLK_K_RCV_DATA 0x0000
  916. #define PI_DESCR_BLK_K_XMT_DATA 0x0800
  917. #define PI_DESCR_BLK_K_SMT_HOST 0x1000
  918. #define PI_DESCR_BLK_K_UNSOL 0x1200
  919. #define PI_DESCR_BLK_K_CMD_RSP 0x1280
  920. #define PI_DESCR_BLK_K_CMD_REQ 0x1300
  921. /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host) */
  922. /* Note a field has been added for later versions of the PDQ to allow for */
  923. /* finer granularity of the rcv buffer alignment. For backwards */
  924. /* compatibility, the two bits (which allow the rcv buffer to be longword */
  925. /* aligned) have been added at the MBZ bits. To support previous drivers, */
  926. /* the MBZ definition is left intact. */
  927. typedef struct
  928. {
  929. PI_UINT32 long_0;
  930. PI_UINT32 long_1;
  931. } PI_RCV_DESCR;
  932. #define PI_RCV_DESCR_M_SOP 0x80000000
  933. #define PI_RCV_DESCR_M_SEG_LEN_LO 0x60000000
  934. #define PI_RCV_DESCR_M_MBZ 0x60000000
  935. #define PI_RCV_DESCR_M_SEG_LEN 0x1F800000
  936. #define PI_RCV_DESCR_M_SEG_LEN_HI 0x1FF00000
  937. #define PI_RCV_DESCR_M_SEG_CNT 0x000F0000
  938. #define PI_RCV_DESCR_M_BUFF_HI 0x0000FFFF
  939. #define PI_RCV_DESCR_V_SOP 31
  940. #define PI_RCV_DESCR_V_SEG_LEN_LO 29
  941. #define PI_RCV_DESCR_V_MBZ 29
  942. #define PI_RCV_DESCR_V_SEG_LEN 23
  943. #define PI_RCV_DESCR_V_SEG_LEN_HI 20
  944. #define PI_RCV_DESCR_V_SEG_CNT 16
  945. #define PI_RCV_DESCR_V_BUFF_HI 0
  946. /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */
  947. typedef struct
  948. {
  949. PI_UINT32 long_0;
  950. PI_UINT32 long_1;
  951. } PI_XMT_DESCR;
  952. #define PI_XMT_DESCR_M_SOP 0x80000000
  953. #define PI_XMT_DESCR_M_EOP 0x40000000
  954. #define PI_XMT_DESCR_M_MBZ 0x20000000
  955. #define PI_XMT_DESCR_M_SEG_LEN 0x1FFF0000
  956. #define PI_XMT_DESCR_M_BUFF_HI 0x0000FFFF
  957. #define PI_XMT_DESCR_V_SOP 31
  958. #define PI_XMT_DESCR_V_EOP 30
  959. #define PI_XMT_DESCR_V_MBZ 29
  960. #define PI_XMT_DESCR_V_SEG_LEN 16
  961. #define PI_XMT_DESCR_V_BUFF_HI 0
  962. /* Define format of the Descriptor Block (resident in host memory) */
  963. #define PI_RCV_DATA_K_NUM_ENTRIES 256
  964. #define PI_XMT_DATA_K_NUM_ENTRIES 256
  965. #define PI_SMT_HOST_K_NUM_ENTRIES 64
  966. #define PI_UNSOL_K_NUM_ENTRIES 16
  967. #define PI_CMD_RSP_K_NUM_ENTRIES 16
  968. #define PI_CMD_REQ_K_NUM_ENTRIES 16
  969. typedef struct
  970. {
  971. PI_RCV_DESCR rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
  972. PI_XMT_DESCR xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
  973. PI_RCV_DESCR smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
  974. PI_RCV_DESCR unsol[PI_UNSOL_K_NUM_ENTRIES];
  975. PI_RCV_DESCR cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
  976. PI_XMT_DESCR cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
  977. } PI_DESCR_BLOCK;
  978. /* Define Port Registers - offsets from PDQ Base address */
  979. #define PI_PDQ_K_REG_PORT_RESET 0x00000000
  980. #define PI_PDQ_K_REG_HOST_DATA 0x00000004
  981. #define PI_PDQ_K_REG_PORT_CTRL 0x00000008
  982. #define PI_PDQ_K_REG_PORT_DATA_A 0x0000000C
  983. #define PI_PDQ_K_REG_PORT_DATA_B 0x00000010
  984. #define PI_PDQ_K_REG_PORT_STATUS 0x00000014
  985. #define PI_PDQ_K_REG_TYPE_0_STATUS 0x00000018
  986. #define PI_PDQ_K_REG_HOST_INT_ENB 0x0000001C
  987. #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 0x00000020
  988. #define PI_PDQ_K_REG_TYPE_2_PROD 0x00000024
  989. #define PI_PDQ_K_REG_CMD_RSP_PROD 0x00000028
  990. #define PI_PDQ_K_REG_CMD_REQ_PROD 0x0000002C
  991. #define PI_PDQ_K_REG_SMT_HOST_PROD 0x00000030
  992. #define PI_PDQ_K_REG_UNSOL_PROD 0x00000034
  993. /* Port Control Register - Command codes for primary commands */
  994. #define PI_PCTRL_M_CMD_ERROR 0x8000
  995. #define PI_PCTRL_M_BLAST_FLASH 0x4000
  996. #define PI_PCTRL_M_HALT 0x2000
  997. #define PI_PCTRL_M_COPY_DATA 0x1000
  998. #define PI_PCTRL_M_ERROR_LOG_START 0x0800
  999. #define PI_PCTRL_M_ERROR_LOG_READ 0x0400
  1000. #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE 0x0200
  1001. #define PI_PCTRL_M_INIT 0x0100
  1002. #define PI_PCTRL_M_INIT_START 0x0080
  1003. #define PI_PCTRL_M_CONS_BLOCK 0x0040
  1004. #define PI_PCTRL_M_UNINIT 0x0020
  1005. #define PI_PCTRL_M_RING_MEMBER 0x0010
  1006. #define PI_PCTRL_M_MLA 0x0008
  1007. #define PI_PCTRL_M_FW_REV_READ 0x0004
  1008. #define PI_PCTRL_M_DEV_SPECIFIC 0x0002
  1009. #define PI_PCTRL_M_SUB_CMD 0x0001
  1010. /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */
  1011. #define PI_SUB_CMD_K_LINK_UNINIT 0x0001
  1012. #define PI_SUB_CMD_K_BURST_SIZE_SET 0x0002
  1013. #define PI_SUB_CMD_K_PDQ_REV_GET 0x0004
  1014. #define PI_SUB_CMD_K_HW_REV_GET 0x0008
  1015. /* Define some Port Data B values */
  1016. #define PI_PDATA_B_DMA_BURST_SIZE_4 0 /* valid values for command */
  1017. #define PI_PDATA_B_DMA_BURST_SIZE_8 1
  1018. #define PI_PDATA_B_DMA_BURST_SIZE_16 2
  1019. #define PI_PDATA_B_DMA_BURST_SIZE_32 3 /* not supported on PCI */
  1020. #define PI_PDATA_B_DMA_BURST_SIZE_DEF PI_PDATA_B_DMA_BURST_SIZE_16
  1021. /* Port Data A Reset state */
  1022. #define PI_PDATA_A_RESET_M_UPGRADE 0x00000001
  1023. #define PI_PDATA_A_RESET_M_SOFT_RESET 0x00000002
  1024. #define PI_PDATA_A_RESET_M_SKIP_ST 0x00000004
  1025. /* Read adapter MLA address port control command constants */
  1026. #define PI_PDATA_A_MLA_K_LO 0
  1027. #define PI_PDATA_A_MLA_K_HI 1
  1028. /* Byte Swap values for init command */
  1029. #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR 0x0FFFFE000
  1030. #define PI_PDATA_A_INIT_M_RESERVED 0x000001FFC
  1031. #define PI_PDATA_A_INIT_M_BSWAP_DATA 0x000000002
  1032. #define PI_PDATA_A_INIT_M_BSWAP_LITERAL 0x000000001
  1033. #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR 13
  1034. #define PI_PDATA_A_INIT_V_RESERVED 3
  1035. #define PI_PDATA_A_INIT_V_BSWAP_DATA 1
  1036. #define PI_PDATA_A_INIT_V_BSWAP_LITERAL 0
  1037. /* Port Reset Register */
  1038. #define PI_RESET_M_ASSERT_RESET 1
  1039. /* Port Status register */
  1040. #define PI_PSTATUS_V_RCV_DATA_PENDING 31
  1041. #define PI_PSTATUS_V_XMT_DATA_PENDING 30
  1042. #define PI_PSTATUS_V_SMT_HOST_PENDING 29
  1043. #define PI_PSTATUS_V_UNSOL_PENDING 28
  1044. #define PI_PSTATUS_V_CMD_RSP_PENDING 27
  1045. #define PI_PSTATUS_V_CMD_REQ_PENDING 26
  1046. #define PI_PSTATUS_V_TYPE_0_PENDING 25
  1047. #define PI_PSTATUS_V_RESERVED_1 16
  1048. #define PI_PSTATUS_V_RESERVED_2 11
  1049. #define PI_PSTATUS_V_STATE 8
  1050. #define PI_PSTATUS_V_HALT_ID 0
  1051. #define PI_PSTATUS_M_RCV_DATA_PENDING 0x80000000
  1052. #define PI_PSTATUS_M_XMT_DATA_PENDING 0x40000000
  1053. #define PI_PSTATUS_M_SMT_HOST_PENDING 0x20000000
  1054. #define PI_PSTATUS_M_UNSOL_PENDING 0x10000000
  1055. #define PI_PSTATUS_M_CMD_RSP_PENDING 0x08000000
  1056. #define PI_PSTATUS_M_CMD_REQ_PENDING 0x04000000
  1057. #define PI_PSTATUS_M_TYPE_0_PENDING 0x02000000
  1058. #define PI_PSTATUS_M_RESERVED_1 0x01FF0000
  1059. #define PI_PSTATUS_M_RESERVED_2 0x0000F800
  1060. #define PI_PSTATUS_M_STATE 0x00000700
  1061. #define PI_PSTATUS_M_HALT_ID 0x000000FF
  1062. /* Define Halt Id's */
  1063. /* Do not insert into this list, only append. */
  1064. #define PI_HALT_ID_K_SELFTEST_TIMEOUT 0
  1065. #define PI_HALT_ID_K_PARITY_ERROR 1
  1066. #define PI_HALT_ID_K_HOST_DIR_HALT 2
  1067. #define PI_HALT_ID_K_SW_FAULT 3
  1068. #define PI_HALT_ID_K_HW_FAULT 4
  1069. #define PI_HALT_ID_K_PC_TRACE 5
  1070. #define PI_HALT_ID_K_DMA_ERROR 6 /* Host Data has error reg */
  1071. #define PI_HALT_ID_K_IMAGE_CRC_ERROR 7 /* Image is bad, update it */
  1072. #define PI_HALT_ID_K_BUS_EXCEPTION 8 /* 68K bus exception */
  1073. /* Host Interrupt Enable Register as seen by host */
  1074. #define PI_HOST_INT_M_XMT_DATA_ENB 0x80000000 /* Type 2 Enables */
  1075. #define PI_HOST_INT_M_RCV_DATA_ENB 0x40000000
  1076. #define PI_HOST_INT_M_SMT_HOST_ENB 0x10000000 /* Type 1 Enables */
  1077. #define PI_HOST_INT_M_UNSOL_ENB 0x20000000
  1078. #define PI_HOST_INT_M_CMD_RSP_ENB 0x08000000
  1079. #define PI_HOST_INT_M_CMD_REQ_ENB 0x04000000
  1080. #define PI_HOST_INT_M_TYPE_1_RESERVED 0x00FF0000
  1081. #define PI_HOST_INT_M_TYPE_0_RESERVED 0x0000FF00 /* Type 0 Enables */
  1082. #define PI_HOST_INT_M_1MS 0x00000080
  1083. #define PI_HOST_INT_M_20MS 0x00000040
  1084. #define PI_HOST_INT_M_CSR_CMD_DONE 0x00000020
  1085. #define PI_HOST_INT_M_STATE_CHANGE 0x00000010
  1086. #define PI_HOST_INT_M_XMT_FLUSH 0x00000008
  1087. #define PI_HOST_INT_M_NXM 0x00000004
  1088. #define PI_HOST_INT_M_PM_PAR_ERR 0x00000002
  1089. #define PI_HOST_INT_M_BUS_PAR_ERR 0x00000001
  1090. #define PI_HOST_INT_V_XMT_DATA_ENB 31 /* Type 2 Enables */
  1091. #define PI_HOST_INT_V_RCV_DATA_ENB 30
  1092. #define PI_HOST_INT_V_SMT_HOST_ENB 29 /* Type 1 Enables */
  1093. #define PI_HOST_INT_V_UNSOL_ENB 28
  1094. #define PI_HOST_INT_V_CMD_RSP_ENB 27
  1095. #define PI_HOST_INT_V_CMD_REQ_ENB 26
  1096. #define PI_HOST_INT_V_TYPE_1_RESERVED 16
  1097. #define PI_HOST_INT_V_TYPE_0_RESERVED 8 /* Type 0 Enables */
  1098. #define PI_HOST_INT_V_1MS_ENB 7
  1099. #define PI_HOST_INT_V_20MS_ENB 6
  1100. #define PI_HOST_INT_V_CSR_CMD_DONE_ENB 5
  1101. #define PI_HOST_INT_V_STATE_CHANGE_ENB 4
  1102. #define PI_HOST_INT_V_XMT_FLUSH_ENB 3
  1103. #define PI_HOST_INT_V_NXM_ENB 2
  1104. #define PI_HOST_INT_V_PM_PAR_ERR_ENB 1
  1105. #define PI_HOST_INT_V_BUS_PAR_ERR_ENB 0
  1106. #define PI_HOST_INT_K_ACK_ALL_TYPE_0 0x000000FF
  1107. #define PI_HOST_INT_K_DISABLE_ALL_INTS 0x00000000
  1108. #define PI_HOST_INT_K_ENABLE_ALL_INTS 0xFFFFFFFF
  1109. #define PI_HOST_INT_K_ENABLE_DEF_INTS 0xC000001F
  1110. /* Type 0 Interrupt Status Register */
  1111. #define PI_TYPE_0_STAT_M_1MS 0x00000080
  1112. #define PI_TYPE_0_STAT_M_20MS 0x00000040
  1113. #define PI_TYPE_0_STAT_M_CSR_CMD_DONE 0x00000020
  1114. #define PI_TYPE_0_STAT_M_STATE_CHANGE 0x00000010
  1115. #define PI_TYPE_0_STAT_M_XMT_FLUSH 0x00000008
  1116. #define PI_TYPE_0_STAT_M_NXM 0x00000004
  1117. #define PI_TYPE_0_STAT_M_PM_PAR_ERR 0x00000002
  1118. #define PI_TYPE_0_STAT_M_BUS_PAR_ERR 0x00000001
  1119. #define PI_TYPE_0_STAT_V_1MS 7
  1120. #define PI_TYPE_0_STAT_V_20MS 6
  1121. #define PI_TYPE_0_STAT_V_CSR_CMD_DONE 5
  1122. #define PI_TYPE_0_STAT_V_STATE_CHANGE 4
  1123. #define PI_TYPE_0_STAT_V_XMT_FLUSH 3
  1124. #define PI_TYPE_0_STAT_V_NXM 2
  1125. #define PI_TYPE_0_STAT_V_PM_PAR_ERR 1
  1126. #define PI_TYPE_0_STAT_V_BUS_PAR_ERR 0
  1127. /* Register definition structures are defined for both big and little endian systems */
  1128. #ifndef __BIG_ENDIAN
  1129. /* Little endian format of Type 1 Producer register */
  1130. typedef union
  1131. {
  1132. PI_UINT32 lword;
  1133. struct
  1134. {
  1135. PI_UINT8 prod;
  1136. PI_UINT8 comp;
  1137. PI_UINT8 mbz_1;
  1138. PI_UINT8 mbz_2;
  1139. } index;
  1140. } PI_TYPE_1_PROD_REG;
  1141. /* Little endian format of Type 2 Producer register */
  1142. typedef union
  1143. {
  1144. PI_UINT32 lword;
  1145. struct
  1146. {
  1147. PI_UINT8 rcv_prod;
  1148. PI_UINT8 xmt_prod;
  1149. PI_UINT8 rcv_comp;
  1150. PI_UINT8 xmt_comp;
  1151. } index;
  1152. } PI_TYPE_2_PROD_REG;
  1153. /* Little endian format of Type 1 Consumer Block longword */
  1154. typedef union
  1155. {
  1156. PI_UINT32 lword;
  1157. struct
  1158. {
  1159. PI_UINT8 cons;
  1160. PI_UINT8 res0;
  1161. PI_UINT8 res1;
  1162. PI_UINT8 res2;
  1163. } index;
  1164. } PI_TYPE_1_CONSUMER;
  1165. /* Little endian format of Type 2 Consumer Block longword */
  1166. typedef union
  1167. {
  1168. PI_UINT32 lword;
  1169. struct
  1170. {
  1171. PI_UINT8 rcv_cons;
  1172. PI_UINT8 res0;
  1173. PI_UINT8 xmt_cons;
  1174. PI_UINT8 res1;
  1175. } index;
  1176. } PI_TYPE_2_CONSUMER;
  1177. /* Define swapping required by DMA transfers. */
  1178. #define PI_PDATA_A_INIT_M_BSWAP_INIT \
  1179. (PI_PDATA_A_INIT_M_BSWAP_DATA)
  1180. #else /* __BIG_ENDIAN */
  1181. /* Big endian format of Type 1 Producer register */
  1182. typedef union
  1183. {
  1184. PI_UINT32 lword;
  1185. struct
  1186. {
  1187. PI_UINT8 mbz_2;
  1188. PI_UINT8 mbz_1;
  1189. PI_UINT8 comp;
  1190. PI_UINT8 prod;
  1191. } index;
  1192. } PI_TYPE_1_PROD_REG;
  1193. /* Big endian format of Type 2 Producer register */
  1194. typedef union
  1195. {
  1196. PI_UINT32 lword;
  1197. struct
  1198. {
  1199. PI_UINT8 xmt_comp;
  1200. PI_UINT8 rcv_comp;
  1201. PI_UINT8 xmt_prod;
  1202. PI_UINT8 rcv_prod;
  1203. } index;
  1204. } PI_TYPE_2_PROD_REG;
  1205. /* Big endian format of Type 1 Consumer Block longword */
  1206. typedef union
  1207. {
  1208. PI_UINT32 lword;
  1209. struct
  1210. {
  1211. PI_UINT8 res2;
  1212. PI_UINT8 res1;
  1213. PI_UINT8 res0;
  1214. PI_UINT8 cons;
  1215. } index;
  1216. } PI_TYPE_1_CONSUMER;
  1217. /* Big endian format of Type 2 Consumer Block longword */
  1218. typedef union
  1219. {
  1220. PI_UINT32 lword;
  1221. struct
  1222. {
  1223. PI_UINT8 res1;
  1224. PI_UINT8 xmt_cons;
  1225. PI_UINT8 res0;
  1226. PI_UINT8 rcv_cons;
  1227. } index;
  1228. } PI_TYPE_2_CONSUMER;
  1229. /* Define swapping required by DMA transfers. */
  1230. #define PI_PDATA_A_INIT_M_BSWAP_INIT \
  1231. (PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
  1232. #endif /* __BIG_ENDIAN */
  1233. /* Define TC PDQ CSR offset and length */
  1234. #define PI_TC_K_CSR_OFFSET 0x100000
  1235. #define PI_TC_K_CSR_LEN 0x40 /* 64 bytes */
  1236. /* Define EISA controller register offsets */
  1237. #define PI_ESIC_K_CSR_IO_LEN 0x40 /* 64 bytes */
  1238. #define PI_ESIC_K_BURST_HOLDOFF_LEN 0x04 /* 4 bytes */
  1239. #define PI_ESIC_K_ESIC_CSR_LEN 0x40 /* 64 bytes */
  1240. #define PI_DEFEA_K_CSR_IO 0x000
  1241. #define PI_DEFEA_K_BURST_HOLDOFF 0x040
  1242. #define PI_ESIC_K_ESIC_CSR 0xC80
  1243. #define PI_ESIC_K_SLOT_ID 0xC80
  1244. #define PI_ESIC_K_SLOT_CNTRL 0xC84
  1245. #define PI_ESIC_K_MEM_ADD_CMP_0 0xC85
  1246. #define PI_ESIC_K_MEM_ADD_CMP_1 0xC86
  1247. #define PI_ESIC_K_MEM_ADD_CMP_2 0xC87
  1248. #define PI_ESIC_K_MEM_ADD_HI_CMP_0 0xC88
  1249. #define PI_ESIC_K_MEM_ADD_HI_CMP_1 0xC89
  1250. #define PI_ESIC_K_MEM_ADD_HI_CMP_2 0xC8A
  1251. #define PI_ESIC_K_MEM_ADD_MASK_0 0xC8B
  1252. #define PI_ESIC_K_MEM_ADD_MASK_1 0xC8C
  1253. #define PI_ESIC_K_MEM_ADD_MASK_2 0xC8D
  1254. #define PI_ESIC_K_MEM_ADD_LO_CMP_0 0xC8E
  1255. #define PI_ESIC_K_MEM_ADD_LO_CMP_1 0xC8F
  1256. #define PI_ESIC_K_MEM_ADD_LO_CMP_2 0xC90
  1257. #define PI_ESIC_K_IO_ADD_CMP_0_0 0xC91
  1258. #define PI_ESIC_K_IO_ADD_CMP_0_1 0xC92
  1259. #define PI_ESIC_K_IO_ADD_CMP_1_0 0xC93
  1260. #define PI_ESIC_K_IO_ADD_CMP_1_1 0xC94
  1261. #define PI_ESIC_K_IO_ADD_CMP_2_0 0xC95
  1262. #define PI_ESIC_K_IO_ADD_CMP_2_1 0xC96
  1263. #define PI_ESIC_K_IO_ADD_CMP_3_0 0xC97
  1264. #define PI_ESIC_K_IO_ADD_CMP_3_1 0xC98
  1265. #define PI_ESIC_K_IO_ADD_MASK_0_0 0xC99
  1266. #define PI_ESIC_K_IO_ADD_MASK_0_1 0xC9A
  1267. #define PI_ESIC_K_IO_ADD_MASK_1_0 0xC9B
  1268. #define PI_ESIC_K_IO_ADD_MASK_1_1 0xC9C
  1269. #define PI_ESIC_K_IO_ADD_MASK_2_0 0xC9D
  1270. #define PI_ESIC_K_IO_ADD_MASK_2_1 0xC9E
  1271. #define PI_ESIC_K_IO_ADD_MASK_3_0 0xC9F
  1272. #define PI_ESIC_K_IO_ADD_MASK_3_1 0xCA0
  1273. #define PI_ESIC_K_MOD_CONFIG_1 0xCA1
  1274. #define PI_ESIC_K_MOD_CONFIG_2 0xCA2
  1275. #define PI_ESIC_K_MOD_CONFIG_3 0xCA3
  1276. #define PI_ESIC_K_MOD_CONFIG_4 0xCA4
  1277. #define PI_ESIC_K_MOD_CONFIG_5 0xCA5
  1278. #define PI_ESIC_K_MOD_CONFIG_6 0xCA6
  1279. #define PI_ESIC_K_MOD_CONFIG_7 0xCA7
  1280. #define PI_ESIC_K_DIP_SWITCH 0xCA8
  1281. #define PI_ESIC_K_IO_CONFIG_STAT_0 0xCA9
  1282. #define PI_ESIC_K_IO_CONFIG_STAT_1 0xCAA
  1283. #define PI_ESIC_K_DMA_CONFIG 0xCAB
  1284. #define PI_ESIC_K_INPUT_PORT 0xCAC
  1285. #define PI_ESIC_K_OUTPUT_PORT 0xCAD
  1286. #define PI_ESIC_K_FUNCTION_CNTRL 0xCAE
  1287. /* Define the bits in the function control register. */
  1288. #define PI_FUNCTION_CNTRL_M_IOCS0 0x01
  1289. #define PI_FUNCTION_CNTRL_M_IOCS1 0x02
  1290. #define PI_FUNCTION_CNTRL_M_IOCS2 0x04
  1291. #define PI_FUNCTION_CNTRL_M_IOCS3 0x08
  1292. #define PI_FUNCTION_CNTRL_M_MEMCS0 0x10
  1293. #define PI_FUNCTION_CNTRL_M_MEMCS1 0x20
  1294. #define PI_FUNCTION_CNTRL_M_DMA 0x80
  1295. /* Define the bits in the slot control register. */
  1296. #define PI_SLOT_CNTRL_M_RESET 0x04 /* Don't use. */
  1297. #define PI_SLOT_CNTRL_M_ERROR 0x02 /* Not implemented. */
  1298. #define PI_SLOT_CNTRL_M_ENB 0x01 /* Must be set. */
  1299. /* Define the bits in the burst holdoff register. */
  1300. #define PI_BURST_HOLDOFF_M_HOLDOFF 0xFC
  1301. #define PI_BURST_HOLDOFF_M_RESERVED 0x02
  1302. #define PI_BURST_HOLDOFF_M_MEM_MAP 0x01
  1303. #define PI_BURST_HOLDOFF_V_HOLDOFF 2
  1304. #define PI_BURST_HOLDOFF_V_RESERVED 1
  1305. #define PI_BURST_HOLDOFF_V_MEM_MAP 0
  1306. /* Define the implicit mask of the Memory Address Compare registers. */
  1307. #define PI_MEM_ADD_MASK_M 0x3ff
  1308. /* Define the fields in the I/O Address Compare and Mask registers. */
  1309. #define PI_IO_CMP_M_SLOT 0xf0
  1310. #define PI_IO_CMP_V_SLOT 4
  1311. /* Define the fields in the Interrupt Channel Configuration and Status reg */
  1312. #define PI_CONFIG_STAT_0_M_PEND 0x80
  1313. #define PI_CONFIG_STAT_0_M_RES_1 0x40
  1314. #define PI_CONFIG_STAT_0_M_IREQ_OUT 0x20
  1315. #define PI_CONFIG_STAT_0_M_IREQ_IN 0x10
  1316. #define PI_CONFIG_STAT_0_M_INT_ENB 0x08
  1317. #define PI_CONFIG_STAT_0_M_RES_0 0x04
  1318. #define PI_CONFIG_STAT_0_M_IRQ 0x03
  1319. #define PI_CONFIG_STAT_0_V_PEND 7
  1320. #define PI_CONFIG_STAT_0_V_RES_1 6
  1321. #define PI_CONFIG_STAT_0_V_IREQ_OUT 5
  1322. #define PI_CONFIG_STAT_0_V_IREQ_IN 4
  1323. #define PI_CONFIG_STAT_0_V_INT_ENB 3
  1324. #define PI_CONFIG_STAT_0_V_RES_0 2
  1325. #define PI_CONFIG_STAT_0_V_IRQ 0
  1326. #define PI_CONFIG_STAT_0_IRQ_K_9 0
  1327. #define PI_CONFIG_STAT_0_IRQ_K_10 1
  1328. #define PI_CONFIG_STAT_0_IRQ_K_11 2
  1329. #define PI_CONFIG_STAT_0_IRQ_K_15 3
  1330. /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */
  1331. #define DEFEA_PRODUCT_ID 0x0030A310 /* DEC product 300 (no rev) */
  1332. #define DEFEA_PROD_ID_1 0x0130A310 /* DEC product 300, rev 1 */
  1333. #define DEFEA_PROD_ID_2 0x0230A310 /* DEC product 300, rev 2 */
  1334. #define DEFEA_PROD_ID_3 0x0330A310 /* DEC product 300, rev 3 */
  1335. #define DEFEA_PROD_ID_4 0x0430A310 /* DEC product 300, rev 4 */
  1336. /**********************************************/
  1337. /* Digital PFI Specification v1.0 Definitions */
  1338. /**********************************************/
  1339. /* PCI Configuration Space Constants */
  1340. #define PFI_K_LAT_TIMER_DEF 0x88 /* def max master latency timer */
  1341. #define PFI_K_LAT_TIMER_MIN 0x20 /* min max master latency timer */
  1342. #define PFI_K_CSR_MEM_LEN 0x80 /* 128 bytes */
  1343. #define PFI_K_CSR_IO_LEN 0x80 /* 128 bytes */
  1344. #define PFI_K_PKT_MEM_LEN 0x10000 /* 64K bytes */
  1345. /* PFI Register Offsets (starting at PDQ Register Base Address) */
  1346. #define PFI_K_REG_RESERVED_0 0X00000038
  1347. #define PFI_K_REG_RESERVED_1 0X0000003C
  1348. #define PFI_K_REG_MODE_CTRL 0X00000040
  1349. #define PFI_K_REG_STATUS 0X00000044
  1350. #define PFI_K_REG_FIFO_WRITE 0X00000048
  1351. #define PFI_K_REG_FIFO_READ 0X0000004C
  1352. /* PFI Mode Control Register Constants */
  1353. #define PFI_MODE_M_RESERVED 0XFFFFFFF0
  1354. #define PFI_MODE_M_TGT_ABORT_ENB 0X00000008
  1355. #define PFI_MODE_M_PDQ_INT_ENB 0X00000004
  1356. #define PFI_MODE_M_PFI_INT_ENB 0X00000002
  1357. #define PFI_MODE_M_DMA_ENB 0X00000001
  1358. #define PFI_MODE_V_RESERVED 4
  1359. #define PFI_MODE_V_TGT_ABORT_ENB 3
  1360. #define PFI_MODE_V_PDQ_INT_ENB 2
  1361. #define PFI_MODE_V_PFI_INT_ENB 1
  1362. #define PFI_MODE_V_DMA_ENB 0
  1363. #define PFI_MODE_K_ALL_DISABLE 0X00000000
  1364. /* PFI Status Register Constants */
  1365. #define PFI_STATUS_M_RESERVED 0XFFFFFFC0
  1366. #define PFI_STATUS_M_PFI_ERROR 0X00000020 /* only valid in rev 1 or later PFI */
  1367. #define PFI_STATUS_M_PDQ_INT 0X00000010
  1368. #define PFI_STATUS_M_PDQ_DMA_ABORT 0X00000008
  1369. #define PFI_STATUS_M_FIFO_FULL 0X00000004
  1370. #define PFI_STATUS_M_FIFO_EMPTY 0X00000002
  1371. #define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001
  1372. #define PFI_STATUS_V_RESERVED 6
  1373. #define PFI_STATUS_V_PFI_ERROR 5 /* only valid in rev 1 or later PFI */
  1374. #define PFI_STATUS_V_PDQ_INT 4
  1375. #define PFI_STATUS_V_PDQ_DMA_ABORT 3
  1376. #define PFI_STATUS_V_FIFO_FULL 2
  1377. #define PFI_STATUS_V_FIFO_EMPTY 1
  1378. #define PFI_STATUS_V_DMA_IN_PROGRESS 0
  1379. #define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */
  1380. #define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */
  1381. #define DFX_PRH1_BYTE 0x38 /* Packet Request Header byte 1 */
  1382. #define DFX_PRH2_BYTE 0x00 /* Packet Request Header byte 2 */
  1383. /* Driver routine status (return) codes */
  1384. #define DFX_K_SUCCESS 0 /* routine succeeded */
  1385. #define DFX_K_FAILURE 1 /* routine failed */
  1386. #define DFX_K_OUTSTATE 2 /* bad state for command */
  1387. #define DFX_K_HW_TIMEOUT 3 /* command timed out */
  1388. /* Define LLC host receive buffer min/max/default values */
  1389. #define RCV_BUFS_MIN 2 /* minimum pre-allocated receive buffers */
  1390. #define RCV_BUFS_MAX 32 /* maximum pre-allocated receive buffers */
  1391. #define RCV_BUFS_DEF 8 /* default pre-allocated receive buffers */
  1392. /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */
  1393. #define RCV_BUFF_K_DESCR 0 /* four byte FMC descriptor */
  1394. #define RCV_BUFF_K_PADDING 4 /* three null bytes */
  1395. #define RCV_BUFF_K_FC 7 /* one byte frame control */
  1396. #define RCV_BUFF_K_DA 8 /* six byte destination address */
  1397. #define RCV_BUFF_K_SA 14 /* six byte source address */
  1398. #define RCV_BUFF_K_DATA 20 /* offset to start of packet data */
  1399. /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */
  1400. #define XMT_BUFF_K_FC 0 /* one byte frame control */
  1401. #define XMT_BUFF_K_DA 1 /* six byte destination address */
  1402. #define XMT_BUFF_K_SA 7 /* six byte source address */
  1403. #define XMT_BUFF_K_DATA 13 /* offset to start of packet data */
  1404. /* Macro for checking a "value" is within a specific range */
  1405. #define IN_RANGE(value,low,high) ((value >= low) && (value <= high))
  1406. /* Only execute special print call when debug driver was built */
  1407. #ifdef DEFXX_DEBUG
  1408. #define DBG_printk(args...) printk(args)
  1409. #else
  1410. #define DBG_printk(args...)
  1411. #endif
  1412. /* Define constants for masking/unmasking interrupts */
  1413. #define DFX_MASK_INTERRUPTS 1
  1414. #define DFX_UNMASK_INTERRUPTS 0
  1415. /* Define structure for driver transmit descriptor block */
  1416. typedef struct
  1417. {
  1418. struct sk_buff *p_skb; /* ptr to skb */
  1419. } XMT_DRIVER_DESCR;
  1420. typedef struct DFX_board_tag
  1421. {
  1422. /* Keep virtual and physical pointers to locked, physically contiguous memory */
  1423. char *kmalloced; /* pci_free_consistent this on unload */
  1424. dma_addr_t kmalloced_dma;
  1425. /* DMA handle for the above */
  1426. PI_DESCR_BLOCK *descr_block_virt; /* PDQ descriptor block virt address */
  1427. dma_addr_t descr_block_phys; /* PDQ descriptor block phys address */
  1428. PI_DMA_CMD_REQ *cmd_req_virt; /* Command request buffer virt address */
  1429. dma_addr_t cmd_req_phys; /* Command request buffer phys address */
  1430. PI_DMA_CMD_RSP *cmd_rsp_virt; /* Command response buffer virt address */
  1431. dma_addr_t cmd_rsp_phys; /* Command response buffer phys address */
  1432. char *rcv_block_virt; /* LLC host receive queue buf blk virt */
  1433. dma_addr_t rcv_block_phys; /* LLC host receive queue buf blk phys */
  1434. PI_CONSUMER_BLOCK *cons_block_virt; /* PDQ consumer block virt address */
  1435. dma_addr_t cons_block_phys; /* PDQ consumer block phys address */
  1436. /* Keep local copies of Type 1 and Type 2 register data */
  1437. PI_TYPE_1_PROD_REG cmd_req_reg; /* Command Request register */
  1438. PI_TYPE_1_PROD_REG cmd_rsp_reg; /* Command Response register */
  1439. PI_TYPE_2_PROD_REG rcv_xmt_reg; /* Type 2 (RCV/XMT) register */
  1440. /* Storage for unicast and multicast address entries in adapter CAM */
  1441. u8 uc_table[1*FDDI_K_ALEN];
  1442. u32 uc_count; /* number of unicast addresses */
  1443. u8 mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN];
  1444. u32 mc_count; /* number of multicast addresses */
  1445. /* Current packet filter settings */
  1446. u32 ind_group_prom; /* LLC individual & group frame prom mode */
  1447. u32 group_prom; /* LLC group (multicast) frame prom mode */
  1448. /* Link available flag needed to determine whether to drop outgoing packet requests */
  1449. u32 link_available; /* is link available? */
  1450. /* Resources to indicate reset type when resetting adapter */
  1451. u32 reset_type; /* skip or rerun diagnostics */
  1452. /* Store pointers to receive buffers for queue processing code */
  1453. char *p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES];
  1454. /* Store pointers to transmit buffers for transmit completion code */
  1455. XMT_DRIVER_DESCR xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES];
  1456. /* Transmit spinlocks */
  1457. spinlock_t lock;
  1458. /* Store device, bus-specific, and parameter information for this adapter */
  1459. struct net_device *dev; /* pointer to device structure */
  1460. union {
  1461. void __iomem *mem;
  1462. int port;
  1463. } base; /* base address */
  1464. struct device *bus_dev;
  1465. u32 full_duplex_enb; /* FDDI Full Duplex enable (1 == on, 2 == off) */
  1466. u32 req_ttrt; /* requested TTRT value (in 80ns units) */
  1467. u32 burst_size; /* adapter burst size (enumerated) */
  1468. u32 rcv_bufs_to_post; /* receive buffers to post for LLC host queue */
  1469. u8 factory_mac_addr[FDDI_K_ALEN]; /* factory (on-board) MAC address */
  1470. /* Common FDDI statistics structure and private counters */
  1471. struct fddi_statistics stats;
  1472. u32 rcv_discards;
  1473. u32 rcv_crc_errors;
  1474. u32 rcv_frame_status_errors;
  1475. u32 rcv_length_errors;
  1476. u32 rcv_total_frames;
  1477. u32 rcv_multicast_frames;
  1478. u32 rcv_total_bytes;
  1479. u32 xmt_discards;
  1480. u32 xmt_length_errors;
  1481. u32 xmt_total_frames;
  1482. u32 xmt_total_bytes;
  1483. } DFX_board_t;
  1484. #endif /* #ifndef _DEFXX_H_ */