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/drivers/net/wan/lmc/lmc_main.c

http://github.com/mirrors/linux
C | 2101 lines | 1308 code | 390 blank | 403 comment | 173 complexity | 9917615412cf4fb912597573bee55d4d MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  4. * All rights reserved. www.lanmedia.com
  5. * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
  6. *
  7. * This code is written by:
  8. * Andrew Stanley-Jones (asj@cban.com)
  9. * Rob Braun (bbraun@vix.com),
  10. * Michael Graff (explorer@vix.com) and
  11. * Matt Thomas (matt@3am-software.com).
  12. *
  13. * With Help By:
  14. * David Boggs
  15. * Ron Crane
  16. * Alan Cox
  17. *
  18. * Driver for the LanMedia LMC5200, LMC5245, LMC1000, LMC1200 cards.
  19. *
  20. * To control link specific options lmcctl is required.
  21. * It can be obtained from ftp.lanmedia.com.
  22. *
  23. * Linux driver notes:
  24. * Linux uses the device struct lmc_private to pass private information
  25. * around.
  26. *
  27. * The initialization portion of this driver (the lmc_reset() and the
  28. * lmc_dec_reset() functions, as well as the led controls and the
  29. * lmc_initcsrs() functions.
  30. *
  31. * The watchdog function runs every second and checks to see if
  32. * we still have link, and that the timing source is what we expected
  33. * it to be. If link is lost, the interface is marked down, and
  34. * we no longer can transmit.
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/string.h>
  39. #include <linux/timer.h>
  40. #include <linux/ptrace.h>
  41. #include <linux/errno.h>
  42. #include <linux/ioport.h>
  43. #include <linux/slab.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/pci.h>
  46. #include <linux/delay.h>
  47. #include <linux/hdlc.h>
  48. #include <linux/in.h>
  49. #include <linux/if_arp.h>
  50. #include <linux/netdevice.h>
  51. #include <linux/etherdevice.h>
  52. #include <linux/skbuff.h>
  53. #include <linux/inet.h>
  54. #include <linux/bitops.h>
  55. #include <asm/processor.h> /* Processor type for cache alignment. */
  56. #include <asm/io.h>
  57. #include <asm/dma.h>
  58. #include <linux/uaccess.h>
  59. //#include <asm/spinlock.h>
  60. #define DRIVER_MAJOR_VERSION 1
  61. #define DRIVER_MINOR_VERSION 34
  62. #define DRIVER_SUB_VERSION 0
  63. #define DRIVER_VERSION ((DRIVER_MAJOR_VERSION << 8) + DRIVER_MINOR_VERSION)
  64. #include "lmc.h"
  65. #include "lmc_var.h"
  66. #include "lmc_ioctl.h"
  67. #include "lmc_debug.h"
  68. #include "lmc_proto.h"
  69. static int LMC_PKT_BUF_SZ = 1542;
  70. static const struct pci_device_id lmc_pci_tbl[] = {
  71. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  72. PCI_VENDOR_ID_LMC, PCI_ANY_ID },
  73. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  74. PCI_ANY_ID, PCI_VENDOR_ID_LMC },
  75. { 0 }
  76. };
  77. MODULE_DEVICE_TABLE(pci, lmc_pci_tbl);
  78. MODULE_LICENSE("GPL v2");
  79. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  80. struct net_device *dev);
  81. static int lmc_rx (struct net_device *dev);
  82. static int lmc_open(struct net_device *dev);
  83. static int lmc_close(struct net_device *dev);
  84. static struct net_device_stats *lmc_get_stats(struct net_device *dev);
  85. static irqreturn_t lmc_interrupt(int irq, void *dev_instance);
  86. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
  87. static void lmc_softreset(lmc_softc_t * const);
  88. static void lmc_running_reset(struct net_device *dev);
  89. static int lmc_ifdown(struct net_device * const);
  90. static void lmc_watchdog(struct timer_list *t);
  91. static void lmc_reset(lmc_softc_t * const sc);
  92. static void lmc_dec_reset(lmc_softc_t * const sc);
  93. static void lmc_driver_timeout(struct net_device *dev, unsigned int txqueue);
  94. /*
  95. * linux reserves 16 device specific IOCTLs. We call them
  96. * LMCIOC* to control various bits of our world.
  97. */
  98. int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/
  99. {
  100. lmc_softc_t *sc = dev_to_sc(dev);
  101. lmc_ctl_t ctl;
  102. int ret = -EOPNOTSUPP;
  103. u16 regVal;
  104. unsigned long flags;
  105. lmc_trace(dev, "lmc_ioctl in");
  106. /*
  107. * Most functions mess with the structure
  108. * Disable interrupts while we do the polling
  109. */
  110. switch (cmd) {
  111. /*
  112. * Return current driver state. Since we keep this up
  113. * To date internally, just copy this out to the user.
  114. */
  115. case LMCIOCGINFO: /*fold01*/
  116. if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
  117. ret = -EFAULT;
  118. else
  119. ret = 0;
  120. break;
  121. case LMCIOCSINFO: /*fold01*/
  122. if (!capable(CAP_NET_ADMIN)) {
  123. ret = -EPERM;
  124. break;
  125. }
  126. if(dev->flags & IFF_UP){
  127. ret = -EBUSY;
  128. break;
  129. }
  130. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  131. ret = -EFAULT;
  132. break;
  133. }
  134. spin_lock_irqsave(&sc->lmc_lock, flags);
  135. sc->lmc_media->set_status (sc, &ctl);
  136. if(ctl.crc_length != sc->ictl.crc_length) {
  137. sc->lmc_media->set_crc_length(sc, ctl.crc_length);
  138. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
  139. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  140. else
  141. sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
  142. }
  143. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  144. ret = 0;
  145. break;
  146. case LMCIOCIFTYPE: /*fold01*/
  147. {
  148. u16 old_type = sc->if_type;
  149. u16 new_type;
  150. if (!capable(CAP_NET_ADMIN)) {
  151. ret = -EPERM;
  152. break;
  153. }
  154. if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
  155. ret = -EFAULT;
  156. break;
  157. }
  158. if (new_type == old_type)
  159. {
  160. ret = 0 ;
  161. break; /* no change */
  162. }
  163. spin_lock_irqsave(&sc->lmc_lock, flags);
  164. lmc_proto_close(sc);
  165. sc->if_type = new_type;
  166. lmc_proto_attach(sc);
  167. ret = lmc_proto_open(sc);
  168. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  169. break;
  170. }
  171. case LMCIOCGETXINFO: /*fold01*/
  172. spin_lock_irqsave(&sc->lmc_lock, flags);
  173. sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
  174. sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
  175. sc->lmc_xinfo.PciSlotNumber = 0;
  176. sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
  177. sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
  178. sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
  179. sc->lmc_xinfo.XilinxRevisionNumber =
  180. lmc_mii_readreg (sc, 0, 3) & 0xf;
  181. sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
  182. sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
  183. sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
  184. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  185. sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
  186. if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
  187. sizeof(struct lmc_xinfo)))
  188. ret = -EFAULT;
  189. else
  190. ret = 0;
  191. break;
  192. case LMCIOCGETLMCSTATS:
  193. spin_lock_irqsave(&sc->lmc_lock, flags);
  194. if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
  195. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
  196. sc->extra_stats.framingBitErrorCount +=
  197. lmc_mii_readreg(sc, 0, 18) & 0xff;
  198. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
  199. sc->extra_stats.framingBitErrorCount +=
  200. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  201. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
  202. sc->extra_stats.lineCodeViolationCount +=
  203. lmc_mii_readreg(sc, 0, 18) & 0xff;
  204. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
  205. sc->extra_stats.lineCodeViolationCount +=
  206. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  207. lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
  208. regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
  209. sc->extra_stats.lossOfFrameCount +=
  210. (regVal & T1FRAMER_LOF_MASK) >> 4;
  211. sc->extra_stats.changeOfFrameAlignmentCount +=
  212. (regVal & T1FRAMER_COFA_MASK) >> 2;
  213. sc->extra_stats.severelyErroredFrameCount +=
  214. regVal & T1FRAMER_SEF_MASK;
  215. }
  216. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  217. if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
  218. sizeof(sc->lmc_device->stats)) ||
  219. copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
  220. &sc->extra_stats, sizeof(sc->extra_stats)))
  221. ret = -EFAULT;
  222. else
  223. ret = 0;
  224. break;
  225. case LMCIOCCLEARLMCSTATS:
  226. if (!capable(CAP_NET_ADMIN)) {
  227. ret = -EPERM;
  228. break;
  229. }
  230. spin_lock_irqsave(&sc->lmc_lock, flags);
  231. memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
  232. memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
  233. sc->extra_stats.check = STATCHECK;
  234. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  235. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  236. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  237. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  238. ret = 0;
  239. break;
  240. case LMCIOCSETCIRCUIT: /*fold01*/
  241. if (!capable(CAP_NET_ADMIN)){
  242. ret = -EPERM;
  243. break;
  244. }
  245. if(dev->flags & IFF_UP){
  246. ret = -EBUSY;
  247. break;
  248. }
  249. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  250. ret = -EFAULT;
  251. break;
  252. }
  253. spin_lock_irqsave(&sc->lmc_lock, flags);
  254. sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
  255. sc->ictl.circuit_type = ctl.circuit_type;
  256. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  257. ret = 0;
  258. break;
  259. case LMCIOCRESET: /*fold01*/
  260. if (!capable(CAP_NET_ADMIN)){
  261. ret = -EPERM;
  262. break;
  263. }
  264. spin_lock_irqsave(&sc->lmc_lock, flags);
  265. /* Reset driver and bring back to current state */
  266. printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  267. lmc_running_reset (dev);
  268. printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  269. LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  270. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  271. ret = 0;
  272. break;
  273. #ifdef DEBUG
  274. case LMCIOCDUMPEVENTLOG:
  275. if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
  276. ret = -EFAULT;
  277. break;
  278. }
  279. if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
  280. sizeof(lmcEventLogBuf)))
  281. ret = -EFAULT;
  282. else
  283. ret = 0;
  284. break;
  285. #endif /* end ifdef _DBG_EVENTLOG */
  286. case LMCIOCT1CONTROL: /*fold01*/
  287. if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
  288. ret = -EOPNOTSUPP;
  289. break;
  290. }
  291. break;
  292. case LMCIOCXILINX: /*fold01*/
  293. {
  294. struct lmc_xilinx_control xc; /*fold02*/
  295. if (!capable(CAP_NET_ADMIN)){
  296. ret = -EPERM;
  297. break;
  298. }
  299. /*
  300. * Stop the xwitter whlie we restart the hardware
  301. */
  302. netif_stop_queue(dev);
  303. if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
  304. ret = -EFAULT;
  305. break;
  306. }
  307. switch(xc.command){
  308. case lmc_xilinx_reset: /*fold02*/
  309. {
  310. u16 mii;
  311. spin_lock_irqsave(&sc->lmc_lock, flags);
  312. mii = lmc_mii_readreg (sc, 0, 16);
  313. /*
  314. * Make all of them 0 and make input
  315. */
  316. lmc_gpio_mkinput(sc, 0xff);
  317. /*
  318. * make the reset output
  319. */
  320. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  321. /*
  322. * RESET low to force configuration. This also forces
  323. * the transmitter clock to be internal, but we expect to reset
  324. * that later anyway.
  325. */
  326. sc->lmc_gpio &= ~LMC_GEP_RESET;
  327. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  328. /*
  329. * hold for more than 10 microseconds
  330. */
  331. udelay(50);
  332. sc->lmc_gpio |= LMC_GEP_RESET;
  333. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  334. /*
  335. * stop driving Xilinx-related signals
  336. */
  337. lmc_gpio_mkinput(sc, 0xff);
  338. /* Reset the frammer hardware */
  339. sc->lmc_media->set_link_status (sc, 1);
  340. sc->lmc_media->set_status (sc, NULL);
  341. // lmc_softreset(sc);
  342. {
  343. int i;
  344. for(i = 0; i < 5; i++){
  345. lmc_led_on(sc, LMC_DS3_LED0);
  346. mdelay(100);
  347. lmc_led_off(sc, LMC_DS3_LED0);
  348. lmc_led_on(sc, LMC_DS3_LED1);
  349. mdelay(100);
  350. lmc_led_off(sc, LMC_DS3_LED1);
  351. lmc_led_on(sc, LMC_DS3_LED3);
  352. mdelay(100);
  353. lmc_led_off(sc, LMC_DS3_LED3);
  354. lmc_led_on(sc, LMC_DS3_LED2);
  355. mdelay(100);
  356. lmc_led_off(sc, LMC_DS3_LED2);
  357. }
  358. }
  359. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  360. ret = 0x0;
  361. }
  362. break;
  363. case lmc_xilinx_load_prom: /*fold02*/
  364. {
  365. u16 mii;
  366. int timeout = 500000;
  367. spin_lock_irqsave(&sc->lmc_lock, flags);
  368. mii = lmc_mii_readreg (sc, 0, 16);
  369. /*
  370. * Make all of them 0 and make input
  371. */
  372. lmc_gpio_mkinput(sc, 0xff);
  373. /*
  374. * make the reset output
  375. */
  376. lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  377. /*
  378. * RESET low to force configuration. This also forces
  379. * the transmitter clock to be internal, but we expect to reset
  380. * that later anyway.
  381. */
  382. sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
  383. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  384. /*
  385. * hold for more than 10 microseconds
  386. */
  387. udelay(50);
  388. sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
  389. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  390. /*
  391. * busy wait for the chip to reset
  392. */
  393. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  394. (timeout-- > 0))
  395. cpu_relax();
  396. /*
  397. * stop driving Xilinx-related signals
  398. */
  399. lmc_gpio_mkinput(sc, 0xff);
  400. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  401. ret = 0x0;
  402. break;
  403. }
  404. case lmc_xilinx_load: /*fold02*/
  405. {
  406. char *data;
  407. int pos;
  408. int timeout = 500000;
  409. if (!xc.data) {
  410. ret = -EINVAL;
  411. break;
  412. }
  413. data = memdup_user(xc.data, xc.len);
  414. if (IS_ERR(data)) {
  415. ret = PTR_ERR(data);
  416. break;
  417. }
  418. printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
  419. spin_lock_irqsave(&sc->lmc_lock, flags);
  420. lmc_gpio_mkinput(sc, 0xff);
  421. /*
  422. * Clear the Xilinx and start prgramming from the DEC
  423. */
  424. /*
  425. * Set ouput as:
  426. * Reset: 0 (active)
  427. * DP: 0 (active)
  428. * Mode: 1
  429. *
  430. */
  431. sc->lmc_gpio = 0x00;
  432. sc->lmc_gpio &= ~LMC_GEP_DP;
  433. sc->lmc_gpio &= ~LMC_GEP_RESET;
  434. sc->lmc_gpio |= LMC_GEP_MODE;
  435. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  436. lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
  437. /*
  438. * Wait at least 10 us 20 to be safe
  439. */
  440. udelay(50);
  441. /*
  442. * Clear reset and activate programming lines
  443. * Reset: Input
  444. * DP: Input
  445. * Clock: Output
  446. * Data: Output
  447. * Mode: Output
  448. */
  449. lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  450. /*
  451. * Set LOAD, DATA, Clock to 1
  452. */
  453. sc->lmc_gpio = 0x00;
  454. sc->lmc_gpio |= LMC_GEP_MODE;
  455. sc->lmc_gpio |= LMC_GEP_DATA;
  456. sc->lmc_gpio |= LMC_GEP_CLK;
  457. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  458. lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
  459. /*
  460. * busy wait for the chip to reset
  461. */
  462. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  463. (timeout-- > 0))
  464. cpu_relax();
  465. printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
  466. for(pos = 0; pos < xc.len; pos++){
  467. switch(data[pos]){
  468. case 0:
  469. sc->lmc_gpio &= ~LMC_GEP_DATA; /* Data is 0 */
  470. break;
  471. case 1:
  472. sc->lmc_gpio |= LMC_GEP_DATA; /* Data is 1 */
  473. break;
  474. default:
  475. printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
  476. sc->lmc_gpio |= LMC_GEP_DATA; /* Assume it's 1 */
  477. }
  478. sc->lmc_gpio &= ~LMC_GEP_CLK; /* Clock to zero */
  479. sc->lmc_gpio |= LMC_GEP_MODE;
  480. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  481. udelay(1);
  482. sc->lmc_gpio |= LMC_GEP_CLK; /* Put the clack back to one */
  483. sc->lmc_gpio |= LMC_GEP_MODE;
  484. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  485. udelay(1);
  486. }
  487. if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
  488. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
  489. }
  490. else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
  491. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
  492. }
  493. else {
  494. printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
  495. }
  496. lmc_gpio_mkinput(sc, 0xff);
  497. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  498. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  499. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  500. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  501. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  502. kfree(data);
  503. ret = 0;
  504. break;
  505. }
  506. default: /*fold02*/
  507. ret = -EBADE;
  508. break;
  509. }
  510. netif_wake_queue(dev);
  511. sc->lmc_txfull = 0;
  512. }
  513. break;
  514. default: /*fold01*/
  515. /* If we don't know what to do, give the protocol a shot. */
  516. ret = lmc_proto_ioctl (sc, ifr, cmd);
  517. break;
  518. }
  519. lmc_trace(dev, "lmc_ioctl out");
  520. return ret;
  521. }
  522. /* the watchdog process that cruises around */
  523. static void lmc_watchdog(struct timer_list *t) /*fold00*/
  524. {
  525. lmc_softc_t *sc = from_timer(sc, t, timer);
  526. struct net_device *dev = sc->lmc_device;
  527. int link_status;
  528. u32 ticks;
  529. unsigned long flags;
  530. lmc_trace(dev, "lmc_watchdog in");
  531. spin_lock_irqsave(&sc->lmc_lock, flags);
  532. if(sc->check != 0xBEAFCAFE){
  533. printk("LMC: Corrupt net_device struct, breaking out\n");
  534. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  535. return;
  536. }
  537. /* Make sure the tx jabber and rx watchdog are off,
  538. * and the transmit and receive processes are running.
  539. */
  540. LMC_CSR_WRITE (sc, csr_15, 0x00000011);
  541. sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN;
  542. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  543. if (sc->lmc_ok == 0)
  544. goto kick_timer;
  545. LMC_EVENT_LOG(LMC_EVENT_WATCHDOG, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  546. /* --- begin time out check -----------------------------------
  547. * check for a transmit interrupt timeout
  548. * Has the packet xmt vs xmt serviced threshold been exceeded */
  549. if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  550. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  551. sc->tx_TimeoutInd == 0)
  552. {
  553. /* wait for the watchdog to come around again */
  554. sc->tx_TimeoutInd = 1;
  555. }
  556. else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  557. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  558. sc->tx_TimeoutInd)
  559. {
  560. LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0);
  561. sc->tx_TimeoutDisplay = 1;
  562. sc->extra_stats.tx_TimeoutCnt++;
  563. /* DEC chip is stuck, hit it with a RESET!!!! */
  564. lmc_running_reset (dev);
  565. /* look at receive & transmit process state to make sure they are running */
  566. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  567. /* look at: DSR - 02 for Reg 16
  568. * CTS - 08
  569. * DCD - 10
  570. * RI - 20
  571. * for Reg 17
  572. */
  573. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg (sc, 0, 16), lmc_mii_readreg (sc, 0, 17));
  574. /* reset the transmit timeout detection flag */
  575. sc->tx_TimeoutInd = 0;
  576. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  577. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  578. } else {
  579. sc->tx_TimeoutInd = 0;
  580. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  581. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  582. }
  583. /* --- end time out check ----------------------------------- */
  584. link_status = sc->lmc_media->get_link_status (sc);
  585. /*
  586. * hardware level link lost, but the interface is marked as up.
  587. * Mark it as down.
  588. */
  589. if ((link_status == 0) && (sc->last_link_status != 0)) {
  590. printk(KERN_WARNING "%s: hardware/physical link down\n", dev->name);
  591. sc->last_link_status = 0;
  592. /* lmc_reset (sc); Why reset??? The link can go down ok */
  593. /* Inform the world that link has been lost */
  594. netif_carrier_off(dev);
  595. }
  596. /*
  597. * hardware link is up, but the interface is marked as down.
  598. * Bring it back up again.
  599. */
  600. if (link_status != 0 && sc->last_link_status == 0) {
  601. printk(KERN_WARNING "%s: hardware/physical link up\n", dev->name);
  602. sc->last_link_status = 1;
  603. /* lmc_reset (sc); Again why reset??? */
  604. netif_carrier_on(dev);
  605. }
  606. /* Call media specific watchdog functions */
  607. sc->lmc_media->watchdog(sc);
  608. /*
  609. * Poke the transmitter to make sure it
  610. * never stops, even if we run out of mem
  611. */
  612. LMC_CSR_WRITE(sc, csr_rxpoll, 0);
  613. /*
  614. * Check for code that failed
  615. * and try and fix it as appropriate
  616. */
  617. if(sc->failed_ring == 1){
  618. /*
  619. * Failed to setup the recv/xmit rin
  620. * Try again
  621. */
  622. sc->failed_ring = 0;
  623. lmc_softreset(sc);
  624. }
  625. if(sc->failed_recv_alloc == 1){
  626. /*
  627. * We failed to alloc mem in the
  628. * interrupt handler, go through the rings
  629. * and rebuild them
  630. */
  631. sc->failed_recv_alloc = 0;
  632. lmc_softreset(sc);
  633. }
  634. /*
  635. * remember the timer value
  636. */
  637. kick_timer:
  638. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  639. LMC_CSR_WRITE (sc, csr_gp_timer, 0xffffffffUL);
  640. sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff);
  641. /*
  642. * restart this timer.
  643. */
  644. sc->timer.expires = jiffies + (HZ);
  645. add_timer (&sc->timer);
  646. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  647. lmc_trace(dev, "lmc_watchdog out");
  648. }
  649. static int lmc_attach(struct net_device *dev, unsigned short encoding,
  650. unsigned short parity)
  651. {
  652. if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
  653. return 0;
  654. return -EINVAL;
  655. }
  656. static const struct net_device_ops lmc_ops = {
  657. .ndo_open = lmc_open,
  658. .ndo_stop = lmc_close,
  659. .ndo_start_xmit = hdlc_start_xmit,
  660. .ndo_do_ioctl = lmc_ioctl,
  661. .ndo_tx_timeout = lmc_driver_timeout,
  662. .ndo_get_stats = lmc_get_stats,
  663. };
  664. static int lmc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  665. {
  666. lmc_softc_t *sc;
  667. struct net_device *dev;
  668. u16 subdevice;
  669. u16 AdapModelNum;
  670. int err;
  671. static int cards_found;
  672. /* lmc_trace(dev, "lmc_init_one in"); */
  673. err = pcim_enable_device(pdev);
  674. if (err) {
  675. printk(KERN_ERR "lmc: pci enable failed: %d\n", err);
  676. return err;
  677. }
  678. err = pci_request_regions(pdev, "lmc");
  679. if (err) {
  680. printk(KERN_ERR "lmc: pci_request_region failed\n");
  681. return err;
  682. }
  683. /*
  684. * Allocate our own device structure
  685. */
  686. sc = devm_kzalloc(&pdev->dev, sizeof(lmc_softc_t), GFP_KERNEL);
  687. if (!sc)
  688. return -ENOMEM;
  689. dev = alloc_hdlcdev(sc);
  690. if (!dev) {
  691. printk(KERN_ERR "lmc:alloc_netdev for device failed\n");
  692. return -ENOMEM;
  693. }
  694. dev->type = ARPHRD_HDLC;
  695. dev_to_hdlc(dev)->xmit = lmc_start_xmit;
  696. dev_to_hdlc(dev)->attach = lmc_attach;
  697. dev->netdev_ops = &lmc_ops;
  698. dev->watchdog_timeo = HZ; /* 1 second */
  699. dev->tx_queue_len = 100;
  700. sc->lmc_device = dev;
  701. sc->name = dev->name;
  702. sc->if_type = LMC_PPP;
  703. sc->check = 0xBEAFCAFE;
  704. dev->base_addr = pci_resource_start(pdev, 0);
  705. dev->irq = pdev->irq;
  706. pci_set_drvdata(pdev, dev);
  707. SET_NETDEV_DEV(dev, &pdev->dev);
  708. /*
  709. * This will get the protocol layer ready and do any 1 time init's
  710. * Must have a valid sc and dev structure
  711. */
  712. lmc_proto_attach(sc);
  713. /* Init the spin lock so can call it latter */
  714. spin_lock_init(&sc->lmc_lock);
  715. pci_set_master(pdev);
  716. printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name,
  717. dev->base_addr, dev->irq);
  718. err = register_hdlc_device(dev);
  719. if (err) {
  720. printk(KERN_ERR "%s: register_netdev failed.\n", dev->name);
  721. free_netdev(dev);
  722. return err;
  723. }
  724. sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN;
  725. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  726. /*
  727. *
  728. * Check either the subvendor or the subdevice, some systems reverse
  729. * the setting in the bois, seems to be version and arch dependent?
  730. * Fix the error, exchange the two values
  731. */
  732. if ((subdevice = pdev->subsystem_device) == PCI_VENDOR_ID_LMC)
  733. subdevice = pdev->subsystem_vendor;
  734. switch (subdevice) {
  735. case PCI_DEVICE_ID_LMC_HSSI:
  736. printk(KERN_INFO "%s: LMC HSSI\n", dev->name);
  737. sc->lmc_cardtype = LMC_CARDTYPE_HSSI;
  738. sc->lmc_media = &lmc_hssi_media;
  739. break;
  740. case PCI_DEVICE_ID_LMC_DS3:
  741. printk(KERN_INFO "%s: LMC DS3\n", dev->name);
  742. sc->lmc_cardtype = LMC_CARDTYPE_DS3;
  743. sc->lmc_media = &lmc_ds3_media;
  744. break;
  745. case PCI_DEVICE_ID_LMC_SSI:
  746. printk(KERN_INFO "%s: LMC SSI\n", dev->name);
  747. sc->lmc_cardtype = LMC_CARDTYPE_SSI;
  748. sc->lmc_media = &lmc_ssi_media;
  749. break;
  750. case PCI_DEVICE_ID_LMC_T1:
  751. printk(KERN_INFO "%s: LMC T1\n", dev->name);
  752. sc->lmc_cardtype = LMC_CARDTYPE_T1;
  753. sc->lmc_media = &lmc_t1_media;
  754. break;
  755. default:
  756. printk(KERN_WARNING "%s: LMC UNKNOWN CARD!\n", dev->name);
  757. break;
  758. }
  759. lmc_initcsrs (sc, dev->base_addr, 8);
  760. lmc_gpio_mkinput (sc, 0xff);
  761. sc->lmc_gpio = 0; /* drive no signals yet */
  762. sc->lmc_media->defaults (sc);
  763. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  764. /* verify that the PCI Sub System ID matches the Adapter Model number
  765. * from the MII register
  766. */
  767. AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4;
  768. if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */
  769. subdevice != PCI_DEVICE_ID_LMC_T1) &&
  770. (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */
  771. subdevice != PCI_DEVICE_ID_LMC_SSI) &&
  772. (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */
  773. subdevice != PCI_DEVICE_ID_LMC_DS3) &&
  774. (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */
  775. subdevice != PCI_DEVICE_ID_LMC_HSSI))
  776. printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI"
  777. " Subsystem ID = 0x%04x\n",
  778. dev->name, AdapModelNum, subdevice);
  779. /*
  780. * reset clock
  781. */
  782. LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL);
  783. sc->board_idx = cards_found++;
  784. sc->extra_stats.check = STATCHECK;
  785. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  786. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  787. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  788. sc->lmc_ok = 0;
  789. sc->last_link_status = 0;
  790. lmc_trace(dev, "lmc_init_one out");
  791. return 0;
  792. }
  793. /*
  794. * Called from pci when removing module.
  795. */
  796. static void lmc_remove_one(struct pci_dev *pdev)
  797. {
  798. struct net_device *dev = pci_get_drvdata(pdev);
  799. if (dev) {
  800. printk(KERN_DEBUG "%s: removing...\n", dev->name);
  801. unregister_hdlc_device(dev);
  802. free_netdev(dev);
  803. }
  804. }
  805. /* After this is called, packets can be sent.
  806. * Does not initialize the addresses
  807. */
  808. static int lmc_open(struct net_device *dev)
  809. {
  810. lmc_softc_t *sc = dev_to_sc(dev);
  811. int err;
  812. lmc_trace(dev, "lmc_open in");
  813. lmc_led_on(sc, LMC_DS3_LED0);
  814. lmc_dec_reset(sc);
  815. lmc_reset(sc);
  816. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0);
  817. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16),
  818. lmc_mii_readreg(sc, 0, 17));
  819. if (sc->lmc_ok){
  820. lmc_trace(dev, "lmc_open lmc_ok out");
  821. return 0;
  822. }
  823. lmc_softreset (sc);
  824. /* Since we have to use PCI bus, this should work on x86,alpha,ppc */
  825. if (request_irq (dev->irq, lmc_interrupt, IRQF_SHARED, dev->name, dev)){
  826. printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
  827. lmc_trace(dev, "lmc_open irq failed out");
  828. return -EAGAIN;
  829. }
  830. sc->got_irq = 1;
  831. /* Assert Terminal Active */
  832. sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
  833. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  834. /*
  835. * reset to last state.
  836. */
  837. sc->lmc_media->set_status (sc, NULL);
  838. /* setup default bits to be used in tulip_desc_t transmit descriptor
  839. * -baz */
  840. sc->TxDescriptControlInit = (
  841. LMC_TDES_INTERRUPT_ON_COMPLETION
  842. | LMC_TDES_FIRST_SEGMENT
  843. | LMC_TDES_LAST_SEGMENT
  844. | LMC_TDES_SECOND_ADDR_CHAINED
  845. | LMC_TDES_DISABLE_PADDING
  846. );
  847. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16) {
  848. /* disable 32 bit CRC generated by ASIC */
  849. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  850. }
  851. sc->lmc_media->set_crc_length(sc, sc->ictl.crc_length);
  852. /* Acknoledge the Terminal Active and light LEDs */
  853. /* dev->flags |= IFF_UP; */
  854. if ((err = lmc_proto_open(sc)) != 0)
  855. return err;
  856. netif_start_queue(dev);
  857. sc->extra_stats.tx_tbusy0++;
  858. /*
  859. * select what interrupts we want to get
  860. */
  861. sc->lmc_intrmask = 0;
  862. /* Should be using the default interrupt mask defined in the .h file. */
  863. sc->lmc_intrmask |= (TULIP_STS_NORMALINTR
  864. | TULIP_STS_RXINTR
  865. | TULIP_STS_TXINTR
  866. | TULIP_STS_ABNRMLINTR
  867. | TULIP_STS_SYSERROR
  868. | TULIP_STS_TXSTOPPED
  869. | TULIP_STS_TXUNDERFLOW
  870. | TULIP_STS_RXSTOPPED
  871. | TULIP_STS_RXNOBUF
  872. );
  873. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  874. sc->lmc_cmdmode |= TULIP_CMD_TXRUN;
  875. sc->lmc_cmdmode |= TULIP_CMD_RXRUN;
  876. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  877. sc->lmc_ok = 1; /* Run watchdog */
  878. /*
  879. * Set the if up now - pfb
  880. */
  881. sc->last_link_status = 1;
  882. /*
  883. * Setup a timer for the watchdog on probe, and start it running.
  884. * Since lmc_ok == 0, it will be a NOP for now.
  885. */
  886. timer_setup(&sc->timer, lmc_watchdog, 0);
  887. sc->timer.expires = jiffies + HZ;
  888. add_timer (&sc->timer);
  889. lmc_trace(dev, "lmc_open out");
  890. return 0;
  891. }
  892. /* Total reset to compensate for the AdTran DSU doing bad things
  893. * under heavy load
  894. */
  895. static void lmc_running_reset (struct net_device *dev) /*fold00*/
  896. {
  897. lmc_softc_t *sc = dev_to_sc(dev);
  898. lmc_trace(dev, "lmc_running_reset in");
  899. /* stop interrupts */
  900. /* Clear the interrupt mask */
  901. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  902. lmc_dec_reset (sc);
  903. lmc_reset (sc);
  904. lmc_softreset (sc);
  905. /* sc->lmc_miireg16 |= LMC_MII16_LED_ALL; */
  906. sc->lmc_media->set_link_status (sc, 1);
  907. sc->lmc_media->set_status (sc, NULL);
  908. netif_wake_queue(dev);
  909. sc->lmc_txfull = 0;
  910. sc->extra_stats.tx_tbusy0++;
  911. sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK;
  912. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  913. sc->lmc_cmdmode |= (TULIP_CMD_TXRUN | TULIP_CMD_RXRUN);
  914. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  915. lmc_trace(dev, "lmc_running_reset_out");
  916. }
  917. /* This is what is called when you ifconfig down a device.
  918. * This disables the timer for the watchdog and keepalives,
  919. * and disables the irq for dev.
  920. */
  921. static int lmc_close(struct net_device *dev)
  922. {
  923. /* not calling release_region() as we should */
  924. lmc_softc_t *sc = dev_to_sc(dev);
  925. lmc_trace(dev, "lmc_close in");
  926. sc->lmc_ok = 0;
  927. sc->lmc_media->set_link_status (sc, 0);
  928. del_timer (&sc->timer);
  929. lmc_proto_close(sc);
  930. lmc_ifdown (dev);
  931. lmc_trace(dev, "lmc_close out");
  932. return 0;
  933. }
  934. /* Ends the transfer of packets */
  935. /* When the interface goes down, this is called */
  936. static int lmc_ifdown (struct net_device *dev) /*fold00*/
  937. {
  938. lmc_softc_t *sc = dev_to_sc(dev);
  939. u32 csr6;
  940. int i;
  941. lmc_trace(dev, "lmc_ifdown in");
  942. /* Don't let anything else go on right now */
  943. // dev->start = 0;
  944. netif_stop_queue(dev);
  945. sc->extra_stats.tx_tbusy1++;
  946. /* stop interrupts */
  947. /* Clear the interrupt mask */
  948. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  949. /* Stop Tx and Rx on the chip */
  950. csr6 = LMC_CSR_READ (sc, csr_command);
  951. csr6 &= ~LMC_DEC_ST; /* Turn off the Transmission bit */
  952. csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
  953. LMC_CSR_WRITE (sc, csr_command, csr6);
  954. sc->lmc_device->stats.rx_missed_errors +=
  955. LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  956. /* release the interrupt */
  957. if(sc->got_irq == 1){
  958. free_irq (dev->irq, dev);
  959. sc->got_irq = 0;
  960. }
  961. /* free skbuffs in the Rx queue */
  962. for (i = 0; i < LMC_RXDESCS; i++)
  963. {
  964. struct sk_buff *skb = sc->lmc_rxq[i];
  965. sc->lmc_rxq[i] = NULL;
  966. sc->lmc_rxring[i].status = 0;
  967. sc->lmc_rxring[i].length = 0;
  968. sc->lmc_rxring[i].buffer1 = 0xDEADBEEF;
  969. if (skb != NULL)
  970. dev_kfree_skb(skb);
  971. sc->lmc_rxq[i] = NULL;
  972. }
  973. for (i = 0; i < LMC_TXDESCS; i++)
  974. {
  975. if (sc->lmc_txq[i] != NULL)
  976. dev_kfree_skb(sc->lmc_txq[i]);
  977. sc->lmc_txq[i] = NULL;
  978. }
  979. lmc_led_off (sc, LMC_MII16_LED_ALL);
  980. netif_wake_queue(dev);
  981. sc->extra_stats.tx_tbusy0++;
  982. lmc_trace(dev, "lmc_ifdown out");
  983. return 0;
  984. }
  985. /* Interrupt handling routine. This will take an incoming packet, or clean
  986. * up after a trasmit.
  987. */
  988. static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/
  989. {
  990. struct net_device *dev = (struct net_device *) dev_instance;
  991. lmc_softc_t *sc = dev_to_sc(dev);
  992. u32 csr;
  993. int i;
  994. s32 stat;
  995. unsigned int badtx;
  996. u32 firstcsr;
  997. int max_work = LMC_RXDESCS;
  998. int handled = 0;
  999. lmc_trace(dev, "lmc_interrupt in");
  1000. spin_lock(&sc->lmc_lock);
  1001. /*
  1002. * Read the csr to find what interrupts we have (if any)
  1003. */
  1004. csr = LMC_CSR_READ (sc, csr_status);
  1005. /*
  1006. * Make sure this is our interrupt
  1007. */
  1008. if ( ! (csr & sc->lmc_intrmask)) {
  1009. goto lmc_int_fail_out;
  1010. }
  1011. firstcsr = csr;
  1012. /* always go through this loop at least once */
  1013. while (csr & sc->lmc_intrmask) {
  1014. handled = 1;
  1015. /*
  1016. * Clear interrupt bits, we handle all case below
  1017. */
  1018. LMC_CSR_WRITE (sc, csr_status, csr);
  1019. /*
  1020. * One of
  1021. * - Transmit process timed out CSR5<1>
  1022. * - Transmit jabber timeout CSR5<3>
  1023. * - Transmit underflow CSR5<5>
  1024. * - Transmit Receiver buffer unavailable CSR5<7>
  1025. * - Receive process stopped CSR5<8>
  1026. * - Receive watchdog timeout CSR5<9>
  1027. * - Early transmit interrupt CSR5<10>
  1028. *
  1029. * Is this really right? Should we do a running reset for jabber?
  1030. * (being a WAN card and all)
  1031. */
  1032. if (csr & TULIP_STS_ABNRMLINTR){
  1033. lmc_running_reset (dev);
  1034. break;
  1035. }
  1036. if (csr & TULIP_STS_RXINTR){
  1037. lmc_trace(dev, "rx interrupt");
  1038. lmc_rx (dev);
  1039. }
  1040. if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) {
  1041. int n_compl = 0 ;
  1042. /* reset the transmit timeout detection flag -baz */
  1043. sc->extra_stats.tx_NoCompleteCnt = 0;
  1044. badtx = sc->lmc_taint_tx;
  1045. i = badtx % LMC_TXDESCS;
  1046. while ((badtx < sc->lmc_next_tx)) {
  1047. stat = sc->lmc_txring[i].status;
  1048. LMC_EVENT_LOG (LMC_EVENT_XMTINT, stat,
  1049. sc->lmc_txring[i].length);
  1050. /*
  1051. * If bit 31 is 1 the tulip owns it break out of the loop
  1052. */
  1053. if (stat & 0x80000000)
  1054. break;
  1055. n_compl++ ; /* i.e., have an empty slot in ring */
  1056. /*
  1057. * If we have no skbuff or have cleared it
  1058. * Already continue to the next buffer
  1059. */
  1060. if (sc->lmc_txq[i] == NULL)
  1061. continue;
  1062. /*
  1063. * Check the total error summary to look for any errors
  1064. */
  1065. if (stat & 0x8000) {
  1066. sc->lmc_device->stats.tx_errors++;
  1067. if (stat & 0x4104)
  1068. sc->lmc_device->stats.tx_aborted_errors++;
  1069. if (stat & 0x0C00)
  1070. sc->lmc_device->stats.tx_carrier_errors++;
  1071. if (stat & 0x0200)
  1072. sc->lmc_device->stats.tx_window_errors++;
  1073. if (stat & 0x0002)
  1074. sc->lmc_device->stats.tx_fifo_errors++;
  1075. } else {
  1076. sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff;
  1077. sc->lmc_device->stats.tx_packets++;
  1078. }
  1079. dev_consume_skb_irq(sc->lmc_txq[i]);
  1080. sc->lmc_txq[i] = NULL;
  1081. badtx++;
  1082. i = badtx % LMC_TXDESCS;
  1083. }
  1084. if (sc->lmc_next_tx - badtx > LMC_TXDESCS)
  1085. {
  1086. printk ("%s: out of sync pointer\n", dev->name);
  1087. badtx += LMC_TXDESCS;
  1088. }
  1089. LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0);
  1090. sc->lmc_txfull = 0;
  1091. netif_wake_queue(dev);
  1092. sc->extra_stats.tx_tbusy0++;
  1093. #ifdef DEBUG
  1094. sc->extra_stats.dirtyTx = badtx;
  1095. sc->extra_stats.lmc_next_tx = sc->lmc_next_tx;
  1096. sc->extra_stats.lmc_txfull = sc->lmc_txfull;
  1097. #endif
  1098. sc->lmc_taint_tx = badtx;
  1099. /*
  1100. * Why was there a break here???
  1101. */
  1102. } /* end handle transmit interrupt */
  1103. if (csr & TULIP_STS_SYSERROR) {
  1104. u32 error;
  1105. printk (KERN_WARNING "%s: system bus error csr: %#8.8x\n", dev->name, csr);
  1106. error = csr>>23 & 0x7;
  1107. switch(error){
  1108. case 0x000:
  1109. printk(KERN_WARNING "%s: Parity Fault (bad)\n", dev->name);
  1110. break;
  1111. case 0x001:
  1112. printk(KERN_WARNING "%s: Master Abort (naughty)\n", dev->name);
  1113. break;
  1114. case 0x002:
  1115. printk(KERN_WARNING "%s: Target Abort (not so naughty)\n", dev->name);
  1116. break;
  1117. default:
  1118. printk(KERN_WARNING "%s: This bus error code was supposed to be reserved!\n", dev->name);
  1119. }
  1120. lmc_dec_reset (sc);
  1121. lmc_reset (sc);
  1122. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1123. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1124. lmc_mii_readreg (sc, 0, 16),
  1125. lmc_mii_readreg (sc, 0, 17));
  1126. }
  1127. if(max_work-- <= 0)
  1128. break;
  1129. /*
  1130. * Get current csr status to make sure
  1131. * we've cleared all interrupts
  1132. */
  1133. csr = LMC_CSR_READ (sc, csr_status);
  1134. } /* end interrupt loop */
  1135. LMC_EVENT_LOG(LMC_EVENT_INT, firstcsr, csr);
  1136. lmc_int_fail_out:
  1137. spin_unlock(&sc->lmc_lock);
  1138. lmc_trace(dev, "lmc_interrupt out");
  1139. return IRQ_RETVAL(handled);
  1140. }
  1141. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  1142. struct net_device *dev)
  1143. {
  1144. lmc_softc_t *sc = dev_to_sc(dev);
  1145. u32 flag;
  1146. int entry;
  1147. unsigned long flags;
  1148. lmc_trace(dev, "lmc_start_xmit in");
  1149. spin_lock_irqsave(&sc->lmc_lock, flags);
  1150. /* normal path, tbusy known to be zero */
  1151. entry = sc->lmc_next_tx % LMC_TXDESCS;
  1152. sc->lmc_txq[entry] = skb;
  1153. sc->lmc_txring[entry].buffer1 = virt_to_bus (skb->data);
  1154. LMC_CONSOLE_LOG("xmit", skb->data, skb->len);
  1155. #ifndef GCOM
  1156. /* If the queue is less than half full, don't interrupt */
  1157. if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS / 2)
  1158. {
  1159. /* Do not interrupt on completion of this packet */
  1160. flag = 0x60000000;
  1161. netif_wake_queue(dev);
  1162. }
  1163. else if (sc->lmc_next_tx - sc->lmc_taint_tx == LMC_TXDESCS / 2)
  1164. {
  1165. /* This generates an interrupt on completion of this packet */
  1166. flag = 0xe0000000;
  1167. netif_wake_queue(dev);
  1168. }
  1169. else if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS - 1)
  1170. {
  1171. /* Do not interrupt on completion of this packet */
  1172. flag = 0x60000000;
  1173. netif_wake_queue(dev);
  1174. }
  1175. else
  1176. {
  1177. /* This generates an interrupt on completion of this packet */
  1178. flag = 0xe0000000;
  1179. sc->lmc_txfull = 1;
  1180. netif_stop_queue(dev);
  1181. }
  1182. #else
  1183. flag = LMC_TDES_INTERRUPT_ON_COMPLETION;
  1184. if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1)
  1185. { /* ring full, go busy */
  1186. sc->lmc_txfull = 1;
  1187. netif_stop_queue(dev);
  1188. sc->extra_stats.tx_tbusy1++;
  1189. LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0);
  1190. }
  1191. #endif
  1192. if (entry == LMC_TXDESCS - 1) /* last descriptor in ring */
  1193. flag |= LMC_TDES_END_OF_RING; /* flag as such for Tulip */
  1194. /* don't pad small packets either */
  1195. flag = sc->lmc_txring[entry].length = (skb->len) | flag |
  1196. sc->TxDescriptControlInit;
  1197. /* set the transmit timeout flag to be checked in
  1198. * the watchdog timer handler. -baz
  1199. */
  1200. sc->extra_stats.tx_NoCompleteCnt++;
  1201. sc->lmc_next_tx++;
  1202. /* give ownership to the chip */
  1203. LMC_EVENT_LOG(LMC_EVENT_XMT, flag, entry);
  1204. sc->lmc_txring[entry].status = 0x80000000;
  1205. /* send now! */
  1206. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1207. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1208. lmc_trace(dev, "lmc_start_xmit_out");
  1209. return NETDEV_TX_OK;
  1210. }
  1211. static int lmc_rx(struct net_device *dev)
  1212. {
  1213. lmc_softc_t *sc = dev_to_sc(dev);
  1214. int i;
  1215. int rx_work_limit = LMC_RXDESCS;
  1216. int rxIntLoopCnt; /* debug -baz */
  1217. int localLengthErrCnt = 0;
  1218. long stat;
  1219. struct sk_buff *skb, *nsb;
  1220. u16 len;
  1221. lmc_trace(dev, "lmc_rx in");
  1222. lmc_led_on(sc, LMC_DS3_LED3);
  1223. rxIntLoopCnt = 0; /* debug -baz */
  1224. i = sc->lmc_next_rx % LMC_RXDESCS;
  1225. while (((stat = sc->lmc_rxring[i].status) & LMC_RDES_OWN_BIT) != DESC_OWNED_BY_DC21X4)
  1226. {
  1227. rxIntLoopCnt++; /* debug -baz */
  1228. len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER);
  1229. if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */
  1230. if ((stat & 0x0000ffff) != 0x7fff) {
  1231. /* Oversized frame */
  1232. sc->lmc_device->stats.rx_length_errors++;
  1233. goto skip_packet;
  1234. }
  1235. }
  1236. if (stat & 0x00000008) { /* Catch a dribbling bit error */
  1237. sc->lmc_device->stats.rx_errors++;
  1238. sc->lmc_device->stats.rx_frame_errors++;
  1239. goto skip_packet;
  1240. }
  1241. if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */
  1242. sc->lmc_device->stats.rx_errors++;
  1243. sc->lmc_device->stats.rx_crc_errors++;
  1244. goto skip_packet;
  1245. }
  1246. if (len > LMC_PKT_BUF_SZ) {
  1247. sc->lmc_device->stats.rx_length_errors++;
  1248. localLengthErrCnt++;
  1249. goto skip_packet;
  1250. }
  1251. if (len < sc->lmc_crcSize + 2) {
  1252. sc->lmc_device->stats.rx_length_errors++;
  1253. sc->extra_stats.rx_SmallPktCnt++;
  1254. localLengthErrCnt++;
  1255. goto skip_packet;
  1256. }
  1257. if(stat & 0x00004000){
  1258. printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name);
  1259. }
  1260. len -= sc->lmc_crcSize;
  1261. skb = sc->lmc_rxq[i];
  1262. /*
  1263. * We ran out of memory at some point
  1264. * just allocate an skb buff and continue.
  1265. */
  1266. if (!skb) {
  1267. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1268. if (nsb) {
  1269. sc->lmc_rxq[i] = nsb;
  1270. nsb->dev = dev;
  1271. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1272. }
  1273. sc->failed_recv_alloc = 1;
  1274. goto skip_packet;
  1275. }
  1276. sc->lmc_device->stats.rx_packets++;
  1277. sc->lmc_device->stats.rx_bytes += len;
  1278. LMC_CONSOLE_LOG("recv", skb->data, len);
  1279. /*
  1280. * I'm not sure of the sanity of this
  1281. * Packets could be arriving at a constant
  1282. * 44.210mbits/sec and we're going to copy
  1283. * them into a new buffer??
  1284. */
  1285. if(len > (LMC_MTU - (LMC_MTU>>2))){ /* len > LMC_MTU * 0.75 */
  1286. /*
  1287. * If it's a large packet don't copy it just hand it up
  1288. */
  1289. give_it_anyways:
  1290. sc->lmc_rxq[i] = NULL;
  1291. sc->lmc_rxring[i].buffer1 = 0x0;
  1292. skb_put (skb, len);
  1293. skb->protocol = lmc_proto_type(sc, skb);
  1294. skb_reset_mac_header(skb);
  1295. /* skb_reset_network_header(skb); */
  1296. skb->dev = dev;
  1297. lmc_proto_netif(sc, skb);
  1298. /*
  1299. * This skb will be destroyed by the upper layers, make a new one
  1300. */
  1301. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1302. if (nsb) {
  1303. sc->lmc_rxq[i] = nsb;
  1304. nsb->dev = dev;
  1305. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1306. /* Transferred to 21140 below */
  1307. }
  1308. else {
  1309. /*
  1310. * We've run out of memory, stop trying to allocate
  1311. * memory and exit the interrupt handler
  1312. *
  1313. * The chip may run out of receivers and stop
  1314. * in which care we'll try to allocate the buffer
  1315. * again. (once a second)
  1316. */
  1317. sc->extra_stats.rx_BuffAllocErr++;
  1318. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1319. sc->failed_recv_alloc = 1;
  1320. goto skip_out_of_mem;
  1321. }
  1322. }
  1323. else {
  1324. nsb = dev_alloc_skb(len);
  1325. if(!nsb) {
  1326. goto give_it_anyways;
  1327. }
  1328. skb_copy_from_linear_data(skb, skb_put(nsb, len), len);
  1329. nsb->protocol = lmc_proto_type(sc, nsb);
  1330. skb_reset_mac_header(nsb);
  1331. /* skb_reset_network_header(nsb); */
  1332. nsb->dev = dev;
  1333. lmc_proto_netif(sc, nsb);
  1334. }
  1335. skip_packet:
  1336. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1337. sc->lmc_rxring[i].status = DESC_OWNED_BY_DC21X4;
  1338. sc->lmc_next_rx++;
  1339. i = sc->lmc_next_rx % LMC_RXDESCS;
  1340. rx_work_limit--;
  1341. if (rx_work_limit < 0)
  1342. break;
  1343. }
  1344. /* detect condition for LMC1000 where DSU cable attaches and fills
  1345. * descriptors with bogus packets
  1346. *
  1347. if (localLengthErrCnt > LMC_RXDESCS - 3) {
  1348. sc->extra_stats.rx_BadPktSurgeCnt++;
  1349. LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt,
  1350. sc->extra_stats.rx_BadPktSurgeCnt);
  1351. } */
  1352. /* save max count of receive descriptors serviced */
  1353. if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt)
  1354. sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */
  1355. #ifdef DEBUG
  1356. if (rxIntLoopCnt == 0)
  1357. {
  1358. for (i = 0; i < LMC_RXDESCS; i++)
  1359. {
  1360. if ((sc->lmc_rxring[i].status & LMC_RDES_OWN_BIT)
  1361. != DESC_OWNED_BY_DC21X4)
  1362. {
  1363. rxIntLoopCnt++;
  1364. }
  1365. }
  1366. LMC_EVENT_LOG(LMC_EVENT_RCVEND, rxIntLoopCnt, 0);
  1367. }
  1368. #endif
  1369. lmc_led_off(sc, LMC_DS3_LED3);
  1370. skip_out_of_mem:
  1371. lmc_trace(dev, "lmc_rx out");
  1372. return 0;
  1373. }
  1374. static struct net_device_stats *lmc_get_stats(struct net_device *dev)
  1375. {
  1376. lmc_softc_t *sc = dev_to_sc(dev);
  1377. unsigned long flags;
  1378. lmc_trace(dev, "lmc_get_stats in");
  1379. spin_lock_irqsave(&sc->lmc_lock, flags);
  1380. sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  1381. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1382. lmc_trace(dev, "lmc_get_stats out");
  1383. return &sc->lmc_device->stats;
  1384. }
  1385. static struct pci_driver lmc_driver = {
  1386. .name = "lmc",
  1387. .id_table = lmc_pci_tbl,
  1388. .probe = lmc_init_one,
  1389. .remove = lmc_remove_one,
  1390. };
  1391. module_pci_driver(lmc_driver);
  1392. unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno) /*fold00*/
  1393. {
  1394. int i;
  1395. int command = (0xf6 << 10) | (devaddr << 5) | regno;
  1396. int retval = 0;
  1397. lmc_trace(sc->lmc_device, "lmc_mii_readreg in");
  1398. LMC_MII_SYNC (sc);
  1399. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done sync");
  1400. for (i = 15; i >= 0; i--)
  1401. {
  1402. int dataval = (command & (1 << i)) ? 0x20000 : 0;
  1403. LMC_CSR_WRITE (sc, csr_9, dataval);
  1404. lmc_delay ();
  1405. /* __SLOW_DOWN_IO; */
  1406. LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
  1407. lmc_delay ();
  1408. /* __SLOW_DOWN_IO; */
  1409. }
  1410. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done1");
  1411. for (i = 19; i > 0; i--)
  1412. {
  1413. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1414. lmc_delay ();
  1415. /* __SLOW_DOWN_IO; */
  1416. retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
  1417. LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
  1418. lmc_delay ();
  1419. /* __SLOW_DOWN_IO; */
  1420. }
  1421. lmc_trace(sc->lmc_device, "lmc_mii_readreg out");
  1422. return (retval >> 1) & 0xffff;
  1423. }
  1424. void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno, unsigned data) /*fold00*/
  1425. {
  1426. int i = 32;
  1427. int command = (0x5002 << 16) | (devaddr << 23) | (regno << 18) | data;
  1428. lmc_trace(sc->lmc_device, "lmc_mii_writereg in");
  1429. LMC_MII_SYNC (sc);
  1430. i = 31;
  1431. while (i >= 0)
  1432. {
  1433. int datav;
  1434. if (command & (1 << i))
  1435. datav = 0x20000;
  1436. else
  1437. datav = 0x00000;
  1438. LMC_CSR_WRITE (sc, csr_9, datav);
  1439. lmc_delay ();
  1440. /* __SLOW_DOWN_IO; */
  1441. LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
  1442. lmc_delay ();
  1443. /* __SLOW_DOWN_IO; */
  1444. i--;
  1445. }
  1446. i = 2;
  1447. while (i > 0)
  1448. {
  1449. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1450. lmc_delay ();
  1451. /* __SLOW_DOWN_IO; */
  1452. LMC_CSR_WRITE (sc, csr_9, 0x50000);
  1453. lmc_delay ();
  1454. /* __SLOW_DOWN_IO; */
  1455. i--;
  1456. }
  1457. lmc_trace(sc->lmc_device, "lmc_mii_writereg out");
  1458. }
  1459. static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/
  1460. {
  1461. int i;
  1462. lmc_trace(sc->lmc_device, "lmc_softreset in");
  1463. /* Initialize the receive rings and buffers. */
  1464. sc->lmc_txfull = 0;
  1465. sc->lmc_next_rx = 0;
  1466. sc->lmc_next_tx = 0;
  1467. sc->lmc_taint_rx = 0;
  1468. sc->lmc_taint_tx = 0;
  1469. /*
  1470. * Setup each one of the receiver buffers
  1471. * allocate an skbuff for each one, setup the descriptor table
  1472. * and point each buffer at the next one
  1473. */
  1474. for (i = 0; i < LMC_RXDESCS; i++)
  1475. {
  1476. struct sk_buff *skb;
  1477. if (sc->lmc_rxq[i] == NULL)
  1478. {
  1479. skb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1480. if(skb == NULL){
  1481. printk(KERN_WARNING "%s: Failed to allocate receiver ring, will try again\n", sc->name);
  1482. sc->failed_ring = 1;
  1483. break;
  1484. }
  1485. else{
  1486. sc->lmc_rxq[i] = skb;
  1487. }
  1488. }
  1489. else
  1490. {
  1491. skb = sc->lmc_rxq[i];
  1492. }
  1493. skb->dev = sc->lmc_device;
  1494. /* owned by 21140 */
  1495. sc->lmc_rxring[i].status = 0x80000000;
  1496. /* used to be PKT_BUF_SZ now uses skb since we lose some to head room */
  1497. sc->lmc_rxring[i].length = skb_tailroom(skb);
  1498. /* use to be tail which is dumb since you're thinking why write
  1499. * to the end of the packj,et but since there's nothing there tail == data
  1500. */
  1501. sc->lmc_rxring[i].buffer1 = virt_to_bus (skb->data);
  1502. /* This is fair since the structure is static and we have the next address */
  1503. sc->lmc_rxring[i].buffer2 = virt_to_bus (&sc->lmc_rxring[i + 1]);
  1504. }
  1505. /*
  1506. * Sets end of ring
  1507. */
  1508. if (i != 0) {
  1509. sc->lmc_rxring[i - 1].length |= 0x02000000; /* Set end of buffers flag */
  1510. sc->lmc_rxring[i - 1].buffer2 = virt_to_bus(&sc->lmc_rxring[0]); /* Point back to the start */
  1511. }
  1512. LMC_CSR_WRITE (sc, csr_rxlist, virt_to_bus (sc->lmc_rxring)); /* write base address */
  1513. /* Initialize the transmit rings and buffers */
  1514. for (i = 0; i < LMC_TXDESCS; i++)
  1515. {
  1516. if (sc->lmc_txq[i] != NULL){ /* have buffer */
  1517. dev_kfree_skb(sc->lmc_txq[i]); /* free it */
  1518. sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */
  1519. }
  1520. sc->lmc_txq[i] = NULL;
  1521. sc->lmc_txring[i].status = 0x00000000;
  1522. sc->lmc_txring[i].buffer2 = virt_to_bus (&sc->lmc_txring[i + 1]);
  1523. }
  1524. sc->lmc_txring[i - 1].buffer2 = virt_to_bus (&sc->lmc_txring[0]);
  1525. LMC_CSR_WRITE (sc, csr_txlist, virt_to_bus (sc->lmc_txring));
  1526. lmc_trace(sc->lmc_device, "lmc_softreset out");
  1527. }
  1528. void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1529. {
  1530. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in");
  1531. sc->lmc_gpio_io &= ~bits;
  1532. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1533. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out");
  1534. }
  1535. void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1536. {
  1537. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in");
  1538. sc->lmc_gpio_io |= bits;
  1539. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1540. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out");
  1541. }
  1542. void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/
  1543. {
  1544. lmc_trace(sc->lmc_device, "lmc_led_on in");
  1545. if((~sc->lmc_miireg16) & led){ /* Already on! */
  1546. lmc_trace(sc->lmc_device, "lmc_led_on aon out");
  1547. return;
  1548. }
  1549. sc->lmc_miireg16 &= ~led;
  1550. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1551. lmc_trace(sc->lmc_device, "lmc_led_on out");
  1552. }
  1553. void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/
  1554. {
  1555. lmc_trace(sc->lmc_device, "lmc_led_off in");
  1556. if(sc->lmc_miireg16 & led){ /* Already set don't do anything */
  1557. lmc_trace(sc->lmc_device, "lmc_led_off aoff out");
  1558. return;
  1559. }
  1560. sc->lmc_miireg16 |= led;
  1561. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1562. lmc_trace(sc->lmc_device, "lmc_led_off out");
  1563. }
  1564. static void lmc_reset(lmc_softc_t * const sc) /*fold00*/
  1565. {
  1566. lmc_trace(sc->lmc_device, "lmc_reset in");
  1567. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  1568. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1569. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  1570. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1571. /*
  1572. * make some of the GPIO pins be outputs
  1573. */
  1574. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  1575. /*
  1576. * RESET low to force state reset. This also forces
  1577. * the transmitter clock to be internal, but we expect to reset
  1578. * that later anyway.
  1579. */
  1580. sc->lmc_gpio &= ~(LMC_GEP_RESET);
  1581. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  1582. /*
  1583. * hold for more than 10 microseconds
  1584. */
  1585. udelay(50);
  1586. /*
  1587. * stop driving Xilinx-related signals
  1588. */
  1589. lmc_gpio_mkinput(sc, LMC_GEP_RESET);
  1590. /*
  1591. * Call media specific init routine
  1592. */
  1593. sc->lmc_media->init(sc);
  1594. sc->extra_stats.resetCount++;
  1595. lmc_trace(sc->lmc_device, "lmc_reset out");
  1596. }
  1597. static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/
  1598. {
  1599. u32 val;
  1600. lmc_trace(sc->lmc_device, "lmc_dec_reset in");
  1601. /*
  1602. * disable all interrupts
  1603. */
  1604. sc->lmc_intrmask = 0;
  1605. LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
  1606. /*
  1607. * Reset the chip with a software reset command.
  1608. * Wait 10 microseconds (actually 50 PCI cycles but at
  1609. * 33MHz that comes to two microseconds but wait a
  1610. * bit longer anyways)
  1611. */
  1612. LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
  1613. udelay(25);
  1614. #ifdef __sparc__
  1615. sc->lmc_busmode = LMC_CSR_READ(sc, csr_busmode);
  1616. sc->lmc_busmode = 0x00100000;
  1617. sc->lmc_busmode &= ~TULIP_BUSMODE_SWRESET;
  1618. LMC_CSR_WRITE(sc, csr_busmode, sc->lmc_busmode);
  1619. #endif
  1620. sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
  1621. /*
  1622. * We want:
  1623. * no ethernet address in frames we write
  1624. * disable padding (txdesc, padding disable)
  1625. * ignore runt frames (rdes0 bit 15)
  1626. * no receiver watchdog or transmitter jabber timer
  1627. * (csr15 bit 0,14 == 1)
  1628. * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
  1629. */
  1630. sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
  1631. | TULIP_CMD_FULLDUPLEX
  1632. | TULIP_CMD_PASSBADPKT
  1633. | TULIP_CMD_NOHEARTBEAT
  1634. | TULIP_CMD_PORTSELECT
  1635. | TULIP_CMD_RECEIVEALL
  1636. | TULIP_CMD_MUSTBEONE
  1637. );
  1638. sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
  1639. | TULIP_CMD_THRESHOLDCTL
  1640. | TULIP_CMD_STOREFWD
  1641. | TULIP_CMD_TXTHRSHLDCTL
  1642. );
  1643. LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
  1644. /*
  1645. * disable receiver watchdog and transmit jabber
  1646. */
  1647. val = LMC_CSR_READ(sc, csr_sia_general);
  1648. val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
  1649. LMC_CSR_WRITE(sc, csr_sia_general, val);
  1650. lmc_trace(sc->lmc_device, "lmc_dec_reset out");
  1651. }
  1652. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/
  1653. size_t csr_size)
  1654. {
  1655. lmc_trace(sc->lmc_device, "lmc_initcsrs in");
  1656. sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
  1657. sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
  1658. sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
  1659. sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
  1660. sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
  1661. sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
  1662. sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
  1663. sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
  1664. sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
  1665. sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
  1666. sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
  1667. sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
  1668. sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
  1669. sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
  1670. sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
  1671. sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
  1672. lmc_trace(sc->lmc_device, "lmc_initcsrs out");
  1673. }
  1674. static void lmc_driver_timeout(struct net_device *dev, unsigned int txqueue)
  1675. {
  1676. lmc_softc_t *sc = dev_to_sc(dev);
  1677. u32 csr6;
  1678. unsigned long flags;
  1679. lmc_trace(dev, "lmc_driver_timeout in");
  1680. spin_lock_irqsave(&sc->lmc_lock, flags);
  1681. printk("%s: Xmitter busy|\n", dev->name);
  1682. sc->extra_stats.tx_tbusy_calls++;
  1683. if (jiffies - dev_trans_start(dev) < TX_TIMEOUT)
  1684. goto bug_out;
  1685. /*
  1686. * Chip seems to have locked up
  1687. * Reset it
  1688. * This whips out all our decriptor
  1689. * table and starts from scartch
  1690. */
  1691. LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO,
  1692. LMC_CSR_READ (sc, csr_status),
  1693. sc->extra_stats.tx_ProcTimeout);
  1694. lmc_running_reset (dev);
  1695. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1696. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1697. lmc_mii_readreg (sc, 0, 16),
  1698. lmc_mii_readreg (sc, 0, 17));
  1699. /* restart the tx processes */
  1700. csr6 = LMC_CSR_READ (sc, csr_command);
  1701. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x0002);
  1702. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x2002);
  1703. /* immediate transmit */
  1704. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1705. sc->lmc_device->stats.tx_errors++;
  1706. sc->extra_stats.tx_ProcTimeout++; /* -baz */
  1707. netif_trans_update(dev); /* prevent tx timeout */
  1708. bug_out:
  1709. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1710. lmc_trace(dev, "lmc_driver_timeout out");
  1711. }