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/drivers/net/ethernet/cadence/macb.c

http://github.com/mirrors/linux
C | 3115 lines | 2260 code | 565 blank | 290 comment | 341 complexity | a06fe750593b1d070c6e82a6f7303045 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. /*
  2. * Cadence MACB/GEM Ethernet Controller driver
  3. *
  4. * Copyright (C) 2004-2006 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11. #include <linux/clk.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/kernel.h>
  15. #include <linux/types.h>
  16. #include <linux/circ_buf.h>
  17. #include <linux/slab.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio.h>
  21. #include <linux/gpio/consumer.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/platform_data/macb.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/phy.h>
  29. #include <linux/of.h>
  30. #include <linux/of_device.h>
  31. #include <linux/of_gpio.h>
  32. #include <linux/of_mdio.h>
  33. #include <linux/of_net.h>
  34. #include "macb.h"
  35. #define MACB_RX_BUFFER_SIZE 128
  36. #define RX_BUFFER_MULTIPLE 64 /* bytes */
  37. #define RX_RING_SIZE 512 /* must be power of 2 */
  38. #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
  39. #define TX_RING_SIZE 128 /* must be power of 2 */
  40. #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
  41. /* level of occupied TX descriptors under which we wake up TX process */
  42. #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
  43. #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
  44. | MACB_BIT(ISR_ROVR))
  45. #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
  46. | MACB_BIT(ISR_RLE) \
  47. | MACB_BIT(TXERR))
  48. #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
  49. #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
  50. #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
  51. #define GEM_MTU_MIN_SIZE 68
  52. #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
  53. #define MACB_WOL_ENABLED (0x1 << 1)
  54. /* Graceful stop timeouts in us. We should allow up to
  55. * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
  56. */
  57. #define MACB_HALT_TIMEOUT 1230
  58. /* Ring buffer accessors */
  59. static unsigned int macb_tx_ring_wrap(unsigned int index)
  60. {
  61. return index & (TX_RING_SIZE - 1);
  62. }
  63. static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
  64. unsigned int index)
  65. {
  66. return &queue->tx_ring[macb_tx_ring_wrap(index)];
  67. }
  68. static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
  69. unsigned int index)
  70. {
  71. return &queue->tx_skb[macb_tx_ring_wrap(index)];
  72. }
  73. static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
  74. {
  75. dma_addr_t offset;
  76. offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
  77. return queue->tx_ring_dma + offset;
  78. }
  79. static unsigned int macb_rx_ring_wrap(unsigned int index)
  80. {
  81. return index & (RX_RING_SIZE - 1);
  82. }
  83. static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
  84. {
  85. return &bp->rx_ring[macb_rx_ring_wrap(index)];
  86. }
  87. static void *macb_rx_buffer(struct macb *bp, unsigned int index)
  88. {
  89. return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
  90. }
  91. /* I/O accessors */
  92. static u32 hw_readl_native(struct macb *bp, int offset)
  93. {
  94. return __raw_readl(bp->regs + offset);
  95. }
  96. static void hw_writel_native(struct macb *bp, int offset, u32 value)
  97. {
  98. __raw_writel(value, bp->regs + offset);
  99. }
  100. static u32 hw_readl(struct macb *bp, int offset)
  101. {
  102. return readl_relaxed(bp->regs + offset);
  103. }
  104. static void hw_writel(struct macb *bp, int offset, u32 value)
  105. {
  106. writel_relaxed(value, bp->regs + offset);
  107. }
  108. /* Find the CPU endianness by using the loopback bit of NCR register. When the
  109. * CPU is in big endian we need to program swapped mode for management
  110. * descriptor access.
  111. */
  112. static bool hw_is_native_io(void __iomem *addr)
  113. {
  114. u32 value = MACB_BIT(LLB);
  115. __raw_writel(value, addr + MACB_NCR);
  116. value = __raw_readl(addr + MACB_NCR);
  117. /* Write 0 back to disable everything */
  118. __raw_writel(0, addr + MACB_NCR);
  119. return value == MACB_BIT(LLB);
  120. }
  121. static bool hw_is_gem(void __iomem *addr, bool native_io)
  122. {
  123. u32 id;
  124. if (native_io)
  125. id = __raw_readl(addr + MACB_MID);
  126. else
  127. id = readl_relaxed(addr + MACB_MID);
  128. return MACB_BFEXT(IDNUM, id) >= 0x2;
  129. }
  130. static void macb_set_hwaddr(struct macb *bp)
  131. {
  132. u32 bottom;
  133. u16 top;
  134. bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
  135. macb_or_gem_writel(bp, SA1B, bottom);
  136. top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
  137. macb_or_gem_writel(bp, SA1T, top);
  138. /* Clear unused address register sets */
  139. macb_or_gem_writel(bp, SA2B, 0);
  140. macb_or_gem_writel(bp, SA2T, 0);
  141. macb_or_gem_writel(bp, SA3B, 0);
  142. macb_or_gem_writel(bp, SA3T, 0);
  143. macb_or_gem_writel(bp, SA4B, 0);
  144. macb_or_gem_writel(bp, SA4T, 0);
  145. }
  146. static void macb_get_hwaddr(struct macb *bp)
  147. {
  148. struct macb_platform_data *pdata;
  149. u32 bottom;
  150. u16 top;
  151. u8 addr[6];
  152. int i;
  153. pdata = dev_get_platdata(&bp->pdev->dev);
  154. /* Check all 4 address register for valid address */
  155. for (i = 0; i < 4; i++) {
  156. bottom = macb_or_gem_readl(bp, SA1B + i * 8);
  157. top = macb_or_gem_readl(bp, SA1T + i * 8);
  158. if (pdata && pdata->rev_eth_addr) {
  159. addr[5] = bottom & 0xff;
  160. addr[4] = (bottom >> 8) & 0xff;
  161. addr[3] = (bottom >> 16) & 0xff;
  162. addr[2] = (bottom >> 24) & 0xff;
  163. addr[1] = top & 0xff;
  164. addr[0] = (top & 0xff00) >> 8;
  165. } else {
  166. addr[0] = bottom & 0xff;
  167. addr[1] = (bottom >> 8) & 0xff;
  168. addr[2] = (bottom >> 16) & 0xff;
  169. addr[3] = (bottom >> 24) & 0xff;
  170. addr[4] = top & 0xff;
  171. addr[5] = (top >> 8) & 0xff;
  172. }
  173. if (is_valid_ether_addr(addr)) {
  174. memcpy(bp->dev->dev_addr, addr, sizeof(addr));
  175. return;
  176. }
  177. }
  178. dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
  179. eth_hw_addr_random(bp->dev);
  180. }
  181. static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  182. {
  183. struct macb *bp = bus->priv;
  184. int value;
  185. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  186. | MACB_BF(RW, MACB_MAN_READ)
  187. | MACB_BF(PHYA, mii_id)
  188. | MACB_BF(REGA, regnum)
  189. | MACB_BF(CODE, MACB_MAN_CODE)));
  190. /* wait for end of transfer */
  191. while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
  192. cpu_relax();
  193. value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
  194. return value;
  195. }
  196. static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  197. u16 value)
  198. {
  199. struct macb *bp = bus->priv;
  200. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  201. | MACB_BF(RW, MACB_MAN_WRITE)
  202. | MACB_BF(PHYA, mii_id)
  203. | MACB_BF(REGA, regnum)
  204. | MACB_BF(CODE, MACB_MAN_CODE)
  205. | MACB_BF(DATA, value)));
  206. /* wait for end of transfer */
  207. while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
  208. cpu_relax();
  209. return 0;
  210. }
  211. /**
  212. * macb_set_tx_clk() - Set a clock to a new frequency
  213. * @clk Pointer to the clock to change
  214. * @rate New frequency in Hz
  215. * @dev Pointer to the struct net_device
  216. */
  217. static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
  218. {
  219. long ferr, rate, rate_rounded;
  220. if (!clk)
  221. return;
  222. switch (speed) {
  223. case SPEED_10:
  224. rate = 2500000;
  225. break;
  226. case SPEED_100:
  227. rate = 25000000;
  228. break;
  229. case SPEED_1000:
  230. rate = 125000000;
  231. break;
  232. default:
  233. return;
  234. }
  235. rate_rounded = clk_round_rate(clk, rate);
  236. if (rate_rounded < 0)
  237. return;
  238. /* RGMII allows 50 ppm frequency error. Test and warn if this limit
  239. * is not satisfied.
  240. */
  241. ferr = abs(rate_rounded - rate);
  242. ferr = DIV_ROUND_UP(ferr, rate / 100000);
  243. if (ferr > 5)
  244. netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
  245. rate);
  246. if (clk_set_rate(clk, rate_rounded))
  247. netdev_err(dev, "adjusting tx_clk failed.\n");
  248. }
  249. static void macb_handle_link_change(struct net_device *dev)
  250. {
  251. struct macb *bp = netdev_priv(dev);
  252. struct phy_device *phydev = dev->phydev;
  253. unsigned long flags;
  254. int status_change = 0;
  255. spin_lock_irqsave(&bp->lock, flags);
  256. if (phydev->link) {
  257. if ((bp->speed != phydev->speed) ||
  258. (bp->duplex != phydev->duplex)) {
  259. u32 reg;
  260. reg = macb_readl(bp, NCFGR);
  261. reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  262. if (macb_is_gem(bp))
  263. reg &= ~GEM_BIT(GBE);
  264. if (phydev->duplex)
  265. reg |= MACB_BIT(FD);
  266. if (phydev->speed == SPEED_100)
  267. reg |= MACB_BIT(SPD);
  268. if (phydev->speed == SPEED_1000 &&
  269. bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
  270. reg |= GEM_BIT(GBE);
  271. macb_or_gem_writel(bp, NCFGR, reg);
  272. bp->speed = phydev->speed;
  273. bp->duplex = phydev->duplex;
  274. status_change = 1;
  275. }
  276. }
  277. if (phydev->link != bp->link) {
  278. if (!phydev->link) {
  279. bp->speed = 0;
  280. bp->duplex = -1;
  281. }
  282. bp->link = phydev->link;
  283. status_change = 1;
  284. }
  285. spin_unlock_irqrestore(&bp->lock, flags);
  286. if (status_change) {
  287. if (phydev->link) {
  288. /* Update the TX clock rate if and only if the link is
  289. * up and there has been a link change.
  290. */
  291. macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
  292. netif_carrier_on(dev);
  293. netdev_info(dev, "link up (%d/%s)\n",
  294. phydev->speed,
  295. phydev->duplex == DUPLEX_FULL ?
  296. "Full" : "Half");
  297. } else {
  298. netif_carrier_off(dev);
  299. netdev_info(dev, "link down\n");
  300. }
  301. }
  302. }
  303. /* based on au1000_eth. c*/
  304. static int macb_mii_probe(struct net_device *dev)
  305. {
  306. struct macb *bp = netdev_priv(dev);
  307. struct macb_platform_data *pdata;
  308. struct phy_device *phydev;
  309. int phy_irq;
  310. int ret;
  311. phydev = phy_find_first(bp->mii_bus);
  312. if (!phydev) {
  313. netdev_err(dev, "no PHY found\n");
  314. return -ENXIO;
  315. }
  316. pdata = dev_get_platdata(&bp->pdev->dev);
  317. if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
  318. ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin,
  319. "phy int");
  320. if (!ret) {
  321. phy_irq = gpio_to_irq(pdata->phy_irq_pin);
  322. phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
  323. }
  324. }
  325. /* attach the mac to the phy */
  326. ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
  327. bp->phy_interface);
  328. if (ret) {
  329. netdev_err(dev, "Could not attach to PHY\n");
  330. return ret;
  331. }
  332. /* mask with MAC supported features */
  333. if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
  334. phydev->supported &= PHY_GBIT_FEATURES;
  335. else
  336. phydev->supported &= PHY_BASIC_FEATURES;
  337. if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
  338. phydev->supported &= ~SUPPORTED_1000baseT_Half;
  339. phydev->advertising = phydev->supported;
  340. bp->link = 0;
  341. bp->speed = 0;
  342. bp->duplex = -1;
  343. return 0;
  344. }
  345. static int macb_mii_init(struct macb *bp)
  346. {
  347. struct macb_platform_data *pdata;
  348. struct device_node *np;
  349. int err = -ENXIO, i;
  350. /* Enable management port */
  351. macb_writel(bp, NCR, MACB_BIT(MPE));
  352. bp->mii_bus = mdiobus_alloc();
  353. if (!bp->mii_bus) {
  354. err = -ENOMEM;
  355. goto err_out;
  356. }
  357. bp->mii_bus->name = "MACB_mii_bus";
  358. bp->mii_bus->read = &macb_mdio_read;
  359. bp->mii_bus->write = &macb_mdio_write;
  360. snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  361. bp->pdev->name, bp->pdev->id);
  362. bp->mii_bus->priv = bp;
  363. bp->mii_bus->parent = &bp->pdev->dev;
  364. pdata = dev_get_platdata(&bp->pdev->dev);
  365. dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
  366. np = bp->pdev->dev.of_node;
  367. if (np) {
  368. /* try dt phy registration */
  369. err = of_mdiobus_register(bp->mii_bus, np);
  370. /* fallback to standard phy registration if no phy were
  371. * found during dt phy registration
  372. */
  373. if (!err && !phy_find_first(bp->mii_bus)) {
  374. for (i = 0; i < PHY_MAX_ADDR; i++) {
  375. struct phy_device *phydev;
  376. phydev = mdiobus_scan(bp->mii_bus, i);
  377. if (IS_ERR(phydev) &&
  378. PTR_ERR(phydev) != -ENODEV) {
  379. err = PTR_ERR(phydev);
  380. break;
  381. }
  382. }
  383. if (err)
  384. goto err_out_unregister_bus;
  385. }
  386. } else {
  387. if (pdata)
  388. bp->mii_bus->phy_mask = pdata->phy_mask;
  389. err = mdiobus_register(bp->mii_bus);
  390. }
  391. if (err)
  392. goto err_out_free_mdiobus;
  393. err = macb_mii_probe(bp->dev);
  394. if (err)
  395. goto err_out_unregister_bus;
  396. return 0;
  397. err_out_unregister_bus:
  398. mdiobus_unregister(bp->mii_bus);
  399. err_out_free_mdiobus:
  400. mdiobus_free(bp->mii_bus);
  401. err_out:
  402. return err;
  403. }
  404. static void macb_update_stats(struct macb *bp)
  405. {
  406. u32 *p = &bp->hw_stats.macb.rx_pause_frames;
  407. u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
  408. int offset = MACB_PFR;
  409. WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
  410. for (; p < end; p++, offset += 4)
  411. *p += bp->macb_reg_readl(bp, offset);
  412. }
  413. static int macb_halt_tx(struct macb *bp)
  414. {
  415. unsigned long halt_time, timeout;
  416. u32 status;
  417. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
  418. timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
  419. do {
  420. halt_time = jiffies;
  421. status = macb_readl(bp, TSR);
  422. if (!(status & MACB_BIT(TGO)))
  423. return 0;
  424. usleep_range(10, 250);
  425. } while (time_before(halt_time, timeout));
  426. return -ETIMEDOUT;
  427. }
  428. static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
  429. {
  430. if (tx_skb->mapping) {
  431. if (tx_skb->mapped_as_page)
  432. dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
  433. tx_skb->size, DMA_TO_DEVICE);
  434. else
  435. dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
  436. tx_skb->size, DMA_TO_DEVICE);
  437. tx_skb->mapping = 0;
  438. }
  439. if (tx_skb->skb) {
  440. dev_kfree_skb_any(tx_skb->skb);
  441. tx_skb->skb = NULL;
  442. }
  443. }
  444. static void macb_tx_error_task(struct work_struct *work)
  445. {
  446. struct macb_queue *queue = container_of(work, struct macb_queue,
  447. tx_error_task);
  448. struct macb *bp = queue->bp;
  449. struct macb_tx_skb *tx_skb;
  450. struct macb_dma_desc *desc;
  451. struct sk_buff *skb;
  452. unsigned int tail;
  453. unsigned long flags;
  454. netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
  455. (unsigned int)(queue - bp->queues),
  456. queue->tx_tail, queue->tx_head);
  457. /* Prevent the queue IRQ handlers from running: each of them may call
  458. * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
  459. * As explained below, we have to halt the transmission before updating
  460. * TBQP registers so we call netif_tx_stop_all_queues() to notify the
  461. * network engine about the macb/gem being halted.
  462. */
  463. spin_lock_irqsave(&bp->lock, flags);
  464. /* Make sure nobody is trying to queue up new packets */
  465. netif_tx_stop_all_queues(bp->dev);
  466. /* Stop transmission now
  467. * (in case we have just queued new packets)
  468. * macb/gem must be halted to write TBQP register
  469. */
  470. if (macb_halt_tx(bp))
  471. /* Just complain for now, reinitializing TX path can be good */
  472. netdev_err(bp->dev, "BUG: halt tx timed out\n");
  473. /* Treat frames in TX queue including the ones that caused the error.
  474. * Free transmit buffers in upper layer.
  475. */
  476. for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
  477. u32 ctrl;
  478. desc = macb_tx_desc(queue, tail);
  479. ctrl = desc->ctrl;
  480. tx_skb = macb_tx_skb(queue, tail);
  481. skb = tx_skb->skb;
  482. if (ctrl & MACB_BIT(TX_USED)) {
  483. /* skb is set for the last buffer of the frame */
  484. while (!skb) {
  485. macb_tx_unmap(bp, tx_skb);
  486. tail++;
  487. tx_skb = macb_tx_skb(queue, tail);
  488. skb = tx_skb->skb;
  489. }
  490. /* ctrl still refers to the first buffer descriptor
  491. * since it's the only one written back by the hardware
  492. */
  493. if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
  494. netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
  495. macb_tx_ring_wrap(tail), skb->data);
  496. bp->stats.tx_packets++;
  497. bp->stats.tx_bytes += skb->len;
  498. }
  499. } else {
  500. /* "Buffers exhausted mid-frame" errors may only happen
  501. * if the driver is buggy, so complain loudly about
  502. * those. Statistics are updated by hardware.
  503. */
  504. if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
  505. netdev_err(bp->dev,
  506. "BUG: TX buffers exhausted mid-frame\n");
  507. desc->ctrl = ctrl | MACB_BIT(TX_USED);
  508. }
  509. macb_tx_unmap(bp, tx_skb);
  510. }
  511. /* Set end of TX queue */
  512. desc = macb_tx_desc(queue, 0);
  513. desc->addr = 0;
  514. desc->ctrl = MACB_BIT(TX_USED);
  515. /* Make descriptor updates visible to hardware */
  516. wmb();
  517. /* Reinitialize the TX desc queue */
  518. queue_writel(queue, TBQP, queue->tx_ring_dma);
  519. /* Make TX ring reflect state of hardware */
  520. queue->tx_head = 0;
  521. queue->tx_tail = 0;
  522. /* Housework before enabling TX IRQ */
  523. macb_writel(bp, TSR, macb_readl(bp, TSR));
  524. queue_writel(queue, IER, MACB_TX_INT_FLAGS);
  525. /* Now we are ready to start transmission again */
  526. netif_tx_start_all_queues(bp->dev);
  527. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  528. spin_unlock_irqrestore(&bp->lock, flags);
  529. }
  530. static void macb_tx_interrupt(struct macb_queue *queue)
  531. {
  532. unsigned int tail;
  533. unsigned int head;
  534. u32 status;
  535. struct macb *bp = queue->bp;
  536. u16 queue_index = queue - bp->queues;
  537. status = macb_readl(bp, TSR);
  538. macb_writel(bp, TSR, status);
  539. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  540. queue_writel(queue, ISR, MACB_BIT(TCOMP));
  541. netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
  542. (unsigned long)status);
  543. head = queue->tx_head;
  544. for (tail = queue->tx_tail; tail != head; tail++) {
  545. struct macb_tx_skb *tx_skb;
  546. struct sk_buff *skb;
  547. struct macb_dma_desc *desc;
  548. u32 ctrl;
  549. desc = macb_tx_desc(queue, tail);
  550. /* Make hw descriptor updates visible to CPU */
  551. rmb();
  552. ctrl = desc->ctrl;
  553. /* TX_USED bit is only set by hardware on the very first buffer
  554. * descriptor of the transmitted frame.
  555. */
  556. if (!(ctrl & MACB_BIT(TX_USED)))
  557. break;
  558. /* Process all buffers of the current transmitted frame */
  559. for (;; tail++) {
  560. tx_skb = macb_tx_skb(queue, tail);
  561. skb = tx_skb->skb;
  562. /* First, update TX stats if needed */
  563. if (skb) {
  564. netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
  565. macb_tx_ring_wrap(tail), skb->data);
  566. bp->stats.tx_packets++;
  567. bp->stats.tx_bytes += skb->len;
  568. }
  569. /* Now we can safely release resources */
  570. macb_tx_unmap(bp, tx_skb);
  571. /* skb is set only for the last buffer of the frame.
  572. * WARNING: at this point skb has been freed by
  573. * macb_tx_unmap().
  574. */
  575. if (skb)
  576. break;
  577. }
  578. }
  579. queue->tx_tail = tail;
  580. if (__netif_subqueue_stopped(bp->dev, queue_index) &&
  581. CIRC_CNT(queue->tx_head, queue->tx_tail,
  582. TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
  583. netif_wake_subqueue(bp->dev, queue_index);
  584. }
  585. static void gem_rx_refill(struct macb *bp)
  586. {
  587. unsigned int entry;
  588. struct sk_buff *skb;
  589. dma_addr_t paddr;
  590. while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,
  591. RX_RING_SIZE) > 0) {
  592. entry = macb_rx_ring_wrap(bp->rx_prepared_head);
  593. /* Make hw descriptor updates visible to CPU */
  594. rmb();
  595. bp->rx_prepared_head++;
  596. if (!bp->rx_skbuff[entry]) {
  597. /* allocate sk_buff for this free entry in ring */
  598. skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
  599. if (unlikely(!skb)) {
  600. netdev_err(bp->dev,
  601. "Unable to allocate sk_buff\n");
  602. break;
  603. }
  604. /* now fill corresponding descriptor entry */
  605. paddr = dma_map_single(&bp->pdev->dev, skb->data,
  606. bp->rx_buffer_size,
  607. DMA_FROM_DEVICE);
  608. if (dma_mapping_error(&bp->pdev->dev, paddr)) {
  609. dev_kfree_skb(skb);
  610. break;
  611. }
  612. bp->rx_skbuff[entry] = skb;
  613. if (entry == RX_RING_SIZE - 1)
  614. paddr |= MACB_BIT(RX_WRAP);
  615. bp->rx_ring[entry].addr = paddr;
  616. bp->rx_ring[entry].ctrl = 0;
  617. /* properly align Ethernet header */
  618. skb_reserve(skb, NET_IP_ALIGN);
  619. } else {
  620. bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
  621. bp->rx_ring[entry].ctrl = 0;
  622. }
  623. }
  624. /* Make descriptor updates visible to hardware */
  625. wmb();
  626. netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
  627. bp->rx_prepared_head, bp->rx_tail);
  628. }
  629. /* Mark DMA descriptors from begin up to and not including end as unused */
  630. static void discard_partial_frame(struct macb *bp, unsigned int begin,
  631. unsigned int end)
  632. {
  633. unsigned int frag;
  634. for (frag = begin; frag != end; frag++) {
  635. struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
  636. desc->addr &= ~MACB_BIT(RX_USED);
  637. }
  638. /* Make descriptor updates visible to hardware */
  639. wmb();
  640. /* When this happens, the hardware stats registers for
  641. * whatever caused this is updated, so we don't have to record
  642. * anything.
  643. */
  644. }
  645. static int gem_rx(struct macb *bp, int budget)
  646. {
  647. unsigned int len;
  648. unsigned int entry;
  649. struct sk_buff *skb;
  650. struct macb_dma_desc *desc;
  651. int count = 0;
  652. while (count < budget) {
  653. u32 addr, ctrl;
  654. entry = macb_rx_ring_wrap(bp->rx_tail);
  655. desc = &bp->rx_ring[entry];
  656. /* Make hw descriptor updates visible to CPU */
  657. rmb();
  658. addr = desc->addr;
  659. ctrl = desc->ctrl;
  660. if (!(addr & MACB_BIT(RX_USED)))
  661. break;
  662. bp->rx_tail++;
  663. count++;
  664. if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
  665. netdev_err(bp->dev,
  666. "not whole frame pointed by descriptor\n");
  667. bp->stats.rx_dropped++;
  668. break;
  669. }
  670. skb = bp->rx_skbuff[entry];
  671. if (unlikely(!skb)) {
  672. netdev_err(bp->dev,
  673. "inconsistent Rx descriptor chain\n");
  674. bp->stats.rx_dropped++;
  675. break;
  676. }
  677. /* now everything is ready for receiving packet */
  678. bp->rx_skbuff[entry] = NULL;
  679. len = ctrl & bp->rx_frm_len_mask;
  680. netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
  681. skb_put(skb, len);
  682. addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
  683. dma_unmap_single(&bp->pdev->dev, addr,
  684. bp->rx_buffer_size, DMA_FROM_DEVICE);
  685. skb->protocol = eth_type_trans(skb, bp->dev);
  686. skb_checksum_none_assert(skb);
  687. if (bp->dev->features & NETIF_F_RXCSUM &&
  688. !(bp->dev->flags & IFF_PROMISC) &&
  689. GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
  690. skb->ip_summed = CHECKSUM_UNNECESSARY;
  691. bp->stats.rx_packets++;
  692. bp->stats.rx_bytes += skb->len;
  693. #if defined(DEBUG) && defined(VERBOSE_DEBUG)
  694. netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
  695. skb->len, skb->csum);
  696. print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
  697. skb_mac_header(skb), 16, true);
  698. print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
  699. skb->data, 32, true);
  700. #endif
  701. netif_receive_skb(skb);
  702. }
  703. gem_rx_refill(bp);
  704. return count;
  705. }
  706. static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
  707. unsigned int last_frag)
  708. {
  709. unsigned int len;
  710. unsigned int frag;
  711. unsigned int offset;
  712. struct sk_buff *skb;
  713. struct macb_dma_desc *desc;
  714. desc = macb_rx_desc(bp, last_frag);
  715. len = desc->ctrl & bp->rx_frm_len_mask;
  716. netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
  717. macb_rx_ring_wrap(first_frag),
  718. macb_rx_ring_wrap(last_frag), len);
  719. /* The ethernet header starts NET_IP_ALIGN bytes into the
  720. * first buffer. Since the header is 14 bytes, this makes the
  721. * payload word-aligned.
  722. *
  723. * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
  724. * the two padding bytes into the skb so that we avoid hitting
  725. * the slowpath in memcpy(), and pull them off afterwards.
  726. */
  727. skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
  728. if (!skb) {
  729. bp->stats.rx_dropped++;
  730. for (frag = first_frag; ; frag++) {
  731. desc = macb_rx_desc(bp, frag);
  732. desc->addr &= ~MACB_BIT(RX_USED);
  733. if (frag == last_frag)
  734. break;
  735. }
  736. /* Make descriptor updates visible to hardware */
  737. wmb();
  738. return 1;
  739. }
  740. offset = 0;
  741. len += NET_IP_ALIGN;
  742. skb_checksum_none_assert(skb);
  743. skb_put(skb, len);
  744. for (frag = first_frag; ; frag++) {
  745. unsigned int frag_len = bp->rx_buffer_size;
  746. if (offset + frag_len > len) {
  747. if (unlikely(frag != last_frag)) {
  748. dev_kfree_skb_any(skb);
  749. return -1;
  750. }
  751. frag_len = len - offset;
  752. }
  753. skb_copy_to_linear_data_offset(skb, offset,
  754. macb_rx_buffer(bp, frag),
  755. frag_len);
  756. offset += bp->rx_buffer_size;
  757. desc = macb_rx_desc(bp, frag);
  758. desc->addr &= ~MACB_BIT(RX_USED);
  759. if (frag == last_frag)
  760. break;
  761. }
  762. /* Make descriptor updates visible to hardware */
  763. wmb();
  764. __skb_pull(skb, NET_IP_ALIGN);
  765. skb->protocol = eth_type_trans(skb, bp->dev);
  766. bp->stats.rx_packets++;
  767. bp->stats.rx_bytes += skb->len;
  768. netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
  769. skb->len, skb->csum);
  770. netif_receive_skb(skb);
  771. return 0;
  772. }
  773. static inline void macb_init_rx_ring(struct macb *bp)
  774. {
  775. dma_addr_t addr;
  776. int i;
  777. addr = bp->rx_buffers_dma;
  778. for (i = 0; i < RX_RING_SIZE; i++) {
  779. bp->rx_ring[i].addr = addr;
  780. bp->rx_ring[i].ctrl = 0;
  781. addr += bp->rx_buffer_size;
  782. }
  783. bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
  784. }
  785. static int macb_rx(struct macb *bp, int budget)
  786. {
  787. bool reset_rx_queue = false;
  788. int received = 0;
  789. unsigned int tail;
  790. int first_frag = -1;
  791. for (tail = bp->rx_tail; budget > 0; tail++) {
  792. struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
  793. u32 addr, ctrl;
  794. /* Make hw descriptor updates visible to CPU */
  795. rmb();
  796. addr = desc->addr;
  797. ctrl = desc->ctrl;
  798. if (!(addr & MACB_BIT(RX_USED)))
  799. break;
  800. if (ctrl & MACB_BIT(RX_SOF)) {
  801. if (first_frag != -1)
  802. discard_partial_frame(bp, first_frag, tail);
  803. first_frag = tail;
  804. }
  805. if (ctrl & MACB_BIT(RX_EOF)) {
  806. int dropped;
  807. if (unlikely(first_frag == -1)) {
  808. reset_rx_queue = true;
  809. continue;
  810. }
  811. dropped = macb_rx_frame(bp, first_frag, tail);
  812. first_frag = -1;
  813. if (unlikely(dropped < 0)) {
  814. reset_rx_queue = true;
  815. continue;
  816. }
  817. if (!dropped) {
  818. received++;
  819. budget--;
  820. }
  821. }
  822. }
  823. if (unlikely(reset_rx_queue)) {
  824. unsigned long flags;
  825. u32 ctrl;
  826. netdev_err(bp->dev, "RX queue corruption: reset it\n");
  827. spin_lock_irqsave(&bp->lock, flags);
  828. ctrl = macb_readl(bp, NCR);
  829. macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
  830. macb_init_rx_ring(bp);
  831. macb_writel(bp, RBQP, bp->rx_ring_dma);
  832. macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
  833. spin_unlock_irqrestore(&bp->lock, flags);
  834. return received;
  835. }
  836. if (first_frag != -1)
  837. bp->rx_tail = first_frag;
  838. else
  839. bp->rx_tail = tail;
  840. return received;
  841. }
  842. static int macb_poll(struct napi_struct *napi, int budget)
  843. {
  844. struct macb *bp = container_of(napi, struct macb, napi);
  845. int work_done;
  846. u32 status;
  847. status = macb_readl(bp, RSR);
  848. macb_writel(bp, RSR, status);
  849. work_done = 0;
  850. netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
  851. (unsigned long)status, budget);
  852. work_done = bp->macbgem_ops.mog_rx(bp, budget);
  853. if (work_done < budget) {
  854. napi_complete(napi);
  855. /* Packets received while interrupts were disabled */
  856. status = macb_readl(bp, RSR);
  857. if (status) {
  858. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  859. macb_writel(bp, ISR, MACB_BIT(RCOMP));
  860. napi_reschedule(napi);
  861. } else {
  862. macb_writel(bp, IER, MACB_RX_INT_FLAGS);
  863. }
  864. }
  865. /* TODO: Handle errors */
  866. return work_done;
  867. }
  868. static irqreturn_t macb_interrupt(int irq, void *dev_id)
  869. {
  870. struct macb_queue *queue = dev_id;
  871. struct macb *bp = queue->bp;
  872. struct net_device *dev = bp->dev;
  873. u32 status, ctrl;
  874. status = queue_readl(queue, ISR);
  875. if (unlikely(!status))
  876. return IRQ_NONE;
  877. spin_lock(&bp->lock);
  878. while (status) {
  879. /* close possible race with dev_close */
  880. if (unlikely(!netif_running(dev))) {
  881. queue_writel(queue, IDR, -1);
  882. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  883. queue_writel(queue, ISR, -1);
  884. break;
  885. }
  886. netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
  887. (unsigned int)(queue - bp->queues),
  888. (unsigned long)status);
  889. if (status & MACB_RX_INT_FLAGS) {
  890. /* There's no point taking any more interrupts
  891. * until we have processed the buffers. The
  892. * scheduling call may fail if the poll routine
  893. * is already scheduled, so disable interrupts
  894. * now.
  895. */
  896. queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
  897. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  898. queue_writel(queue, ISR, MACB_BIT(RCOMP));
  899. if (napi_schedule_prep(&bp->napi)) {
  900. netdev_vdbg(bp->dev, "scheduling RX softirq\n");
  901. __napi_schedule(&bp->napi);
  902. }
  903. }
  904. if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
  905. queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
  906. schedule_work(&queue->tx_error_task);
  907. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  908. queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
  909. break;
  910. }
  911. if (status & MACB_BIT(TCOMP))
  912. macb_tx_interrupt(queue);
  913. /* Link change detection isn't possible with RMII, so we'll
  914. * add that if/when we get our hands on a full-blown MII PHY.
  915. */
  916. /* There is a hardware issue under heavy load where DMA can
  917. * stop, this causes endless "used buffer descriptor read"
  918. * interrupts but it can be cleared by re-enabling RX. See
  919. * the at91 manual, section 41.3.1 or the Zynq manual
  920. * section 16.7.4 for details.
  921. */
  922. if (status & MACB_BIT(RXUBR)) {
  923. ctrl = macb_readl(bp, NCR);
  924. macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
  925. macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
  926. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  927. queue_writel(queue, ISR, MACB_BIT(RXUBR));
  928. }
  929. if (status & MACB_BIT(ISR_ROVR)) {
  930. /* We missed at least one packet */
  931. if (macb_is_gem(bp))
  932. bp->hw_stats.gem.rx_overruns++;
  933. else
  934. bp->hw_stats.macb.rx_overruns++;
  935. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  936. queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
  937. }
  938. if (status & MACB_BIT(HRESP)) {
  939. /* TODO: Reset the hardware, and maybe move the
  940. * netdev_err to a lower-priority context as well
  941. * (work queue?)
  942. */
  943. netdev_err(dev, "DMA bus error: HRESP not OK\n");
  944. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  945. queue_writel(queue, ISR, MACB_BIT(HRESP));
  946. }
  947. status = queue_readl(queue, ISR);
  948. }
  949. spin_unlock(&bp->lock);
  950. return IRQ_HANDLED;
  951. }
  952. #ifdef CONFIG_NET_POLL_CONTROLLER
  953. /* Polling receive - used by netconsole and other diagnostic tools
  954. * to allow network i/o with interrupts disabled.
  955. */
  956. static void macb_poll_controller(struct net_device *dev)
  957. {
  958. struct macb *bp = netdev_priv(dev);
  959. struct macb_queue *queue;
  960. unsigned long flags;
  961. unsigned int q;
  962. local_irq_save(flags);
  963. for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
  964. macb_interrupt(dev->irq, queue);
  965. local_irq_restore(flags);
  966. }
  967. #endif
  968. static unsigned int macb_tx_map(struct macb *bp,
  969. struct macb_queue *queue,
  970. struct sk_buff *skb)
  971. {
  972. dma_addr_t mapping;
  973. unsigned int len, entry, i, tx_head = queue->tx_head;
  974. struct macb_tx_skb *tx_skb = NULL;
  975. struct macb_dma_desc *desc;
  976. unsigned int offset, size, count = 0;
  977. unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
  978. unsigned int eof = 1;
  979. u32 ctrl;
  980. /* First, map non-paged data */
  981. len = skb_headlen(skb);
  982. offset = 0;
  983. while (len) {
  984. size = min(len, bp->max_tx_length);
  985. entry = macb_tx_ring_wrap(tx_head);
  986. tx_skb = &queue->tx_skb[entry];
  987. mapping = dma_map_single(&bp->pdev->dev,
  988. skb->data + offset,
  989. size, DMA_TO_DEVICE);
  990. if (dma_mapping_error(&bp->pdev->dev, mapping))
  991. goto dma_error;
  992. /* Save info to properly release resources */
  993. tx_skb->skb = NULL;
  994. tx_skb->mapping = mapping;
  995. tx_skb->size = size;
  996. tx_skb->mapped_as_page = false;
  997. len -= size;
  998. offset += size;
  999. count++;
  1000. tx_head++;
  1001. }
  1002. /* Then, map paged data from fragments */
  1003. for (f = 0; f < nr_frags; f++) {
  1004. const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
  1005. len = skb_frag_size(frag);
  1006. offset = 0;
  1007. while (len) {
  1008. size = min(len, bp->max_tx_length);
  1009. entry = macb_tx_ring_wrap(tx_head);
  1010. tx_skb = &queue->tx_skb[entry];
  1011. mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
  1012. offset, size, DMA_TO_DEVICE);
  1013. if (dma_mapping_error(&bp->pdev->dev, mapping))
  1014. goto dma_error;
  1015. /* Save info to properly release resources */
  1016. tx_skb->skb = NULL;
  1017. tx_skb->mapping = mapping;
  1018. tx_skb->size = size;
  1019. tx_skb->mapped_as_page = true;
  1020. len -= size;
  1021. offset += size;
  1022. count++;
  1023. tx_head++;
  1024. }
  1025. }
  1026. /* Should never happen */
  1027. if (unlikely(!tx_skb)) {
  1028. netdev_err(bp->dev, "BUG! empty skb!\n");
  1029. return 0;
  1030. }
  1031. /* This is the last buffer of the frame: save socket buffer */
  1032. tx_skb->skb = skb;
  1033. /* Update TX ring: update buffer descriptors in reverse order
  1034. * to avoid race condition
  1035. */
  1036. /* Set 'TX_USED' bit in buffer descriptor at tx_head position
  1037. * to set the end of TX queue
  1038. */
  1039. i = tx_head;
  1040. entry = macb_tx_ring_wrap(i);
  1041. ctrl = MACB_BIT(TX_USED);
  1042. desc = &queue->tx_ring[entry];
  1043. desc->ctrl = ctrl;
  1044. do {
  1045. i--;
  1046. entry = macb_tx_ring_wrap(i);
  1047. tx_skb = &queue->tx_skb[entry];
  1048. desc = &queue->tx_ring[entry];
  1049. ctrl = (u32)tx_skb->size;
  1050. if (eof) {
  1051. ctrl |= MACB_BIT(TX_LAST);
  1052. eof = 0;
  1053. }
  1054. if (unlikely(entry == (TX_RING_SIZE - 1)))
  1055. ctrl |= MACB_BIT(TX_WRAP);
  1056. /* Set TX buffer descriptor */
  1057. desc->addr = tx_skb->mapping;
  1058. /* desc->addr must be visible to hardware before clearing
  1059. * 'TX_USED' bit in desc->ctrl.
  1060. */
  1061. wmb();
  1062. desc->ctrl = ctrl;
  1063. } while (i != queue->tx_head);
  1064. queue->tx_head = tx_head;
  1065. return count;
  1066. dma_error:
  1067. netdev_err(bp->dev, "TX DMA map failed\n");
  1068. for (i = queue->tx_head; i != tx_head; i++) {
  1069. tx_skb = macb_tx_skb(queue, i);
  1070. macb_tx_unmap(bp, tx_skb);
  1071. }
  1072. return 0;
  1073. }
  1074. static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1075. {
  1076. u16 queue_index = skb_get_queue_mapping(skb);
  1077. struct macb *bp = netdev_priv(dev);
  1078. struct macb_queue *queue = &bp->queues[queue_index];
  1079. unsigned long flags;
  1080. unsigned int count, nr_frags, frag_size, f;
  1081. #if defined(DEBUG) && defined(VERBOSE_DEBUG)
  1082. netdev_vdbg(bp->dev,
  1083. "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
  1084. queue_index, skb->len, skb->head, skb->data,
  1085. skb_tail_pointer(skb), skb_end_pointer(skb));
  1086. print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
  1087. skb->data, 16, true);
  1088. #endif
  1089. /* Count how many TX buffer descriptors are needed to send this
  1090. * socket buffer: skb fragments of jumbo frames may need to be
  1091. * split into many buffer descriptors.
  1092. */
  1093. count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
  1094. nr_frags = skb_shinfo(skb)->nr_frags;
  1095. for (f = 0; f < nr_frags; f++) {
  1096. frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
  1097. count += DIV_ROUND_UP(frag_size, bp->max_tx_length);
  1098. }
  1099. spin_lock_irqsave(&bp->lock, flags);
  1100. /* This is a hard error, log it. */
  1101. if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
  1102. netif_stop_subqueue(dev, queue_index);
  1103. spin_unlock_irqrestore(&bp->lock, flags);
  1104. netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
  1105. queue->tx_head, queue->tx_tail);
  1106. return NETDEV_TX_BUSY;
  1107. }
  1108. /* Map socket buffer for DMA transfer */
  1109. if (!macb_tx_map(bp, queue, skb)) {
  1110. dev_kfree_skb_any(skb);
  1111. goto unlock;
  1112. }
  1113. /* Make newly initialized descriptor visible to hardware */
  1114. wmb();
  1115. skb_tx_timestamp(skb);
  1116. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  1117. if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
  1118. netif_stop_subqueue(dev, queue_index);
  1119. unlock:
  1120. spin_unlock_irqrestore(&bp->lock, flags);
  1121. return NETDEV_TX_OK;
  1122. }
  1123. static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
  1124. {
  1125. if (!macb_is_gem(bp)) {
  1126. bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
  1127. } else {
  1128. bp->rx_buffer_size = size;
  1129. if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
  1130. netdev_dbg(bp->dev,
  1131. "RX buffer must be multiple of %d bytes, expanding\n",
  1132. RX_BUFFER_MULTIPLE);
  1133. bp->rx_buffer_size =
  1134. roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
  1135. }
  1136. }
  1137. netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
  1138. bp->dev->mtu, bp->rx_buffer_size);
  1139. }
  1140. static void gem_free_rx_buffers(struct macb *bp)
  1141. {
  1142. struct sk_buff *skb;
  1143. struct macb_dma_desc *desc;
  1144. dma_addr_t addr;
  1145. int i;
  1146. if (!bp->rx_skbuff)
  1147. return;
  1148. for (i = 0; i < RX_RING_SIZE; i++) {
  1149. skb = bp->rx_skbuff[i];
  1150. if (!skb)
  1151. continue;
  1152. desc = &bp->rx_ring[i];
  1153. addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
  1154. dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
  1155. DMA_FROM_DEVICE);
  1156. dev_kfree_skb_any(skb);
  1157. skb = NULL;
  1158. }
  1159. kfree(bp->rx_skbuff);
  1160. bp->rx_skbuff = NULL;
  1161. }
  1162. static void macb_free_rx_buffers(struct macb *bp)
  1163. {
  1164. if (bp->rx_buffers) {
  1165. dma_free_coherent(&bp->pdev->dev,
  1166. RX_RING_SIZE * bp->rx_buffer_size,
  1167. bp->rx_buffers, bp->rx_buffers_dma);
  1168. bp->rx_buffers = NULL;
  1169. }
  1170. }
  1171. static void macb_free_consistent(struct macb *bp)
  1172. {
  1173. struct macb_queue *queue;
  1174. unsigned int q;
  1175. bp->macbgem_ops.mog_free_rx_buffers(bp);
  1176. if (bp->rx_ring) {
  1177. dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
  1178. bp->rx_ring, bp->rx_ring_dma);
  1179. bp->rx_ring = NULL;
  1180. }
  1181. for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
  1182. kfree(queue->tx_skb);
  1183. queue->tx_skb = NULL;
  1184. if (queue->tx_ring) {
  1185. dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
  1186. queue->tx_ring, queue->tx_ring_dma);
  1187. queue->tx_ring = NULL;
  1188. }
  1189. }
  1190. }
  1191. static int gem_alloc_rx_buffers(struct macb *bp)
  1192. {
  1193. int size;
  1194. size = RX_RING_SIZE * sizeof(struct sk_buff *);
  1195. bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
  1196. if (!bp->rx_skbuff)
  1197. return -ENOMEM;
  1198. netdev_dbg(bp->dev,
  1199. "Allocated %d RX struct sk_buff entries at %p\n",
  1200. RX_RING_SIZE, bp->rx_skbuff);
  1201. return 0;
  1202. }
  1203. static int macb_alloc_rx_buffers(struct macb *bp)
  1204. {
  1205. int size;
  1206. size = RX_RING_SIZE * bp->rx_buffer_size;
  1207. bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
  1208. &bp->rx_buffers_dma, GFP_KERNEL);
  1209. if (!bp->rx_buffers)
  1210. return -ENOMEM;
  1211. netdev_dbg(bp->dev,
  1212. "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
  1213. size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
  1214. return 0;
  1215. }
  1216. static int macb_alloc_consistent(struct macb *bp)
  1217. {
  1218. struct macb_queue *queue;
  1219. unsigned int q;
  1220. int size;
  1221. for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
  1222. size = TX_RING_BYTES;
  1223. queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  1224. &queue->tx_ring_dma,
  1225. GFP_KERNEL);
  1226. if (!queue->tx_ring)
  1227. goto out_err;
  1228. netdev_dbg(bp->dev,
  1229. "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
  1230. q, size, (unsigned long)queue->tx_ring_dma,
  1231. queue->tx_ring);
  1232. size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
  1233. queue->tx_skb = kmalloc(size, GFP_KERNEL);
  1234. if (!queue->tx_skb)
  1235. goto out_err;
  1236. }
  1237. size = RX_RING_BYTES;
  1238. bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  1239. &bp->rx_ring_dma, GFP_KERNEL);
  1240. if (!bp->rx_ring)
  1241. goto out_err;
  1242. netdev_dbg(bp->dev,
  1243. "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
  1244. size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
  1245. if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
  1246. goto out_err;
  1247. return 0;
  1248. out_err:
  1249. macb_free_consistent(bp);
  1250. return -ENOMEM;
  1251. }
  1252. static void gem_init_rings(struct macb *bp)
  1253. {
  1254. struct macb_queue *queue;
  1255. unsigned int q;
  1256. int i;
  1257. for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
  1258. for (i = 0; i < TX_RING_SIZE; i++) {
  1259. queue->tx_ring[i].addr = 0;
  1260. queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
  1261. }
  1262. queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
  1263. queue->tx_head = 0;
  1264. queue->tx_tail = 0;
  1265. }
  1266. bp->rx_tail = 0;
  1267. bp->rx_prepared_head = 0;
  1268. gem_rx_refill(bp);
  1269. }
  1270. static void macb_init_rings(struct macb *bp)
  1271. {
  1272. int i;
  1273. macb_init_rx_ring(bp);
  1274. for (i = 0; i < TX_RING_SIZE; i++) {
  1275. bp->queues[0].tx_ring[i].addr = 0;
  1276. bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
  1277. }
  1278. bp->queues[0].tx_head = 0;
  1279. bp->queues[0].tx_tail = 0;
  1280. bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
  1281. bp->rx_tail = 0;
  1282. }
  1283. static void macb_reset_hw(struct macb *bp)
  1284. {
  1285. struct macb_queue *queue;
  1286. unsigned int q;
  1287. /* Disable RX and TX (XXX: Should we halt the transmission
  1288. * more gracefully?)
  1289. */
  1290. macb_writel(bp, NCR, 0);
  1291. /* Clear the stats registers (XXX: Update stats first?) */
  1292. macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
  1293. /* Clear all status flags */
  1294. macb_writel(bp, TSR, -1);
  1295. macb_writel(bp, RSR, -1);
  1296. /* Disable all interrupts */
  1297. for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
  1298. queue_writel(queue, IDR, -1);
  1299. queue_readl(queue, ISR);
  1300. if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
  1301. queue_writel(queue, ISR, -1);
  1302. }
  1303. }
  1304. static u32 gem_mdc_clk_div(struct macb *bp)
  1305. {
  1306. u32 config;
  1307. unsigned long pclk_hz = clk_get_rate(bp->pclk);
  1308. if (pclk_hz <= 20000000)
  1309. config = GEM_BF(CLK, GEM_CLK_DIV8);
  1310. else if (pclk_hz <= 40000000)
  1311. config = GEM_BF(CLK, GEM_CLK_DIV16);
  1312. else if (pclk_hz <= 80000000)
  1313. config = GEM_BF(CLK, GEM_CLK_DIV32);
  1314. else if (pclk_hz <= 120000000)
  1315. config = GEM_BF(CLK, GEM_CLK_DIV48);
  1316. else if (pclk_hz <= 160000000)
  1317. config = GEM_BF(CLK, GEM_CLK_DIV64);
  1318. else
  1319. config = GEM_BF(CLK, GEM_CLK_DIV96);
  1320. return config;
  1321. }
  1322. static u32 macb_mdc_clk_div(struct macb *bp)
  1323. {
  1324. u32 config;
  1325. unsigned long pclk_hz;
  1326. if (macb_is_gem(bp))
  1327. return gem_mdc_clk_div(bp);
  1328. pclk_hz = clk_get_rate(bp->pclk);
  1329. if (pclk_hz <= 20000000)
  1330. config = MACB_BF(CLK, MACB_CLK_DIV8);
  1331. else if (pclk_hz <= 40000000)
  1332. config = MACB_BF(CLK, MACB_CLK_DIV16);
  1333. else if (pclk_hz <= 80000000)
  1334. config = MACB_BF(CLK, MACB_CLK_DIV32);
  1335. else
  1336. config = MACB_BF(CLK, MACB_CLK_DIV64);
  1337. return config;
  1338. }
  1339. /* Get the DMA bus width field of the network configuration register that we
  1340. * should program. We find the width from decoding the design configuration
  1341. * register to find the maximum supported data bus width.
  1342. */
  1343. static u32 macb_dbw(struct macb *bp)
  1344. {
  1345. if (!macb_is_gem(bp))
  1346. return 0;
  1347. switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
  1348. case 4:
  1349. return GEM_BF(DBW, GEM_DBW128);
  1350. case 2:
  1351. return GEM_BF(DBW, GEM_DBW64);
  1352. case 1:
  1353. default:
  1354. return GEM_BF(DBW, GEM_DBW32);
  1355. }
  1356. }
  1357. /* Configure the receive DMA engine
  1358. * - use the correct receive buffer size
  1359. * - set best burst length for DMA operations
  1360. * (if not supported by FIFO, it will fallback to default)
  1361. * - set both rx/tx packet buffers to full memory size
  1362. * These are configurable parameters for GEM.
  1363. */
  1364. static void macb_configure_dma(struct macb *bp)
  1365. {
  1366. u32 dmacfg;
  1367. if (macb_is_gem(bp)) {
  1368. dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
  1369. dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
  1370. if (bp->dma_burst_length)
  1371. dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
  1372. dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
  1373. dmacfg &= ~GEM_BIT(ENDIA_PKT);
  1374. if (bp->native_io)
  1375. dmacfg &= ~GEM_BIT(ENDIA_DESC);
  1376. else
  1377. dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
  1378. if (bp->dev->features & NETIF_F_HW_CSUM)
  1379. dmacfg |= GEM_BIT(TXCOEN);
  1380. else
  1381. dmacfg &= ~GEM_BIT(TXCOEN);
  1382. netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
  1383. dmacfg);
  1384. gem_writel(bp, DMACFG, dmacfg);
  1385. }
  1386. }
  1387. static void macb_init_hw(struct macb *bp)
  1388. {
  1389. struct macb_queue *queue;
  1390. unsigned int q;
  1391. u32 config;
  1392. macb_reset_hw(bp);
  1393. macb_set_hwaddr(bp);
  1394. config = macb_mdc_clk_div(bp);
  1395. if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
  1396. config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
  1397. config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
  1398. config |= MACB_BIT(PAE); /* PAuse Enable */
  1399. config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
  1400. if (bp->caps & MACB_CAPS_JUMBO)
  1401. config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
  1402. else
  1403. config |= MACB_BIT(BIG); /* Receive oversized frames */
  1404. if (bp->dev->flags & IFF_PROMISC)
  1405. config |= MACB_BIT(CAF); /* Copy All Frames */
  1406. else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
  1407. config |= GEM_BIT(RXCOEN);
  1408. if (!(bp->dev->flags & IFF_BROADCAST))
  1409. config |= MACB_BIT(NBC); /* No BroadCast */
  1410. config |= macb_dbw(bp);
  1411. macb_writel(bp, NCFGR, config);
  1412. if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
  1413. gem_writel(bp, JML, bp->jumbo_max_len);
  1414. bp->speed = SPEED_10;
  1415. bp->duplex = DUPLEX_HALF;
  1416. bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
  1417. if (bp->caps & MACB_CAPS_JUMBO)
  1418. bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
  1419. macb_configure_dma(bp);
  1420. /* Initialize TX and RX buffers */
  1421. macb_writel(bp, RBQP, bp->rx_ring_dma);
  1422. for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
  1423. queue_writel(queue, TBQP, queue->tx_ring_dma);
  1424. /* Enable interrupts */
  1425. queue_writel(queue, IER,
  1426. MACB_RX_INT_FLAGS |
  1427. MACB_TX_INT_FLAGS |
  1428. MACB_BIT(HRESP));
  1429. }
  1430. /* Enable TX and RX */
  1431. macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
  1432. }
  1433. /* The hash address register is 64 bits long and takes up two
  1434. * locations in the memory map. The least significant bits are stored
  1435. * in EMAC_HSL and the most significant bits in EMAC_HSH.
  1436. *
  1437. * The unicast hash enable and the multicast hash enable bits in the
  1438. * network configuration register enable the reception of hash matched
  1439. * frames. The destination address is reduced to a 6 bit index into
  1440. * the 64 bit hash register using the following hash function. The
  1441. * hash function is an exclusive or of every sixth bit of the
  1442. * destination address.
  1443. *
  1444. * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
  1445. * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
  1446. * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
  1447. * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
  1448. * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
  1449. * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
  1450. *
  1451. * da[0] represents the least significant bit of the first byte
  1452. * received, that is, the multicast/unicast indicator, and da[47]
  1453. * represents the most significant bit of the last byte received. If
  1454. * the hash index, hi[n], points to a bit that is set in the hash
  1455. * register then the frame will be matched according to whether the
  1456. * frame is multicast or unicast. A multicast match will be signalled
  1457. * if the multicast hash enable bit is set, da[0] is 1 and the hash
  1458. * index points to a bit set in the hash register. A unicast match
  1459. * will be signalled if the unicast hash enable bit is set, da[0] is 0
  1460. * and the hash index points to a bit set in the hash register. To
  1461. * receive all multicast frames, the hash register should be set with
  1462. * all ones and the multicast hash enable bit should be set in the
  1463. * network configuration register.
  1464. */
  1465. static inline int hash_bit_value(int bitnr, __u8 *addr)
  1466. {
  1467. if (addr[bitnr / 8] & (1 << (bitnr % 8)))
  1468. return 1;
  1469. return 0;
  1470. }
  1471. /* Return the hash index value for the specified address. */
  1472. static int hash_get_index(__u8 *addr)
  1473. {
  1474. int i, j, bitval;
  1475. int hash_index = 0;
  1476. for (j = 0; j < 6; j++) {
  1477. for (i = 0, bitval = 0; i < 8; i++)
  1478. bitval ^= hash_bit_value(i * 6 + j, addr);
  1479. hash_index |= (bitval << j);
  1480. }
  1481. return hash_index;
  1482. }
  1483. /* Add multicast addresses to the internal multicast-hash table. */
  1484. static void macb_sethashtable(struct net_device *dev)
  1485. {
  1486. struct netdev_hw_addr *ha;
  1487. unsigned long mc_filter[2];
  1488. unsigned int bitnr;
  1489. struct macb *bp = netdev_priv(dev);
  1490. mc_filter[0] = 0;
  1491. mc_filter[1] = 0;
  1492. netdev_for_each_mc_addr(ha, dev) {
  1493. bitnr = hash_get_index(ha->addr);
  1494. mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
  1495. }
  1496. macb_or_gem_writel(bp, HRB, mc_filter[0]);
  1497. macb_or_gem_writel(bp, HRT, mc_filter[1]);
  1498. }
  1499. /* Enable/Disable promiscuous and multicast modes. */
  1500. static void macb_set_rx_mode(struct net_device *dev)
  1501. {
  1502. unsigned long cfg;
  1503. struct macb *bp = netdev_priv(dev);
  1504. cfg = macb_readl(bp, NCFGR);
  1505. if (dev->flags & IFF_PROMISC) {
  1506. /* Enable promiscuous mode */
  1507. cfg |= MACB_BIT(CAF);
  1508. /* Disable RX checksum offload */
  1509. if (macb_is_gem(bp))
  1510. cfg &= ~GEM_BIT(RXCOEN);
  1511. } else {
  1512. /* Disable promiscuous mode */
  1513. cfg &= ~MACB_BIT(CAF);
  1514. /* Enable RX checksum offload only if requested */
  1515. if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
  1516. cfg |= GEM_BIT(RXCOEN);
  1517. }
  1518. if (dev->flags & IFF_ALLMULTI) {
  1519. /* Enable all multicast mode */
  1520. macb_or_gem_writel(bp, HRB, -1);
  1521. macb_or_gem_writel(bp, HRT, -1);
  1522. cfg |= MACB_BIT(NCFGR_MTI);
  1523. } else if (!netdev_mc_empty(dev)) {
  1524. /* Enable specific multicasts */
  1525. macb_sethashtable(dev);
  1526. cfg |= MACB_BIT(NCFGR_MTI);
  1527. } else if (dev->flags & (~IFF_ALLMULTI)) {
  1528. /* Disable all multicast mode */
  1529. macb_or_gem_writel(bp, HRB, 0);
  1530. macb_or_gem_writel(bp, HRT, 0);
  1531. cfg &= ~MACB_BIT(NCFGR_MTI);
  1532. }
  1533. macb_writel(bp, NCFGR, cfg);
  1534. }
  1535. static int macb_open(struct net_device *dev)
  1536. {
  1537. struct macb *bp = netdev_priv(dev);
  1538. size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
  1539. int err;
  1540. netdev_dbg(bp->dev, "open\n");
  1541. /* carrier starts down */
  1542. netif_carrier_off(dev);
  1543. /* if the phy is not yet register, retry later*/
  1544. if (!dev->phydev)
  1545. return -EAGAIN;
  1546. /* RX buffers initialization */
  1547. macb_init_rx_buffer_size(bp, bufsz);
  1548. err = macb_alloc_consistent(bp);
  1549. if (err) {
  1550. netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
  1551. err);
  1552. return err;
  1553. }
  1554. napi_enable(&bp->napi);
  1555. bp->macbgem_ops.mog_init_rings(bp);
  1556. macb_init_hw(bp);
  1557. /* schedule a link state check */
  1558. phy_start(dev->phydev);
  1559. netif_tx_start_all_queues(dev);
  1560. return 0;
  1561. }
  1562. static int macb_close(struct net_device *dev)
  1563. {
  1564. struct macb *bp = netdev_priv(dev);
  1565. unsigned long flags;
  1566. netif_tx_stop_all_queues(dev);
  1567. napi_disable(&bp->napi);
  1568. if (dev->phydev)
  1569. phy_stop(dev->phydev);
  1570. spin_lock_irqsave(&bp->lock, flags);
  1571. macb_reset_hw(bp);
  1572. netif_carrier_off(dev);
  1573. spin_unlock_irqrestore(&bp->lock, flags);
  1574. macb_free_consistent(bp);
  1575. return 0;
  1576. }
  1577. static int macb_change_mtu(struct net_device *dev, int new_mtu)
  1578. {
  1579. struct macb *bp = netdev_priv(dev);
  1580. u32 max_mtu;
  1581. if (netif_running(dev))
  1582. return -EBUSY;
  1583. max_mtu = ETH_DATA_LEN;
  1584. if (bp->caps & MACB_CAPS_JUMBO)
  1585. max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
  1586. if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
  1587. return -EINVAL;
  1588. dev->mtu = new_mtu;
  1589. return 0;
  1590. }
  1591. static void gem_update_stats(struct macb *bp)
  1592. {
  1593. unsigned int i;
  1594. u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
  1595. for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
  1596. u32 offset = gem_statistics[i].offset;
  1597. u64 val = bp->macb_reg_readl(bp, offset);
  1598. bp->ethtool_stats[i] += val;
  1599. *p += val;
  1600. if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
  1601. /* Add GEM_OCTTXH, GEM_OCTRXH */
  1602. val = bp->macb_reg_readl(bp, offset + 4);
  1603. bp->ethtool_stats[i] += ((u64)val) << 32;
  1604. *(++p) += val;
  1605. }
  1606. }
  1607. }
  1608. static struct net_device_stats *gem_get_stats(struct macb *bp)
  1609. {
  1610. struct gem_stats *hwstat = &bp->hw_stats.gem;
  1611. struct net_device_stats *nstat = &bp->stats;
  1612. gem_update_stats(bp);
  1613. nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
  1614. hwstat->rx_alignment_errors +
  1615. hwstat->rx_resource_errors +
  1616. hwstat->rx_overruns +
  1617. hwstat->rx_oversize_frames +
  1618. hwstat->rx_jabbers +
  1619. hwstat->rx_undersized_frames +
  1620. hwstat->rx_length_field_frame_errors);
  1621. nstat->tx_errors = (hwstat->tx_late_collisions +
  1622. hwstat->tx_excessive_collisions +
  1623. hwstat->tx_underrun +
  1624. hwstat->tx_carrier_sense_errors);
  1625. nstat->multicast = hwstat->rx_multicast_frames;
  1626. nstat->collisions = (hwstat->tx_single_collision_frames +
  1627. hwstat->tx_multiple_collision_frames +
  1628. hwstat->tx_excessive_collisions);
  1629. nstat->rx_length_errors = (hwstat->rx_oversize_frames +
  1630. hwstat->rx_jabbers +
  1631. hwstat->rx_undersized_frames +
  1632. hwstat->rx_length_field_frame_errors);
  1633. nstat->rx_over_errors = hwstat->rx_resource_errors;
  1634. nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
  1635. nstat->rx_frame_errors = hwstat->rx_alignment_errors;
  1636. nstat->rx_fifo_errors = hwstat->rx_overruns;
  1637. nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
  1638. nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
  1639. nstat->tx_fifo_errors = hwstat->tx_underrun;
  1640. return nstat;
  1641. }
  1642. static void gem_get_ethtool_stats(struct net_device *dev,
  1643. struct ethtool_stats *stats, u64 *data)
  1644. {
  1645. struct macb *bp;
  1646. bp = netdev_priv(dev);
  1647. gem_update_stats(bp);
  1648. memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
  1649. }
  1650. static int gem_get_sset_count(struct net_device *dev, int sset)
  1651. {
  1652. switch (sset) {
  1653. case ETH_SS_STATS:
  1654. return GEM_STATS_LEN;
  1655. default:
  1656. return -EOPNOTSUPP;
  1657. }
  1658. }
  1659. static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
  1660. {
  1661. unsigned int i;
  1662. switch (sset) {
  1663. case ETH_SS_STATS:
  1664. for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
  1665. memcpy(p, gem_statistics[i].stat_string,
  1666. ETH_GSTRING_LEN);
  1667. break;
  1668. }
  1669. }
  1670. static struct net_device_stats *macb_get_stats(struct net_device *dev)
  1671. {
  1672. struct macb *bp = netdev_priv(dev);
  1673. struct net_device_stats *nstat = &bp->stats;
  1674. struct macb_stats *hwstat = &bp->hw_stats.macb;
  1675. if (macb_is_gem(bp))
  1676. return gem_get_stats(bp);
  1677. /* read stats from hardware */
  1678. macb_update_stats(bp);
  1679. /* Convert HW stats into netdevice stats */
  1680. nstat->rx_errors = (hwstat->rx_fcs_errors +
  1681. hwstat->rx_align_errors +
  1682. hwstat->rx_resource_errors +
  1683. hwstat->rx_overruns +
  1684. hwstat->rx_oversize_pkts +
  1685. hwstat->rx_jabbers +
  1686. hwstat->rx_undersize_pkts +
  1687. hwstat->rx_length_mismatch);
  1688. nstat->tx_errors = (hwstat->tx_late_cols +
  1689. hwstat->tx_excessive_cols +
  1690. hwstat->tx_underruns +
  1691. hwstat->tx_carrier_errors +
  1692. hwstat->sqe_test_errors);
  1693. nstat->collisions = (hwstat->tx_single_cols +
  1694. hwstat->tx_multiple_cols +
  1695. hwstat->tx_excessive_cols);
  1696. nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
  1697. hwstat->rx_jabbers +
  1698. hwstat->rx_undersize_pkts +
  1699. hwstat->rx_length_mismatch);
  1700. nstat->rx_over_errors = hwstat->rx_resource_errors +
  1701. hwstat->rx_overruns;
  1702. nstat->rx_crc_errors = hwstat->rx_fcs_errors;
  1703. nstat->rx_frame_errors = hwstat->rx_align_errors;
  1704. nstat->rx_fifo_errors = hwstat->rx_overruns;
  1705. /* XXX: What does "missed" mean? */
  1706. nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
  1707. nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
  1708. nstat->tx_fifo_errors = hwstat->tx_underruns;
  1709. /* Don't know about heartbeat or window errors... */
  1710. return nstat;
  1711. }
  1712. static int macb_get_regs_len(struct net_device *netdev)
  1713. {
  1714. return MACB_GREGS_NBR * sizeof(u32);
  1715. }
  1716. static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  1717. void *p)
  1718. {
  1719. struct macb *bp = netdev_priv(dev);
  1720. unsigned int tail, head;
  1721. u32 *regs_buff = p;
  1722. regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
  1723. | MACB_GREGS_VERSION;
  1724. tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
  1725. head = macb_tx_ring_wrap(bp->queues[0].tx_head);
  1726. regs_buff[0] = macb_readl(bp, NCR);
  1727. regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
  1728. regs_buff[2] = macb_readl(bp, NSR);
  1729. regs_buff[3] = macb_readl(bp, TSR);
  1730. regs_buff[4] = macb_readl(bp, RBQP);
  1731. regs_buff[5] = macb_readl(bp, TBQP);
  1732. regs_buff[6] = macb_readl(bp, RSR);
  1733. regs_buff[7] = macb_readl(bp, IMR);
  1734. regs_buff[8] = tail;
  1735. regs_buff[9] = head;
  1736. regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
  1737. regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
  1738. if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
  1739. regs_buff[12] = macb_or_gem_readl(bp, USRIO);
  1740. if (macb_is_gem(bp))
  1741. regs_buff[13] = gem_readl(bp, DMACFG);
  1742. }
  1743. static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
  1744. {
  1745. struct macb *bp = netdev_priv(netdev);
  1746. wol->supported = 0;
  1747. wol->wolopts = 0;
  1748. if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
  1749. wol->supported = WAKE_MAGIC;
  1750. if (bp->wol & MACB_WOL_ENABLED)
  1751. wol->wolopts |= WAKE_MAGIC;
  1752. }
  1753. }
  1754. static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
  1755. {
  1756. struct macb *bp = netdev_priv(netdev);
  1757. if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
  1758. (wol->wolopts & ~WAKE_MAGIC))
  1759. return -EOPNOTSUPP;
  1760. if (wol->wolopts & WAKE_MAGIC)
  1761. bp->wol |= MACB_WOL_ENABLED;
  1762. else
  1763. bp->wol &= ~MACB_WOL_ENABLED;
  1764. device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
  1765. return 0;
  1766. }
  1767. static const struct ethtool_ops macb_ethtool_ops = {
  1768. .get_regs_len = macb_get_regs_len,
  1769. .get_regs = macb_get_regs,
  1770. .get_link = ethtool_op_get_link,
  1771. .get_ts_info = ethtool_op_get_ts_info,
  1772. .get_wol = macb_get_wol,
  1773. .set_wol = macb_set_wol,
  1774. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  1775. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  1776. };
  1777. static const struct ethtool_ops gem_ethtool_ops = {
  1778. .get_regs_len = macb_get_regs_len,
  1779. .get_regs = macb_get_regs,
  1780. .get_link = ethtool_op_get_link,
  1781. .get_ts_info = ethtool_op_get_ts_info,
  1782. .get_ethtool_stats = gem_get_ethtool_stats,
  1783. .get_strings = gem_get_ethtool_strings,
  1784. .get_sset_count = gem_get_sset_count,
  1785. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  1786. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  1787. };
  1788. static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1789. {
  1790. struct phy_device *phydev = dev->phydev;
  1791. if (!netif_running(dev))
  1792. return -EINVAL;
  1793. if (!phydev)
  1794. return -ENODEV;
  1795. return phy_mii_ioctl(phydev, rq, cmd);
  1796. }
  1797. static int macb_set_features(struct net_device *netdev,
  1798. netdev_features_t features)
  1799. {
  1800. struct macb *bp = netdev_priv(netdev);
  1801. netdev_features_t changed = features ^ netdev->features;
  1802. /* TX checksum offload */
  1803. if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
  1804. u32 dmacfg;
  1805. dmacfg = gem_readl(bp, DMACFG);
  1806. if (features & NETIF_F_HW_CSUM)
  1807. dmacfg |= GEM_BIT(TXCOEN);
  1808. else
  1809. dmacfg &= ~GEM_BIT(TXCOEN);
  1810. gem_writel(bp, DMACFG, dmacfg);
  1811. }
  1812. /* RX checksum offload */
  1813. if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
  1814. u32 netcfg;
  1815. netcfg = gem_readl(bp, NCFGR);
  1816. if (features & NETIF_F_RXCSUM &&
  1817. !(netdev->flags & IFF_PROMISC))
  1818. netcfg |= GEM_BIT(RXCOEN);
  1819. else
  1820. netcfg &= ~GEM_BIT(RXCOEN);
  1821. gem_writel(bp, NCFGR, netcfg);
  1822. }
  1823. return 0;
  1824. }
  1825. static const struct net_device_ops macb_netdev_ops = {
  1826. .ndo_open = macb_open,
  1827. .ndo_stop = macb_close,
  1828. .ndo_start_xmit = macb_start_xmit,
  1829. .ndo_set_rx_mode = macb_set_rx_mode,
  1830. .ndo_get_stats = macb_get_stats,
  1831. .ndo_do_ioctl = macb_ioctl,
  1832. .ndo_validate_addr = eth_validate_addr,
  1833. .ndo_change_mtu = macb_change_mtu,
  1834. .ndo_set_mac_address = eth_mac_addr,
  1835. #ifdef CONFIG_NET_POLL_CONTROLLER
  1836. .ndo_poll_controller = macb_poll_controller,
  1837. #endif
  1838. .ndo_set_features = macb_set_features,
  1839. };
  1840. /* Configure peripheral capabilities according to device tree
  1841. * and integration options used
  1842. */
  1843. static void macb_configure_caps(struct macb *bp,
  1844. const struct macb_config *dt_conf)
  1845. {
  1846. u32 dcfg;
  1847. if (dt_conf)
  1848. bp->caps = dt_conf->caps;
  1849. if (hw_is_gem(bp->regs, bp->native_io)) {
  1850. bp->caps |= MACB_CAPS_MACB_IS_GEM;
  1851. dcfg = gem_readl(bp, DCFG1);
  1852. if (GEM_BFEXT(IRQCOR, dcfg) == 0)
  1853. bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
  1854. dcfg = gem_readl(bp, DCFG2);
  1855. if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
  1856. bp->caps |= MACB_CAPS_FIFO_MODE;
  1857. }
  1858. dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
  1859. }
  1860. static void macb_probe_queues(void __iomem *mem,
  1861. bool native_io,
  1862. unsigned int *queue_mask,
  1863. unsigned int *num_queues)
  1864. {
  1865. unsigned int hw_q;
  1866. *queue_mask = 0x1;
  1867. *num_queues = 1;
  1868. /* is it macb or gem ?
  1869. *
  1870. * We need to read directly from the hardware here because
  1871. * we are early in the probe process and don't have the
  1872. * MACB_CAPS_MACB_IS_GEM flag positioned
  1873. */
  1874. if (!hw_is_gem(mem, native_io))
  1875. return;
  1876. /* bit 0 is never set but queue 0 always exists */
  1877. *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
  1878. *queue_mask |= 0x1;
  1879. for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
  1880. if (*queue_mask & (1 << hw_q))
  1881. (*num_queues)++;
  1882. }
  1883. static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
  1884. struct clk **hclk, struct clk **tx_clk)
  1885. {
  1886. int err;
  1887. *pclk = devm_clk_get(&pdev->dev, "pclk");
  1888. if (IS_ERR(*pclk)) {
  1889. err = PTR_ERR(*pclk);
  1890. dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
  1891. return err;
  1892. }
  1893. *hclk = devm_clk_get(&pdev->dev, "hclk");
  1894. if (IS_ERR(*hclk)) {
  1895. err = PTR_ERR(*hclk);
  1896. dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
  1897. return err;
  1898. }
  1899. *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
  1900. if (IS_ERR(*tx_clk))
  1901. *tx_clk = NULL;
  1902. err = clk_prepare_enable(*pclk);
  1903. if (err) {
  1904. dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
  1905. return err;
  1906. }
  1907. err = clk_prepare_enable(*hclk);
  1908. if (err) {
  1909. dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
  1910. goto err_disable_pclk;
  1911. }
  1912. err = clk_prepare_enable(*tx_clk);
  1913. if (err) {
  1914. dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
  1915. goto err_disable_hclk;
  1916. }
  1917. return 0;
  1918. err_disable_hclk:
  1919. clk_disable_unprepare(*hclk);
  1920. err_disable_pclk:
  1921. clk_disable_unprepare(*pclk);
  1922. return err;
  1923. }
  1924. static int macb_init(struct platform_device *pdev)
  1925. {
  1926. struct net_device *dev = platform_get_drvdata(pdev);
  1927. unsigned int hw_q, q;
  1928. struct macb *bp = netdev_priv(dev);
  1929. struct macb_queue *queue;
  1930. int err;
  1931. u32 val;
  1932. /* set the queue register mapping once for all: queue0 has a special
  1933. * register mapping but we don't want to test the queue index then
  1934. * compute the corresponding register offset at run time.
  1935. */
  1936. for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
  1937. if (!(bp->queue_mask & (1 << hw_q)))
  1938. continue;
  1939. queue = &bp->queues[q];
  1940. queue->bp = bp;
  1941. if (hw_q) {
  1942. queue->ISR = GEM_ISR(hw_q - 1);
  1943. queue->IER = GEM_IER(hw_q - 1);
  1944. queue->IDR = GEM_IDR(hw_q - 1);
  1945. queue->IMR = GEM_IMR(hw_q - 1);
  1946. queue->TBQP = GEM_TBQP(hw_q - 1);
  1947. } else {
  1948. /* queue0 uses legacy registers */
  1949. queue->ISR = MACB_ISR;
  1950. queue->IER = MACB_IER;
  1951. queue->IDR = MACB_IDR;
  1952. queue->IMR = MACB_IMR;
  1953. queue->TBQP = MACB_TBQP;
  1954. }
  1955. /* get irq: here we use the linux queue index, not the hardware
  1956. * queue index. the queue irq definitions in the device tree
  1957. * must remove the optional gaps that could exist in the
  1958. * hardware queue mask.
  1959. */
  1960. queue->irq = platform_get_irq(pdev, q);
  1961. err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
  1962. IRQF_SHARED, dev->name, queue);
  1963. if (err) {
  1964. dev_err(&pdev->dev,
  1965. "Unable to request IRQ %d (error %d)\n",
  1966. queue->irq, err);
  1967. return err;
  1968. }
  1969. INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
  1970. q++;
  1971. }
  1972. dev->netdev_ops = &macb_netdev_ops;
  1973. netif_napi_add(dev, &bp->napi, macb_poll, 64);
  1974. /* setup appropriated routines according to adapter type */
  1975. if (macb_is_gem(bp)) {
  1976. bp->max_tx_length = GEM_MAX_TX_LEN;
  1977. bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
  1978. bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
  1979. bp->macbgem_ops.mog_init_rings = gem_init_rings;
  1980. bp->macbgem_ops.mog_rx = gem_rx;
  1981. dev->ethtool_ops = &gem_ethtool_ops;
  1982. } else {
  1983. bp->max_tx_length = MACB_MAX_TX_LEN;
  1984. bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
  1985. bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
  1986. bp->macbgem_ops.mog_init_rings = macb_init_rings;
  1987. bp->macbgem_ops.mog_rx = macb_rx;
  1988. dev->ethtool_ops = &macb_ethtool_ops;
  1989. }
  1990. /* Set features */
  1991. dev->hw_features = NETIF_F_SG;
  1992. /* Checksum offload is only available on gem with packet buffer */
  1993. if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
  1994. dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
  1995. if (bp->caps & MACB_CAPS_SG_DISABLED)
  1996. dev->hw_features &= ~NETIF_F_SG;
  1997. dev->features = dev->hw_features;
  1998. if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
  1999. val = 0;
  2000. if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
  2001. val = GEM_BIT(RGMII);
  2002. else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
  2003. (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
  2004. val = MACB_BIT(RMII);
  2005. else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
  2006. val = MACB_BIT(MII);
  2007. if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
  2008. val |= MACB_BIT(CLKEN);
  2009. macb_or_gem_writel(bp, USRIO, val);
  2010. }
  2011. /* Set MII management clock divider */
  2012. val = macb_mdc_clk_div(bp);
  2013. val |= macb_dbw(bp);
  2014. if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
  2015. val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
  2016. macb_writel(bp, NCFGR, val);
  2017. return 0;
  2018. }
  2019. #if defined(CONFIG_OF)
  2020. /* 1518 rounded up */
  2021. #define AT91ETHER_MAX_RBUFF_SZ 0x600
  2022. /* max number of receive buffers */
  2023. #define AT91ETHER_MAX_RX_DESCR 9
  2024. /* Initialize and start the Receiver and Transmit subsystems */
  2025. static int at91ether_start(struct net_device *dev)
  2026. {
  2027. struct macb *lp = netdev_priv(dev);
  2028. dma_addr_t addr;
  2029. u32 ctl;
  2030. int i;
  2031. lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
  2032. (AT91ETHER_MAX_RX_DESCR *
  2033. sizeof(struct macb_dma_desc)),
  2034. &lp->rx_ring_dma, GFP_KERNEL);
  2035. if (!lp->rx_ring)
  2036. return -ENOMEM;
  2037. lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
  2038. AT91ETHER_MAX_RX_DESCR *
  2039. AT91ETHER_MAX_RBUFF_SZ,
  2040. &lp->rx_buffers_dma, GFP_KERNEL);
  2041. if (!lp->rx_buffers) {
  2042. dma_free_coherent(&lp->pdev->dev,
  2043. AT91ETHER_MAX_RX_DESCR *
  2044. sizeof(struct macb_dma_desc),
  2045. lp->rx_ring, lp->rx_ring_dma);
  2046. lp->rx_ring = NULL;
  2047. return -ENOMEM;
  2048. }
  2049. addr = lp->rx_buffers_dma;
  2050. for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
  2051. lp->rx_ring[i].addr = addr;
  2052. lp->rx_ring[i].ctrl = 0;
  2053. addr += AT91ETHER_MAX_RBUFF_SZ;
  2054. }
  2055. /* Set the Wrap bit on the last descriptor */
  2056. lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
  2057. /* Reset buffer index */
  2058. lp->rx_tail = 0;
  2059. /* Program address of descriptor list in Rx Buffer Queue register */
  2060. macb_writel(lp, RBQP, lp->rx_ring_dma);
  2061. /* Enable Receive and Transmit */
  2062. ctl = macb_readl(lp, NCR);
  2063. macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
  2064. return 0;
  2065. }
  2066. /* Open the ethernet interface */
  2067. static int at91ether_open(struct net_device *dev)
  2068. {
  2069. struct macb *lp = netdev_priv(dev);
  2070. u32 ctl;
  2071. int ret;
  2072. /* Clear internal statistics */
  2073. ctl = macb_readl(lp, NCR);
  2074. macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
  2075. macb_set_hwaddr(lp);
  2076. ret = at91ether_start(dev);
  2077. if (ret)
  2078. return ret;
  2079. /* Enable MAC interrupts */
  2080. macb_writel(lp, IER, MACB_BIT(RCOMP) |
  2081. MACB_BIT(RXUBR) |
  2082. MACB_BIT(ISR_TUND) |
  2083. MACB_BIT(ISR_RLE) |
  2084. MACB_BIT(TCOMP) |
  2085. MACB_BIT(ISR_ROVR) |
  2086. MACB_BIT(HRESP));
  2087. /* schedule a link state check */
  2088. phy_start(dev->phydev);
  2089. netif_start_queue(dev);
  2090. return 0;
  2091. }
  2092. /* Close the interface */
  2093. static int at91ether_close(struct net_device *dev)
  2094. {
  2095. struct macb *lp = netdev_priv(dev);
  2096. u32 ctl;
  2097. /* Disable Receiver and Transmitter */
  2098. ctl = macb_readl(lp, NCR);
  2099. macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
  2100. /* Disable MAC interrupts */
  2101. macb_writel(lp, IDR, MACB_BIT(RCOMP) |
  2102. MACB_BIT(RXUBR) |
  2103. MACB_BIT(ISR_TUND) |
  2104. MACB_BIT(ISR_RLE) |
  2105. MACB_BIT(TCOMP) |
  2106. MACB_BIT(ISR_ROVR) |
  2107. MACB_BIT(HRESP));
  2108. netif_stop_queue(dev);
  2109. dma_free_coherent(&lp->pdev->dev,
  2110. AT91ETHER_MAX_RX_DESCR *
  2111. sizeof(struct macb_dma_desc),
  2112. lp->rx_ring, lp->rx_ring_dma);
  2113. lp->rx_ring = NULL;
  2114. dma_free_coherent(&lp->pdev->dev,
  2115. AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
  2116. lp->rx_buffers, lp->rx_buffers_dma);
  2117. lp->rx_buffers = NULL;
  2118. return 0;
  2119. }
  2120. /* Transmit packet */
  2121. static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2122. {
  2123. struct macb *lp = netdev_priv(dev);
  2124. if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
  2125. netif_stop_queue(dev);
  2126. /* Store packet information (to free when Tx completed) */
  2127. lp->skb = skb;
  2128. lp->skb_length = skb->len;
  2129. lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
  2130. DMA_TO_DEVICE);
  2131. /* Set address of the data in the Transmit Address register */
  2132. macb_writel(lp, TAR, lp->skb_physaddr);
  2133. /* Set length of the packet in the Transmit Control register */
  2134. macb_writel(lp, TCR, skb->len);
  2135. } else {
  2136. netdev_err(dev, "%s called, but device is busy!\n", __func__);
  2137. return NETDEV_TX_BUSY;
  2138. }
  2139. return NETDEV_TX_OK;
  2140. }
  2141. /* Extract received frame from buffer descriptors and sent to upper layers.
  2142. * (Called from interrupt context)
  2143. */
  2144. static void at91ether_rx(struct net_device *dev)
  2145. {
  2146. struct macb *lp = netdev_priv(dev);
  2147. unsigned char *p_recv;
  2148. struct sk_buff *skb;
  2149. unsigned int pktlen;
  2150. while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
  2151. p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
  2152. pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
  2153. skb = netdev_alloc_skb(dev, pktlen + 2);
  2154. if (skb) {
  2155. skb_reserve(skb, 2);
  2156. memcpy(skb_put(skb, pktlen), p_recv, pktlen);
  2157. skb->protocol = eth_type_trans(skb, dev);
  2158. lp->stats.rx_packets++;
  2159. lp->stats.rx_bytes += pktlen;
  2160. netif_rx(skb);
  2161. } else {
  2162. lp->stats.rx_dropped++;
  2163. }
  2164. if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
  2165. lp->stats.multicast++;
  2166. /* reset ownership bit */
  2167. lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
  2168. /* wrap after last buffer */
  2169. if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
  2170. lp->rx_tail = 0;
  2171. else
  2172. lp->rx_tail++;
  2173. }
  2174. }
  2175. /* MAC interrupt handler */
  2176. static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
  2177. {
  2178. struct net_device *dev = dev_id;
  2179. struct macb *lp = netdev_priv(dev);
  2180. u32 intstatus, ctl;
  2181. /* MAC Interrupt Status register indicates what interrupts are pending.
  2182. * It is automatically cleared once read.
  2183. */
  2184. intstatus = macb_readl(lp, ISR);
  2185. /* Receive complete */
  2186. if (intstatus & MACB_BIT(RCOMP))
  2187. at91ether_rx(dev);
  2188. /* Transmit complete */
  2189. if (intstatus & MACB_BIT(TCOMP)) {
  2190. /* The TCOM bit is set even if the transmission failed */
  2191. if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
  2192. lp->stats.tx_errors++;
  2193. if (lp->skb) {
  2194. dev_kfree_skb_irq(lp->skb);
  2195. lp->skb = NULL;
  2196. dma_unmap_single(NULL, lp->skb_physaddr,
  2197. lp->skb_length, DMA_TO_DEVICE);
  2198. lp->stats.tx_packets++;
  2199. lp->stats.tx_bytes += lp->skb_length;
  2200. }
  2201. netif_wake_queue(dev);
  2202. }
  2203. /* Work-around for EMAC Errata section 41.3.1 */
  2204. if (intstatus & MACB_BIT(RXUBR)) {
  2205. ctl = macb_readl(lp, NCR);
  2206. macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
  2207. macb_writel(lp, NCR, ctl | MACB_BIT(RE));
  2208. }
  2209. if (intstatus & MACB_BIT(ISR_ROVR))
  2210. netdev_err(dev, "ROVR error\n");
  2211. return IRQ_HANDLED;
  2212. }
  2213. #ifdef CONFIG_NET_POLL_CONTROLLER
  2214. static void at91ether_poll_controller(struct net_device *dev)
  2215. {
  2216. unsigned long flags;
  2217. local_irq_save(flags);
  2218. at91ether_interrupt(dev->irq, dev);
  2219. local_irq_restore(flags);
  2220. }
  2221. #endif
  2222. static const struct net_device_ops at91ether_netdev_ops = {
  2223. .ndo_open = at91ether_open,
  2224. .ndo_stop = at91ether_close,
  2225. .ndo_start_xmit = at91ether_start_xmit,
  2226. .ndo_get_stats = macb_get_stats,
  2227. .ndo_set_rx_mode = macb_set_rx_mode,
  2228. .ndo_set_mac_address = eth_mac_addr,
  2229. .ndo_do_ioctl = macb_ioctl,
  2230. .ndo_validate_addr = eth_validate_addr,
  2231. .ndo_change_mtu = eth_change_mtu,
  2232. #ifdef CONFIG_NET_POLL_CONTROLLER
  2233. .ndo_poll_controller = at91ether_poll_controller,
  2234. #endif
  2235. };
  2236. static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
  2237. struct clk **hclk, struct clk **tx_clk)
  2238. {
  2239. int err;
  2240. *hclk = NULL;
  2241. *tx_clk = NULL;
  2242. *pclk = devm_clk_get(&pdev->dev, "ether_clk");
  2243. if (IS_ERR(*pclk))
  2244. return PTR_ERR(*pclk);
  2245. err = clk_prepare_enable(*pclk);
  2246. if (err) {
  2247. dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
  2248. return err;
  2249. }
  2250. return 0;
  2251. }
  2252. static int at91ether_init(struct platform_device *pdev)
  2253. {
  2254. struct net_device *dev = platform_get_drvdata(pdev);
  2255. struct macb *bp = netdev_priv(dev);
  2256. int err;
  2257. u32 reg;
  2258. dev->netdev_ops = &at91ether_netdev_ops;
  2259. dev->ethtool_ops = &macb_ethtool_ops;
  2260. err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
  2261. 0, dev->name, dev);
  2262. if (err)
  2263. return err;
  2264. macb_writel(bp, NCR, 0);
  2265. reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
  2266. if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
  2267. reg |= MACB_BIT(RM9200_RMII);
  2268. macb_writel(bp, NCFGR, reg);
  2269. return 0;
  2270. }
  2271. static const struct macb_config at91sam9260_config = {
  2272. .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
  2273. .clk_init = macb_clk_init,
  2274. .init = macb_init,
  2275. };
  2276. static const struct macb_config pc302gem_config = {
  2277. .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
  2278. .dma_burst_length = 16,
  2279. .clk_init = macb_clk_init,
  2280. .init = macb_init,
  2281. };
  2282. static const struct macb_config sama5d2_config = {
  2283. .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
  2284. .dma_burst_length = 16,
  2285. .clk_init = macb_clk_init,
  2286. .init = macb_init,
  2287. };
  2288. static const struct macb_config sama5d3_config = {
  2289. .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
  2290. | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
  2291. .dma_burst_length = 16,
  2292. .clk_init = macb_clk_init,
  2293. .init = macb_init,
  2294. };
  2295. static const struct macb_config sama5d4_config = {
  2296. .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
  2297. .dma_burst_length = 4,
  2298. .clk_init = macb_clk_init,
  2299. .init = macb_init,
  2300. };
  2301. static const struct macb_config emac_config = {
  2302. .clk_init = at91ether_clk_init,
  2303. .init = at91ether_init,
  2304. };
  2305. static const struct macb_config np4_config = {
  2306. .caps = MACB_CAPS_USRIO_DISABLED,
  2307. .clk_init = macb_clk_init,
  2308. .init = macb_init,
  2309. };
  2310. static const struct macb_config zynqmp_config = {
  2311. .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
  2312. .dma_burst_length = 16,
  2313. .clk_init = macb_clk_init,
  2314. .init = macb_init,
  2315. .jumbo_max_len = 10240,
  2316. };
  2317. static const struct macb_config zynq_config = {
  2318. .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
  2319. .dma_burst_length = 16,
  2320. .clk_init = macb_clk_init,
  2321. .init = macb_init,
  2322. };
  2323. static const struct of_device_id macb_dt_ids[] = {
  2324. { .compatible = "cdns,at32ap7000-macb" },
  2325. { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
  2326. { .compatible = "cdns,macb" },
  2327. { .compatible = "cdns,np4-macb", .data = &np4_config },
  2328. { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
  2329. { .compatible = "cdns,gem", .data = &pc302gem_config },
  2330. { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
  2331. { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
  2332. { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
  2333. { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
  2334. { .compatible = "cdns,emac", .data = &emac_config },
  2335. { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
  2336. { .compatible = "cdns,zynq-gem", .data = &zynq_config },
  2337. { /* sentinel */ }
  2338. };
  2339. MODULE_DEVICE_TABLE(of, macb_dt_ids);
  2340. #endif /* CONFIG_OF */
  2341. static int macb_probe(struct platform_device *pdev)
  2342. {
  2343. int (*clk_init)(struct platform_device *, struct clk **,
  2344. struct clk **, struct clk **)
  2345. = macb_clk_init;
  2346. int (*init)(struct platform_device *) = macb_init;
  2347. struct device_node *np = pdev->dev.of_node;
  2348. struct device_node *phy_node;
  2349. const struct macb_config *macb_config = NULL;
  2350. struct clk *pclk, *hclk = NULL, *tx_clk = NULL;
  2351. unsigned int queue_mask, num_queues;
  2352. struct macb_platform_data *pdata;
  2353. bool native_io;
  2354. struct phy_device *phydev;
  2355. struct net_device *dev;
  2356. struct resource *regs;
  2357. void __iomem *mem;
  2358. const char *mac;
  2359. struct macb *bp;
  2360. int err;
  2361. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2362. mem = devm_ioremap_resource(&pdev->dev, regs);
  2363. if (IS_ERR(mem))
  2364. return PTR_ERR(mem);
  2365. if (np) {
  2366. const struct of_device_id *match;
  2367. match = of_match_node(macb_dt_ids, np);
  2368. if (match && match->data) {
  2369. macb_config = match->data;
  2370. clk_init = macb_config->clk_init;
  2371. init = macb_config->init;
  2372. }
  2373. }
  2374. err = clk_init(pdev, &pclk, &hclk, &tx_clk);
  2375. if (err)
  2376. return err;
  2377. native_io = hw_is_native_io(mem);
  2378. macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
  2379. dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
  2380. if (!dev) {
  2381. err = -ENOMEM;
  2382. goto err_disable_clocks;
  2383. }
  2384. dev->base_addr = regs->start;
  2385. SET_NETDEV_DEV(dev, &pdev->dev);
  2386. bp = netdev_priv(dev);
  2387. bp->pdev = pdev;
  2388. bp->dev = dev;
  2389. bp->regs = mem;
  2390. bp->native_io = native_io;
  2391. if (native_io) {
  2392. bp->macb_reg_readl = hw_readl_native;
  2393. bp->macb_reg_writel = hw_writel_native;
  2394. } else {
  2395. bp->macb_reg_readl = hw_readl;
  2396. bp->macb_reg_writel = hw_writel;
  2397. }
  2398. bp->num_queues = num_queues;
  2399. bp->queue_mask = queue_mask;
  2400. if (macb_config)
  2401. bp->dma_burst_length = macb_config->dma_burst_length;
  2402. bp->pclk = pclk;
  2403. bp->hclk = hclk;
  2404. bp->tx_clk = tx_clk;
  2405. if (macb_config)
  2406. bp->jumbo_max_len = macb_config->jumbo_max_len;
  2407. bp->wol = 0;
  2408. if (of_get_property(np, "magic-packet", NULL))
  2409. bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
  2410. device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
  2411. spin_lock_init(&bp->lock);
  2412. /* setup capabilities */
  2413. macb_configure_caps(bp, macb_config);
  2414. platform_set_drvdata(pdev, dev);
  2415. dev->irq = platform_get_irq(pdev, 0);
  2416. if (dev->irq < 0) {
  2417. err = dev->irq;
  2418. goto err_disable_clocks;
  2419. }
  2420. mac = of_get_mac_address(np);
  2421. if (mac)
  2422. ether_addr_copy(bp->dev->dev_addr, mac);
  2423. else
  2424. macb_get_hwaddr(bp);
  2425. /* Power up the PHY if there is a GPIO reset */
  2426. phy_node = of_get_next_available_child(np, NULL);
  2427. if (phy_node) {
  2428. int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
  2429. if (gpio_is_valid(gpio)) {
  2430. bp->reset_gpio = gpio_to_desc(gpio);
  2431. gpiod_direction_output(bp->reset_gpio, 1);
  2432. }
  2433. }
  2434. of_node_put(phy_node);
  2435. err = of_get_phy_mode(np);
  2436. if (err < 0) {
  2437. pdata = dev_get_platdata(&pdev->dev);
  2438. if (pdata && pdata->is_rmii)
  2439. bp->phy_interface = PHY_INTERFACE_MODE_RMII;
  2440. else
  2441. bp->phy_interface = PHY_INTERFACE_MODE_MII;
  2442. } else {
  2443. bp->phy_interface = err;
  2444. }
  2445. /* IP specific init */
  2446. err = init(pdev);
  2447. if (err)
  2448. goto err_out_free_netdev;
  2449. err = macb_mii_init(bp);
  2450. if (err)
  2451. goto err_out_free_netdev;
  2452. phydev = dev->phydev;
  2453. netif_carrier_off(dev);
  2454. err = register_netdev(dev);
  2455. if (err) {
  2456. dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
  2457. goto err_out_unregister_mdio;
  2458. }
  2459. phy_attached_info(phydev);
  2460. netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
  2461. macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
  2462. dev->base_addr, dev->irq, dev->dev_addr);
  2463. return 0;
  2464. err_out_unregister_mdio:
  2465. phy_disconnect(dev->phydev);
  2466. mdiobus_unregister(bp->mii_bus);
  2467. mdiobus_free(bp->mii_bus);
  2468. /* Shutdown the PHY if there is a GPIO reset */
  2469. if (bp->reset_gpio)
  2470. gpiod_set_value(bp->reset_gpio, 0);
  2471. err_out_free_netdev:
  2472. free_netdev(dev);
  2473. err_disable_clocks:
  2474. clk_disable_unprepare(tx_clk);
  2475. clk_disable_unprepare(hclk);
  2476. clk_disable_unprepare(pclk);
  2477. return err;
  2478. }
  2479. static int macb_remove(struct platform_device *pdev)
  2480. {
  2481. struct net_device *dev;
  2482. struct macb *bp;
  2483. dev = platform_get_drvdata(pdev);
  2484. if (dev) {
  2485. bp = netdev_priv(dev);
  2486. if (dev->phydev)
  2487. phy_disconnect(dev->phydev);
  2488. mdiobus_unregister(bp->mii_bus);
  2489. mdiobus_free(bp->mii_bus);
  2490. /* Shutdown the PHY if there is a GPIO reset */
  2491. if (bp->reset_gpio)
  2492. gpiod_set_value(bp->reset_gpio, 0);
  2493. unregister_netdev(dev);
  2494. clk_disable_unprepare(bp->tx_clk);
  2495. clk_disable_unprepare(bp->hclk);
  2496. clk_disable_unprepare(bp->pclk);
  2497. free_netdev(dev);
  2498. }
  2499. return 0;
  2500. }
  2501. static int __maybe_unused macb_suspend(struct device *dev)
  2502. {
  2503. struct platform_device *pdev = to_platform_device(dev);
  2504. struct net_device *netdev = platform_get_drvdata(pdev);
  2505. struct macb *bp = netdev_priv(netdev);
  2506. netif_carrier_off(netdev);
  2507. netif_device_detach(netdev);
  2508. if (bp->wol & MACB_WOL_ENABLED) {
  2509. macb_writel(bp, IER, MACB_BIT(WOL));
  2510. macb_writel(bp, WOL, MACB_BIT(MAG));
  2511. enable_irq_wake(bp->queues[0].irq);
  2512. } else {
  2513. clk_disable_unprepare(bp->tx_clk);
  2514. clk_disable_unprepare(bp->hclk);
  2515. clk_disable_unprepare(bp->pclk);
  2516. }
  2517. return 0;
  2518. }
  2519. static int __maybe_unused macb_resume(struct device *dev)
  2520. {
  2521. struct platform_device *pdev = to_platform_device(dev);
  2522. struct net_device *netdev = platform_get_drvdata(pdev);
  2523. struct macb *bp = netdev_priv(netdev);
  2524. if (bp->wol & MACB_WOL_ENABLED) {
  2525. macb_writel(bp, IDR, MACB_BIT(WOL));
  2526. macb_writel(bp, WOL, 0);
  2527. disable_irq_wake(bp->queues[0].irq);
  2528. } else {
  2529. clk_prepare_enable(bp->pclk);
  2530. clk_prepare_enable(bp->hclk);
  2531. clk_prepare_enable(bp->tx_clk);
  2532. }
  2533. netif_device_attach(netdev);
  2534. return 0;
  2535. }
  2536. static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
  2537. static struct platform_driver macb_driver = {
  2538. .probe = macb_probe,
  2539. .remove = macb_remove,
  2540. .driver = {
  2541. .name = "macb",
  2542. .of_match_table = of_match_ptr(macb_dt_ids),
  2543. .pm = &macb_pm_ops,
  2544. },
  2545. };
  2546. module_platform_driver(macb_driver);
  2547. MODULE_LICENSE("GPL");
  2548. MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
  2549. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  2550. MODULE_ALIAS("platform:macb");