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/drivers/net/ethernet/broadcom/bnx2.c

http://github.com/mirrors/linux
C | 8845 lines | 6903 code | 1592 blank | 350 comment | 1327 complexity | 08a381652f80ecee18c3449f12095e97 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. /* bnx2.c: QLogic bnx2 network driver.
  2. *
  3. * Copyright (c) 2004-2014 Broadcom Corporation
  4. * Copyright (c) 2014-2015 QLogic Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Written by: Michael Chan (mchan@broadcom.com)
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/stringify.h>
  16. #include <linux/kernel.h>
  17. #include <linux/timer.h>
  18. #include <linux/errno.h>
  19. #include <linux/ioport.h>
  20. #include <linux/slab.h>
  21. #include <linux/vmalloc.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/pci.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/skbuff.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/bitops.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <linux/delay.h>
  32. #include <asm/byteorder.h>
  33. #include <asm/page.h>
  34. #include <linux/time.h>
  35. #include <linux/ethtool.h>
  36. #include <linux/mii.h>
  37. #include <linux/if.h>
  38. #include <linux/if_vlan.h>
  39. #include <net/ip.h>
  40. #include <net/tcp.h>
  41. #include <net/checksum.h>
  42. #include <linux/workqueue.h>
  43. #include <linux/crc32.h>
  44. #include <linux/prefetch.h>
  45. #include <linux/cache.h>
  46. #include <linux/firmware.h>
  47. #include <linux/log2.h>
  48. #include <linux/aer.h>
  49. #include <linux/crash_dump.h>
  50. #if IS_ENABLED(CONFIG_CNIC)
  51. #define BCM_CNIC 1
  52. #include "cnic_if.h"
  53. #endif
  54. #include "bnx2.h"
  55. #include "bnx2_fw.h"
  56. #define DRV_MODULE_NAME "bnx2"
  57. #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
  58. #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
  59. #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
  60. #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
  61. #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
  62. #define RUN_AT(x) (jiffies + (x))
  63. /* Time in jiffies before concluding the transmitter is hung. */
  64. #define TX_TIMEOUT (5*HZ)
  65. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  66. MODULE_DESCRIPTION("QLogic BCM5706/5708/5709/5716 Driver");
  67. MODULE_LICENSE("GPL");
  68. MODULE_FIRMWARE(FW_MIPS_FILE_06);
  69. MODULE_FIRMWARE(FW_RV2P_FILE_06);
  70. MODULE_FIRMWARE(FW_MIPS_FILE_09);
  71. MODULE_FIRMWARE(FW_RV2P_FILE_09);
  72. MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
  73. static int disable_msi = 0;
  74. module_param(disable_msi, int, 0444);
  75. MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  76. typedef enum {
  77. BCM5706 = 0,
  78. NC370T,
  79. NC370I,
  80. BCM5706S,
  81. NC370F,
  82. BCM5708,
  83. BCM5708S,
  84. BCM5709,
  85. BCM5709S,
  86. BCM5716,
  87. BCM5716S,
  88. } board_t;
  89. /* indexed by board_t, above */
  90. static struct {
  91. char *name;
  92. } board_info[] = {
  93. { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  94. { "HP NC370T Multifunction Gigabit Server Adapter" },
  95. { "HP NC370i Multifunction Gigabit Server Adapter" },
  96. { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  97. { "HP NC370F Multifunction Gigabit Server Adapter" },
  98. { "Broadcom NetXtreme II BCM5708 1000Base-T" },
  99. { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
  100. { "Broadcom NetXtreme II BCM5709 1000Base-T" },
  101. { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
  102. { "Broadcom NetXtreme II BCM5716 1000Base-T" },
  103. { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
  104. };
  105. static const struct pci_device_id bnx2_pci_tbl[] = {
  106. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  107. PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  108. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  109. PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  110. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  111. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  112. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
  113. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
  114. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  115. PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  116. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  117. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  118. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
  119. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
  120. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
  121. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
  122. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
  123. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
  124. { PCI_VENDOR_ID_BROADCOM, 0x163b,
  125. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
  126. { PCI_VENDOR_ID_BROADCOM, 0x163c,
  127. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
  128. { 0, }
  129. };
  130. static const struct flash_spec flash_table[] =
  131. {
  132. #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
  133. #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
  134. /* Slow EEPROM */
  135. {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  136. BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  137. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  138. "EEPROM - slow"},
  139. /* Expansion entry 0001 */
  140. {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  141. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  142. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  143. "Entry 0001"},
  144. /* Saifun SA25F010 (non-buffered flash) */
  145. /* strap, cfg1, & write1 need updates */
  146. {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  147. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  148. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  149. "Non-buffered flash (128kB)"},
  150. /* Saifun SA25F020 (non-buffered flash) */
  151. /* strap, cfg1, & write1 need updates */
  152. {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
  153. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  154. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
  155. "Non-buffered flash (256kB)"},
  156. /* Expansion entry 0100 */
  157. {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
  158. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  159. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  160. "Entry 0100"},
  161. /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
  162. {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
  163. NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  164. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
  165. "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
  166. /* Entry 0110: ST M45PE20 (non-buffered flash)*/
  167. {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
  168. NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  169. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
  170. "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
  171. /* Saifun SA25F005 (non-buffered flash) */
  172. /* strap, cfg1, & write1 need updates */
  173. {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
  174. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  175. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
  176. "Non-buffered flash (64kB)"},
  177. /* Fast EEPROM */
  178. {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
  179. BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  180. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  181. "EEPROM - fast"},
  182. /* Expansion entry 1001 */
  183. {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
  184. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  185. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  186. "Entry 1001"},
  187. /* Expansion entry 1010 */
  188. {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
  189. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  190. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  191. "Entry 1010"},
  192. /* ATMEL AT45DB011B (buffered flash) */
  193. {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
  194. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  195. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
  196. "Buffered flash (128kB)"},
  197. /* Expansion entry 1100 */
  198. {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
  199. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  200. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  201. "Entry 1100"},
  202. /* Expansion entry 1101 */
  203. {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
  204. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  205. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  206. "Entry 1101"},
  207. /* Ateml Expansion entry 1110 */
  208. {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
  209. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  210. BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
  211. "Entry 1110 (Atmel)"},
  212. /* ATMEL AT45DB021B (buffered flash) */
  213. {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
  214. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  215. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
  216. "Buffered flash (256kB)"},
  217. };
  218. static const struct flash_spec flash_5709 = {
  219. .flags = BNX2_NV_BUFFERED,
  220. .page_bits = BCM5709_FLASH_PAGE_BITS,
  221. .page_size = BCM5709_FLASH_PAGE_SIZE,
  222. .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
  223. .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
  224. .name = "5709 Buffered flash (256kB)",
  225. };
  226. MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
  227. static void bnx2_init_napi(struct bnx2 *bp);
  228. static void bnx2_del_napi(struct bnx2 *bp);
  229. static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
  230. {
  231. u32 diff;
  232. /* The ring uses 256 indices for 255 entries, one of them
  233. * needs to be skipped.
  234. */
  235. diff = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
  236. if (unlikely(diff >= BNX2_TX_DESC_CNT)) {
  237. diff &= 0xffff;
  238. if (diff == BNX2_TX_DESC_CNT)
  239. diff = BNX2_MAX_TX_DESC_CNT;
  240. }
  241. return bp->tx_ring_size - diff;
  242. }
  243. static u32
  244. bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
  245. {
  246. unsigned long flags;
  247. u32 val;
  248. spin_lock_irqsave(&bp->indirect_lock, flags);
  249. BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  250. val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
  251. spin_unlock_irqrestore(&bp->indirect_lock, flags);
  252. return val;
  253. }
  254. static void
  255. bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
  256. {
  257. unsigned long flags;
  258. spin_lock_irqsave(&bp->indirect_lock, flags);
  259. BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  260. BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
  261. spin_unlock_irqrestore(&bp->indirect_lock, flags);
  262. }
  263. static void
  264. bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
  265. {
  266. bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
  267. }
  268. static u32
  269. bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
  270. {
  271. return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
  272. }
  273. static void
  274. bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
  275. {
  276. unsigned long flags;
  277. offset += cid_addr;
  278. spin_lock_irqsave(&bp->indirect_lock, flags);
  279. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  280. int i;
  281. BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
  282. BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
  283. offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
  284. for (i = 0; i < 5; i++) {
  285. val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
  286. if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
  287. break;
  288. udelay(5);
  289. }
  290. } else {
  291. BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
  292. BNX2_WR(bp, BNX2_CTX_DATA, val);
  293. }
  294. spin_unlock_irqrestore(&bp->indirect_lock, flags);
  295. }
  296. #ifdef BCM_CNIC
  297. static int
  298. bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
  299. {
  300. struct bnx2 *bp = netdev_priv(dev);
  301. struct drv_ctl_io *io = &info->data.io;
  302. switch (info->cmd) {
  303. case DRV_CTL_IO_WR_CMD:
  304. bnx2_reg_wr_ind(bp, io->offset, io->data);
  305. break;
  306. case DRV_CTL_IO_RD_CMD:
  307. io->data = bnx2_reg_rd_ind(bp, io->offset);
  308. break;
  309. case DRV_CTL_CTX_WR_CMD:
  310. bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
  311. break;
  312. default:
  313. return -EINVAL;
  314. }
  315. return 0;
  316. }
  317. static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
  318. {
  319. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  320. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  321. int sb_id;
  322. if (bp->flags & BNX2_FLAG_USING_MSIX) {
  323. cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
  324. bnapi->cnic_present = 0;
  325. sb_id = bp->irq_nvecs;
  326. cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
  327. } else {
  328. cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
  329. bnapi->cnic_tag = bnapi->last_status_idx;
  330. bnapi->cnic_present = 1;
  331. sb_id = 0;
  332. cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
  333. }
  334. cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
  335. cp->irq_arr[0].status_blk = (void *)
  336. ((unsigned long) bnapi->status_blk.msi +
  337. (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
  338. cp->irq_arr[0].status_blk_num = sb_id;
  339. cp->num_irq = 1;
  340. }
  341. static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
  342. void *data)
  343. {
  344. struct bnx2 *bp = netdev_priv(dev);
  345. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  346. if (!ops)
  347. return -EINVAL;
  348. if (cp->drv_state & CNIC_DRV_STATE_REGD)
  349. return -EBUSY;
  350. if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
  351. return -ENODEV;
  352. bp->cnic_data = data;
  353. rcu_assign_pointer(bp->cnic_ops, ops);
  354. cp->num_irq = 0;
  355. cp->drv_state = CNIC_DRV_STATE_REGD;
  356. bnx2_setup_cnic_irq_info(bp);
  357. return 0;
  358. }
  359. static int bnx2_unregister_cnic(struct net_device *dev)
  360. {
  361. struct bnx2 *bp = netdev_priv(dev);
  362. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  363. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  364. mutex_lock(&bp->cnic_lock);
  365. cp->drv_state = 0;
  366. bnapi->cnic_present = 0;
  367. RCU_INIT_POINTER(bp->cnic_ops, NULL);
  368. mutex_unlock(&bp->cnic_lock);
  369. synchronize_rcu();
  370. return 0;
  371. }
  372. static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
  373. {
  374. struct bnx2 *bp = netdev_priv(dev);
  375. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  376. if (!cp->max_iscsi_conn)
  377. return NULL;
  378. cp->drv_owner = THIS_MODULE;
  379. cp->chip_id = bp->chip_id;
  380. cp->pdev = bp->pdev;
  381. cp->io_base = bp->regview;
  382. cp->drv_ctl = bnx2_drv_ctl;
  383. cp->drv_register_cnic = bnx2_register_cnic;
  384. cp->drv_unregister_cnic = bnx2_unregister_cnic;
  385. return cp;
  386. }
  387. static void
  388. bnx2_cnic_stop(struct bnx2 *bp)
  389. {
  390. struct cnic_ops *c_ops;
  391. struct cnic_ctl_info info;
  392. mutex_lock(&bp->cnic_lock);
  393. c_ops = rcu_dereference_protected(bp->cnic_ops,
  394. lockdep_is_held(&bp->cnic_lock));
  395. if (c_ops) {
  396. info.cmd = CNIC_CTL_STOP_CMD;
  397. c_ops->cnic_ctl(bp->cnic_data, &info);
  398. }
  399. mutex_unlock(&bp->cnic_lock);
  400. }
  401. static void
  402. bnx2_cnic_start(struct bnx2 *bp)
  403. {
  404. struct cnic_ops *c_ops;
  405. struct cnic_ctl_info info;
  406. mutex_lock(&bp->cnic_lock);
  407. c_ops = rcu_dereference_protected(bp->cnic_ops,
  408. lockdep_is_held(&bp->cnic_lock));
  409. if (c_ops) {
  410. if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
  411. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  412. bnapi->cnic_tag = bnapi->last_status_idx;
  413. }
  414. info.cmd = CNIC_CTL_START_CMD;
  415. c_ops->cnic_ctl(bp->cnic_data, &info);
  416. }
  417. mutex_unlock(&bp->cnic_lock);
  418. }
  419. #else
  420. static void
  421. bnx2_cnic_stop(struct bnx2 *bp)
  422. {
  423. }
  424. static void
  425. bnx2_cnic_start(struct bnx2 *bp)
  426. {
  427. }
  428. #endif
  429. static int
  430. bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
  431. {
  432. u32 val1;
  433. int i, ret;
  434. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  435. val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  436. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  437. BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  438. BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  439. udelay(40);
  440. }
  441. val1 = (bp->phy_addr << 21) | (reg << 16) |
  442. BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
  443. BNX2_EMAC_MDIO_COMM_START_BUSY;
  444. BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  445. for (i = 0; i < 50; i++) {
  446. udelay(10);
  447. val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
  448. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  449. udelay(5);
  450. val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
  451. val1 &= BNX2_EMAC_MDIO_COMM_DATA;
  452. break;
  453. }
  454. }
  455. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
  456. *val = 0x0;
  457. ret = -EBUSY;
  458. }
  459. else {
  460. *val = val1;
  461. ret = 0;
  462. }
  463. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  464. val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  465. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  466. BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  467. BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  468. udelay(40);
  469. }
  470. return ret;
  471. }
  472. static int
  473. bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
  474. {
  475. u32 val1;
  476. int i, ret;
  477. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  478. val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  479. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  480. BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  481. BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  482. udelay(40);
  483. }
  484. val1 = (bp->phy_addr << 21) | (reg << 16) | val |
  485. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
  486. BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
  487. BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  488. for (i = 0; i < 50; i++) {
  489. udelay(10);
  490. val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
  491. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  492. udelay(5);
  493. break;
  494. }
  495. }
  496. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
  497. ret = -EBUSY;
  498. else
  499. ret = 0;
  500. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  501. val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  502. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  503. BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  504. BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
  505. udelay(40);
  506. }
  507. return ret;
  508. }
  509. static void
  510. bnx2_disable_int(struct bnx2 *bp)
  511. {
  512. int i;
  513. struct bnx2_napi *bnapi;
  514. for (i = 0; i < bp->irq_nvecs; i++) {
  515. bnapi = &bp->bnx2_napi[i];
  516. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  517. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  518. }
  519. BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  520. }
  521. static void
  522. bnx2_enable_int(struct bnx2 *bp)
  523. {
  524. int i;
  525. struct bnx2_napi *bnapi;
  526. for (i = 0; i < bp->irq_nvecs; i++) {
  527. bnapi = &bp->bnx2_napi[i];
  528. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  529. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  530. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  531. bnapi->last_status_idx);
  532. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  533. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  534. bnapi->last_status_idx);
  535. }
  536. BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  537. }
  538. static void
  539. bnx2_disable_int_sync(struct bnx2 *bp)
  540. {
  541. int i;
  542. atomic_inc(&bp->intr_sem);
  543. if (!netif_running(bp->dev))
  544. return;
  545. bnx2_disable_int(bp);
  546. for (i = 0; i < bp->irq_nvecs; i++)
  547. synchronize_irq(bp->irq_tbl[i].vector);
  548. }
  549. static void
  550. bnx2_napi_disable(struct bnx2 *bp)
  551. {
  552. int i;
  553. for (i = 0; i < bp->irq_nvecs; i++)
  554. napi_disable(&bp->bnx2_napi[i].napi);
  555. }
  556. static void
  557. bnx2_napi_enable(struct bnx2 *bp)
  558. {
  559. int i;
  560. for (i = 0; i < bp->irq_nvecs; i++)
  561. napi_enable(&bp->bnx2_napi[i].napi);
  562. }
  563. static void
  564. bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
  565. {
  566. if (stop_cnic)
  567. bnx2_cnic_stop(bp);
  568. if (netif_running(bp->dev)) {
  569. bnx2_napi_disable(bp);
  570. netif_tx_disable(bp->dev);
  571. }
  572. bnx2_disable_int_sync(bp);
  573. netif_carrier_off(bp->dev); /* prevent tx timeout */
  574. }
  575. static void
  576. bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
  577. {
  578. if (atomic_dec_and_test(&bp->intr_sem)) {
  579. if (netif_running(bp->dev)) {
  580. netif_tx_wake_all_queues(bp->dev);
  581. spin_lock_bh(&bp->phy_lock);
  582. if (bp->link_up)
  583. netif_carrier_on(bp->dev);
  584. spin_unlock_bh(&bp->phy_lock);
  585. bnx2_napi_enable(bp);
  586. bnx2_enable_int(bp);
  587. if (start_cnic)
  588. bnx2_cnic_start(bp);
  589. }
  590. }
  591. }
  592. static void
  593. bnx2_free_tx_mem(struct bnx2 *bp)
  594. {
  595. int i;
  596. for (i = 0; i < bp->num_tx_rings; i++) {
  597. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  598. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  599. if (txr->tx_desc_ring) {
  600. dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
  601. txr->tx_desc_ring,
  602. txr->tx_desc_mapping);
  603. txr->tx_desc_ring = NULL;
  604. }
  605. kfree(txr->tx_buf_ring);
  606. txr->tx_buf_ring = NULL;
  607. }
  608. }
  609. static void
  610. bnx2_free_rx_mem(struct bnx2 *bp)
  611. {
  612. int i;
  613. for (i = 0; i < bp->num_rx_rings; i++) {
  614. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  615. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  616. int j;
  617. for (j = 0; j < bp->rx_max_ring; j++) {
  618. if (rxr->rx_desc_ring[j])
  619. dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
  620. rxr->rx_desc_ring[j],
  621. rxr->rx_desc_mapping[j]);
  622. rxr->rx_desc_ring[j] = NULL;
  623. }
  624. vfree(rxr->rx_buf_ring);
  625. rxr->rx_buf_ring = NULL;
  626. for (j = 0; j < bp->rx_max_pg_ring; j++) {
  627. if (rxr->rx_pg_desc_ring[j])
  628. dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
  629. rxr->rx_pg_desc_ring[j],
  630. rxr->rx_pg_desc_mapping[j]);
  631. rxr->rx_pg_desc_ring[j] = NULL;
  632. }
  633. vfree(rxr->rx_pg_ring);
  634. rxr->rx_pg_ring = NULL;
  635. }
  636. }
  637. static int
  638. bnx2_alloc_tx_mem(struct bnx2 *bp)
  639. {
  640. int i;
  641. for (i = 0; i < bp->num_tx_rings; i++) {
  642. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  643. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  644. txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
  645. if (!txr->tx_buf_ring)
  646. return -ENOMEM;
  647. txr->tx_desc_ring =
  648. dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
  649. &txr->tx_desc_mapping, GFP_KERNEL);
  650. if (!txr->tx_desc_ring)
  651. return -ENOMEM;
  652. }
  653. return 0;
  654. }
  655. static int
  656. bnx2_alloc_rx_mem(struct bnx2 *bp)
  657. {
  658. int i;
  659. for (i = 0; i < bp->num_rx_rings; i++) {
  660. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  661. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  662. int j;
  663. rxr->rx_buf_ring =
  664. vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring));
  665. if (!rxr->rx_buf_ring)
  666. return -ENOMEM;
  667. for (j = 0; j < bp->rx_max_ring; j++) {
  668. rxr->rx_desc_ring[j] =
  669. dma_alloc_coherent(&bp->pdev->dev,
  670. RXBD_RING_SIZE,
  671. &rxr->rx_desc_mapping[j],
  672. GFP_KERNEL);
  673. if (!rxr->rx_desc_ring[j])
  674. return -ENOMEM;
  675. }
  676. if (bp->rx_pg_ring_size) {
  677. rxr->rx_pg_ring =
  678. vzalloc(array_size(SW_RXPG_RING_SIZE,
  679. bp->rx_max_pg_ring));
  680. if (!rxr->rx_pg_ring)
  681. return -ENOMEM;
  682. }
  683. for (j = 0; j < bp->rx_max_pg_ring; j++) {
  684. rxr->rx_pg_desc_ring[j] =
  685. dma_alloc_coherent(&bp->pdev->dev,
  686. RXBD_RING_SIZE,
  687. &rxr->rx_pg_desc_mapping[j],
  688. GFP_KERNEL);
  689. if (!rxr->rx_pg_desc_ring[j])
  690. return -ENOMEM;
  691. }
  692. }
  693. return 0;
  694. }
  695. static void
  696. bnx2_free_stats_blk(struct net_device *dev)
  697. {
  698. struct bnx2 *bp = netdev_priv(dev);
  699. if (bp->status_blk) {
  700. dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
  701. bp->status_blk,
  702. bp->status_blk_mapping);
  703. bp->status_blk = NULL;
  704. bp->stats_blk = NULL;
  705. }
  706. }
  707. static int
  708. bnx2_alloc_stats_blk(struct net_device *dev)
  709. {
  710. int status_blk_size;
  711. void *status_blk;
  712. struct bnx2 *bp = netdev_priv(dev);
  713. /* Combine status and statistics blocks into one allocation. */
  714. status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
  715. if (bp->flags & BNX2_FLAG_MSIX_CAP)
  716. status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
  717. BNX2_SBLK_MSIX_ALIGN_SIZE);
  718. bp->status_stats_size = status_blk_size +
  719. sizeof(struct statistics_block);
  720. status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
  721. &bp->status_blk_mapping, GFP_KERNEL);
  722. if (!status_blk)
  723. return -ENOMEM;
  724. bp->status_blk = status_blk;
  725. bp->stats_blk = status_blk + status_blk_size;
  726. bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
  727. return 0;
  728. }
  729. static void
  730. bnx2_free_mem(struct bnx2 *bp)
  731. {
  732. int i;
  733. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  734. bnx2_free_tx_mem(bp);
  735. bnx2_free_rx_mem(bp);
  736. for (i = 0; i < bp->ctx_pages; i++) {
  737. if (bp->ctx_blk[i]) {
  738. dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,
  739. bp->ctx_blk[i],
  740. bp->ctx_blk_mapping[i]);
  741. bp->ctx_blk[i] = NULL;
  742. }
  743. }
  744. if (bnapi->status_blk.msi)
  745. bnapi->status_blk.msi = NULL;
  746. }
  747. static int
  748. bnx2_alloc_mem(struct bnx2 *bp)
  749. {
  750. int i, err;
  751. struct bnx2_napi *bnapi;
  752. bnapi = &bp->bnx2_napi[0];
  753. bnapi->status_blk.msi = bp->status_blk;
  754. bnapi->hw_tx_cons_ptr =
  755. &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
  756. bnapi->hw_rx_cons_ptr =
  757. &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
  758. if (bp->flags & BNX2_FLAG_MSIX_CAP) {
  759. for (i = 1; i < bp->irq_nvecs; i++) {
  760. struct status_block_msix *sblk;
  761. bnapi = &bp->bnx2_napi[i];
  762. sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
  763. bnapi->status_blk.msix = sblk;
  764. bnapi->hw_tx_cons_ptr =
  765. &sblk->status_tx_quick_consumer_index;
  766. bnapi->hw_rx_cons_ptr =
  767. &sblk->status_rx_quick_consumer_index;
  768. bnapi->int_num = i << 24;
  769. }
  770. }
  771. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  772. bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;
  773. if (bp->ctx_pages == 0)
  774. bp->ctx_pages = 1;
  775. for (i = 0; i < bp->ctx_pages; i++) {
  776. bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
  777. BNX2_PAGE_SIZE,
  778. &bp->ctx_blk_mapping[i],
  779. GFP_KERNEL);
  780. if (!bp->ctx_blk[i])
  781. goto alloc_mem_err;
  782. }
  783. }
  784. err = bnx2_alloc_rx_mem(bp);
  785. if (err)
  786. goto alloc_mem_err;
  787. err = bnx2_alloc_tx_mem(bp);
  788. if (err)
  789. goto alloc_mem_err;
  790. return 0;
  791. alloc_mem_err:
  792. bnx2_free_mem(bp);
  793. return -ENOMEM;
  794. }
  795. static void
  796. bnx2_report_fw_link(struct bnx2 *bp)
  797. {
  798. u32 fw_link_status = 0;
  799. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  800. return;
  801. if (bp->link_up) {
  802. u32 bmsr;
  803. switch (bp->line_speed) {
  804. case SPEED_10:
  805. if (bp->duplex == DUPLEX_HALF)
  806. fw_link_status = BNX2_LINK_STATUS_10HALF;
  807. else
  808. fw_link_status = BNX2_LINK_STATUS_10FULL;
  809. break;
  810. case SPEED_100:
  811. if (bp->duplex == DUPLEX_HALF)
  812. fw_link_status = BNX2_LINK_STATUS_100HALF;
  813. else
  814. fw_link_status = BNX2_LINK_STATUS_100FULL;
  815. break;
  816. case SPEED_1000:
  817. if (bp->duplex == DUPLEX_HALF)
  818. fw_link_status = BNX2_LINK_STATUS_1000HALF;
  819. else
  820. fw_link_status = BNX2_LINK_STATUS_1000FULL;
  821. break;
  822. case SPEED_2500:
  823. if (bp->duplex == DUPLEX_HALF)
  824. fw_link_status = BNX2_LINK_STATUS_2500HALF;
  825. else
  826. fw_link_status = BNX2_LINK_STATUS_2500FULL;
  827. break;
  828. }
  829. fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
  830. if (bp->autoneg) {
  831. fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
  832. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  833. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  834. if (!(bmsr & BMSR_ANEGCOMPLETE) ||
  835. bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
  836. fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
  837. else
  838. fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
  839. }
  840. }
  841. else
  842. fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
  843. bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
  844. }
  845. static char *
  846. bnx2_xceiver_str(struct bnx2 *bp)
  847. {
  848. return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
  849. ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
  850. "Copper");
  851. }
  852. static void
  853. bnx2_report_link(struct bnx2 *bp)
  854. {
  855. if (bp->link_up) {
  856. netif_carrier_on(bp->dev);
  857. netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
  858. bnx2_xceiver_str(bp),
  859. bp->line_speed,
  860. bp->duplex == DUPLEX_FULL ? "full" : "half");
  861. if (bp->flow_ctrl) {
  862. if (bp->flow_ctrl & FLOW_CTRL_RX) {
  863. pr_cont(", receive ");
  864. if (bp->flow_ctrl & FLOW_CTRL_TX)
  865. pr_cont("& transmit ");
  866. }
  867. else {
  868. pr_cont(", transmit ");
  869. }
  870. pr_cont("flow control ON");
  871. }
  872. pr_cont("\n");
  873. } else {
  874. netif_carrier_off(bp->dev);
  875. netdev_err(bp->dev, "NIC %s Link is Down\n",
  876. bnx2_xceiver_str(bp));
  877. }
  878. bnx2_report_fw_link(bp);
  879. }
  880. static void
  881. bnx2_resolve_flow_ctrl(struct bnx2 *bp)
  882. {
  883. u32 local_adv, remote_adv;
  884. bp->flow_ctrl = 0;
  885. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  886. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  887. if (bp->duplex == DUPLEX_FULL) {
  888. bp->flow_ctrl = bp->req_flow_ctrl;
  889. }
  890. return;
  891. }
  892. if (bp->duplex != DUPLEX_FULL) {
  893. return;
  894. }
  895. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  896. (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
  897. u32 val;
  898. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  899. if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
  900. bp->flow_ctrl |= FLOW_CTRL_TX;
  901. if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
  902. bp->flow_ctrl |= FLOW_CTRL_RX;
  903. return;
  904. }
  905. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  906. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  907. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  908. u32 new_local_adv = 0;
  909. u32 new_remote_adv = 0;
  910. if (local_adv & ADVERTISE_1000XPAUSE)
  911. new_local_adv |= ADVERTISE_PAUSE_CAP;
  912. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  913. new_local_adv |= ADVERTISE_PAUSE_ASYM;
  914. if (remote_adv & ADVERTISE_1000XPAUSE)
  915. new_remote_adv |= ADVERTISE_PAUSE_CAP;
  916. if (remote_adv & ADVERTISE_1000XPSE_ASYM)
  917. new_remote_adv |= ADVERTISE_PAUSE_ASYM;
  918. local_adv = new_local_adv;
  919. remote_adv = new_remote_adv;
  920. }
  921. /* See Table 28B-3 of 802.3ab-1999 spec. */
  922. if (local_adv & ADVERTISE_PAUSE_CAP) {
  923. if(local_adv & ADVERTISE_PAUSE_ASYM) {
  924. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  925. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  926. }
  927. else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
  928. bp->flow_ctrl = FLOW_CTRL_RX;
  929. }
  930. }
  931. else {
  932. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  933. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  934. }
  935. }
  936. }
  937. else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  938. if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
  939. (remote_adv & ADVERTISE_PAUSE_ASYM)) {
  940. bp->flow_ctrl = FLOW_CTRL_TX;
  941. }
  942. }
  943. }
  944. static int
  945. bnx2_5709s_linkup(struct bnx2 *bp)
  946. {
  947. u32 val, speed;
  948. bp->link_up = 1;
  949. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
  950. bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
  951. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  952. if ((bp->autoneg & AUTONEG_SPEED) == 0) {
  953. bp->line_speed = bp->req_line_speed;
  954. bp->duplex = bp->req_duplex;
  955. return 0;
  956. }
  957. speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
  958. switch (speed) {
  959. case MII_BNX2_GP_TOP_AN_SPEED_10:
  960. bp->line_speed = SPEED_10;
  961. break;
  962. case MII_BNX2_GP_TOP_AN_SPEED_100:
  963. bp->line_speed = SPEED_100;
  964. break;
  965. case MII_BNX2_GP_TOP_AN_SPEED_1G:
  966. case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
  967. bp->line_speed = SPEED_1000;
  968. break;
  969. case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
  970. bp->line_speed = SPEED_2500;
  971. break;
  972. }
  973. if (val & MII_BNX2_GP_TOP_AN_FD)
  974. bp->duplex = DUPLEX_FULL;
  975. else
  976. bp->duplex = DUPLEX_HALF;
  977. return 0;
  978. }
  979. static int
  980. bnx2_5708s_linkup(struct bnx2 *bp)
  981. {
  982. u32 val;
  983. bp->link_up = 1;
  984. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  985. switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
  986. case BCM5708S_1000X_STAT1_SPEED_10:
  987. bp->line_speed = SPEED_10;
  988. break;
  989. case BCM5708S_1000X_STAT1_SPEED_100:
  990. bp->line_speed = SPEED_100;
  991. break;
  992. case BCM5708S_1000X_STAT1_SPEED_1G:
  993. bp->line_speed = SPEED_1000;
  994. break;
  995. case BCM5708S_1000X_STAT1_SPEED_2G5:
  996. bp->line_speed = SPEED_2500;
  997. break;
  998. }
  999. if (val & BCM5708S_1000X_STAT1_FD)
  1000. bp->duplex = DUPLEX_FULL;
  1001. else
  1002. bp->duplex = DUPLEX_HALF;
  1003. return 0;
  1004. }
  1005. static int
  1006. bnx2_5706s_linkup(struct bnx2 *bp)
  1007. {
  1008. u32 bmcr, local_adv, remote_adv, common;
  1009. bp->link_up = 1;
  1010. bp->line_speed = SPEED_1000;
  1011. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1012. if (bmcr & BMCR_FULLDPLX) {
  1013. bp->duplex = DUPLEX_FULL;
  1014. }
  1015. else {
  1016. bp->duplex = DUPLEX_HALF;
  1017. }
  1018. if (!(bmcr & BMCR_ANENABLE)) {
  1019. return 0;
  1020. }
  1021. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  1022. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  1023. common = local_adv & remote_adv;
  1024. if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
  1025. if (common & ADVERTISE_1000XFULL) {
  1026. bp->duplex = DUPLEX_FULL;
  1027. }
  1028. else {
  1029. bp->duplex = DUPLEX_HALF;
  1030. }
  1031. }
  1032. return 0;
  1033. }
  1034. static int
  1035. bnx2_copper_linkup(struct bnx2 *bp)
  1036. {
  1037. u32 bmcr;
  1038. bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;
  1039. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1040. if (bmcr & BMCR_ANENABLE) {
  1041. u32 local_adv, remote_adv, common;
  1042. bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
  1043. bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
  1044. common = local_adv & (remote_adv >> 2);
  1045. if (common & ADVERTISE_1000FULL) {
  1046. bp->line_speed = SPEED_1000;
  1047. bp->duplex = DUPLEX_FULL;
  1048. }
  1049. else if (common & ADVERTISE_1000HALF) {
  1050. bp->line_speed = SPEED_1000;
  1051. bp->duplex = DUPLEX_HALF;
  1052. }
  1053. else {
  1054. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  1055. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  1056. common = local_adv & remote_adv;
  1057. if (common & ADVERTISE_100FULL) {
  1058. bp->line_speed = SPEED_100;
  1059. bp->duplex = DUPLEX_FULL;
  1060. }
  1061. else if (common & ADVERTISE_100HALF) {
  1062. bp->line_speed = SPEED_100;
  1063. bp->duplex = DUPLEX_HALF;
  1064. }
  1065. else if (common & ADVERTISE_10FULL) {
  1066. bp->line_speed = SPEED_10;
  1067. bp->duplex = DUPLEX_FULL;
  1068. }
  1069. else if (common & ADVERTISE_10HALF) {
  1070. bp->line_speed = SPEED_10;
  1071. bp->duplex = DUPLEX_HALF;
  1072. }
  1073. else {
  1074. bp->line_speed = 0;
  1075. bp->link_up = 0;
  1076. }
  1077. }
  1078. }
  1079. else {
  1080. if (bmcr & BMCR_SPEED100) {
  1081. bp->line_speed = SPEED_100;
  1082. }
  1083. else {
  1084. bp->line_speed = SPEED_10;
  1085. }
  1086. if (bmcr & BMCR_FULLDPLX) {
  1087. bp->duplex = DUPLEX_FULL;
  1088. }
  1089. else {
  1090. bp->duplex = DUPLEX_HALF;
  1091. }
  1092. }
  1093. if (bp->link_up) {
  1094. u32 ext_status;
  1095. bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);
  1096. if (ext_status & EXT_STATUS_MDIX)
  1097. bp->phy_flags |= BNX2_PHY_FLAG_MDIX;
  1098. }
  1099. return 0;
  1100. }
  1101. static void
  1102. bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
  1103. {
  1104. u32 val, rx_cid_addr = GET_CID_ADDR(cid);
  1105. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
  1106. val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
  1107. val |= 0x02 << 8;
  1108. if (bp->flow_ctrl & FLOW_CTRL_TX)
  1109. val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
  1110. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  1111. }
  1112. static void
  1113. bnx2_init_all_rx_contexts(struct bnx2 *bp)
  1114. {
  1115. int i;
  1116. u32 cid;
  1117. for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
  1118. if (i == 1)
  1119. cid = RX_RSS_CID;
  1120. bnx2_init_rx_context(bp, cid);
  1121. }
  1122. }
  1123. static void
  1124. bnx2_set_mac_link(struct bnx2 *bp)
  1125. {
  1126. u32 val;
  1127. BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
  1128. if (bp->link_up && (bp->line_speed == SPEED_1000) &&
  1129. (bp->duplex == DUPLEX_HALF)) {
  1130. BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
  1131. }
  1132. /* Configure the EMAC mode register. */
  1133. val = BNX2_RD(bp, BNX2_EMAC_MODE);
  1134. val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  1135. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  1136. BNX2_EMAC_MODE_25G_MODE);
  1137. if (bp->link_up) {
  1138. switch (bp->line_speed) {
  1139. case SPEED_10:
  1140. if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {
  1141. val |= BNX2_EMAC_MODE_PORT_MII_10M;
  1142. break;
  1143. }
  1144. /* fall through */
  1145. case SPEED_100:
  1146. val |= BNX2_EMAC_MODE_PORT_MII;
  1147. break;
  1148. case SPEED_2500:
  1149. val |= BNX2_EMAC_MODE_25G_MODE;
  1150. /* fall through */
  1151. case SPEED_1000:
  1152. val |= BNX2_EMAC_MODE_PORT_GMII;
  1153. break;
  1154. }
  1155. }
  1156. else {
  1157. val |= BNX2_EMAC_MODE_PORT_GMII;
  1158. }
  1159. /* Set the MAC to operate in the appropriate duplex mode. */
  1160. if (bp->duplex == DUPLEX_HALF)
  1161. val |= BNX2_EMAC_MODE_HALF_DUPLEX;
  1162. BNX2_WR(bp, BNX2_EMAC_MODE, val);
  1163. /* Enable/disable rx PAUSE. */
  1164. bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
  1165. if (bp->flow_ctrl & FLOW_CTRL_RX)
  1166. bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
  1167. BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
  1168. /* Enable/disable tx PAUSE. */
  1169. val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
  1170. val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
  1171. if (bp->flow_ctrl & FLOW_CTRL_TX)
  1172. val |= BNX2_EMAC_TX_MODE_FLOW_EN;
  1173. BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
  1174. /* Acknowledge the interrupt. */
  1175. BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
  1176. bnx2_init_all_rx_contexts(bp);
  1177. }
  1178. static void
  1179. bnx2_enable_bmsr1(struct bnx2 *bp)
  1180. {
  1181. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1182. (BNX2_CHIP(bp) == BNX2_CHIP_5709))
  1183. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1184. MII_BNX2_BLK_ADDR_GP_STATUS);
  1185. }
  1186. static void
  1187. bnx2_disable_bmsr1(struct bnx2 *bp)
  1188. {
  1189. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1190. (BNX2_CHIP(bp) == BNX2_CHIP_5709))
  1191. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1192. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1193. }
  1194. static int
  1195. bnx2_test_and_enable_2g5(struct bnx2 *bp)
  1196. {
  1197. u32 up1;
  1198. int ret = 1;
  1199. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1200. return 0;
  1201. if (bp->autoneg & AUTONEG_SPEED)
  1202. bp->advertising |= ADVERTISED_2500baseX_Full;
  1203. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  1204. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1205. bnx2_read_phy(bp, bp->mii_up1, &up1);
  1206. if (!(up1 & BCM5708S_UP1_2G5)) {
  1207. up1 |= BCM5708S_UP1_2G5;
  1208. bnx2_write_phy(bp, bp->mii_up1, up1);
  1209. ret = 0;
  1210. }
  1211. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  1212. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1213. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1214. return ret;
  1215. }
  1216. static int
  1217. bnx2_test_and_disable_2g5(struct bnx2 *bp)
  1218. {
  1219. u32 up1;
  1220. int ret = 0;
  1221. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1222. return 0;
  1223. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  1224. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1225. bnx2_read_phy(bp, bp->mii_up1, &up1);
  1226. if (up1 & BCM5708S_UP1_2G5) {
  1227. up1 &= ~BCM5708S_UP1_2G5;
  1228. bnx2_write_phy(bp, bp->mii_up1, up1);
  1229. ret = 1;
  1230. }
  1231. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  1232. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1233. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1234. return ret;
  1235. }
  1236. static void
  1237. bnx2_enable_forced_2g5(struct bnx2 *bp)
  1238. {
  1239. u32 uninitialized_var(bmcr);
  1240. int err;
  1241. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1242. return;
  1243. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  1244. u32 val;
  1245. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1246. MII_BNX2_BLK_ADDR_SERDES_DIG);
  1247. if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
  1248. val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
  1249. val |= MII_BNX2_SD_MISC1_FORCE |
  1250. MII_BNX2_SD_MISC1_FORCE_2_5G;
  1251. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
  1252. }
  1253. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1254. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1255. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1256. } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
  1257. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1258. if (!err)
  1259. bmcr |= BCM5708S_BMCR_FORCE_2500;
  1260. } else {
  1261. return;
  1262. }
  1263. if (err)
  1264. return;
  1265. if (bp->autoneg & AUTONEG_SPEED) {
  1266. bmcr &= ~BMCR_ANENABLE;
  1267. if (bp->req_duplex == DUPLEX_FULL)
  1268. bmcr |= BMCR_FULLDPLX;
  1269. }
  1270. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1271. }
  1272. static void
  1273. bnx2_disable_forced_2g5(struct bnx2 *bp)
  1274. {
  1275. u32 uninitialized_var(bmcr);
  1276. int err;
  1277. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1278. return;
  1279. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  1280. u32 val;
  1281. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1282. MII_BNX2_BLK_ADDR_SERDES_DIG);
  1283. if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
  1284. val &= ~MII_BNX2_SD_MISC1_FORCE;
  1285. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
  1286. }
  1287. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1288. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1289. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1290. } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
  1291. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1292. if (!err)
  1293. bmcr &= ~BCM5708S_BMCR_FORCE_2500;
  1294. } else {
  1295. return;
  1296. }
  1297. if (err)
  1298. return;
  1299. if (bp->autoneg & AUTONEG_SPEED)
  1300. bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
  1301. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1302. }
  1303. static void
  1304. bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
  1305. {
  1306. u32 val;
  1307. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
  1308. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
  1309. if (start)
  1310. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
  1311. else
  1312. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
  1313. }
  1314. static int
  1315. bnx2_set_link(struct bnx2 *bp)
  1316. {
  1317. u32 bmsr;
  1318. u8 link_up;
  1319. if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
  1320. bp->link_up = 1;
  1321. return 0;
  1322. }
  1323. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  1324. return 0;
  1325. link_up = bp->link_up;
  1326. bnx2_enable_bmsr1(bp);
  1327. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  1328. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  1329. bnx2_disable_bmsr1(bp);
  1330. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1331. (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {
  1332. u32 val, an_dbg;
  1333. if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
  1334. bnx2_5706s_force_link_dn(bp, 0);
  1335. bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
  1336. }
  1337. val = BNX2_RD(bp, BNX2_EMAC_STATUS);
  1338. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  1339. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  1340. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  1341. if ((val & BNX2_EMAC_STATUS_LINK) &&
  1342. !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
  1343. bmsr |= BMSR_LSTATUS;
  1344. else
  1345. bmsr &= ~BMSR_LSTATUS;
  1346. }
  1347. if (bmsr & BMSR_LSTATUS) {
  1348. bp->link_up = 1;
  1349. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1350. if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
  1351. bnx2_5706s_linkup(bp);
  1352. else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
  1353. bnx2_5708s_linkup(bp);
  1354. else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  1355. bnx2_5709s_linkup(bp);
  1356. }
  1357. else {
  1358. bnx2_copper_linkup(bp);
  1359. }
  1360. bnx2_resolve_flow_ctrl(bp);
  1361. }
  1362. else {
  1363. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1364. (bp->autoneg & AUTONEG_SPEED))
  1365. bnx2_disable_forced_2g5(bp);
  1366. if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
  1367. u32 bmcr;
  1368. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1369. bmcr |= BMCR_ANENABLE;
  1370. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1371. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  1372. }
  1373. bp->link_up = 0;
  1374. }
  1375. if (bp->link_up != link_up) {
  1376. bnx2_report_link(bp);
  1377. }
  1378. bnx2_set_mac_link(bp);
  1379. return 0;
  1380. }
  1381. static int
  1382. bnx2_reset_phy(struct bnx2 *bp)
  1383. {
  1384. int i;
  1385. u32 reg;
  1386. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
  1387. #define PHY_RESET_MAX_WAIT 100
  1388. for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
  1389. udelay(10);
  1390. bnx2_read_phy(bp, bp->mii_bmcr, &reg);
  1391. if (!(reg & BMCR_RESET)) {
  1392. udelay(20);
  1393. break;
  1394. }
  1395. }
  1396. if (i == PHY_RESET_MAX_WAIT) {
  1397. return -EBUSY;
  1398. }
  1399. return 0;
  1400. }
  1401. static u32
  1402. bnx2_phy_get_pause_adv(struct bnx2 *bp)
  1403. {
  1404. u32 adv = 0;
  1405. if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
  1406. (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
  1407. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1408. adv = ADVERTISE_1000XPAUSE;
  1409. }
  1410. else {
  1411. adv = ADVERTISE_PAUSE_CAP;
  1412. }
  1413. }
  1414. else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
  1415. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1416. adv = ADVERTISE_1000XPSE_ASYM;
  1417. }
  1418. else {
  1419. adv = ADVERTISE_PAUSE_ASYM;
  1420. }
  1421. }
  1422. else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
  1423. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1424. adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1425. }
  1426. else {
  1427. adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1428. }
  1429. }
  1430. return adv;
  1431. }
  1432. static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
  1433. static int
  1434. bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
  1435. __releases(&bp->phy_lock)
  1436. __acquires(&bp->phy_lock)
  1437. {
  1438. u32 speed_arg = 0, pause_adv;
  1439. pause_adv = bnx2_phy_get_pause_adv(bp);
  1440. if (bp->autoneg & AUTONEG_SPEED) {
  1441. speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
  1442. if (bp->advertising & ADVERTISED_10baseT_Half)
  1443. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
  1444. if (bp->advertising & ADVERTISED_10baseT_Full)
  1445. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
  1446. if (bp->advertising & ADVERTISED_100baseT_Half)
  1447. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
  1448. if (bp->advertising & ADVERTISED_100baseT_Full)
  1449. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
  1450. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1451. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
  1452. if (bp->advertising & ADVERTISED_2500baseX_Full)
  1453. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
  1454. } else {
  1455. if (bp->req_line_speed == SPEED_2500)
  1456. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
  1457. else if (bp->req_line_speed == SPEED_1000)
  1458. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
  1459. else if (bp->req_line_speed == SPEED_100) {
  1460. if (bp->req_duplex == DUPLEX_FULL)
  1461. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
  1462. else
  1463. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
  1464. } else if (bp->req_line_speed == SPEED_10) {
  1465. if (bp->req_duplex == DUPLEX_FULL)
  1466. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
  1467. else
  1468. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
  1469. }
  1470. }
  1471. if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
  1472. speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
  1473. if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
  1474. speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
  1475. if (port == PORT_TP)
  1476. speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
  1477. BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
  1478. bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
  1479. spin_unlock_bh(&bp->phy_lock);
  1480. bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
  1481. spin_lock_bh(&bp->phy_lock);
  1482. return 0;
  1483. }
  1484. static int
  1485. bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
  1486. __releases(&bp->phy_lock)
  1487. __acquires(&bp->phy_lock)
  1488. {
  1489. u32 adv, bmcr;
  1490. u32 new_adv = 0;
  1491. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  1492. return bnx2_setup_remote_phy(bp, port);
  1493. if (!(bp->autoneg & AUTONEG_SPEED)) {
  1494. u32 new_bmcr;
  1495. int force_link_down = 0;
  1496. if (bp->req_line_speed == SPEED_2500) {
  1497. if (!bnx2_test_and_enable_2g5(bp))
  1498. force_link_down = 1;
  1499. } else if (bp->req_line_speed == SPEED_1000) {
  1500. if (bnx2_test_and_disable_2g5(bp))
  1501. force_link_down = 1;
  1502. }
  1503. bnx2_read_phy(bp, bp->mii_adv, &adv);
  1504. adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
  1505. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1506. new_bmcr = bmcr & ~BMCR_ANENABLE;
  1507. new_bmcr |= BMCR_SPEED1000;
  1508. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  1509. if (bp->req_line_speed == SPEED_2500)
  1510. bnx2_enable_forced_2g5(bp);
  1511. else if (bp->req_line_speed == SPEED_1000) {
  1512. bnx2_disable_forced_2g5(bp);
  1513. new_bmcr &= ~0x2000;
  1514. }
  1515. } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
  1516. if (bp->req_line_speed == SPEED_2500)
  1517. new_bmcr |= BCM5708S_BMCR_FORCE_2500;
  1518. else
  1519. new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
  1520. }
  1521. if (bp->req_duplex == DUPLEX_FULL) {
  1522. adv |= ADVERTISE_1000XFULL;
  1523. new_bmcr |= BMCR_FULLDPLX;
  1524. }
  1525. else {
  1526. adv |= ADVERTISE_1000XHALF;
  1527. new_bmcr &= ~BMCR_FULLDPLX;
  1528. }
  1529. if ((new_bmcr != bmcr) || (force_link_down)) {
  1530. /* Force a link down visible on the other side */
  1531. if (bp->link_up) {
  1532. bnx2_write_phy(bp, bp->mii_adv, adv &
  1533. ~(ADVERTISE_1000XFULL |
  1534. ADVERTISE_1000XHALF));
  1535. bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
  1536. BMCR_ANRESTART | BMCR_ANENABLE);
  1537. bp->link_up = 0;
  1538. netif_carrier_off(bp->dev);
  1539. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1540. bnx2_report_link(bp);
  1541. }
  1542. bnx2_write_phy(bp, bp->mii_adv, adv);
  1543. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1544. } else {
  1545. bnx2_resolve_flow_ctrl(bp);
  1546. bnx2_set_mac_link(bp);
  1547. }
  1548. return 0;
  1549. }
  1550. bnx2_test_and_enable_2g5(bp);
  1551. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1552. new_adv |= ADVERTISE_1000XFULL;
  1553. new_adv |= bnx2_phy_get_pause_adv(bp);
  1554. bnx2_read_phy(bp, bp->mii_adv, &adv);
  1555. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1556. bp->serdes_an_pending = 0;
  1557. if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
  1558. /* Force a link down visible on the other side */
  1559. if (bp->link_up) {
  1560. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  1561. spin_unlock_bh(&bp->phy_lock);
  1562. msleep(20);
  1563. spin_lock_bh(&bp->phy_lock);
  1564. }
  1565. bnx2_write_phy(bp, bp->mii_adv, new_adv);
  1566. bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
  1567. BMCR_ANENABLE);
  1568. /* Speed up link-up time when the link partner
  1569. * does not autonegotiate which is very common
  1570. * in blade servers. Some blade servers use
  1571. * IPMI for kerboard input and it's important
  1572. * to minimize link disruptions. Autoneg. involves
  1573. * exchanging base pages plus 3 next pages and
  1574. * normally completes in about 120 msec.
  1575. */
  1576. bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
  1577. bp->serdes_an_pending = 1;
  1578. mod_timer(&bp->timer, jiffies + bp->current_interval);
  1579. } else {
  1580. bnx2_resolve_flow_ctrl(bp);
  1581. bnx2_set_mac_link(bp);
  1582. }
  1583. return 0;
  1584. }
  1585. #define ETHTOOL_ALL_FIBRE_SPEED \
  1586. (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
  1587. (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
  1588. (ADVERTISED_1000baseT_Full)
  1589. #define ETHTOOL_ALL_COPPER_SPEED \
  1590. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
  1591. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
  1592. ADVERTISED_1000baseT_Full)
  1593. #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
  1594. ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
  1595. #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
  1596. static void
  1597. bnx2_set_default_remote_link(struct bnx2 *bp)
  1598. {
  1599. u32 link;
  1600. if (bp->phy_port == PORT_TP)
  1601. link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
  1602. else
  1603. link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
  1604. if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
  1605. bp->req_line_speed = 0;
  1606. bp->autoneg |= AUTONEG_SPEED;
  1607. bp->advertising = ADVERTISED_Autoneg;
  1608. if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
  1609. bp->advertising |= ADVERTISED_10baseT_Half;
  1610. if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
  1611. bp->advertising |= ADVERTISED_10baseT_Full;
  1612. if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
  1613. bp->advertising |= ADVERTISED_100baseT_Half;
  1614. if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
  1615. bp->advertising |= ADVERTISED_100baseT_Full;
  1616. if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
  1617. bp->advertising |= ADVERTISED_1000baseT_Full;
  1618. if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
  1619. bp->advertising |= ADVERTISED_2500baseX_Full;
  1620. } else {
  1621. bp->autoneg = 0;
  1622. bp->advertising = 0;
  1623. bp->req_duplex = DUPLEX_FULL;
  1624. if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
  1625. bp->req_line_speed = SPEED_10;
  1626. if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
  1627. bp->req_duplex = DUPLEX_HALF;
  1628. }
  1629. if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
  1630. bp->req_line_speed = SPEED_100;
  1631. if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
  1632. bp->req_duplex = DUPLEX_HALF;
  1633. }
  1634. if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
  1635. bp->req_line_speed = SPEED_1000;
  1636. if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
  1637. bp->req_line_speed = SPEED_2500;
  1638. }
  1639. }
  1640. static void
  1641. bnx2_set_default_link(struct bnx2 *bp)
  1642. {
  1643. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  1644. bnx2_set_default_remote_link(bp);
  1645. return;
  1646. }
  1647. bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
  1648. bp->req_line_speed = 0;
  1649. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1650. u32 reg;
  1651. bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
  1652. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
  1653. reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
  1654. if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
  1655. bp->autoneg = 0;
  1656. bp->req_line_speed = bp->line_speed = SPEED_1000;
  1657. bp->req_duplex = DUPLEX_FULL;
  1658. }
  1659. } else
  1660. bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
  1661. }
  1662. static void
  1663. bnx2_send_heart_beat(struct bnx2 *bp)
  1664. {
  1665. u32 msg;
  1666. u32 addr;
  1667. spin_lock(&bp->indirect_lock);
  1668. msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
  1669. addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
  1670. BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
  1671. BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
  1672. spin_unlock(&bp->indirect_lock);
  1673. }
  1674. static void
  1675. bnx2_remote_phy_event(struct bnx2 *bp)
  1676. {
  1677. u32 msg;
  1678. u8 link_up = bp->link_up;
  1679. u8 old_port;
  1680. msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
  1681. if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
  1682. bnx2_send_heart_beat(bp);
  1683. msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
  1684. if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
  1685. bp->link_up = 0;
  1686. else {
  1687. u32 speed;
  1688. bp->link_up = 1;
  1689. speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
  1690. bp->duplex = DUPLEX_FULL;
  1691. switch (speed) {
  1692. case BNX2_LINK_STATUS_10HALF:
  1693. bp->duplex = DUPLEX_HALF;
  1694. /* fall through */
  1695. case BNX2_LINK_STATUS_10FULL:
  1696. bp->line_speed = SPEED_10;
  1697. break;
  1698. case BNX2_LINK_STATUS_100HALF:
  1699. bp->duplex = DUPLEX_HALF;
  1700. /* fall through */
  1701. case BNX2_LINK_STATUS_100BASE_T4:
  1702. case BNX2_LINK_STATUS_100FULL:
  1703. bp->line_speed = SPEED_100;
  1704. break;
  1705. case BNX2_LINK_STATUS_1000HALF:
  1706. bp->duplex = DUPLEX_HALF;
  1707. /* fall through */
  1708. case BNX2_LINK_STATUS_1000FULL:
  1709. bp->line_speed = SPEED_1000;
  1710. break;
  1711. case BNX2_LINK_STATUS_2500HALF:
  1712. bp->duplex = DUPLEX_HALF;
  1713. /* fall through */
  1714. case BNX2_LINK_STATUS_2500FULL:
  1715. bp->line_speed = SPEED_2500;
  1716. break;
  1717. default:
  1718. bp->line_speed = 0;
  1719. break;
  1720. }
  1721. bp->flow_ctrl = 0;
  1722. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  1723. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  1724. if (bp->duplex == DUPLEX_FULL)
  1725. bp->flow_ctrl = bp->req_flow_ctrl;
  1726. } else {
  1727. if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
  1728. bp->flow_ctrl |= FLOW_CTRL_TX;
  1729. if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
  1730. bp->flow_ctrl |= FLOW_CTRL_RX;
  1731. }
  1732. old_port = bp->phy_port;
  1733. if (msg & BNX2_LINK_STATUS_SERDES_LINK)
  1734. bp->phy_port = PORT_FIBRE;
  1735. else
  1736. bp->phy_port = PORT_TP;
  1737. if (old_port != bp->phy_port)
  1738. bnx2_set_default_link(bp);
  1739. }
  1740. if (bp->link_up != link_up)
  1741. bnx2_report_link(bp);
  1742. bnx2_set_mac_link(bp);
  1743. }
  1744. static int
  1745. bnx2_set_remote_link(struct bnx2 *bp)
  1746. {
  1747. u32 evt_code;
  1748. evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
  1749. switch (evt_code) {
  1750. case BNX2_FW_EVT_CODE_LINK_EVENT:
  1751. bnx2_remote_phy_event(bp);
  1752. break;
  1753. case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
  1754. default:
  1755. bnx2_send_heart_beat(bp);
  1756. break;
  1757. }
  1758. return 0;
  1759. }
  1760. static int
  1761. bnx2_setup_copper_phy(struct bnx2 *bp)
  1762. __releases(&bp->phy_lock)
  1763. __acquires(&bp->phy_lock)
  1764. {
  1765. u32 bmcr, adv_reg, new_adv = 0;
  1766. u32 new_bmcr;
  1767. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1768. bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
  1769. adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
  1770. ADVERTISE_PAUSE_ASYM);
  1771. new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);
  1772. if (bp->autoneg & AUTONEG_SPEED) {
  1773. u32 adv1000_reg;
  1774. u32 new_adv1000 = 0;
  1775. new_adv |= bnx2_phy_get_pause_adv(bp);
  1776. bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
  1777. adv1000_reg &= PHY_ALL_1000_SPEED;
  1778. new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
  1779. if ((adv1000_reg != new_adv1000) ||
  1780. (adv_reg != new_adv) ||
  1781. ((bmcr & BMCR_ANENABLE) == 0)) {
  1782. bnx2_write_phy(bp, bp->mii_adv, new_adv);
  1783. bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
  1784. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
  1785. BMCR_ANENABLE);
  1786. }
  1787. else if (bp->link_up) {
  1788. /* Flow ctrl may have changed from auto to forced */
  1789. /* or vice-versa. */
  1790. bnx2_resolve_flow_ctrl(bp);
  1791. bnx2_set_mac_link(bp);
  1792. }
  1793. return 0;
  1794. }
  1795. /* advertise nothing when forcing speed */
  1796. if (adv_reg != new_adv)
  1797. bnx2_write_phy(bp, bp->mii_adv, new_adv);
  1798. new_bmcr = 0;
  1799. if (bp->req_line_speed == SPEED_100) {
  1800. new_bmcr |= BMCR_SPEED100;
  1801. }
  1802. if (bp->req_duplex == DUPLEX_FULL) {
  1803. new_bmcr |= BMCR_FULLDPLX;
  1804. }
  1805. if (new_bmcr != bmcr) {
  1806. u32 bmsr;
  1807. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1808. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1809. if (bmsr & BMSR_LSTATUS) {
  1810. /* Force link down */
  1811. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  1812. spin_unlock_bh(&bp->phy_lock);
  1813. msleep(50);
  1814. spin_lock_bh(&bp->phy_lock);
  1815. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1816. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1817. }
  1818. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1819. /* Normally, the new speed is setup after the link has
  1820. * gone down and up again. In some cases, link will not go
  1821. * down so we need to set up the new speed here.
  1822. */
  1823. if (bmsr & BMSR_LSTATUS) {
  1824. bp->line_speed = bp->req_line_speed;
  1825. bp->duplex = bp->req_duplex;
  1826. bnx2_resolve_flow_ctrl(bp);
  1827. bnx2_set_mac_link(bp);
  1828. }
  1829. } else {
  1830. bnx2_resolve_flow_ctrl(bp);
  1831. bnx2_set_mac_link(bp);
  1832. }
  1833. return 0;
  1834. }
  1835. static int
  1836. bnx2_setup_phy(struct bnx2 *bp, u8 port)
  1837. __releases(&bp->phy_lock)
  1838. __acquires(&bp->phy_lock)
  1839. {
  1840. if (bp->loopback == MAC_LOOPBACK)
  1841. return 0;
  1842. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1843. return bnx2_setup_serdes_phy(bp, port);
  1844. }
  1845. else {
  1846. return bnx2_setup_copper_phy(bp);
  1847. }
  1848. }
  1849. static int
  1850. bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
  1851. {
  1852. u32 val;
  1853. bp->mii_bmcr = MII_BMCR + 0x10;
  1854. bp->mii_bmsr = MII_BMSR + 0x10;
  1855. bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
  1856. bp->mii_adv = MII_ADVERTISE + 0x10;
  1857. bp->mii_lpa = MII_LPA + 0x10;
  1858. bp->mii_up1 = MII_BNX2_OVER1G_UP1;
  1859. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
  1860. bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
  1861. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1862. if (reset_phy)
  1863. bnx2_reset_phy(bp);
  1864. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
  1865. bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
  1866. val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
  1867. val |= MII_BNX2_SD_1000XCTL1_FIBER;
  1868. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
  1869. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1870. bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
  1871. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
  1872. val |= BCM5708S_UP1_2G5;
  1873. else
  1874. val &= ~BCM5708S_UP1_2G5;
  1875. bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
  1876. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
  1877. bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
  1878. val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
  1879. bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
  1880. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
  1881. val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
  1882. MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
  1883. bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
  1884. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1885. return 0;
  1886. }
  1887. static int
  1888. bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
  1889. {
  1890. u32 val;
  1891. if (reset_phy)
  1892. bnx2_reset_phy(bp);
  1893. bp->mii_up1 = BCM5708S_UP1;
  1894. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
  1895. bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
  1896. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1897. bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
  1898. val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
  1899. bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
  1900. bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
  1901. val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
  1902. bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
  1903. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
  1904. bnx2_read_phy(bp, BCM5708S_UP1, &val);
  1905. val |= BCM5708S_UP1_2G5;
  1906. bnx2_write_phy(bp, BCM5708S_UP1, val);
  1907. }
  1908. if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
  1909. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
  1910. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {
  1911. /* increase tx signal amplitude */
  1912. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1913. BCM5708S_BLK_ADDR_TX_MISC);
  1914. bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
  1915. val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
  1916. bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
  1917. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1918. }
  1919. val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
  1920. BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
  1921. if (val) {
  1922. u32 is_backplane;
  1923. is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
  1924. if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
  1925. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1926. BCM5708S_BLK_ADDR_TX_MISC);
  1927. bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
  1928. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1929. BCM5708S_BLK_ADDR_DIG);
  1930. }
  1931. }
  1932. return 0;
  1933. }
  1934. static int
  1935. bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
  1936. {
  1937. if (reset_phy)
  1938. bnx2_reset_phy(bp);
  1939. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  1940. if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
  1941. BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
  1942. if (bp->dev->mtu > ETH_DATA_LEN) {
  1943. u32 val;
  1944. /* Set extended packet length bit */
  1945. bnx2_write_phy(bp, 0x18, 0x7);
  1946. bnx2_read_phy(bp, 0x18, &val);
  1947. bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
  1948. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1949. bnx2_read_phy(bp, 0x1c, &val);
  1950. bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
  1951. }
  1952. else {
  1953. u32 val;
  1954. bnx2_write_phy(bp, 0x18, 0x7);
  1955. bnx2_read_phy(bp, 0x18, &val);
  1956. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  1957. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1958. bnx2_read_phy(bp, 0x1c, &val);
  1959. bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
  1960. }
  1961. return 0;
  1962. }
  1963. static int
  1964. bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
  1965. {
  1966. u32 val;
  1967. if (reset_phy)
  1968. bnx2_reset_phy(bp);
  1969. if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
  1970. bnx2_write_phy(bp, 0x18, 0x0c00);
  1971. bnx2_write_phy(bp, 0x17, 0x000a);
  1972. bnx2_write_phy(bp, 0x15, 0x310b);
  1973. bnx2_write_phy(bp, 0x17, 0x201f);
  1974. bnx2_write_phy(bp, 0x15, 0x9506);
  1975. bnx2_write_phy(bp, 0x17, 0x401f);
  1976. bnx2_write_phy(bp, 0x15, 0x14e2);
  1977. bnx2_write_phy(bp, 0x18, 0x0400);
  1978. }
  1979. if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
  1980. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
  1981. MII_BNX2_DSP_EXPAND_REG | 0x8);
  1982. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
  1983. val &= ~(1 << 8);
  1984. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
  1985. }
  1986. if (bp->dev->mtu > ETH_DATA_LEN) {
  1987. /* Set extended packet length bit */
  1988. bnx2_write_phy(bp, 0x18, 0x7);
  1989. bnx2_read_phy(bp, 0x18, &val);
  1990. bnx2_write_phy(bp, 0x18, val | 0x4000);
  1991. bnx2_read_phy(bp, 0x10, &val);
  1992. bnx2_write_phy(bp, 0x10, val | 0x1);
  1993. }
  1994. else {
  1995. bnx2_write_phy(bp, 0x18, 0x7);
  1996. bnx2_read_phy(bp, 0x18, &val);
  1997. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  1998. bnx2_read_phy(bp, 0x10, &val);
  1999. bnx2_write_phy(bp, 0x10, val & ~0x1);
  2000. }
  2001. /* ethernet@wirespeed */
  2002. bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);
  2003. bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);
  2004. val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED;
  2005. /* auto-mdix */
  2006. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  2007. val |= AUX_CTL_MISC_CTL_AUTOMDIX;
  2008. bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
  2009. return 0;
  2010. }
  2011. static int
  2012. bnx2_init_phy(struct bnx2 *bp, int reset_phy)
  2013. __releases(&bp->phy_lock)
  2014. __acquires(&bp->phy_lock)
  2015. {
  2016. u32 val;
  2017. int rc = 0;
  2018. bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
  2019. bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
  2020. bp->mii_bmcr = MII_BMCR;
  2021. bp->mii_bmsr = MII_BMSR;
  2022. bp->mii_bmsr1 = MII_BMSR;
  2023. bp->mii_adv = MII_ADVERTISE;
  2024. bp->mii_lpa = MII_LPA;
  2025. BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  2026. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  2027. goto setup_phy;
  2028. bnx2_read_phy(bp, MII_PHYSID1, &val);
  2029. bp->phy_id = val << 16;
  2030. bnx2_read_phy(bp, MII_PHYSID2, &val);
  2031. bp->phy_id |= val & 0xffff;
  2032. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  2033. if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
  2034. rc = bnx2_init_5706s_phy(bp, reset_phy);
  2035. else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
  2036. rc = bnx2_init_5708s_phy(bp, reset_phy);
  2037. else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  2038. rc = bnx2_init_5709s_phy(bp, reset_phy);
  2039. }
  2040. else {
  2041. rc = bnx2_init_copper_phy(bp, reset_phy);
  2042. }
  2043. setup_phy:
  2044. if (!rc)
  2045. rc = bnx2_setup_phy(bp, bp->phy_port);
  2046. return rc;
  2047. }
  2048. static int
  2049. bnx2_set_mac_loopback(struct bnx2 *bp)
  2050. {
  2051. u32 mac_mode;
  2052. mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
  2053. mac_mode &= ~BNX2_EMAC_MODE_PORT;
  2054. mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
  2055. BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
  2056. bp->link_up = 1;
  2057. return 0;
  2058. }
  2059. static int bnx2_test_link(struct bnx2 *);
  2060. static int
  2061. bnx2_set_phy_loopback(struct bnx2 *bp)
  2062. {
  2063. u32 mac_mode;
  2064. int rc, i;
  2065. spin_lock_bh(&bp->phy_lock);
  2066. rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
  2067. BMCR_SPEED1000);
  2068. spin_unlock_bh(&bp->phy_lock);
  2069. if (rc)
  2070. return rc;
  2071. for (i = 0; i < 10; i++) {
  2072. if (bnx2_test_link(bp) == 0)
  2073. break;
  2074. msleep(100);
  2075. }
  2076. mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
  2077. mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  2078. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  2079. BNX2_EMAC_MODE_25G_MODE);
  2080. mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
  2081. BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
  2082. bp->link_up = 1;
  2083. return 0;
  2084. }
  2085. static void
  2086. bnx2_dump_mcp_state(struct bnx2 *bp)
  2087. {
  2088. struct net_device *dev = bp->dev;
  2089. u32 mcp_p0, mcp_p1;
  2090. netdev_err(dev, "<--- start MCP states dump --->\n");
  2091. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  2092. mcp_p0 = BNX2_MCP_STATE_P0;
  2093. mcp_p1 = BNX2_MCP_STATE_P1;
  2094. } else {
  2095. mcp_p0 = BNX2_MCP_STATE_P0_5708;
  2096. mcp_p1 = BNX2_MCP_STATE_P1_5708;
  2097. }
  2098. netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
  2099. bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
  2100. netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
  2101. bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
  2102. bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
  2103. bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
  2104. netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
  2105. bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
  2106. bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
  2107. bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
  2108. netdev_err(dev, "DEBUG: shmem states:\n");
  2109. netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
  2110. bnx2_shmem_rd(bp, BNX2_DRV_MB),
  2111. bnx2_shmem_rd(bp, BNX2_FW_MB),
  2112. bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
  2113. pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
  2114. netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
  2115. bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
  2116. bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
  2117. pr_cont(" condition[%08x]\n",
  2118. bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
  2119. DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
  2120. DP_SHMEM_LINE(bp, 0x3cc);
  2121. DP_SHMEM_LINE(bp, 0x3dc);
  2122. DP_SHMEM_LINE(bp, 0x3ec);
  2123. netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
  2124. netdev_err(dev, "<--- end MCP states dump --->\n");
  2125. }
  2126. static int
  2127. bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
  2128. {
  2129. int i;
  2130. u32 val;
  2131. bp->fw_wr_seq++;
  2132. msg_data |= bp->fw_wr_seq;
  2133. bp->fw_last_msg = msg_data;
  2134. bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
  2135. if (!ack)
  2136. return 0;
  2137. /* wait for an acknowledgement. */
  2138. for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
  2139. msleep(10);
  2140. val = bnx2_shmem_rd(bp, BNX2_FW_MB);
  2141. if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
  2142. break;
  2143. }
  2144. if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
  2145. return 0;
  2146. /* If we timed out, inform the firmware that this is the case. */
  2147. if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
  2148. msg_data &= ~BNX2_DRV_MSG_CODE;
  2149. msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
  2150. bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
  2151. if (!silent) {
  2152. pr_err("fw sync timeout, reset code = %x\n", msg_data);
  2153. bnx2_dump_mcp_state(bp);
  2154. }
  2155. return -EBUSY;
  2156. }
  2157. if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
  2158. return -EIO;
  2159. return 0;
  2160. }
  2161. static int
  2162. bnx2_init_5709_context(struct bnx2 *bp)
  2163. {
  2164. int i, ret = 0;
  2165. u32 val;
  2166. val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
  2167. val |= (BNX2_PAGE_BITS - 8) << 16;
  2168. BNX2_WR(bp, BNX2_CTX_COMMAND, val);
  2169. for (i = 0; i < 10; i++) {
  2170. val = BNX2_RD(bp, BNX2_CTX_COMMAND);
  2171. if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
  2172. break;
  2173. udelay(2);
  2174. }
  2175. if (val & BNX2_CTX_COMMAND_MEM_INIT)
  2176. return -EBUSY;
  2177. for (i = 0; i < bp->ctx_pages; i++) {
  2178. int j;
  2179. if (bp->ctx_blk[i])
  2180. memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);
  2181. else
  2182. return -ENOMEM;
  2183. BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2184. (bp->ctx_blk_mapping[i] & 0xffffffff) |
  2185. BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
  2186. BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2187. (u64) bp->ctx_blk_mapping[i] >> 32);
  2188. BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
  2189. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2190. for (j = 0; j < 10; j++) {
  2191. val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2192. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2193. break;
  2194. udelay(5);
  2195. }
  2196. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2197. ret = -EBUSY;
  2198. break;
  2199. }
  2200. }
  2201. return ret;
  2202. }
  2203. static void
  2204. bnx2_init_context(struct bnx2 *bp)
  2205. {
  2206. u32 vcid;
  2207. vcid = 96;
  2208. while (vcid) {
  2209. u32 vcid_addr, pcid_addr, offset;
  2210. int i;
  2211. vcid--;
  2212. if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
  2213. u32 new_vcid;
  2214. vcid_addr = GET_PCID_ADDR(vcid);
  2215. if (vcid & 0x8) {
  2216. new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
  2217. }
  2218. else {
  2219. new_vcid = vcid;
  2220. }
  2221. pcid_addr = GET_PCID_ADDR(new_vcid);
  2222. }
  2223. else {
  2224. vcid_addr = GET_CID_ADDR(vcid);
  2225. pcid_addr = vcid_addr;
  2226. }
  2227. for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
  2228. vcid_addr += (i << PHY_CTX_SHIFT);
  2229. pcid_addr += (i << PHY_CTX_SHIFT);
  2230. BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
  2231. BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
  2232. /* Zero out the context. */
  2233. for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
  2234. bnx2_ctx_wr(bp, vcid_addr, offset, 0);
  2235. }
  2236. }
  2237. }
  2238. static int
  2239. bnx2_alloc_bad_rbuf(struct bnx2 *bp)
  2240. {
  2241. u16 *good_mbuf;
  2242. u32 good_mbuf_cnt;
  2243. u32 val;
  2244. good_mbuf = kmalloc_array(512, sizeof(u16), GFP_KERNEL);
  2245. if (!good_mbuf)
  2246. return -ENOMEM;
  2247. BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  2248. BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
  2249. good_mbuf_cnt = 0;
  2250. /* Allocate a bunch of mbufs and save the good ones in an array. */
  2251. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
  2252. while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
  2253. bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
  2254. BNX2_RBUF_COMMAND_ALLOC_REQ);
  2255. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
  2256. val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
  2257. /* The addresses with Bit 9 set are bad memory blocks. */
  2258. if (!(val & (1 << 9))) {
  2259. good_mbuf[good_mbuf_cnt] = (u16) val;
  2260. good_mbuf_cnt++;
  2261. }
  2262. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
  2263. }
  2264. /* Free the good ones back to the mbuf pool thus discarding
  2265. * all the bad ones. */
  2266. while (good_mbuf_cnt) {
  2267. good_mbuf_cnt--;
  2268. val = good_mbuf[good_mbuf_cnt];
  2269. val = (val << 9) | val | 1;
  2270. bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
  2271. }
  2272. kfree(good_mbuf);
  2273. return 0;
  2274. }
  2275. static void
  2276. bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
  2277. {
  2278. u32 val;
  2279. val = (mac_addr[0] << 8) | mac_addr[1];
  2280. BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
  2281. val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
  2282. (mac_addr[4] << 8) | mac_addr[5];
  2283. BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
  2284. }
  2285. static inline int
  2286. bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
  2287. {
  2288. dma_addr_t mapping;
  2289. struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
  2290. struct bnx2_rx_bd *rxbd =
  2291. &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
  2292. struct page *page = alloc_page(gfp);
  2293. if (!page)
  2294. return -ENOMEM;
  2295. mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
  2296. PCI_DMA_FROMDEVICE);
  2297. if (dma_mapping_error(&bp->pdev->dev, mapping)) {
  2298. __free_page(page);
  2299. return -EIO;
  2300. }
  2301. rx_pg->page = page;
  2302. dma_unmap_addr_set(rx_pg, mapping, mapping);
  2303. rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
  2304. rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  2305. return 0;
  2306. }
  2307. static void
  2308. bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
  2309. {
  2310. struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
  2311. struct page *page = rx_pg->page;
  2312. if (!page)
  2313. return;
  2314. dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
  2315. PAGE_SIZE, PCI_DMA_FROMDEVICE);
  2316. __free_page(page);
  2317. rx_pg->page = NULL;
  2318. }
  2319. static inline int
  2320. bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
  2321. {
  2322. u8 *data;
  2323. struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index];
  2324. dma_addr_t mapping;
  2325. struct bnx2_rx_bd *rxbd =
  2326. &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
  2327. data = kmalloc(bp->rx_buf_size, gfp);
  2328. if (!data)
  2329. return -ENOMEM;
  2330. mapping = dma_map_single(&bp->pdev->dev,
  2331. get_l2_fhdr(data),
  2332. bp->rx_buf_use_size,
  2333. PCI_DMA_FROMDEVICE);
  2334. if (dma_mapping_error(&bp->pdev->dev, mapping)) {
  2335. kfree(data);
  2336. return -EIO;
  2337. }
  2338. rx_buf->data = data;
  2339. dma_unmap_addr_set(rx_buf, mapping, mapping);
  2340. rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
  2341. rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  2342. rxr->rx_prod_bseq += bp->rx_buf_use_size;
  2343. return 0;
  2344. }
  2345. static int
  2346. bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
  2347. {
  2348. struct status_block *sblk = bnapi->status_blk.msi;
  2349. u32 new_link_state, old_link_state;
  2350. int is_set = 1;
  2351. new_link_state = sblk->status_attn_bits & event;
  2352. old_link_state = sblk->status_attn_bits_ack & event;
  2353. if (new_link_state != old_link_state) {
  2354. if (new_link_state)
  2355. BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
  2356. else
  2357. BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
  2358. } else
  2359. is_set = 0;
  2360. return is_set;
  2361. }
  2362. static void
  2363. bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2364. {
  2365. spin_lock(&bp->phy_lock);
  2366. if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
  2367. bnx2_set_link(bp);
  2368. if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
  2369. bnx2_set_remote_link(bp);
  2370. spin_unlock(&bp->phy_lock);
  2371. }
  2372. static inline u16
  2373. bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
  2374. {
  2375. u16 cons;
  2376. cons = READ_ONCE(*bnapi->hw_tx_cons_ptr);
  2377. if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT))
  2378. cons++;
  2379. return cons;
  2380. }
  2381. static int
  2382. bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
  2383. {
  2384. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2385. u16 hw_cons, sw_cons, sw_ring_cons;
  2386. int tx_pkt = 0, index;
  2387. unsigned int tx_bytes = 0;
  2388. struct netdev_queue *txq;
  2389. index = (bnapi - bp->bnx2_napi);
  2390. txq = netdev_get_tx_queue(bp->dev, index);
  2391. hw_cons = bnx2_get_hw_tx_cons(bnapi);
  2392. sw_cons = txr->tx_cons;
  2393. while (sw_cons != hw_cons) {
  2394. struct bnx2_sw_tx_bd *tx_buf;
  2395. struct sk_buff *skb;
  2396. int i, last;
  2397. sw_ring_cons = BNX2_TX_RING_IDX(sw_cons);
  2398. tx_buf = &txr->tx_buf_ring[sw_ring_cons];
  2399. skb = tx_buf->skb;
  2400. /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
  2401. prefetch(&skb->end);
  2402. /* partial BD completions possible with TSO packets */
  2403. if (tx_buf->is_gso) {
  2404. u16 last_idx, last_ring_idx;
  2405. last_idx = sw_cons + tx_buf->nr_frags + 1;
  2406. last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
  2407. if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) {
  2408. last_idx++;
  2409. }
  2410. if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
  2411. break;
  2412. }
  2413. }
  2414. dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
  2415. skb_headlen(skb), PCI_DMA_TODEVICE);
  2416. tx_buf->skb = NULL;
  2417. last = tx_buf->nr_frags;
  2418. for (i = 0; i < last; i++) {
  2419. struct bnx2_sw_tx_bd *tx_buf;
  2420. sw_cons = BNX2_NEXT_TX_BD(sw_cons);
  2421. tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)];
  2422. dma_unmap_page(&bp->pdev->dev,
  2423. dma_unmap_addr(tx_buf, mapping),
  2424. skb_frag_size(&skb_shinfo(skb)->frags[i]),
  2425. PCI_DMA_TODEVICE);
  2426. }
  2427. sw_cons = BNX2_NEXT_TX_BD(sw_cons);
  2428. tx_bytes += skb->len;
  2429. dev_kfree_skb_any(skb);
  2430. tx_pkt++;
  2431. if (tx_pkt == budget)
  2432. break;
  2433. if (hw_cons == sw_cons)
  2434. hw_cons = bnx2_get_hw_tx_cons(bnapi);
  2435. }
  2436. netdev_tx_completed_queue(txq, tx_pkt, tx_bytes);
  2437. txr->hw_tx_cons = hw_cons;
  2438. txr->tx_cons = sw_cons;
  2439. /* Need to make the tx_cons update visible to bnx2_start_xmit()
  2440. * before checking for netif_tx_queue_stopped(). Without the
  2441. * memory barrier, there is a small possibility that bnx2_start_xmit()
  2442. * will miss it and cause the queue to be stopped forever.
  2443. */
  2444. smp_mb();
  2445. if (unlikely(netif_tx_queue_stopped(txq)) &&
  2446. (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
  2447. __netif_tx_lock(txq, smp_processor_id());
  2448. if ((netif_tx_queue_stopped(txq)) &&
  2449. (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
  2450. netif_tx_wake_queue(txq);
  2451. __netif_tx_unlock(txq);
  2452. }
  2453. return tx_pkt;
  2454. }
  2455. static void
  2456. bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
  2457. struct sk_buff *skb, int count)
  2458. {
  2459. struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg;
  2460. struct bnx2_rx_bd *cons_bd, *prod_bd;
  2461. int i;
  2462. u16 hw_prod, prod;
  2463. u16 cons = rxr->rx_pg_cons;
  2464. cons_rx_pg = &rxr->rx_pg_ring[cons];
  2465. /* The caller was unable to allocate a new page to replace the
  2466. * last one in the frags array, so we need to recycle that page
  2467. * and then free the skb.
  2468. */
  2469. if (skb) {
  2470. struct page *page;
  2471. struct skb_shared_info *shinfo;
  2472. shinfo = skb_shinfo(skb);
  2473. shinfo->nr_frags--;
  2474. page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
  2475. __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
  2476. cons_rx_pg->page = page;
  2477. dev_kfree_skb(skb);
  2478. }
  2479. hw_prod = rxr->rx_pg_prod;
  2480. for (i = 0; i < count; i++) {
  2481. prod = BNX2_RX_PG_RING_IDX(hw_prod);
  2482. prod_rx_pg = &rxr->rx_pg_ring[prod];
  2483. cons_rx_pg = &rxr->rx_pg_ring[cons];
  2484. cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)]
  2485. [BNX2_RX_IDX(cons)];
  2486. prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)]
  2487. [BNX2_RX_IDX(prod)];
  2488. if (prod != cons) {
  2489. prod_rx_pg->page = cons_rx_pg->page;
  2490. cons_rx_pg->page = NULL;
  2491. dma_unmap_addr_set(prod_rx_pg, mapping,
  2492. dma_unmap_addr(cons_rx_pg, mapping));
  2493. prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
  2494. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  2495. }
  2496. cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons));
  2497. hw_prod = BNX2_NEXT_RX_BD(hw_prod);
  2498. }
  2499. rxr->rx_pg_prod = hw_prod;
  2500. rxr->rx_pg_cons = cons;
  2501. }
  2502. static inline void
  2503. bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
  2504. u8 *data, u16 cons, u16 prod)
  2505. {
  2506. struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf;
  2507. struct bnx2_rx_bd *cons_bd, *prod_bd;
  2508. cons_rx_buf = &rxr->rx_buf_ring[cons];
  2509. prod_rx_buf = &rxr->rx_buf_ring[prod];
  2510. dma_sync_single_for_device(&bp->pdev->dev,
  2511. dma_unmap_addr(cons_rx_buf, mapping),
  2512. BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
  2513. rxr->rx_prod_bseq += bp->rx_buf_use_size;
  2514. prod_rx_buf->data = data;
  2515. if (cons == prod)
  2516. return;
  2517. dma_unmap_addr_set(prod_rx_buf, mapping,
  2518. dma_unmap_addr(cons_rx_buf, mapping));
  2519. cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)];
  2520. prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)];
  2521. prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
  2522. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  2523. }
  2524. static struct sk_buff *
  2525. bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
  2526. unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
  2527. u32 ring_idx)
  2528. {
  2529. int err;
  2530. u16 prod = ring_idx & 0xffff;
  2531. struct sk_buff *skb;
  2532. err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
  2533. if (unlikely(err)) {
  2534. bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
  2535. error:
  2536. if (hdr_len) {
  2537. unsigned int raw_len = len + 4;
  2538. int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
  2539. bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
  2540. }
  2541. return NULL;
  2542. }
  2543. dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
  2544. PCI_DMA_FROMDEVICE);
  2545. skb = build_skb(data, 0);
  2546. if (!skb) {
  2547. kfree(data);
  2548. goto error;
  2549. }
  2550. skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
  2551. if (hdr_len == 0) {
  2552. skb_put(skb, len);
  2553. return skb;
  2554. } else {
  2555. unsigned int i, frag_len, frag_size, pages;
  2556. struct bnx2_sw_pg *rx_pg;
  2557. u16 pg_cons = rxr->rx_pg_cons;
  2558. u16 pg_prod = rxr->rx_pg_prod;
  2559. frag_size = len + 4 - hdr_len;
  2560. pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
  2561. skb_put(skb, hdr_len);
  2562. for (i = 0; i < pages; i++) {
  2563. dma_addr_t mapping_old;
  2564. frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
  2565. if (unlikely(frag_len <= 4)) {
  2566. unsigned int tail = 4 - frag_len;
  2567. rxr->rx_pg_cons = pg_cons;
  2568. rxr->rx_pg_prod = pg_prod;
  2569. bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
  2570. pages - i);
  2571. skb->len -= tail;
  2572. if (i == 0) {
  2573. skb->tail -= tail;
  2574. } else {
  2575. skb_frag_t *frag =
  2576. &skb_shinfo(skb)->frags[i - 1];
  2577. skb_frag_size_sub(frag, tail);
  2578. skb->data_len -= tail;
  2579. }
  2580. return skb;
  2581. }
  2582. rx_pg = &rxr->rx_pg_ring[pg_cons];
  2583. /* Don't unmap yet. If we're unable to allocate a new
  2584. * page, we need to recycle the page and the DMA addr.
  2585. */
  2586. mapping_old = dma_unmap_addr(rx_pg, mapping);
  2587. if (i == pages - 1)
  2588. frag_len -= 4;
  2589. skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
  2590. rx_pg->page = NULL;
  2591. err = bnx2_alloc_rx_page(bp, rxr,
  2592. BNX2_RX_PG_RING_IDX(pg_prod),
  2593. GFP_ATOMIC);
  2594. if (unlikely(err)) {
  2595. rxr->rx_pg_cons = pg_cons;
  2596. rxr->rx_pg_prod = pg_prod;
  2597. bnx2_reuse_rx_skb_pages(bp, rxr, skb,
  2598. pages - i);
  2599. return NULL;
  2600. }
  2601. dma_unmap_page(&bp->pdev->dev, mapping_old,
  2602. PAGE_SIZE, PCI_DMA_FROMDEVICE);
  2603. frag_size -= frag_len;
  2604. skb->data_len += frag_len;
  2605. skb->truesize += PAGE_SIZE;
  2606. skb->len += frag_len;
  2607. pg_prod = BNX2_NEXT_RX_BD(pg_prod);
  2608. pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons));
  2609. }
  2610. rxr->rx_pg_prod = pg_prod;
  2611. rxr->rx_pg_cons = pg_cons;
  2612. }
  2613. return skb;
  2614. }
  2615. static inline u16
  2616. bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
  2617. {
  2618. u16 cons;
  2619. cons = READ_ONCE(*bnapi->hw_rx_cons_ptr);
  2620. if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT))
  2621. cons++;
  2622. return cons;
  2623. }
  2624. static int
  2625. bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
  2626. {
  2627. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2628. u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
  2629. struct l2_fhdr *rx_hdr;
  2630. int rx_pkt = 0, pg_ring_used = 0;
  2631. if (budget <= 0)
  2632. return rx_pkt;
  2633. hw_cons = bnx2_get_hw_rx_cons(bnapi);
  2634. sw_cons = rxr->rx_cons;
  2635. sw_prod = rxr->rx_prod;
  2636. /* Memory barrier necessary as speculative reads of the rx
  2637. * buffer can be ahead of the index in the status block
  2638. */
  2639. rmb();
  2640. while (sw_cons != hw_cons) {
  2641. unsigned int len, hdr_len;
  2642. u32 status;
  2643. struct bnx2_sw_bd *rx_buf, *next_rx_buf;
  2644. struct sk_buff *skb;
  2645. dma_addr_t dma_addr;
  2646. u8 *data;
  2647. u16 next_ring_idx;
  2648. sw_ring_cons = BNX2_RX_RING_IDX(sw_cons);
  2649. sw_ring_prod = BNX2_RX_RING_IDX(sw_prod);
  2650. rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
  2651. data = rx_buf->data;
  2652. rx_buf->data = NULL;
  2653. rx_hdr = get_l2_fhdr(data);
  2654. prefetch(rx_hdr);
  2655. dma_addr = dma_unmap_addr(rx_buf, mapping);
  2656. dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
  2657. BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
  2658. PCI_DMA_FROMDEVICE);
  2659. next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons));
  2660. next_rx_buf = &rxr->rx_buf_ring[next_ring_idx];
  2661. prefetch(get_l2_fhdr(next_rx_buf->data));
  2662. len = rx_hdr->l2_fhdr_pkt_len;
  2663. status = rx_hdr->l2_fhdr_status;
  2664. hdr_len = 0;
  2665. if (status & L2_FHDR_STATUS_SPLIT) {
  2666. hdr_len = rx_hdr->l2_fhdr_ip_xsum;
  2667. pg_ring_used = 1;
  2668. } else if (len > bp->rx_jumbo_thresh) {
  2669. hdr_len = bp->rx_jumbo_thresh;
  2670. pg_ring_used = 1;
  2671. }
  2672. if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
  2673. L2_FHDR_ERRORS_PHY_DECODE |
  2674. L2_FHDR_ERRORS_ALIGNMENT |
  2675. L2_FHDR_ERRORS_TOO_SHORT |
  2676. L2_FHDR_ERRORS_GIANT_FRAME))) {
  2677. bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
  2678. sw_ring_prod);
  2679. if (pg_ring_used) {
  2680. int pages;
  2681. pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
  2682. bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
  2683. }
  2684. goto next_rx;
  2685. }
  2686. len -= 4;
  2687. if (len <= bp->rx_copy_thresh) {
  2688. skb = netdev_alloc_skb(bp->dev, len + 6);
  2689. if (!skb) {
  2690. bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
  2691. sw_ring_prod);
  2692. goto next_rx;
  2693. }
  2694. /* aligned copy */
  2695. memcpy(skb->data,
  2696. (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
  2697. len + 6);
  2698. skb_reserve(skb, 6);
  2699. skb_put(skb, len);
  2700. bnx2_reuse_rx_data(bp, rxr, data,
  2701. sw_ring_cons, sw_ring_prod);
  2702. } else {
  2703. skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
  2704. (sw_ring_cons << 16) | sw_ring_prod);
  2705. if (!skb)
  2706. goto next_rx;
  2707. }
  2708. if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
  2709. !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
  2710. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag);
  2711. skb->protocol = eth_type_trans(skb, bp->dev);
  2712. if (len > (bp->dev->mtu + ETH_HLEN) &&
  2713. skb->protocol != htons(0x8100) &&
  2714. skb->protocol != htons(ETH_P_8021AD)) {
  2715. dev_kfree_skb(skb);
  2716. goto next_rx;
  2717. }
  2718. skb_checksum_none_assert(skb);
  2719. if ((bp->dev->features & NETIF_F_RXCSUM) &&
  2720. (status & (L2_FHDR_STATUS_TCP_SEGMENT |
  2721. L2_FHDR_STATUS_UDP_DATAGRAM))) {
  2722. if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
  2723. L2_FHDR_ERRORS_UDP_XSUM)) == 0))
  2724. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2725. }
  2726. if ((bp->dev->features & NETIF_F_RXHASH) &&
  2727. ((status & L2_FHDR_STATUS_USE_RXHASH) ==
  2728. L2_FHDR_STATUS_USE_RXHASH))
  2729. skb_set_hash(skb, rx_hdr->l2_fhdr_hash,
  2730. PKT_HASH_TYPE_L3);
  2731. skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
  2732. napi_gro_receive(&bnapi->napi, skb);
  2733. rx_pkt++;
  2734. next_rx:
  2735. sw_cons = BNX2_NEXT_RX_BD(sw_cons);
  2736. sw_prod = BNX2_NEXT_RX_BD(sw_prod);
  2737. if (rx_pkt == budget)
  2738. break;
  2739. /* Refresh hw_cons to see if there is new work */
  2740. if (sw_cons == hw_cons) {
  2741. hw_cons = bnx2_get_hw_rx_cons(bnapi);
  2742. rmb();
  2743. }
  2744. }
  2745. rxr->rx_cons = sw_cons;
  2746. rxr->rx_prod = sw_prod;
  2747. if (pg_ring_used)
  2748. BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
  2749. BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);
  2750. BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
  2751. return rx_pkt;
  2752. }
  2753. /* MSI ISR - The only difference between this and the INTx ISR
  2754. * is that the MSI interrupt is always serviced.
  2755. */
  2756. static irqreturn_t
  2757. bnx2_msi(int irq, void *dev_instance)
  2758. {
  2759. struct bnx2_napi *bnapi = dev_instance;
  2760. struct bnx2 *bp = bnapi->bp;
  2761. prefetch(bnapi->status_blk.msi);
  2762. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2763. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  2764. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2765. /* Return here if interrupt is disabled. */
  2766. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2767. return IRQ_HANDLED;
  2768. napi_schedule(&bnapi->napi);
  2769. return IRQ_HANDLED;
  2770. }
  2771. static irqreturn_t
  2772. bnx2_msi_1shot(int irq, void *dev_instance)
  2773. {
  2774. struct bnx2_napi *bnapi = dev_instance;
  2775. struct bnx2 *bp = bnapi->bp;
  2776. prefetch(bnapi->status_blk.msi);
  2777. /* Return here if interrupt is disabled. */
  2778. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2779. return IRQ_HANDLED;
  2780. napi_schedule(&bnapi->napi);
  2781. return IRQ_HANDLED;
  2782. }
  2783. static irqreturn_t
  2784. bnx2_interrupt(int irq, void *dev_instance)
  2785. {
  2786. struct bnx2_napi *bnapi = dev_instance;
  2787. struct bnx2 *bp = bnapi->bp;
  2788. struct status_block *sblk = bnapi->status_blk.msi;
  2789. /* When using INTx, it is possible for the interrupt to arrive
  2790. * at the CPU before the status block posted prior to the
  2791. * interrupt. Reading a register will flush the status block.
  2792. * When using MSI, the MSI message will always complete after
  2793. * the status block write.
  2794. */
  2795. if ((sblk->status_idx == bnapi->last_status_idx) &&
  2796. (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
  2797. BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
  2798. return IRQ_NONE;
  2799. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2800. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  2801. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2802. /* Read back to deassert IRQ immediately to avoid too many
  2803. * spurious interrupts.
  2804. */
  2805. BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  2806. /* Return here if interrupt is shared and is disabled. */
  2807. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2808. return IRQ_HANDLED;
  2809. if (napi_schedule_prep(&bnapi->napi)) {
  2810. bnapi->last_status_idx = sblk->status_idx;
  2811. __napi_schedule(&bnapi->napi);
  2812. }
  2813. return IRQ_HANDLED;
  2814. }
  2815. static inline int
  2816. bnx2_has_fast_work(struct bnx2_napi *bnapi)
  2817. {
  2818. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2819. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2820. if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
  2821. (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
  2822. return 1;
  2823. return 0;
  2824. }
  2825. #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
  2826. STATUS_ATTN_BITS_TIMER_ABORT)
  2827. static inline int
  2828. bnx2_has_work(struct bnx2_napi *bnapi)
  2829. {
  2830. struct status_block *sblk = bnapi->status_blk.msi;
  2831. if (bnx2_has_fast_work(bnapi))
  2832. return 1;
  2833. #ifdef BCM_CNIC
  2834. if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
  2835. return 1;
  2836. #endif
  2837. if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
  2838. (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
  2839. return 1;
  2840. return 0;
  2841. }
  2842. static void
  2843. bnx2_chk_missed_msi(struct bnx2 *bp)
  2844. {
  2845. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  2846. u32 msi_ctrl;
  2847. if (bnx2_has_work(bnapi)) {
  2848. msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
  2849. if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
  2850. return;
  2851. if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
  2852. BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
  2853. ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
  2854. BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
  2855. bnx2_msi(bp->irq_tbl[0].vector, bnapi);
  2856. }
  2857. }
  2858. bp->idle_chk_status_idx = bnapi->last_status_idx;
  2859. }
  2860. #ifdef BCM_CNIC
  2861. static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2862. {
  2863. struct cnic_ops *c_ops;
  2864. if (!bnapi->cnic_present)
  2865. return;
  2866. rcu_read_lock();
  2867. c_ops = rcu_dereference(bp->cnic_ops);
  2868. if (c_ops)
  2869. bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
  2870. bnapi->status_blk.msi);
  2871. rcu_read_unlock();
  2872. }
  2873. #endif
  2874. static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2875. {
  2876. struct status_block *sblk = bnapi->status_blk.msi;
  2877. u32 status_attn_bits = sblk->status_attn_bits;
  2878. u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
  2879. if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
  2880. (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
  2881. bnx2_phy_int(bp, bnapi);
  2882. /* This is needed to take care of transient status
  2883. * during link changes.
  2884. */
  2885. BNX2_WR(bp, BNX2_HC_COMMAND,
  2886. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2887. BNX2_RD(bp, BNX2_HC_COMMAND);
  2888. }
  2889. }
  2890. static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
  2891. int work_done, int budget)
  2892. {
  2893. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2894. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2895. if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
  2896. bnx2_tx_int(bp, bnapi, 0);
  2897. if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
  2898. work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
  2899. return work_done;
  2900. }
  2901. static int bnx2_poll_msix(struct napi_struct *napi, int budget)
  2902. {
  2903. struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
  2904. struct bnx2 *bp = bnapi->bp;
  2905. int work_done = 0;
  2906. struct status_block_msix *sblk = bnapi->status_blk.msix;
  2907. while (1) {
  2908. work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
  2909. if (unlikely(work_done >= budget))
  2910. break;
  2911. bnapi->last_status_idx = sblk->status_idx;
  2912. /* status idx must be read before checking for more work. */
  2913. rmb();
  2914. if (likely(!bnx2_has_fast_work(bnapi))) {
  2915. napi_complete_done(napi, work_done);
  2916. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  2917. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2918. bnapi->last_status_idx);
  2919. break;
  2920. }
  2921. }
  2922. return work_done;
  2923. }
  2924. static int bnx2_poll(struct napi_struct *napi, int budget)
  2925. {
  2926. struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
  2927. struct bnx2 *bp = bnapi->bp;
  2928. int work_done = 0;
  2929. struct status_block *sblk = bnapi->status_blk.msi;
  2930. while (1) {
  2931. bnx2_poll_link(bp, bnapi);
  2932. work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
  2933. #ifdef BCM_CNIC
  2934. bnx2_poll_cnic(bp, bnapi);
  2935. #endif
  2936. /* bnapi->last_status_idx is used below to tell the hw how
  2937. * much work has been processed, so we must read it before
  2938. * checking for more work.
  2939. */
  2940. bnapi->last_status_idx = sblk->status_idx;
  2941. if (unlikely(work_done >= budget))
  2942. break;
  2943. rmb();
  2944. if (likely(!bnx2_has_work(bnapi))) {
  2945. napi_complete_done(napi, work_done);
  2946. if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
  2947. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2948. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2949. bnapi->last_status_idx);
  2950. break;
  2951. }
  2952. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2953. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2954. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  2955. bnapi->last_status_idx);
  2956. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2957. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2958. bnapi->last_status_idx);
  2959. break;
  2960. }
  2961. }
  2962. return work_done;
  2963. }
  2964. /* Called with rtnl_lock from vlan functions and also netif_tx_lock
  2965. * from set_multicast.
  2966. */
  2967. static void
  2968. bnx2_set_rx_mode(struct net_device *dev)
  2969. {
  2970. struct bnx2 *bp = netdev_priv(dev);
  2971. u32 rx_mode, sort_mode;
  2972. struct netdev_hw_addr *ha;
  2973. int i;
  2974. if (!netif_running(dev))
  2975. return;
  2976. spin_lock_bh(&bp->phy_lock);
  2977. rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
  2978. BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
  2979. sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
  2980. if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
  2981. (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
  2982. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  2983. if (dev->flags & IFF_PROMISC) {
  2984. /* Promiscuous mode. */
  2985. rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
  2986. sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
  2987. BNX2_RPM_SORT_USER0_PROM_VLAN;
  2988. }
  2989. else if (dev->flags & IFF_ALLMULTI) {
  2990. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  2991. BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  2992. 0xffffffff);
  2993. }
  2994. sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
  2995. }
  2996. else {
  2997. /* Accept one or more multicast(s). */
  2998. u32 mc_filter[NUM_MC_HASH_REGISTERS];
  2999. u32 regidx;
  3000. u32 bit;
  3001. u32 crc;
  3002. memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
  3003. netdev_for_each_mc_addr(ha, dev) {
  3004. crc = ether_crc_le(ETH_ALEN, ha->addr);
  3005. bit = crc & 0xff;
  3006. regidx = (bit & 0xe0) >> 5;
  3007. bit &= 0x1f;
  3008. mc_filter[regidx] |= (1 << bit);
  3009. }
  3010. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  3011. BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  3012. mc_filter[i]);
  3013. }
  3014. sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
  3015. }
  3016. if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
  3017. rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
  3018. sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
  3019. BNX2_RPM_SORT_USER0_PROM_VLAN;
  3020. } else if (!(dev->flags & IFF_PROMISC)) {
  3021. /* Add all entries into to the match filter list */
  3022. i = 0;
  3023. netdev_for_each_uc_addr(ha, dev) {
  3024. bnx2_set_mac_addr(bp, ha->addr,
  3025. i + BNX2_START_UNICAST_ADDRESS_INDEX);
  3026. sort_mode |= (1 <<
  3027. (i + BNX2_START_UNICAST_ADDRESS_INDEX));
  3028. i++;
  3029. }
  3030. }
  3031. if (rx_mode != bp->rx_mode) {
  3032. bp->rx_mode = rx_mode;
  3033. BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
  3034. }
  3035. BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  3036. BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
  3037. BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
  3038. spin_unlock_bh(&bp->phy_lock);
  3039. }
  3040. static int
  3041. check_fw_section(const struct firmware *fw,
  3042. const struct bnx2_fw_file_section *section,
  3043. u32 alignment, bool non_empty)
  3044. {
  3045. u32 offset = be32_to_cpu(section->offset);
  3046. u32 len = be32_to_cpu(section->len);
  3047. if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
  3048. return -EINVAL;
  3049. if ((non_empty && len == 0) || len > fw->size - offset ||
  3050. len & (alignment - 1))
  3051. return -EINVAL;
  3052. return 0;
  3053. }
  3054. static int
  3055. check_mips_fw_entry(const struct firmware *fw,
  3056. const struct bnx2_mips_fw_file_entry *entry)
  3057. {
  3058. if (check_fw_section(fw, &entry->text, 4, true) ||
  3059. check_fw_section(fw, &entry->data, 4, false) ||
  3060. check_fw_section(fw, &entry->rodata, 4, false))
  3061. return -EINVAL;
  3062. return 0;
  3063. }
  3064. static void bnx2_release_firmware(struct bnx2 *bp)
  3065. {
  3066. if (bp->rv2p_firmware) {
  3067. release_firmware(bp->mips_firmware);
  3068. release_firmware(bp->rv2p_firmware);
  3069. bp->rv2p_firmware = NULL;
  3070. }
  3071. }
  3072. static int bnx2_request_uncached_firmware(struct bnx2 *bp)
  3073. {
  3074. const char *mips_fw_file, *rv2p_fw_file;
  3075. const struct bnx2_mips_fw_file *mips_fw;
  3076. const struct bnx2_rv2p_fw_file *rv2p_fw;
  3077. int rc;
  3078. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  3079. mips_fw_file = FW_MIPS_FILE_09;
  3080. if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||
  3081. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))
  3082. rv2p_fw_file = FW_RV2P_FILE_09_Ax;
  3083. else
  3084. rv2p_fw_file = FW_RV2P_FILE_09;
  3085. } else {
  3086. mips_fw_file = FW_MIPS_FILE_06;
  3087. rv2p_fw_file = FW_RV2P_FILE_06;
  3088. }
  3089. rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
  3090. if (rc) {
  3091. pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
  3092. goto out;
  3093. }
  3094. rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
  3095. if (rc) {
  3096. pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
  3097. goto err_release_mips_firmware;
  3098. }
  3099. mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
  3100. rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
  3101. if (bp->mips_firmware->size < sizeof(*mips_fw) ||
  3102. check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
  3103. check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
  3104. check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
  3105. check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
  3106. check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
  3107. pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
  3108. rc = -EINVAL;
  3109. goto err_release_firmware;
  3110. }
  3111. if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
  3112. check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
  3113. check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
  3114. pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
  3115. rc = -EINVAL;
  3116. goto err_release_firmware;
  3117. }
  3118. out:
  3119. return rc;
  3120. err_release_firmware:
  3121. release_firmware(bp->rv2p_firmware);
  3122. bp->rv2p_firmware = NULL;
  3123. err_release_mips_firmware:
  3124. release_firmware(bp->mips_firmware);
  3125. goto out;
  3126. }
  3127. static int bnx2_request_firmware(struct bnx2 *bp)
  3128. {
  3129. return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
  3130. }
  3131. static u32
  3132. rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
  3133. {
  3134. switch (idx) {
  3135. case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
  3136. rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
  3137. rv2p_code |= RV2P_BD_PAGE_SIZE;
  3138. break;
  3139. }
  3140. return rv2p_code;
  3141. }
  3142. static int
  3143. load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
  3144. const struct bnx2_rv2p_fw_file_entry *fw_entry)
  3145. {
  3146. u32 rv2p_code_len, file_offset;
  3147. __be32 *rv2p_code;
  3148. int i;
  3149. u32 val, cmd, addr;
  3150. rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
  3151. file_offset = be32_to_cpu(fw_entry->rv2p.offset);
  3152. rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
  3153. if (rv2p_proc == RV2P_PROC1) {
  3154. cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
  3155. addr = BNX2_RV2P_PROC1_ADDR_CMD;
  3156. } else {
  3157. cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
  3158. addr = BNX2_RV2P_PROC2_ADDR_CMD;
  3159. }
  3160. for (i = 0; i < rv2p_code_len; i += 8) {
  3161. BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
  3162. rv2p_code++;
  3163. BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
  3164. rv2p_code++;
  3165. val = (i / 8) | cmd;
  3166. BNX2_WR(bp, addr, val);
  3167. }
  3168. rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
  3169. for (i = 0; i < 8; i++) {
  3170. u32 loc, code;
  3171. loc = be32_to_cpu(fw_entry->fixup[i]);
  3172. if (loc && ((loc * 4) < rv2p_code_len)) {
  3173. code = be32_to_cpu(*(rv2p_code + loc - 1));
  3174. BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
  3175. code = be32_to_cpu(*(rv2p_code + loc));
  3176. code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
  3177. BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
  3178. val = (loc / 2) | cmd;
  3179. BNX2_WR(bp, addr, val);
  3180. }
  3181. }
  3182. /* Reset the processor, un-stall is done later. */
  3183. if (rv2p_proc == RV2P_PROC1) {
  3184. BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
  3185. }
  3186. else {
  3187. BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
  3188. }
  3189. return 0;
  3190. }
  3191. static int
  3192. load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
  3193. const struct bnx2_mips_fw_file_entry *fw_entry)
  3194. {
  3195. u32 addr, len, file_offset;
  3196. __be32 *data;
  3197. u32 offset;
  3198. u32 val;
  3199. /* Halt the CPU. */
  3200. val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
  3201. val |= cpu_reg->mode_value_halt;
  3202. bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
  3203. bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
  3204. /* Load the Text area. */
  3205. addr = be32_to_cpu(fw_entry->text.addr);
  3206. len = be32_to_cpu(fw_entry->text.len);
  3207. file_offset = be32_to_cpu(fw_entry->text.offset);
  3208. data = (__be32 *)(bp->mips_firmware->data + file_offset);
  3209. offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
  3210. if (len) {
  3211. int j;
  3212. for (j = 0; j < (len / 4); j++, offset += 4)
  3213. bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
  3214. }
  3215. /* Load the Data area. */
  3216. addr = be32_to_cpu(fw_entry->data.addr);
  3217. len = be32_to_cpu(fw_entry->data.len);
  3218. file_offset = be32_to_cpu(fw_entry->data.offset);
  3219. data = (__be32 *)(bp->mips_firmware->data + file_offset);
  3220. offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
  3221. if (len) {
  3222. int j;
  3223. for (j = 0; j < (len / 4); j++, offset += 4)
  3224. bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
  3225. }
  3226. /* Load the Read-Only area. */
  3227. addr = be32_to_cpu(fw_entry->rodata.addr);
  3228. len = be32_to_cpu(fw_entry->rodata.len);
  3229. file_offset = be32_to_cpu(fw_entry->rodata.offset);
  3230. data = (__be32 *)(bp->mips_firmware->data + file_offset);
  3231. offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
  3232. if (len) {
  3233. int j;
  3234. for (j = 0; j < (len / 4); j++, offset += 4)
  3235. bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
  3236. }
  3237. /* Clear the pre-fetch instruction. */
  3238. bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
  3239. val = be32_to_cpu(fw_entry->start_addr);
  3240. bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
  3241. /* Start the CPU. */
  3242. val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
  3243. val &= ~cpu_reg->mode_value_halt;
  3244. bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
  3245. bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
  3246. return 0;
  3247. }
  3248. static int
  3249. bnx2_init_cpus(struct bnx2 *bp)
  3250. {
  3251. const struct bnx2_mips_fw_file *mips_fw =
  3252. (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
  3253. const struct bnx2_rv2p_fw_file *rv2p_fw =
  3254. (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
  3255. int rc;
  3256. /* Initialize the RV2P processor. */
  3257. load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
  3258. load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
  3259. /* Initialize the RX Processor. */
  3260. rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
  3261. if (rc)
  3262. goto init_cpu_err;
  3263. /* Initialize the TX Processor. */
  3264. rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
  3265. if (rc)
  3266. goto init_cpu_err;
  3267. /* Initialize the TX Patch-up Processor. */
  3268. rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
  3269. if (rc)
  3270. goto init_cpu_err;
  3271. /* Initialize the Completion Processor. */
  3272. rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
  3273. if (rc)
  3274. goto init_cpu_err;
  3275. /* Initialize the Command Processor. */
  3276. rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
  3277. init_cpu_err:
  3278. return rc;
  3279. }
  3280. static void
  3281. bnx2_setup_wol(struct bnx2 *bp)
  3282. {
  3283. int i;
  3284. u32 val, wol_msg;
  3285. if (bp->wol) {
  3286. u32 advertising;
  3287. u8 autoneg;
  3288. autoneg = bp->autoneg;
  3289. advertising = bp->advertising;
  3290. if (bp->phy_port == PORT_TP) {
  3291. bp->autoneg = AUTONEG_SPEED;
  3292. bp->advertising = ADVERTISED_10baseT_Half |
  3293. ADVERTISED_10baseT_Full |
  3294. ADVERTISED_100baseT_Half |
  3295. ADVERTISED_100baseT_Full |
  3296. ADVERTISED_Autoneg;
  3297. }
  3298. spin_lock_bh(&bp->phy_lock);
  3299. bnx2_setup_phy(bp, bp->phy_port);
  3300. spin_unlock_bh(&bp->phy_lock);
  3301. bp->autoneg = autoneg;
  3302. bp->advertising = advertising;
  3303. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  3304. val = BNX2_RD(bp, BNX2_EMAC_MODE);
  3305. /* Enable port mode. */
  3306. val &= ~BNX2_EMAC_MODE_PORT;
  3307. val |= BNX2_EMAC_MODE_MPKT_RCVD |
  3308. BNX2_EMAC_MODE_ACPI_RCVD |
  3309. BNX2_EMAC_MODE_MPKT;
  3310. if (bp->phy_port == PORT_TP) {
  3311. val |= BNX2_EMAC_MODE_PORT_MII;
  3312. } else {
  3313. val |= BNX2_EMAC_MODE_PORT_GMII;
  3314. if (bp->line_speed == SPEED_2500)
  3315. val |= BNX2_EMAC_MODE_25G_MODE;
  3316. }
  3317. BNX2_WR(bp, BNX2_EMAC_MODE, val);
  3318. /* receive all multicast */
  3319. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  3320. BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  3321. 0xffffffff);
  3322. }
  3323. BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
  3324. val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN;
  3325. BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  3326. BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
  3327. BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
  3328. /* Need to enable EMAC and RPM for WOL. */
  3329. BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  3330. BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
  3331. BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
  3332. BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
  3333. val = BNX2_RD(bp, BNX2_RPM_CONFIG);
  3334. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  3335. BNX2_WR(bp, BNX2_RPM_CONFIG, val);
  3336. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  3337. } else {
  3338. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  3339. }
  3340. if (!(bp->flags & BNX2_FLAG_NO_WOL)) {
  3341. u32 val;
  3342. wol_msg |= BNX2_DRV_MSG_DATA_WAIT3;
  3343. if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {
  3344. bnx2_fw_sync(bp, wol_msg, 1, 0);
  3345. return;
  3346. }
  3347. /* Tell firmware not to power down the PHY yet, otherwise
  3348. * the chip will take a long time to respond to MMIO reads.
  3349. */
  3350. val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
  3351. bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,
  3352. val | BNX2_PORT_FEATURE_ASF_ENABLED);
  3353. bnx2_fw_sync(bp, wol_msg, 1, 0);
  3354. bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);
  3355. }
  3356. }
  3357. static int
  3358. bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
  3359. {
  3360. switch (state) {
  3361. case PCI_D0: {
  3362. u32 val;
  3363. pci_enable_wake(bp->pdev, PCI_D0, false);
  3364. pci_set_power_state(bp->pdev, PCI_D0);
  3365. val = BNX2_RD(bp, BNX2_EMAC_MODE);
  3366. val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
  3367. val &= ~BNX2_EMAC_MODE_MPKT;
  3368. BNX2_WR(bp, BNX2_EMAC_MODE, val);
  3369. val = BNX2_RD(bp, BNX2_RPM_CONFIG);
  3370. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  3371. BNX2_WR(bp, BNX2_RPM_CONFIG, val);
  3372. break;
  3373. }
  3374. case PCI_D3hot: {
  3375. bnx2_setup_wol(bp);
  3376. pci_wake_from_d3(bp->pdev, bp->wol);
  3377. if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
  3378. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {
  3379. if (bp->wol)
  3380. pci_set_power_state(bp->pdev, PCI_D3hot);
  3381. break;
  3382. }
  3383. if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  3384. u32 val;
  3385. /* Tell firmware not to power down the PHY yet,
  3386. * otherwise the other port may not respond to
  3387. * MMIO reads.
  3388. */
  3389. val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
  3390. val &= ~BNX2_CONDITION_PM_STATE_MASK;
  3391. val |= BNX2_CONDITION_PM_STATE_UNPREP;
  3392. bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);
  3393. }
  3394. pci_set_power_state(bp->pdev, PCI_D3hot);
  3395. /* No more memory access after this point until
  3396. * device is brought back to D0.
  3397. */
  3398. break;
  3399. }
  3400. default:
  3401. return -EINVAL;
  3402. }
  3403. return 0;
  3404. }
  3405. static int
  3406. bnx2_acquire_nvram_lock(struct bnx2 *bp)
  3407. {
  3408. u32 val;
  3409. int j;
  3410. /* Request access to the flash interface. */
  3411. BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
  3412. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3413. val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
  3414. if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
  3415. break;
  3416. udelay(5);
  3417. }
  3418. if (j >= NVRAM_TIMEOUT_COUNT)
  3419. return -EBUSY;
  3420. return 0;
  3421. }
  3422. static int
  3423. bnx2_release_nvram_lock(struct bnx2 *bp)
  3424. {
  3425. int j;
  3426. u32 val;
  3427. /* Relinquish nvram interface. */
  3428. BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
  3429. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3430. val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
  3431. if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
  3432. break;
  3433. udelay(5);
  3434. }
  3435. if (j >= NVRAM_TIMEOUT_COUNT)
  3436. return -EBUSY;
  3437. return 0;
  3438. }
  3439. static int
  3440. bnx2_enable_nvram_write(struct bnx2 *bp)
  3441. {
  3442. u32 val;
  3443. val = BNX2_RD(bp, BNX2_MISC_CFG);
  3444. BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
  3445. if (bp->flash_info->flags & BNX2_NV_WREN) {
  3446. int j;
  3447. BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3448. BNX2_WR(bp, BNX2_NVM_COMMAND,
  3449. BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
  3450. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3451. udelay(5);
  3452. val = BNX2_RD(bp, BNX2_NVM_COMMAND);
  3453. if (val & BNX2_NVM_COMMAND_DONE)
  3454. break;
  3455. }
  3456. if (j >= NVRAM_TIMEOUT_COUNT)
  3457. return -EBUSY;
  3458. }
  3459. return 0;
  3460. }
  3461. static void
  3462. bnx2_disable_nvram_write(struct bnx2 *bp)
  3463. {
  3464. u32 val;
  3465. val = BNX2_RD(bp, BNX2_MISC_CFG);
  3466. BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
  3467. }
  3468. static void
  3469. bnx2_enable_nvram_access(struct bnx2 *bp)
  3470. {
  3471. u32 val;
  3472. val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  3473. /* Enable both bits, even on read. */
  3474. BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  3475. val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
  3476. }
  3477. static void
  3478. bnx2_disable_nvram_access(struct bnx2 *bp)
  3479. {
  3480. u32 val;
  3481. val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  3482. /* Disable both bits, even after read. */
  3483. BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  3484. val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
  3485. BNX2_NVM_ACCESS_ENABLE_WR_EN));
  3486. }
  3487. static int
  3488. bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
  3489. {
  3490. u32 cmd;
  3491. int j;
  3492. if (bp->flash_info->flags & BNX2_NV_BUFFERED)
  3493. /* Buffered flash, no erase needed */
  3494. return 0;
  3495. /* Build an erase command */
  3496. cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
  3497. BNX2_NVM_COMMAND_DOIT;
  3498. /* Need to clear DONE bit separately. */
  3499. BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3500. /* Address of the NVRAM to read from. */
  3501. BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3502. /* Issue an erase command. */
  3503. BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
  3504. /* Wait for completion. */
  3505. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3506. u32 val;
  3507. udelay(5);
  3508. val = BNX2_RD(bp, BNX2_NVM_COMMAND);
  3509. if (val & BNX2_NVM_COMMAND_DONE)
  3510. break;
  3511. }
  3512. if (j >= NVRAM_TIMEOUT_COUNT)
  3513. return -EBUSY;
  3514. return 0;
  3515. }
  3516. static int
  3517. bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
  3518. {
  3519. u32 cmd;
  3520. int j;
  3521. /* Build the command word. */
  3522. cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
  3523. /* Calculate an offset of a buffered flash, not needed for 5709. */
  3524. if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
  3525. offset = ((offset / bp->flash_info->page_size) <<
  3526. bp->flash_info->page_bits) +
  3527. (offset % bp->flash_info->page_size);
  3528. }
  3529. /* Need to clear DONE bit separately. */
  3530. BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3531. /* Address of the NVRAM to read from. */
  3532. BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3533. /* Issue a read command. */
  3534. BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
  3535. /* Wait for completion. */
  3536. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3537. u32 val;
  3538. udelay(5);
  3539. val = BNX2_RD(bp, BNX2_NVM_COMMAND);
  3540. if (val & BNX2_NVM_COMMAND_DONE) {
  3541. __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
  3542. memcpy(ret_val, &v, 4);
  3543. break;
  3544. }
  3545. }
  3546. if (j >= NVRAM_TIMEOUT_COUNT)
  3547. return -EBUSY;
  3548. return 0;
  3549. }
  3550. static int
  3551. bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
  3552. {
  3553. u32 cmd;
  3554. __be32 val32;
  3555. int j;
  3556. /* Build the command word. */
  3557. cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
  3558. /* Calculate an offset of a buffered flash, not needed for 5709. */
  3559. if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
  3560. offset = ((offset / bp->flash_info->page_size) <<
  3561. bp->flash_info->page_bits) +
  3562. (offset % bp->flash_info->page_size);
  3563. }
  3564. /* Need to clear DONE bit separately. */
  3565. BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3566. memcpy(&val32, val, 4);
  3567. /* Write the data. */
  3568. BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
  3569. /* Address of the NVRAM to write to. */
  3570. BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3571. /* Issue the write command. */
  3572. BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
  3573. /* Wait for completion. */
  3574. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3575. udelay(5);
  3576. if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
  3577. break;
  3578. }
  3579. if (j >= NVRAM_TIMEOUT_COUNT)
  3580. return -EBUSY;
  3581. return 0;
  3582. }
  3583. static int
  3584. bnx2_init_nvram(struct bnx2 *bp)
  3585. {
  3586. u32 val;
  3587. int j, entry_count, rc = 0;
  3588. const struct flash_spec *flash;
  3589. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  3590. bp->flash_info = &flash_5709;
  3591. goto get_flash_size;
  3592. }
  3593. /* Determine the selected interface. */
  3594. val = BNX2_RD(bp, BNX2_NVM_CFG1);
  3595. entry_count = ARRAY_SIZE(flash_table);
  3596. if (val & 0x40000000) {
  3597. /* Flash interface has been reconfigured */
  3598. for (j = 0, flash = &flash_table[0]; j < entry_count;
  3599. j++, flash++) {
  3600. if ((val & FLASH_BACKUP_STRAP_MASK) ==
  3601. (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
  3602. bp->flash_info = flash;
  3603. break;
  3604. }
  3605. }
  3606. }
  3607. else {
  3608. u32 mask;
  3609. /* Not yet been reconfigured */
  3610. if (val & (1 << 23))
  3611. mask = FLASH_BACKUP_STRAP_MASK;
  3612. else
  3613. mask = FLASH_STRAP_MASK;
  3614. for (j = 0, flash = &flash_table[0]; j < entry_count;
  3615. j++, flash++) {
  3616. if ((val & mask) == (flash->strapping & mask)) {
  3617. bp->flash_info = flash;
  3618. /* Request access to the flash interface. */
  3619. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3620. return rc;
  3621. /* Enable access to flash interface */
  3622. bnx2_enable_nvram_access(bp);
  3623. /* Reconfigure the flash interface */
  3624. BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
  3625. BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
  3626. BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
  3627. BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
  3628. /* Disable access to flash interface */
  3629. bnx2_disable_nvram_access(bp);
  3630. bnx2_release_nvram_lock(bp);
  3631. break;
  3632. }
  3633. }
  3634. } /* if (val & 0x40000000) */
  3635. if (j == entry_count) {
  3636. bp->flash_info = NULL;
  3637. pr_alert("Unknown flash/EEPROM type\n");
  3638. return -ENODEV;
  3639. }
  3640. get_flash_size:
  3641. val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
  3642. val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
  3643. if (val)
  3644. bp->flash_size = val;
  3645. else
  3646. bp->flash_size = bp->flash_info->total_size;
  3647. return rc;
  3648. }
  3649. static int
  3650. bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
  3651. int buf_size)
  3652. {
  3653. int rc = 0;
  3654. u32 cmd_flags, offset32, len32, extra;
  3655. if (buf_size == 0)
  3656. return 0;
  3657. /* Request access to the flash interface. */
  3658. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3659. return rc;
  3660. /* Enable access to flash interface */
  3661. bnx2_enable_nvram_access(bp);
  3662. len32 = buf_size;
  3663. offset32 = offset;
  3664. extra = 0;
  3665. cmd_flags = 0;
  3666. if (offset32 & 3) {
  3667. u8 buf[4];
  3668. u32 pre_len;
  3669. offset32 &= ~3;
  3670. pre_len = 4 - (offset & 3);
  3671. if (pre_len >= len32) {
  3672. pre_len = len32;
  3673. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  3674. BNX2_NVM_COMMAND_LAST;
  3675. }
  3676. else {
  3677. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3678. }
  3679. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3680. if (rc)
  3681. return rc;
  3682. memcpy(ret_buf, buf + (offset & 3), pre_len);
  3683. offset32 += 4;
  3684. ret_buf += pre_len;
  3685. len32 -= pre_len;
  3686. }
  3687. if (len32 & 3) {
  3688. extra = 4 - (len32 & 3);
  3689. len32 = (len32 + 4) & ~3;
  3690. }
  3691. if (len32 == 4) {
  3692. u8 buf[4];
  3693. if (cmd_flags)
  3694. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3695. else
  3696. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  3697. BNX2_NVM_COMMAND_LAST;
  3698. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3699. memcpy(ret_buf, buf, 4 - extra);
  3700. }
  3701. else if (len32 > 0) {
  3702. u8 buf[4];
  3703. /* Read the first word. */
  3704. if (cmd_flags)
  3705. cmd_flags = 0;
  3706. else
  3707. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3708. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
  3709. /* Advance to the next dword. */
  3710. offset32 += 4;
  3711. ret_buf += 4;
  3712. len32 -= 4;
  3713. while (len32 > 4 && rc == 0) {
  3714. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
  3715. /* Advance to the next dword. */
  3716. offset32 += 4;
  3717. ret_buf += 4;
  3718. len32 -= 4;
  3719. }
  3720. if (rc)
  3721. return rc;
  3722. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3723. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3724. memcpy(ret_buf, buf, 4 - extra);
  3725. }
  3726. /* Disable access to flash interface */
  3727. bnx2_disable_nvram_access(bp);
  3728. bnx2_release_nvram_lock(bp);
  3729. return rc;
  3730. }
  3731. static int
  3732. bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
  3733. int buf_size)
  3734. {
  3735. u32 written, offset32, len32;
  3736. u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
  3737. int rc = 0;
  3738. int align_start, align_end;
  3739. buf = data_buf;
  3740. offset32 = offset;
  3741. len32 = buf_size;
  3742. align_start = align_end = 0;
  3743. if ((align_start = (offset32 & 3))) {
  3744. offset32 &= ~3;
  3745. len32 += align_start;
  3746. if (len32 < 4)
  3747. len32 = 4;
  3748. if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
  3749. return rc;
  3750. }
  3751. if (len32 & 3) {
  3752. align_end = 4 - (len32 & 3);
  3753. len32 += align_end;
  3754. if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
  3755. return rc;
  3756. }
  3757. if (align_start || align_end) {
  3758. align_buf = kmalloc(len32, GFP_KERNEL);
  3759. if (!align_buf)
  3760. return -ENOMEM;
  3761. if (align_start) {
  3762. memcpy(align_buf, start, 4);
  3763. }
  3764. if (align_end) {
  3765. memcpy(align_buf + len32 - 4, end, 4);
  3766. }
  3767. memcpy(align_buf + align_start, data_buf, buf_size);
  3768. buf = align_buf;
  3769. }
  3770. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3771. flash_buffer = kmalloc(264, GFP_KERNEL);
  3772. if (!flash_buffer) {
  3773. rc = -ENOMEM;
  3774. goto nvram_write_end;
  3775. }
  3776. }
  3777. written = 0;
  3778. while ((written < len32) && (rc == 0)) {
  3779. u32 page_start, page_end, data_start, data_end;
  3780. u32 addr, cmd_flags;
  3781. int i;
  3782. /* Find the page_start addr */
  3783. page_start = offset32 + written;
  3784. page_start -= (page_start % bp->flash_info->page_size);
  3785. /* Find the page_end addr */
  3786. page_end = page_start + bp->flash_info->page_size;
  3787. /* Find the data_start addr */
  3788. data_start = (written == 0) ? offset32 : page_start;
  3789. /* Find the data_end addr */
  3790. data_end = (page_end > offset32 + len32) ?
  3791. (offset32 + len32) : page_end;
  3792. /* Request access to the flash interface. */
  3793. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3794. goto nvram_write_end;
  3795. /* Enable access to flash interface */
  3796. bnx2_enable_nvram_access(bp);
  3797. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3798. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3799. int j;
  3800. /* Read the whole page into the buffer
  3801. * (non-buffer flash only) */
  3802. for (j = 0; j < bp->flash_info->page_size; j += 4) {
  3803. if (j == (bp->flash_info->page_size - 4)) {
  3804. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  3805. }
  3806. rc = bnx2_nvram_read_dword(bp,
  3807. page_start + j,
  3808. &flash_buffer[j],
  3809. cmd_flags);
  3810. if (rc)
  3811. goto nvram_write_end;
  3812. cmd_flags = 0;
  3813. }
  3814. }
  3815. /* Enable writes to flash interface (unlock write-protect) */
  3816. if ((rc = bnx2_enable_nvram_write(bp)) != 0)
  3817. goto nvram_write_end;
  3818. /* Loop to write back the buffer data from page_start to
  3819. * data_start */
  3820. i = 0;
  3821. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3822. /* Erase the page */
  3823. if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
  3824. goto nvram_write_end;
  3825. /* Re-enable the write again for the actual write */
  3826. bnx2_enable_nvram_write(bp);
  3827. for (addr = page_start; addr < data_start;
  3828. addr += 4, i += 4) {
  3829. rc = bnx2_nvram_write_dword(bp, addr,
  3830. &flash_buffer[i], cmd_flags);
  3831. if (rc != 0)
  3832. goto nvram_write_end;
  3833. cmd_flags = 0;
  3834. }
  3835. }
  3836. /* Loop to write the new data from data_start to data_end */
  3837. for (addr = data_start; addr < data_end; addr += 4, i += 4) {
  3838. if ((addr == page_end - 4) ||
  3839. ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
  3840. (addr == data_end - 4))) {
  3841. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  3842. }
  3843. rc = bnx2_nvram_write_dword(bp, addr, buf,
  3844. cmd_flags);
  3845. if (rc != 0)
  3846. goto nvram_write_end;
  3847. cmd_flags = 0;
  3848. buf += 4;
  3849. }
  3850. /* Loop to write back the buffer data from data_end
  3851. * to page_end */
  3852. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3853. for (addr = data_end; addr < page_end;
  3854. addr += 4, i += 4) {
  3855. if (addr == page_end-4) {
  3856. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3857. }
  3858. rc = bnx2_nvram_write_dword(bp, addr,
  3859. &flash_buffer[i], cmd_flags);
  3860. if (rc != 0)
  3861. goto nvram_write_end;
  3862. cmd_flags = 0;
  3863. }
  3864. }
  3865. /* Disable writes to flash interface (lock write-protect) */
  3866. bnx2_disable_nvram_write(bp);
  3867. /* Disable access to flash interface */
  3868. bnx2_disable_nvram_access(bp);
  3869. bnx2_release_nvram_lock(bp);
  3870. /* Increment written */
  3871. written += data_end - data_start;
  3872. }
  3873. nvram_write_end:
  3874. kfree(flash_buffer);
  3875. kfree(align_buf);
  3876. return rc;
  3877. }
  3878. static void
  3879. bnx2_init_fw_cap(struct bnx2 *bp)
  3880. {
  3881. u32 val, sig = 0;
  3882. bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
  3883. bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
  3884. if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
  3885. bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
  3886. val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
  3887. if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
  3888. return;
  3889. if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
  3890. bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
  3891. sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
  3892. }
  3893. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  3894. (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
  3895. u32 link;
  3896. bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
  3897. link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
  3898. if (link & BNX2_LINK_STATUS_SERDES_LINK)
  3899. bp->phy_port = PORT_FIBRE;
  3900. else
  3901. bp->phy_port = PORT_TP;
  3902. sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
  3903. BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
  3904. }
  3905. if (netif_running(bp->dev) && sig)
  3906. bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
  3907. }
  3908. static void
  3909. bnx2_setup_msix_tbl(struct bnx2 *bp)
  3910. {
  3911. BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
  3912. BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
  3913. BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
  3914. }
  3915. static void
  3916. bnx2_wait_dma_complete(struct bnx2 *bp)
  3917. {
  3918. u32 val;
  3919. int i;
  3920. /*
  3921. * Wait for the current PCI transaction to complete before
  3922. * issuing a reset.
  3923. */
  3924. if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
  3925. (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
  3926. BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
  3927. BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
  3928. BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
  3929. BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
  3930. BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
  3931. val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
  3932. udelay(5);
  3933. } else { /* 5709 */
  3934. val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
  3935. val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
  3936. BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
  3937. val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
  3938. for (i = 0; i < 100; i++) {
  3939. msleep(1);
  3940. val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
  3941. if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
  3942. break;
  3943. }
  3944. }
  3945. return;
  3946. }
  3947. static int
  3948. bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
  3949. {
  3950. u32 val;
  3951. int i, rc = 0;
  3952. u8 old_port;
  3953. /* Wait for the current PCI transaction to complete before
  3954. * issuing a reset. */
  3955. bnx2_wait_dma_complete(bp);
  3956. /* Wait for the firmware to tell us it is ok to issue a reset. */
  3957. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
  3958. /* Deposit a driver reset signature so the firmware knows that
  3959. * this is a soft reset. */
  3960. bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
  3961. BNX2_DRV_RESET_SIGNATURE_MAGIC);
  3962. /* Do a dummy read to force the chip to complete all current transaction
  3963. * before we issue a reset. */
  3964. val = BNX2_RD(bp, BNX2_MISC_ID);
  3965. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  3966. BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
  3967. BNX2_RD(bp, BNX2_MISC_COMMAND);
  3968. udelay(5);
  3969. val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  3970. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  3971. BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
  3972. } else {
  3973. val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3974. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  3975. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  3976. /* Chip reset. */
  3977. BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
  3978. /* Reading back any register after chip reset will hang the
  3979. * bus on 5706 A0 and A1. The msleep below provides plenty
  3980. * of margin for write posting.
  3981. */
  3982. if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
  3983. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))
  3984. msleep(20);
  3985. /* Reset takes approximate 30 usec */
  3986. for (i = 0; i < 10; i++) {
  3987. val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
  3988. if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3989. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
  3990. break;
  3991. udelay(10);
  3992. }
  3993. if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3994. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
  3995. pr_err("Chip reset did not complete\n");
  3996. return -EBUSY;
  3997. }
  3998. }
  3999. /* Make sure byte swapping is properly configured. */
  4000. val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
  4001. if (val != 0x01020304) {
  4002. pr_err("Chip not in correct endian mode\n");
  4003. return -ENODEV;
  4004. }
  4005. /* Wait for the firmware to finish its initialization. */
  4006. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
  4007. if (rc)
  4008. return rc;
  4009. spin_lock_bh(&bp->phy_lock);
  4010. old_port = bp->phy_port;
  4011. bnx2_init_fw_cap(bp);
  4012. if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
  4013. old_port != bp->phy_port)
  4014. bnx2_set_default_remote_link(bp);
  4015. spin_unlock_bh(&bp->phy_lock);
  4016. if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
  4017. /* Adjust the voltage regular to two steps lower. The default
  4018. * of this register is 0x0000000e. */
  4019. BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
  4020. /* Remove bad rbuf memory from the free pool. */
  4021. rc = bnx2_alloc_bad_rbuf(bp);
  4022. }
  4023. if (bp->flags & BNX2_FLAG_USING_MSIX) {
  4024. bnx2_setup_msix_tbl(bp);
  4025. /* Prevent MSIX table reads and write from timing out */
  4026. BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
  4027. BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
  4028. }
  4029. return rc;
  4030. }
  4031. static int
  4032. bnx2_init_chip(struct bnx2 *bp)
  4033. {
  4034. u32 val, mtu;
  4035. int rc, i;
  4036. /* Make sure the interrupt is not active. */
  4037. BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  4038. val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
  4039. BNX2_DMA_CONFIG_DATA_WORD_SWAP |
  4040. #ifdef __BIG_ENDIAN
  4041. BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
  4042. #endif
  4043. BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
  4044. DMA_READ_CHANS << 12 |
  4045. DMA_WRITE_CHANS << 16;
  4046. val |= (0x2 << 20) | (1 << 11);
  4047. if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
  4048. val |= (1 << 23);
  4049. if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&
  4050. (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&
  4051. !(bp->flags & BNX2_FLAG_PCIX))
  4052. val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
  4053. BNX2_WR(bp, BNX2_DMA_CONFIG, val);
  4054. if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
  4055. val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
  4056. val |= BNX2_TDMA_CONFIG_ONE_DMA;
  4057. BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
  4058. }
  4059. if (bp->flags & BNX2_FLAG_PCIX) {
  4060. u16 val16;
  4061. pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  4062. &val16);
  4063. pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  4064. val16 & ~PCI_X_CMD_ERO);
  4065. }
  4066. BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  4067. BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
  4068. BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
  4069. BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
  4070. /* Initialize context mapping and zero out the quick contexts. The
  4071. * context block must have already been enabled. */
  4072. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  4073. rc = bnx2_init_5709_context(bp);
  4074. if (rc)
  4075. return rc;
  4076. } else
  4077. bnx2_init_context(bp);
  4078. if ((rc = bnx2_init_cpus(bp)) != 0)
  4079. return rc;
  4080. bnx2_init_nvram(bp);
  4081. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  4082. val = BNX2_RD(bp, BNX2_MQ_CONFIG);
  4083. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  4084. val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
  4085. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  4086. val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
  4087. if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
  4088. val |= BNX2_MQ_CONFIG_HALT_DIS;
  4089. }
  4090. BNX2_WR(bp, BNX2_MQ_CONFIG, val);
  4091. val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
  4092. BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
  4093. BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
  4094. val = (BNX2_PAGE_BITS - 8) << 24;
  4095. BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
  4096. /* Configure page size. */
  4097. val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
  4098. val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
  4099. val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40;
  4100. BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
  4101. val = bp->mac_addr[0] +
  4102. (bp->mac_addr[1] << 8) +
  4103. (bp->mac_addr[2] << 16) +
  4104. bp->mac_addr[3] +
  4105. (bp->mac_addr[4] << 8) +
  4106. (bp->mac_addr[5] << 16);
  4107. BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
  4108. /* Program the MTU. Also include 4 bytes for CRC32. */
  4109. mtu = bp->dev->mtu;
  4110. val = mtu + ETH_HLEN + ETH_FCS_LEN;
  4111. if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4))
  4112. val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
  4113. BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
  4114. if (mtu < ETH_DATA_LEN)
  4115. mtu = ETH_DATA_LEN;
  4116. bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
  4117. bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
  4118. bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
  4119. memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
  4120. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
  4121. bp->bnx2_napi[i].last_status_idx = 0;
  4122. bp->idle_chk_status_idx = 0xffff;
  4123. /* Set up how to generate a link change interrupt. */
  4124. BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  4125. BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
  4126. (u64) bp->status_blk_mapping & 0xffffffff);
  4127. BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
  4128. BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
  4129. (u64) bp->stats_blk_mapping & 0xffffffff);
  4130. BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
  4131. (u64) bp->stats_blk_mapping >> 32);
  4132. BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
  4133. (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
  4134. BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
  4135. (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
  4136. BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
  4137. (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
  4138. BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
  4139. BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
  4140. BNX2_WR(bp, BNX2_HC_COM_TICKS,
  4141. (bp->com_ticks_int << 16) | bp->com_ticks);
  4142. BNX2_WR(bp, BNX2_HC_CMD_TICKS,
  4143. (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
  4144. if (bp->flags & BNX2_FLAG_BROKEN_STATS)
  4145. BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
  4146. else
  4147. BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
  4148. BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
  4149. if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)
  4150. val = BNX2_HC_CONFIG_COLLECT_STATS;
  4151. else {
  4152. val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
  4153. BNX2_HC_CONFIG_COLLECT_STATS;
  4154. }
  4155. if (bp->flags & BNX2_FLAG_USING_MSIX) {
  4156. BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
  4157. BNX2_HC_MSIX_BIT_VECTOR_VAL);
  4158. val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
  4159. }
  4160. if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
  4161. val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
  4162. BNX2_WR(bp, BNX2_HC_CONFIG, val);
  4163. if (bp->rx_ticks < 25)
  4164. bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
  4165. else
  4166. bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
  4167. for (i = 1; i < bp->irq_nvecs; i++) {
  4168. u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  4169. BNX2_HC_SB_CONFIG_1;
  4170. BNX2_WR(bp, base,
  4171. BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
  4172. BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
  4173. BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  4174. BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
  4175. (bp->tx_quick_cons_trip_int << 16) |
  4176. bp->tx_quick_cons_trip);
  4177. BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
  4178. (bp->tx_ticks_int << 16) | bp->tx_ticks);
  4179. BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
  4180. (bp->rx_quick_cons_trip_int << 16) |
  4181. bp->rx_quick_cons_trip);
  4182. BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
  4183. (bp->rx_ticks_int << 16) | bp->rx_ticks);
  4184. }
  4185. /* Clear internal stats counters. */
  4186. BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
  4187. BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
  4188. /* Initialize the receive filter. */
  4189. bnx2_set_rx_mode(bp->dev);
  4190. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  4191. val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
  4192. val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
  4193. BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
  4194. }
  4195. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
  4196. 1, 0);
  4197. BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
  4198. BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
  4199. udelay(20);
  4200. bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
  4201. return rc;
  4202. }
  4203. static void
  4204. bnx2_clear_ring_states(struct bnx2 *bp)
  4205. {
  4206. struct bnx2_napi *bnapi;
  4207. struct bnx2_tx_ring_info *txr;
  4208. struct bnx2_rx_ring_info *rxr;
  4209. int i;
  4210. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
  4211. bnapi = &bp->bnx2_napi[i];
  4212. txr = &bnapi->tx_ring;
  4213. rxr = &bnapi->rx_ring;
  4214. txr->tx_cons = 0;
  4215. txr->hw_tx_cons = 0;
  4216. rxr->rx_prod_bseq = 0;
  4217. rxr->rx_prod = 0;
  4218. rxr->rx_cons = 0;
  4219. rxr->rx_pg_prod = 0;
  4220. rxr->rx_pg_cons = 0;
  4221. }
  4222. }
  4223. static void
  4224. bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
  4225. {
  4226. u32 val, offset0, offset1, offset2, offset3;
  4227. u32 cid_addr = GET_CID_ADDR(cid);
  4228. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  4229. offset0 = BNX2_L2CTX_TYPE_XI;
  4230. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  4231. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  4232. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  4233. } else {
  4234. offset0 = BNX2_L2CTX_TYPE;
  4235. offset1 = BNX2_L2CTX_CMD_TYPE;
  4236. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  4237. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  4238. }
  4239. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  4240. bnx2_ctx_wr(bp, cid_addr, offset0, val);
  4241. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  4242. bnx2_ctx_wr(bp, cid_addr, offset1, val);
  4243. val = (u64) txr->tx_desc_mapping >> 32;
  4244. bnx2_ctx_wr(bp, cid_addr, offset2, val);
  4245. val = (u64) txr->tx_desc_mapping & 0xffffffff;
  4246. bnx2_ctx_wr(bp, cid_addr, offset3, val);
  4247. }
  4248. static void
  4249. bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
  4250. {
  4251. struct bnx2_tx_bd *txbd;
  4252. u32 cid = TX_CID;
  4253. struct bnx2_napi *bnapi;
  4254. struct bnx2_tx_ring_info *txr;
  4255. bnapi = &bp->bnx2_napi[ring_num];
  4256. txr = &bnapi->tx_ring;
  4257. if (ring_num == 0)
  4258. cid = TX_CID;
  4259. else
  4260. cid = TX_TSS_CID + ring_num - 1;
  4261. bp->tx_wake_thresh = bp->tx_ring_size / 2;
  4262. txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT];
  4263. txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
  4264. txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
  4265. txr->tx_prod = 0;
  4266. txr->tx_prod_bseq = 0;
  4267. txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
  4268. txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
  4269. bnx2_init_tx_context(bp, cid, txr);
  4270. }
  4271. static void
  4272. bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[],
  4273. u32 buf_size, int num_rings)
  4274. {
  4275. int i;
  4276. struct bnx2_rx_bd *rxbd;
  4277. for (i = 0; i < num_rings; i++) {
  4278. int j;
  4279. rxbd = &rx_ring[i][0];
  4280. for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) {
  4281. rxbd->rx_bd_len = buf_size;
  4282. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  4283. }
  4284. if (i == (num_rings - 1))
  4285. j = 0;
  4286. else
  4287. j = i + 1;
  4288. rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
  4289. rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
  4290. }
  4291. }
  4292. static void
  4293. bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
  4294. {
  4295. int i;
  4296. u16 prod, ring_prod;
  4297. u32 cid, rx_cid_addr, val;
  4298. struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
  4299. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  4300. if (ring_num == 0)
  4301. cid = RX_CID;
  4302. else
  4303. cid = RX_RSS_CID + ring_num - 1;
  4304. rx_cid_addr = GET_CID_ADDR(cid);
  4305. bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
  4306. bp->rx_buf_use_size, bp->rx_max_ring);
  4307. bnx2_init_rx_context(bp, cid);
  4308. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  4309. val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
  4310. BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
  4311. }
  4312. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
  4313. if (bp->rx_pg_ring_size) {
  4314. bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
  4315. rxr->rx_pg_desc_mapping,
  4316. PAGE_SIZE, bp->rx_max_pg_ring);
  4317. val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
  4318. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
  4319. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
  4320. BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
  4321. val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
  4322. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
  4323. val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
  4324. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
  4325. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  4326. BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
  4327. }
  4328. val = (u64) rxr->rx_desc_mapping[0] >> 32;
  4329. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  4330. val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
  4331. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  4332. ring_prod = prod = rxr->rx_pg_prod;
  4333. for (i = 0; i < bp->rx_pg_ring_size; i++) {
  4334. if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
  4335. netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
  4336. ring_num, i, bp->rx_pg_ring_size);
  4337. break;
  4338. }
  4339. prod = BNX2_NEXT_RX_BD(prod);
  4340. ring_prod = BNX2_RX_PG_RING_IDX(prod);
  4341. }
  4342. rxr->rx_pg_prod = prod;
  4343. ring_prod = prod = rxr->rx_prod;
  4344. for (i = 0; i < bp->rx_ring_size; i++) {
  4345. if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
  4346. netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
  4347. ring_num, i, bp->rx_ring_size);
  4348. break;
  4349. }
  4350. prod = BNX2_NEXT_RX_BD(prod);
  4351. ring_prod = BNX2_RX_RING_IDX(prod);
  4352. }
  4353. rxr->rx_prod = prod;
  4354. rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
  4355. rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
  4356. rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
  4357. BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
  4358. BNX2_WR16(bp, rxr->rx_bidx_addr, prod);
  4359. BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
  4360. }
  4361. static void
  4362. bnx2_init_all_rings(struct bnx2 *bp)
  4363. {
  4364. int i;
  4365. u32 val;
  4366. bnx2_clear_ring_states(bp);
  4367. BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
  4368. for (i = 0; i < bp->num_tx_rings; i++)
  4369. bnx2_init_tx_ring(bp, i);
  4370. if (bp->num_tx_rings > 1)
  4371. BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
  4372. (TX_TSS_CID << 7));
  4373. BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
  4374. bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
  4375. for (i = 0; i < bp->num_rx_rings; i++)
  4376. bnx2_init_rx_ring(bp, i);
  4377. if (bp->num_rx_rings > 1) {
  4378. u32 tbl_32 = 0;
  4379. for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
  4380. int shift = (i % 8) << 2;
  4381. tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
  4382. if ((i % 8) == 7) {
  4383. BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
  4384. BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
  4385. BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
  4386. BNX2_RLUP_RSS_COMMAND_WRITE |
  4387. BNX2_RLUP_RSS_COMMAND_HASH_MASK);
  4388. tbl_32 = 0;
  4389. }
  4390. }
  4391. val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
  4392. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
  4393. BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
  4394. }
  4395. }
  4396. static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
  4397. {
  4398. u32 max, num_rings = 1;
  4399. while (ring_size > BNX2_MAX_RX_DESC_CNT) {
  4400. ring_size -= BNX2_MAX_RX_DESC_CNT;
  4401. num_rings++;
  4402. }
  4403. /* round to next power of 2 */
  4404. max = max_size;
  4405. while ((max & num_rings) == 0)
  4406. max >>= 1;
  4407. if (num_rings != max)
  4408. max <<= 1;
  4409. return max;
  4410. }
  4411. static void
  4412. bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
  4413. {
  4414. u32 rx_size, rx_space, jumbo_size;
  4415. /* 8 for CRC and VLAN */
  4416. rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
  4417. rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
  4418. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  4419. bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
  4420. bp->rx_pg_ring_size = 0;
  4421. bp->rx_max_pg_ring = 0;
  4422. bp->rx_max_pg_ring_idx = 0;
  4423. if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
  4424. int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
  4425. jumbo_size = size * pages;
  4426. if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT)
  4427. jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
  4428. bp->rx_pg_ring_size = jumbo_size;
  4429. bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
  4430. BNX2_MAX_RX_PG_RINGS);
  4431. bp->rx_max_pg_ring_idx =
  4432. (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;
  4433. rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
  4434. bp->rx_copy_thresh = 0;
  4435. }
  4436. bp->rx_buf_use_size = rx_size;
  4437. /* hw alignment + build_skb() overhead*/
  4438. bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
  4439. NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  4440. bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
  4441. bp->rx_ring_size = size;
  4442. bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);
  4443. bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;
  4444. }
  4445. static void
  4446. bnx2_free_tx_skbs(struct bnx2 *bp)
  4447. {
  4448. int i;
  4449. for (i = 0; i < bp->num_tx_rings; i++) {
  4450. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  4451. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  4452. int j;
  4453. if (!txr->tx_buf_ring)
  4454. continue;
  4455. for (j = 0; j < BNX2_TX_DESC_CNT; ) {
  4456. struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
  4457. struct sk_buff *skb = tx_buf->skb;
  4458. int k, last;
  4459. if (!skb) {
  4460. j = BNX2_NEXT_TX_BD(j);
  4461. continue;
  4462. }
  4463. dma_unmap_single(&bp->pdev->dev,
  4464. dma_unmap_addr(tx_buf, mapping),
  4465. skb_headlen(skb),
  4466. PCI_DMA_TODEVICE);
  4467. tx_buf->skb = NULL;
  4468. last = tx_buf->nr_frags;
  4469. j = BNX2_NEXT_TX_BD(j);
  4470. for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) {
  4471. tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)];
  4472. dma_unmap_page(&bp->pdev->dev,
  4473. dma_unmap_addr(tx_buf, mapping),
  4474. skb_frag_size(&skb_shinfo(skb)->frags[k]),
  4475. PCI_DMA_TODEVICE);
  4476. }
  4477. dev_kfree_skb(skb);
  4478. }
  4479. netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
  4480. }
  4481. }
  4482. static void
  4483. bnx2_free_rx_skbs(struct bnx2 *bp)
  4484. {
  4485. int i;
  4486. for (i = 0; i < bp->num_rx_rings; i++) {
  4487. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  4488. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  4489. int j;
  4490. if (!rxr->rx_buf_ring)
  4491. return;
  4492. for (j = 0; j < bp->rx_max_ring_idx; j++) {
  4493. struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j];
  4494. u8 *data = rx_buf->data;
  4495. if (!data)
  4496. continue;
  4497. dma_unmap_single(&bp->pdev->dev,
  4498. dma_unmap_addr(rx_buf, mapping),
  4499. bp->rx_buf_use_size,
  4500. PCI_DMA_FROMDEVICE);
  4501. rx_buf->data = NULL;
  4502. kfree(data);
  4503. }
  4504. for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
  4505. bnx2_free_rx_page(bp, rxr, j);
  4506. }
  4507. }
  4508. static void
  4509. bnx2_free_skbs(struct bnx2 *bp)
  4510. {
  4511. bnx2_free_tx_skbs(bp);
  4512. bnx2_free_rx_skbs(bp);
  4513. }
  4514. static int
  4515. bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
  4516. {
  4517. int rc;
  4518. rc = bnx2_reset_chip(bp, reset_code);
  4519. bnx2_free_skbs(bp);
  4520. if (rc)
  4521. return rc;
  4522. if ((rc = bnx2_init_chip(bp)) != 0)
  4523. return rc;
  4524. bnx2_init_all_rings(bp);
  4525. return 0;
  4526. }
  4527. static int
  4528. bnx2_init_nic(struct bnx2 *bp, int reset_phy)
  4529. {
  4530. int rc;
  4531. if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
  4532. return rc;
  4533. spin_lock_bh(&bp->phy_lock);
  4534. bnx2_init_phy(bp, reset_phy);
  4535. bnx2_set_link(bp);
  4536. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4537. bnx2_remote_phy_event(bp);
  4538. spin_unlock_bh(&bp->phy_lock);
  4539. return 0;
  4540. }
  4541. static int
  4542. bnx2_shutdown_chip(struct bnx2 *bp)
  4543. {
  4544. u32 reset_code;
  4545. if (bp->flags & BNX2_FLAG_NO_WOL)
  4546. reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
  4547. else if (bp->wol)
  4548. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  4549. else
  4550. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  4551. return bnx2_reset_chip(bp, reset_code);
  4552. }
  4553. static int
  4554. bnx2_test_registers(struct bnx2 *bp)
  4555. {
  4556. int ret;
  4557. int i, is_5709;
  4558. static const struct {
  4559. u16 offset;
  4560. u16 flags;
  4561. #define BNX2_FL_NOT_5709 1
  4562. u32 rw_mask;
  4563. u32 ro_mask;
  4564. } reg_tbl[] = {
  4565. { 0x006c, 0, 0x00000000, 0x0000003f },
  4566. { 0x0090, 0, 0xffffffff, 0x00000000 },
  4567. { 0x0094, 0, 0x00000000, 0x00000000 },
  4568. { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
  4569. { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4570. { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4571. { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
  4572. { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
  4573. { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
  4574. { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
  4575. { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4576. { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4577. { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4578. { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4579. { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4580. { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4581. { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4582. { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4583. { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
  4584. { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
  4585. { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
  4586. { 0x1000, 0, 0x00000000, 0x00000001 },
  4587. { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
  4588. { 0x1408, 0, 0x01c00800, 0x00000000 },
  4589. { 0x149c, 0, 0x8000ffff, 0x00000000 },
  4590. { 0x14a8, 0, 0x00000000, 0x000001ff },
  4591. { 0x14ac, 0, 0x0fffffff, 0x10000000 },
  4592. { 0x14b0, 0, 0x00000002, 0x00000001 },
  4593. { 0x14b8, 0, 0x00000000, 0x00000000 },
  4594. { 0x14c0, 0, 0x00000000, 0x00000009 },
  4595. { 0x14c4, 0, 0x00003fff, 0x00000000 },
  4596. { 0x14cc, 0, 0x00000000, 0x00000001 },
  4597. { 0x14d0, 0, 0xffffffff, 0x00000000 },
  4598. { 0x1800, 0, 0x00000000, 0x00000001 },
  4599. { 0x1804, 0, 0x00000000, 0x00000003 },
  4600. { 0x2800, 0, 0x00000000, 0x00000001 },
  4601. { 0x2804, 0, 0x00000000, 0x00003f01 },
  4602. { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
  4603. { 0x2810, 0, 0xffff0000, 0x00000000 },
  4604. { 0x2814, 0, 0xffff0000, 0x00000000 },
  4605. { 0x2818, 0, 0xffff0000, 0x00000000 },
  4606. { 0x281c, 0, 0xffff0000, 0x00000000 },
  4607. { 0x2834, 0, 0xffffffff, 0x00000000 },
  4608. { 0x2840, 0, 0x00000000, 0xffffffff },
  4609. { 0x2844, 0, 0x00000000, 0xffffffff },
  4610. { 0x2848, 0, 0xffffffff, 0x00000000 },
  4611. { 0x284c, 0, 0xf800f800, 0x07ff07ff },
  4612. { 0x2c00, 0, 0x00000000, 0x00000011 },
  4613. { 0x2c04, 0, 0x00000000, 0x00030007 },
  4614. { 0x3c00, 0, 0x00000000, 0x00000001 },
  4615. { 0x3c04, 0, 0x00000000, 0x00070000 },
  4616. { 0x3c08, 0, 0x00007f71, 0x07f00000 },
  4617. { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
  4618. { 0x3c10, 0, 0xffffffff, 0x00000000 },
  4619. { 0x3c14, 0, 0x00000000, 0xffffffff },
  4620. { 0x3c18, 0, 0x00000000, 0xffffffff },
  4621. { 0x3c1c, 0, 0xfffff000, 0x00000000 },
  4622. { 0x3c20, 0, 0xffffff00, 0x00000000 },
  4623. { 0x5004, 0, 0x00000000, 0x0000007f },
  4624. { 0x5008, 0, 0x0f0007ff, 0x00000000 },
  4625. { 0x5c00, 0, 0x00000000, 0x00000001 },
  4626. { 0x5c04, 0, 0x00000000, 0x0003000f },
  4627. { 0x5c08, 0, 0x00000003, 0x00000000 },
  4628. { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
  4629. { 0x5c10, 0, 0x00000000, 0xffffffff },
  4630. { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
  4631. { 0x5c84, 0, 0x00000000, 0x0000f333 },
  4632. { 0x5c88, 0, 0x00000000, 0x00077373 },
  4633. { 0x5c8c, 0, 0x00000000, 0x0007f737 },
  4634. { 0x6808, 0, 0x0000ff7f, 0x00000000 },
  4635. { 0x680c, 0, 0xffffffff, 0x00000000 },
  4636. { 0x6810, 0, 0xffffffff, 0x00000000 },
  4637. { 0x6814, 0, 0xffffffff, 0x00000000 },
  4638. { 0x6818, 0, 0xffffffff, 0x00000000 },
  4639. { 0x681c, 0, 0xffffffff, 0x00000000 },
  4640. { 0x6820, 0, 0x00ff00ff, 0x00000000 },
  4641. { 0x6824, 0, 0x00ff00ff, 0x00000000 },
  4642. { 0x6828, 0, 0x00ff00ff, 0x00000000 },
  4643. { 0x682c, 0, 0x03ff03ff, 0x00000000 },
  4644. { 0x6830, 0, 0x03ff03ff, 0x00000000 },
  4645. { 0x6834, 0, 0x03ff03ff, 0x00000000 },
  4646. { 0x6838, 0, 0x03ff03ff, 0x00000000 },
  4647. { 0x683c, 0, 0x0000ffff, 0x00000000 },
  4648. { 0x6840, 0, 0x00000ff0, 0x00000000 },
  4649. { 0x6844, 0, 0x00ffff00, 0x00000000 },
  4650. { 0x684c, 0, 0xffffffff, 0x00000000 },
  4651. { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
  4652. { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
  4653. { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
  4654. { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
  4655. { 0x6908, 0, 0x00000000, 0x0001ff0f },
  4656. { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
  4657. { 0xffff, 0, 0x00000000, 0x00000000 },
  4658. };
  4659. ret = 0;
  4660. is_5709 = 0;
  4661. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  4662. is_5709 = 1;
  4663. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  4664. u32 offset, rw_mask, ro_mask, save_val, val;
  4665. u16 flags = reg_tbl[i].flags;
  4666. if (is_5709 && (flags & BNX2_FL_NOT_5709))
  4667. continue;
  4668. offset = (u32) reg_tbl[i].offset;
  4669. rw_mask = reg_tbl[i].rw_mask;
  4670. ro_mask = reg_tbl[i].ro_mask;
  4671. save_val = readl(bp->regview + offset);
  4672. writel(0, bp->regview + offset);
  4673. val = readl(bp->regview + offset);
  4674. if ((val & rw_mask) != 0) {
  4675. goto reg_test_err;
  4676. }
  4677. if ((val & ro_mask) != (save_val & ro_mask)) {
  4678. goto reg_test_err;
  4679. }
  4680. writel(0xffffffff, bp->regview + offset);
  4681. val = readl(bp->regview + offset);
  4682. if ((val & rw_mask) != rw_mask) {
  4683. goto reg_test_err;
  4684. }
  4685. if ((val & ro_mask) != (save_val & ro_mask)) {
  4686. goto reg_test_err;
  4687. }
  4688. writel(save_val, bp->regview + offset);
  4689. continue;
  4690. reg_test_err:
  4691. writel(save_val, bp->regview + offset);
  4692. ret = -ENODEV;
  4693. break;
  4694. }
  4695. return ret;
  4696. }
  4697. static int
  4698. bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
  4699. {
  4700. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
  4701. 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
  4702. int i;
  4703. for (i = 0; i < sizeof(test_pattern) / 4; i++) {
  4704. u32 offset;
  4705. for (offset = 0; offset < size; offset += 4) {
  4706. bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
  4707. if (bnx2_reg_rd_ind(bp, start + offset) !=
  4708. test_pattern[i]) {
  4709. return -ENODEV;
  4710. }
  4711. }
  4712. }
  4713. return 0;
  4714. }
  4715. static int
  4716. bnx2_test_memory(struct bnx2 *bp)
  4717. {
  4718. int ret = 0;
  4719. int i;
  4720. static struct mem_entry {
  4721. u32 offset;
  4722. u32 len;
  4723. } mem_tbl_5706[] = {
  4724. { 0x60000, 0x4000 },
  4725. { 0xa0000, 0x3000 },
  4726. { 0xe0000, 0x4000 },
  4727. { 0x120000, 0x4000 },
  4728. { 0x1a0000, 0x4000 },
  4729. { 0x160000, 0x4000 },
  4730. { 0xffffffff, 0 },
  4731. },
  4732. mem_tbl_5709[] = {
  4733. { 0x60000, 0x4000 },
  4734. { 0xa0000, 0x3000 },
  4735. { 0xe0000, 0x4000 },
  4736. { 0x120000, 0x4000 },
  4737. { 0x1a0000, 0x4000 },
  4738. { 0xffffffff, 0 },
  4739. };
  4740. struct mem_entry *mem_tbl;
  4741. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  4742. mem_tbl = mem_tbl_5709;
  4743. else
  4744. mem_tbl = mem_tbl_5706;
  4745. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  4746. if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
  4747. mem_tbl[i].len)) != 0) {
  4748. return ret;
  4749. }
  4750. }
  4751. return ret;
  4752. }
  4753. #define BNX2_MAC_LOOPBACK 0
  4754. #define BNX2_PHY_LOOPBACK 1
  4755. static int
  4756. bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
  4757. {
  4758. unsigned int pkt_size, num_pkts, i;
  4759. struct sk_buff *skb;
  4760. u8 *data;
  4761. unsigned char *packet;
  4762. u16 rx_start_idx, rx_idx;
  4763. dma_addr_t map;
  4764. struct bnx2_tx_bd *txbd;
  4765. struct bnx2_sw_bd *rx_buf;
  4766. struct l2_fhdr *rx_hdr;
  4767. int ret = -ENODEV;
  4768. struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
  4769. struct bnx2_tx_ring_info *txr;
  4770. struct bnx2_rx_ring_info *rxr;
  4771. tx_napi = bnapi;
  4772. txr = &tx_napi->tx_ring;
  4773. rxr = &bnapi->rx_ring;
  4774. if (loopback_mode == BNX2_MAC_LOOPBACK) {
  4775. bp->loopback = MAC_LOOPBACK;
  4776. bnx2_set_mac_loopback(bp);
  4777. }
  4778. else if (loopback_mode == BNX2_PHY_LOOPBACK) {
  4779. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4780. return 0;
  4781. bp->loopback = PHY_LOOPBACK;
  4782. bnx2_set_phy_loopback(bp);
  4783. }
  4784. else
  4785. return -EINVAL;
  4786. pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
  4787. skb = netdev_alloc_skb(bp->dev, pkt_size);
  4788. if (!skb)
  4789. return -ENOMEM;
  4790. packet = skb_put(skb, pkt_size);
  4791. memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
  4792. memset(packet + ETH_ALEN, 0x0, 8);
  4793. for (i = 14; i < pkt_size; i++)
  4794. packet[i] = (unsigned char) (i & 0xff);
  4795. map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
  4796. PCI_DMA_TODEVICE);
  4797. if (dma_mapping_error(&bp->pdev->dev, map)) {
  4798. dev_kfree_skb(skb);
  4799. return -EIO;
  4800. }
  4801. BNX2_WR(bp, BNX2_HC_COMMAND,
  4802. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  4803. BNX2_RD(bp, BNX2_HC_COMMAND);
  4804. udelay(5);
  4805. rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
  4806. num_pkts = 0;
  4807. txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)];
  4808. txbd->tx_bd_haddr_hi = (u64) map >> 32;
  4809. txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
  4810. txbd->tx_bd_mss_nbytes = pkt_size;
  4811. txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
  4812. num_pkts++;
  4813. txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod);
  4814. txr->tx_prod_bseq += pkt_size;
  4815. BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
  4816. BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
  4817. udelay(100);
  4818. BNX2_WR(bp, BNX2_HC_COMMAND,
  4819. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  4820. BNX2_RD(bp, BNX2_HC_COMMAND);
  4821. udelay(5);
  4822. dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
  4823. dev_kfree_skb(skb);
  4824. if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
  4825. goto loopback_test_done;
  4826. rx_idx = bnx2_get_hw_rx_cons(bnapi);
  4827. if (rx_idx != rx_start_idx + num_pkts) {
  4828. goto loopback_test_done;
  4829. }
  4830. rx_buf = &rxr->rx_buf_ring[rx_start_idx];
  4831. data = rx_buf->data;
  4832. rx_hdr = get_l2_fhdr(data);
  4833. data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
  4834. dma_sync_single_for_cpu(&bp->pdev->dev,
  4835. dma_unmap_addr(rx_buf, mapping),
  4836. bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
  4837. if (rx_hdr->l2_fhdr_status &
  4838. (L2_FHDR_ERRORS_BAD_CRC |
  4839. L2_FHDR_ERRORS_PHY_DECODE |
  4840. L2_FHDR_ERRORS_ALIGNMENT |
  4841. L2_FHDR_ERRORS_TOO_SHORT |
  4842. L2_FHDR_ERRORS_GIANT_FRAME)) {
  4843. goto loopback_test_done;
  4844. }
  4845. if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
  4846. goto loopback_test_done;
  4847. }
  4848. for (i = 14; i < pkt_size; i++) {
  4849. if (*(data + i) != (unsigned char) (i & 0xff)) {
  4850. goto loopback_test_done;
  4851. }
  4852. }
  4853. ret = 0;
  4854. loopback_test_done:
  4855. bp->loopback = 0;
  4856. return ret;
  4857. }
  4858. #define BNX2_MAC_LOOPBACK_FAILED 1
  4859. #define BNX2_PHY_LOOPBACK_FAILED 2
  4860. #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
  4861. BNX2_PHY_LOOPBACK_FAILED)
  4862. static int
  4863. bnx2_test_loopback(struct bnx2 *bp)
  4864. {
  4865. int rc = 0;
  4866. if (!netif_running(bp->dev))
  4867. return BNX2_LOOPBACK_FAILED;
  4868. bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
  4869. spin_lock_bh(&bp->phy_lock);
  4870. bnx2_init_phy(bp, 1);
  4871. spin_unlock_bh(&bp->phy_lock);
  4872. if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
  4873. rc |= BNX2_MAC_LOOPBACK_FAILED;
  4874. if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
  4875. rc |= BNX2_PHY_LOOPBACK_FAILED;
  4876. return rc;
  4877. }
  4878. #define NVRAM_SIZE 0x200
  4879. #define CRC32_RESIDUAL 0xdebb20e3
  4880. static int
  4881. bnx2_test_nvram(struct bnx2 *bp)
  4882. {
  4883. __be32 buf[NVRAM_SIZE / 4];
  4884. u8 *data = (u8 *) buf;
  4885. int rc = 0;
  4886. u32 magic, csum;
  4887. if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
  4888. goto test_nvram_done;
  4889. magic = be32_to_cpu(buf[0]);
  4890. if (magic != 0x669955aa) {
  4891. rc = -ENODEV;
  4892. goto test_nvram_done;
  4893. }
  4894. if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
  4895. goto test_nvram_done;
  4896. csum = ether_crc_le(0x100, data);
  4897. if (csum != CRC32_RESIDUAL) {
  4898. rc = -ENODEV;
  4899. goto test_nvram_done;
  4900. }
  4901. csum = ether_crc_le(0x100, data + 0x100);
  4902. if (csum != CRC32_RESIDUAL) {
  4903. rc = -ENODEV;
  4904. }
  4905. test_nvram_done:
  4906. return rc;
  4907. }
  4908. static int
  4909. bnx2_test_link(struct bnx2 *bp)
  4910. {
  4911. u32 bmsr;
  4912. if (!netif_running(bp->dev))
  4913. return -ENODEV;
  4914. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  4915. if (bp->link_up)
  4916. return 0;
  4917. return -ENODEV;
  4918. }
  4919. spin_lock_bh(&bp->phy_lock);
  4920. bnx2_enable_bmsr1(bp);
  4921. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  4922. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  4923. bnx2_disable_bmsr1(bp);
  4924. spin_unlock_bh(&bp->phy_lock);
  4925. if (bmsr & BMSR_LSTATUS) {
  4926. return 0;
  4927. }
  4928. return -ENODEV;
  4929. }
  4930. static int
  4931. bnx2_test_intr(struct bnx2 *bp)
  4932. {
  4933. int i;
  4934. u16 status_idx;
  4935. if (!netif_running(bp->dev))
  4936. return -ENODEV;
  4937. status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
  4938. /* This register is not touched during run-time. */
  4939. BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  4940. BNX2_RD(bp, BNX2_HC_COMMAND);
  4941. for (i = 0; i < 10; i++) {
  4942. if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
  4943. status_idx) {
  4944. break;
  4945. }
  4946. msleep_interruptible(10);
  4947. }
  4948. if (i < 10)
  4949. return 0;
  4950. return -ENODEV;
  4951. }
  4952. /* Determining link for parallel detection. */
  4953. static int
  4954. bnx2_5706_serdes_has_link(struct bnx2 *bp)
  4955. {
  4956. u32 mode_ctl, an_dbg, exp;
  4957. if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
  4958. return 0;
  4959. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
  4960. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
  4961. if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
  4962. return 0;
  4963. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  4964. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  4965. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  4966. if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
  4967. return 0;
  4968. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
  4969. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
  4970. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
  4971. if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
  4972. return 0;
  4973. return 1;
  4974. }
  4975. static void
  4976. bnx2_5706_serdes_timer(struct bnx2 *bp)
  4977. {
  4978. int check_link = 1;
  4979. spin_lock(&bp->phy_lock);
  4980. if (bp->serdes_an_pending) {
  4981. bp->serdes_an_pending--;
  4982. check_link = 0;
  4983. } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  4984. u32 bmcr;
  4985. bp->current_interval = BNX2_TIMER_INTERVAL;
  4986. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  4987. if (bmcr & BMCR_ANENABLE) {
  4988. if (bnx2_5706_serdes_has_link(bp)) {
  4989. bmcr &= ~BMCR_ANENABLE;
  4990. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  4991. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  4992. bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
  4993. }
  4994. }
  4995. }
  4996. else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
  4997. (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
  4998. u32 phy2;
  4999. bnx2_write_phy(bp, 0x17, 0x0f01);
  5000. bnx2_read_phy(bp, 0x15, &phy2);
  5001. if (phy2 & 0x20) {
  5002. u32 bmcr;
  5003. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  5004. bmcr |= BMCR_ANENABLE;
  5005. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  5006. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  5007. }
  5008. } else
  5009. bp->current_interval = BNX2_TIMER_INTERVAL;
  5010. if (check_link) {
  5011. u32 val;
  5012. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  5013. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
  5014. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
  5015. if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
  5016. if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
  5017. bnx2_5706s_force_link_dn(bp, 1);
  5018. bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
  5019. } else
  5020. bnx2_set_link(bp);
  5021. } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
  5022. bnx2_set_link(bp);
  5023. }
  5024. spin_unlock(&bp->phy_lock);
  5025. }
  5026. static void
  5027. bnx2_5708_serdes_timer(struct bnx2 *bp)
  5028. {
  5029. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  5030. return;
  5031. if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
  5032. bp->serdes_an_pending = 0;
  5033. return;
  5034. }
  5035. spin_lock(&bp->phy_lock);
  5036. if (bp->serdes_an_pending)
  5037. bp->serdes_an_pending--;
  5038. else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  5039. u32 bmcr;
  5040. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  5041. if (bmcr & BMCR_ANENABLE) {
  5042. bnx2_enable_forced_2g5(bp);
  5043. bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
  5044. } else {
  5045. bnx2_disable_forced_2g5(bp);
  5046. bp->serdes_an_pending = 2;
  5047. bp->current_interval = BNX2_TIMER_INTERVAL;
  5048. }
  5049. } else
  5050. bp->current_interval = BNX2_TIMER_INTERVAL;
  5051. spin_unlock(&bp->phy_lock);
  5052. }
  5053. static void
  5054. bnx2_timer(struct timer_list *t)
  5055. {
  5056. struct bnx2 *bp = from_timer(bp, t, timer);
  5057. if (!netif_running(bp->dev))
  5058. return;
  5059. if (atomic_read(&bp->intr_sem) != 0)
  5060. goto bnx2_restart_timer;
  5061. if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
  5062. BNX2_FLAG_USING_MSI)
  5063. bnx2_chk_missed_msi(bp);
  5064. bnx2_send_heart_beat(bp);
  5065. bp->stats_blk->stat_FwRxDrop =
  5066. bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
  5067. /* workaround occasional corrupted counters */
  5068. if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
  5069. BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
  5070. BNX2_HC_COMMAND_STATS_NOW);
  5071. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  5072. if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
  5073. bnx2_5706_serdes_timer(bp);
  5074. else
  5075. bnx2_5708_serdes_timer(bp);
  5076. }
  5077. bnx2_restart_timer:
  5078. mod_timer(&bp->timer, jiffies + bp->current_interval);
  5079. }
  5080. static int
  5081. bnx2_request_irq(struct bnx2 *bp)
  5082. {
  5083. unsigned long flags;
  5084. struct bnx2_irq *irq;
  5085. int rc = 0, i;
  5086. if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
  5087. flags = 0;
  5088. else
  5089. flags = IRQF_SHARED;
  5090. for (i = 0; i < bp->irq_nvecs; i++) {
  5091. irq = &bp->irq_tbl[i];
  5092. rc = request_irq(irq->vector, irq->handler, flags, irq->name,
  5093. &bp->bnx2_napi[i]);
  5094. if (rc)
  5095. break;
  5096. irq->requested = 1;
  5097. }
  5098. return rc;
  5099. }
  5100. static void
  5101. __bnx2_free_irq(struct bnx2 *bp)
  5102. {
  5103. struct bnx2_irq *irq;
  5104. int i;
  5105. for (i = 0; i < bp->irq_nvecs; i++) {
  5106. irq = &bp->irq_tbl[i];
  5107. if (irq->requested)
  5108. free_irq(irq->vector, &bp->bnx2_napi[i]);
  5109. irq->requested = 0;
  5110. }
  5111. }
  5112. static void
  5113. bnx2_free_irq(struct bnx2 *bp)
  5114. {
  5115. __bnx2_free_irq(bp);
  5116. if (bp->flags & BNX2_FLAG_USING_MSI)
  5117. pci_disable_msi(bp->pdev);
  5118. else if (bp->flags & BNX2_FLAG_USING_MSIX)
  5119. pci_disable_msix(bp->pdev);
  5120. bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
  5121. }
  5122. static void
  5123. bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
  5124. {
  5125. int i, total_vecs;
  5126. struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
  5127. struct net_device *dev = bp->dev;
  5128. const int len = sizeof(bp->irq_tbl[0].name);
  5129. bnx2_setup_msix_tbl(bp);
  5130. BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
  5131. BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
  5132. BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
  5133. /* Need to flush the previous three writes to ensure MSI-X
  5134. * is setup properly */
  5135. BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
  5136. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
  5137. msix_ent[i].entry = i;
  5138. msix_ent[i].vector = 0;
  5139. }
  5140. total_vecs = msix_vecs;
  5141. #ifdef BCM_CNIC
  5142. total_vecs++;
  5143. #endif
  5144. total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,
  5145. BNX2_MIN_MSIX_VEC, total_vecs);
  5146. if (total_vecs < 0)
  5147. return;
  5148. msix_vecs = total_vecs;
  5149. #ifdef BCM_CNIC
  5150. msix_vecs--;
  5151. #endif
  5152. bp->irq_nvecs = msix_vecs;
  5153. bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
  5154. for (i = 0; i < total_vecs; i++) {
  5155. bp->irq_tbl[i].vector = msix_ent[i].vector;
  5156. snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
  5157. bp->irq_tbl[i].handler = bnx2_msi_1shot;
  5158. }
  5159. }
  5160. static int
  5161. bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
  5162. {
  5163. int cpus = netif_get_num_default_rss_queues();
  5164. int msix_vecs;
  5165. if (!bp->num_req_rx_rings)
  5166. msix_vecs = max(cpus + 1, bp->num_req_tx_rings);
  5167. else if (!bp->num_req_tx_rings)
  5168. msix_vecs = max(cpus, bp->num_req_rx_rings);
  5169. else
  5170. msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);
  5171. msix_vecs = min(msix_vecs, RX_MAX_RINGS);
  5172. bp->irq_tbl[0].handler = bnx2_interrupt;
  5173. strcpy(bp->irq_tbl[0].name, bp->dev->name);
  5174. bp->irq_nvecs = 1;
  5175. bp->irq_tbl[0].vector = bp->pdev->irq;
  5176. if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
  5177. bnx2_enable_msix(bp, msix_vecs);
  5178. if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
  5179. !(bp->flags & BNX2_FLAG_USING_MSIX)) {
  5180. if (pci_enable_msi(bp->pdev) == 0) {
  5181. bp->flags |= BNX2_FLAG_USING_MSI;
  5182. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  5183. bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
  5184. bp->irq_tbl[0].handler = bnx2_msi_1shot;
  5185. } else
  5186. bp->irq_tbl[0].handler = bnx2_msi;
  5187. bp->irq_tbl[0].vector = bp->pdev->irq;
  5188. }
  5189. }
  5190. if (!bp->num_req_tx_rings)
  5191. bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
  5192. else
  5193. bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);
  5194. if (!bp->num_req_rx_rings)
  5195. bp->num_rx_rings = bp->irq_nvecs;
  5196. else
  5197. bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);
  5198. netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
  5199. return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
  5200. }
  5201. /* Called with rtnl_lock */
  5202. static int
  5203. bnx2_open(struct net_device *dev)
  5204. {
  5205. struct bnx2 *bp = netdev_priv(dev);
  5206. int rc;
  5207. rc = bnx2_request_firmware(bp);
  5208. if (rc < 0)
  5209. goto out;
  5210. netif_carrier_off(dev);
  5211. bnx2_disable_int(bp);
  5212. rc = bnx2_setup_int_mode(bp, disable_msi);
  5213. if (rc)
  5214. goto open_err;
  5215. bnx2_init_napi(bp);
  5216. bnx2_napi_enable(bp);
  5217. rc = bnx2_alloc_mem(bp);
  5218. if (rc)
  5219. goto open_err;
  5220. rc = bnx2_request_irq(bp);
  5221. if (rc)
  5222. goto open_err;
  5223. rc = bnx2_init_nic(bp, 1);
  5224. if (rc)
  5225. goto open_err;
  5226. mod_timer(&bp->timer, jiffies + bp->current_interval);
  5227. atomic_set(&bp->intr_sem, 0);
  5228. memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
  5229. bnx2_enable_int(bp);
  5230. if (bp->flags & BNX2_FLAG_USING_MSI) {
  5231. /* Test MSI to make sure it is working
  5232. * If MSI test fails, go back to INTx mode
  5233. */
  5234. if (bnx2_test_intr(bp) != 0) {
  5235. netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
  5236. bnx2_disable_int(bp);
  5237. bnx2_free_irq(bp);
  5238. bnx2_setup_int_mode(bp, 1);
  5239. rc = bnx2_init_nic(bp, 0);
  5240. if (!rc)
  5241. rc = bnx2_request_irq(bp);
  5242. if (rc) {
  5243. del_timer_sync(&bp->timer);
  5244. goto open_err;
  5245. }
  5246. bnx2_enable_int(bp);
  5247. }
  5248. }
  5249. if (bp->flags & BNX2_FLAG_USING_MSI)
  5250. netdev_info(dev, "using MSI\n");
  5251. else if (bp->flags & BNX2_FLAG_USING_MSIX)
  5252. netdev_info(dev, "using MSIX\n");
  5253. netif_tx_start_all_queues(dev);
  5254. out:
  5255. return rc;
  5256. open_err:
  5257. bnx2_napi_disable(bp);
  5258. bnx2_free_skbs(bp);
  5259. bnx2_free_irq(bp);
  5260. bnx2_free_mem(bp);
  5261. bnx2_del_napi(bp);
  5262. bnx2_release_firmware(bp);
  5263. goto out;
  5264. }
  5265. static void
  5266. bnx2_reset_task(struct work_struct *work)
  5267. {
  5268. struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
  5269. int rc;
  5270. u16 pcicmd;
  5271. rtnl_lock();
  5272. if (!netif_running(bp->dev)) {
  5273. rtnl_unlock();
  5274. return;
  5275. }
  5276. bnx2_netif_stop(bp, true);
  5277. pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);
  5278. if (!(pcicmd & PCI_COMMAND_MEMORY)) {
  5279. /* in case PCI block has reset */
  5280. pci_restore_state(bp->pdev);
  5281. pci_save_state(bp->pdev);
  5282. }
  5283. rc = bnx2_init_nic(bp, 1);
  5284. if (rc) {
  5285. netdev_err(bp->dev, "failed to reset NIC, closing\n");
  5286. bnx2_napi_enable(bp);
  5287. dev_close(bp->dev);
  5288. rtnl_unlock();
  5289. return;
  5290. }
  5291. atomic_set(&bp->intr_sem, 1);
  5292. bnx2_netif_start(bp, true);
  5293. rtnl_unlock();
  5294. }
  5295. #define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL }
  5296. static void
  5297. bnx2_dump_ftq(struct bnx2 *bp)
  5298. {
  5299. int i;
  5300. u32 reg, bdidx, cid, valid;
  5301. struct net_device *dev = bp->dev;
  5302. static const struct ftq_reg {
  5303. char *name;
  5304. u32 off;
  5305. } ftq_arr[] = {
  5306. BNX2_FTQ_ENTRY(RV2P_P),
  5307. BNX2_FTQ_ENTRY(RV2P_T),
  5308. BNX2_FTQ_ENTRY(RV2P_M),
  5309. BNX2_FTQ_ENTRY(TBDR_),
  5310. BNX2_FTQ_ENTRY(TDMA_),
  5311. BNX2_FTQ_ENTRY(TXP_),
  5312. BNX2_FTQ_ENTRY(TXP_),
  5313. BNX2_FTQ_ENTRY(TPAT_),
  5314. BNX2_FTQ_ENTRY(RXP_C),
  5315. BNX2_FTQ_ENTRY(RXP_),
  5316. BNX2_FTQ_ENTRY(COM_COMXQ_),
  5317. BNX2_FTQ_ENTRY(COM_COMTQ_),
  5318. BNX2_FTQ_ENTRY(COM_COMQ_),
  5319. BNX2_FTQ_ENTRY(CP_CPQ_),
  5320. };
  5321. netdev_err(dev, "<--- start FTQ dump --->\n");
  5322. for (i = 0; i < ARRAY_SIZE(ftq_arr); i++)
  5323. netdev_err(dev, "%s %08x\n", ftq_arr[i].name,
  5324. bnx2_reg_rd_ind(bp, ftq_arr[i].off));
  5325. netdev_err(dev, "CPU states:\n");
  5326. for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000)
  5327. netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n",
  5328. reg, bnx2_reg_rd_ind(bp, reg),
  5329. bnx2_reg_rd_ind(bp, reg + 4),
  5330. bnx2_reg_rd_ind(bp, reg + 8),
  5331. bnx2_reg_rd_ind(bp, reg + 0x1c),
  5332. bnx2_reg_rd_ind(bp, reg + 0x1c),
  5333. bnx2_reg_rd_ind(bp, reg + 0x20));
  5334. netdev_err(dev, "<--- end FTQ dump --->\n");
  5335. netdev_err(dev, "<--- start TBDC dump --->\n");
  5336. netdev_err(dev, "TBDC free cnt: %ld\n",
  5337. BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
  5338. netdev_err(dev, "LINE CID BIDX CMD VALIDS\n");
  5339. for (i = 0; i < 0x20; i++) {
  5340. int j = 0;
  5341. BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
  5342. BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
  5343. BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ);
  5344. BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
  5345. while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
  5346. BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100)
  5347. j++;
  5348. cid = BNX2_RD(bp, BNX2_TBDC_CID);
  5349. bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
  5350. valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
  5351. netdev_err(dev, "%02x %06x %04lx %02x [%x]\n",
  5352. i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX,
  5353. bdidx >> 24, (valid >> 8) & 0x0ff);
  5354. }
  5355. netdev_err(dev, "<--- end TBDC dump --->\n");
  5356. }
  5357. static void
  5358. bnx2_dump_state(struct bnx2 *bp)
  5359. {
  5360. struct net_device *dev = bp->dev;
  5361. u32 val1, val2;
  5362. pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
  5363. netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
  5364. atomic_read(&bp->intr_sem), val1);
  5365. pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
  5366. pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
  5367. netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
  5368. netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
  5369. BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
  5370. BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
  5371. netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
  5372. BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
  5373. netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
  5374. BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
  5375. if (bp->flags & BNX2_FLAG_USING_MSIX)
  5376. netdev_err(dev, "DEBUG: PBA[%08x]\n",
  5377. BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
  5378. }
  5379. static void
  5380. bnx2_tx_timeout(struct net_device *dev, unsigned int txqueue)
  5381. {
  5382. struct bnx2 *bp = netdev_priv(dev);
  5383. bnx2_dump_ftq(bp);
  5384. bnx2_dump_state(bp);
  5385. bnx2_dump_mcp_state(bp);
  5386. /* This allows the netif to be shutdown gracefully before resetting */
  5387. schedule_work(&bp->reset_task);
  5388. }
  5389. /* Called with netif_tx_lock.
  5390. * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
  5391. * netif_wake_queue().
  5392. */
  5393. static netdev_tx_t
  5394. bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
  5395. {
  5396. struct bnx2 *bp = netdev_priv(dev);
  5397. dma_addr_t mapping;
  5398. struct bnx2_tx_bd *txbd;
  5399. struct bnx2_sw_tx_bd *tx_buf;
  5400. u32 len, vlan_tag_flags, last_frag, mss;
  5401. u16 prod, ring_prod;
  5402. int i;
  5403. struct bnx2_napi *bnapi;
  5404. struct bnx2_tx_ring_info *txr;
  5405. struct netdev_queue *txq;
  5406. /* Determine which tx ring we will be placed on */
  5407. i = skb_get_queue_mapping(skb);
  5408. bnapi = &bp->bnx2_napi[i];
  5409. txr = &bnapi->tx_ring;
  5410. txq = netdev_get_tx_queue(dev, i);
  5411. if (unlikely(bnx2_tx_avail(bp, txr) <
  5412. (skb_shinfo(skb)->nr_frags + 1))) {
  5413. netif_tx_stop_queue(txq);
  5414. netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
  5415. return NETDEV_TX_BUSY;
  5416. }
  5417. len = skb_headlen(skb);
  5418. prod = txr->tx_prod;
  5419. ring_prod = BNX2_TX_RING_IDX(prod);
  5420. vlan_tag_flags = 0;
  5421. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  5422. vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
  5423. }
  5424. if (skb_vlan_tag_present(skb)) {
  5425. vlan_tag_flags |=
  5426. (TX_BD_FLAGS_VLAN_TAG | (skb_vlan_tag_get(skb) << 16));
  5427. }
  5428. if ((mss = skb_shinfo(skb)->gso_size)) {
  5429. u32 tcp_opt_len;
  5430. struct iphdr *iph;
  5431. vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
  5432. tcp_opt_len = tcp_optlen(skb);
  5433. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
  5434. u32 tcp_off = skb_transport_offset(skb) -
  5435. sizeof(struct ipv6hdr) - ETH_HLEN;
  5436. vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
  5437. TX_BD_FLAGS_SW_FLAGS;
  5438. if (likely(tcp_off == 0))
  5439. vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
  5440. else {
  5441. tcp_off >>= 3;
  5442. vlan_tag_flags |= ((tcp_off & 0x3) <<
  5443. TX_BD_FLAGS_TCP6_OFF0_SHL) |
  5444. ((tcp_off & 0x10) <<
  5445. TX_BD_FLAGS_TCP6_OFF4_SHL);
  5446. mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
  5447. }
  5448. } else {
  5449. iph = ip_hdr(skb);
  5450. if (tcp_opt_len || (iph->ihl > 5)) {
  5451. vlan_tag_flags |= ((iph->ihl - 5) +
  5452. (tcp_opt_len >> 2)) << 8;
  5453. }
  5454. }
  5455. } else
  5456. mss = 0;
  5457. mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
  5458. if (dma_mapping_error(&bp->pdev->dev, mapping)) {
  5459. dev_kfree_skb_any(skb);
  5460. return NETDEV_TX_OK;
  5461. }
  5462. tx_buf = &txr->tx_buf_ring[ring_prod];
  5463. tx_buf->skb = skb;
  5464. dma_unmap_addr_set(tx_buf, mapping, mapping);
  5465. txbd = &txr->tx_desc_ring[ring_prod];
  5466. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  5467. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  5468. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  5469. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
  5470. last_frag = skb_shinfo(skb)->nr_frags;
  5471. tx_buf->nr_frags = last_frag;
  5472. tx_buf->is_gso = skb_is_gso(skb);
  5473. for (i = 0; i < last_frag; i++) {
  5474. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  5475. prod = BNX2_NEXT_TX_BD(prod);
  5476. ring_prod = BNX2_TX_RING_IDX(prod);
  5477. txbd = &txr->tx_desc_ring[ring_prod];
  5478. len = skb_frag_size(frag);
  5479. mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
  5480. DMA_TO_DEVICE);
  5481. if (dma_mapping_error(&bp->pdev->dev, mapping))
  5482. goto dma_error;
  5483. dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
  5484. mapping);
  5485. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  5486. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  5487. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  5488. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
  5489. }
  5490. txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
  5491. /* Sync BD data before updating TX mailbox */
  5492. wmb();
  5493. netdev_tx_sent_queue(txq, skb->len);
  5494. prod = BNX2_NEXT_TX_BD(prod);
  5495. txr->tx_prod_bseq += skb->len;
  5496. BNX2_WR16(bp, txr->tx_bidx_addr, prod);
  5497. BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
  5498. txr->tx_prod = prod;
  5499. if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
  5500. netif_tx_stop_queue(txq);
  5501. /* netif_tx_stop_queue() must be done before checking
  5502. * tx index in bnx2_tx_avail() below, because in
  5503. * bnx2_tx_int(), we update tx index before checking for
  5504. * netif_tx_queue_stopped().
  5505. */
  5506. smp_mb();
  5507. if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
  5508. netif_tx_wake_queue(txq);
  5509. }
  5510. return NETDEV_TX_OK;
  5511. dma_error:
  5512. /* save value of frag that failed */
  5513. last_frag = i;
  5514. /* start back at beginning and unmap skb */
  5515. prod = txr->tx_prod;
  5516. ring_prod = BNX2_TX_RING_IDX(prod);
  5517. tx_buf = &txr->tx_buf_ring[ring_prod];
  5518. tx_buf->skb = NULL;
  5519. dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
  5520. skb_headlen(skb), PCI_DMA_TODEVICE);
  5521. /* unmap remaining mapped pages */
  5522. for (i = 0; i < last_frag; i++) {
  5523. prod = BNX2_NEXT_TX_BD(prod);
  5524. ring_prod = BNX2_TX_RING_IDX(prod);
  5525. tx_buf = &txr->tx_buf_ring[ring_prod];
  5526. dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
  5527. skb_frag_size(&skb_shinfo(skb)->frags[i]),
  5528. PCI_DMA_TODEVICE);
  5529. }
  5530. dev_kfree_skb_any(skb);
  5531. return NETDEV_TX_OK;
  5532. }
  5533. /* Called with rtnl_lock */
  5534. static int
  5535. bnx2_close(struct net_device *dev)
  5536. {
  5537. struct bnx2 *bp = netdev_priv(dev);
  5538. bnx2_disable_int_sync(bp);
  5539. bnx2_napi_disable(bp);
  5540. netif_tx_disable(dev);
  5541. del_timer_sync(&bp->timer);
  5542. bnx2_shutdown_chip(bp);
  5543. bnx2_free_irq(bp);
  5544. bnx2_free_skbs(bp);
  5545. bnx2_free_mem(bp);
  5546. bnx2_del_napi(bp);
  5547. bp->link_up = 0;
  5548. netif_carrier_off(bp->dev);
  5549. return 0;
  5550. }
  5551. static void
  5552. bnx2_save_stats(struct bnx2 *bp)
  5553. {
  5554. u32 *hw_stats = (u32 *) bp->stats_blk;
  5555. u32 *temp_stats = (u32 *) bp->temp_stats_blk;
  5556. int i;
  5557. /* The 1st 10 counters are 64-bit counters */
  5558. for (i = 0; i < 20; i += 2) {
  5559. u32 hi;
  5560. u64 lo;
  5561. hi = temp_stats[i] + hw_stats[i];
  5562. lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
  5563. if (lo > 0xffffffff)
  5564. hi++;
  5565. temp_stats[i] = hi;
  5566. temp_stats[i + 1] = lo & 0xffffffff;
  5567. }
  5568. for ( ; i < sizeof(struct statistics_block) / 4; i++)
  5569. temp_stats[i] += hw_stats[i];
  5570. }
  5571. #define GET_64BIT_NET_STATS64(ctr) \
  5572. (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
  5573. #define GET_64BIT_NET_STATS(ctr) \
  5574. GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
  5575. GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
  5576. #define GET_32BIT_NET_STATS(ctr) \
  5577. (unsigned long) (bp->stats_blk->ctr + \
  5578. bp->temp_stats_blk->ctr)
  5579. static void
  5580. bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
  5581. {
  5582. struct bnx2 *bp = netdev_priv(dev);
  5583. if (!bp->stats_blk)
  5584. return;
  5585. net_stats->rx_packets =
  5586. GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
  5587. GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
  5588. GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
  5589. net_stats->tx_packets =
  5590. GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
  5591. GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
  5592. GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
  5593. net_stats->rx_bytes =
  5594. GET_64BIT_NET_STATS(stat_IfHCInOctets);
  5595. net_stats->tx_bytes =
  5596. GET_64BIT_NET_STATS(stat_IfHCOutOctets);
  5597. net_stats->multicast =
  5598. GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
  5599. net_stats->collisions =
  5600. GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
  5601. net_stats->rx_length_errors =
  5602. GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
  5603. GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
  5604. net_stats->rx_over_errors =
  5605. GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
  5606. GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
  5607. net_stats->rx_frame_errors =
  5608. GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
  5609. net_stats->rx_crc_errors =
  5610. GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
  5611. net_stats->rx_errors = net_stats->rx_length_errors +
  5612. net_stats->rx_over_errors + net_stats->rx_frame_errors +
  5613. net_stats->rx_crc_errors;
  5614. net_stats->tx_aborted_errors =
  5615. GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
  5616. GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
  5617. if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
  5618. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
  5619. net_stats->tx_carrier_errors = 0;
  5620. else {
  5621. net_stats->tx_carrier_errors =
  5622. GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
  5623. }
  5624. net_stats->tx_errors =
  5625. GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
  5626. net_stats->tx_aborted_errors +
  5627. net_stats->tx_carrier_errors;
  5628. net_stats->rx_missed_errors =
  5629. GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
  5630. GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
  5631. GET_32BIT_NET_STATS(stat_FwRxDrop);
  5632. }
  5633. /* All ethtool functions called with rtnl_lock */
  5634. static int
  5635. bnx2_get_link_ksettings(struct net_device *dev,
  5636. struct ethtool_link_ksettings *cmd)
  5637. {
  5638. struct bnx2 *bp = netdev_priv(dev);
  5639. int support_serdes = 0, support_copper = 0;
  5640. u32 supported, advertising;
  5641. supported = SUPPORTED_Autoneg;
  5642. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  5643. support_serdes = 1;
  5644. support_copper = 1;
  5645. } else if (bp->phy_port == PORT_FIBRE)
  5646. support_serdes = 1;
  5647. else
  5648. support_copper = 1;
  5649. if (support_serdes) {
  5650. supported |= SUPPORTED_1000baseT_Full |
  5651. SUPPORTED_FIBRE;
  5652. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
  5653. supported |= SUPPORTED_2500baseX_Full;
  5654. }
  5655. if (support_copper) {
  5656. supported |= SUPPORTED_10baseT_Half |
  5657. SUPPORTED_10baseT_Full |
  5658. SUPPORTED_100baseT_Half |
  5659. SUPPORTED_100baseT_Full |
  5660. SUPPORTED_1000baseT_Full |
  5661. SUPPORTED_TP;
  5662. }
  5663. spin_lock_bh(&bp->phy_lock);
  5664. cmd->base.port = bp->phy_port;
  5665. advertising = bp->advertising;
  5666. if (bp->autoneg & AUTONEG_SPEED) {
  5667. cmd->base.autoneg = AUTONEG_ENABLE;
  5668. } else {
  5669. cmd->base.autoneg = AUTONEG_DISABLE;
  5670. }
  5671. if (netif_carrier_ok(dev)) {
  5672. cmd->base.speed = bp->line_speed;
  5673. cmd->base.duplex = bp->duplex;
  5674. if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {
  5675. if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)
  5676. cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
  5677. else
  5678. cmd->base.eth_tp_mdix = ETH_TP_MDI;
  5679. }
  5680. }
  5681. else {
  5682. cmd->base.speed = SPEED_UNKNOWN;
  5683. cmd->base.duplex = DUPLEX_UNKNOWN;
  5684. }
  5685. spin_unlock_bh(&bp->phy_lock);
  5686. cmd->base.phy_address = bp->phy_addr;
  5687. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
  5688. supported);
  5689. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
  5690. advertising);
  5691. return 0;
  5692. }
  5693. static int
  5694. bnx2_set_link_ksettings(struct net_device *dev,
  5695. const struct ethtool_link_ksettings *cmd)
  5696. {
  5697. struct bnx2 *bp = netdev_priv(dev);
  5698. u8 autoneg = bp->autoneg;
  5699. u8 req_duplex = bp->req_duplex;
  5700. u16 req_line_speed = bp->req_line_speed;
  5701. u32 advertising = bp->advertising;
  5702. int err = -EINVAL;
  5703. spin_lock_bh(&bp->phy_lock);
  5704. if (cmd->base.port != PORT_TP && cmd->base.port != PORT_FIBRE)
  5705. goto err_out_unlock;
  5706. if (cmd->base.port != bp->phy_port &&
  5707. !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
  5708. goto err_out_unlock;
  5709. /* If device is down, we can store the settings only if the user
  5710. * is setting the currently active port.
  5711. */
  5712. if (!netif_running(dev) && cmd->base.port != bp->phy_port)
  5713. goto err_out_unlock;
  5714. if (cmd->base.autoneg == AUTONEG_ENABLE) {
  5715. autoneg |= AUTONEG_SPEED;
  5716. ethtool_convert_link_mode_to_legacy_u32(
  5717. &advertising, cmd->link_modes.advertising);
  5718. if (cmd->base.port == PORT_TP) {
  5719. advertising &= ETHTOOL_ALL_COPPER_SPEED;
  5720. if (!advertising)
  5721. advertising = ETHTOOL_ALL_COPPER_SPEED;
  5722. } else {
  5723. advertising &= ETHTOOL_ALL_FIBRE_SPEED;
  5724. if (!advertising)
  5725. advertising = ETHTOOL_ALL_FIBRE_SPEED;
  5726. }
  5727. advertising |= ADVERTISED_Autoneg;
  5728. }
  5729. else {
  5730. u32 speed = cmd->base.speed;
  5731. if (cmd->base.port == PORT_FIBRE) {
  5732. if ((speed != SPEED_1000 &&
  5733. speed != SPEED_2500) ||
  5734. (cmd->base.duplex != DUPLEX_FULL))
  5735. goto err_out_unlock;
  5736. if (speed == SPEED_2500 &&
  5737. !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  5738. goto err_out_unlock;
  5739. } else if (speed == SPEED_1000 || speed == SPEED_2500)
  5740. goto err_out_unlock;
  5741. autoneg &= ~AUTONEG_SPEED;
  5742. req_line_speed = speed;
  5743. req_duplex = cmd->base.duplex;
  5744. advertising = 0;
  5745. }
  5746. bp->autoneg = autoneg;
  5747. bp->advertising = advertising;
  5748. bp->req_line_speed = req_line_speed;
  5749. bp->req_duplex = req_duplex;
  5750. err = 0;
  5751. /* If device is down, the new settings will be picked up when it is
  5752. * brought up.
  5753. */
  5754. if (netif_running(dev))
  5755. err = bnx2_setup_phy(bp, cmd->base.port);
  5756. err_out_unlock:
  5757. spin_unlock_bh(&bp->phy_lock);
  5758. return err;
  5759. }
  5760. static void
  5761. bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  5762. {
  5763. struct bnx2 *bp = netdev_priv(dev);
  5764. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  5765. strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
  5766. strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
  5767. }
  5768. #define BNX2_REGDUMP_LEN (32 * 1024)
  5769. static int
  5770. bnx2_get_regs_len(struct net_device *dev)
  5771. {
  5772. return BNX2_REGDUMP_LEN;
  5773. }
  5774. static void
  5775. bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
  5776. {
  5777. u32 *p = _p, i, offset;
  5778. u8 *orig_p = _p;
  5779. struct bnx2 *bp = netdev_priv(dev);
  5780. static const u32 reg_boundaries[] = {
  5781. 0x0000, 0x0098, 0x0400, 0x045c,
  5782. 0x0800, 0x0880, 0x0c00, 0x0c10,
  5783. 0x0c30, 0x0d08, 0x1000, 0x101c,
  5784. 0x1040, 0x1048, 0x1080, 0x10a4,
  5785. 0x1400, 0x1490, 0x1498, 0x14f0,
  5786. 0x1500, 0x155c, 0x1580, 0x15dc,
  5787. 0x1600, 0x1658, 0x1680, 0x16d8,
  5788. 0x1800, 0x1820, 0x1840, 0x1854,
  5789. 0x1880, 0x1894, 0x1900, 0x1984,
  5790. 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
  5791. 0x1c80, 0x1c94, 0x1d00, 0x1d84,
  5792. 0x2000, 0x2030, 0x23c0, 0x2400,
  5793. 0x2800, 0x2820, 0x2830, 0x2850,
  5794. 0x2b40, 0x2c10, 0x2fc0, 0x3058,
  5795. 0x3c00, 0x3c94, 0x4000, 0x4010,
  5796. 0x4080, 0x4090, 0x43c0, 0x4458,
  5797. 0x4c00, 0x4c18, 0x4c40, 0x4c54,
  5798. 0x4fc0, 0x5010, 0x53c0, 0x5444,
  5799. 0x5c00, 0x5c18, 0x5c80, 0x5c90,
  5800. 0x5fc0, 0x6000, 0x6400, 0x6428,
  5801. 0x6800, 0x6848, 0x684c, 0x6860,
  5802. 0x6888, 0x6910, 0x8000
  5803. };
  5804. regs->version = 0;
  5805. memset(p, 0, BNX2_REGDUMP_LEN);
  5806. if (!netif_running(bp->dev))
  5807. return;
  5808. i = 0;
  5809. offset = reg_boundaries[0];
  5810. p += offset;
  5811. while (offset < BNX2_REGDUMP_LEN) {
  5812. *p++ = BNX2_RD(bp, offset);
  5813. offset += 4;
  5814. if (offset == reg_boundaries[i + 1]) {
  5815. offset = reg_boundaries[i + 2];
  5816. p = (u32 *) (orig_p + offset);
  5817. i += 2;
  5818. }
  5819. }
  5820. }
  5821. static void
  5822. bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  5823. {
  5824. struct bnx2 *bp = netdev_priv(dev);
  5825. if (bp->flags & BNX2_FLAG_NO_WOL) {
  5826. wol->supported = 0;
  5827. wol->wolopts = 0;
  5828. }
  5829. else {
  5830. wol->supported = WAKE_MAGIC;
  5831. if (bp->wol)
  5832. wol->wolopts = WAKE_MAGIC;
  5833. else
  5834. wol->wolopts = 0;
  5835. }
  5836. memset(&wol->sopass, 0, sizeof(wol->sopass));
  5837. }
  5838. static int
  5839. bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  5840. {
  5841. struct bnx2 *bp = netdev_priv(dev);
  5842. if (wol->wolopts & ~WAKE_MAGIC)
  5843. return -EINVAL;
  5844. if (wol->wolopts & WAKE_MAGIC) {
  5845. if (bp->flags & BNX2_FLAG_NO_WOL)
  5846. return -EINVAL;
  5847. bp->wol = 1;
  5848. }
  5849. else {
  5850. bp->wol = 0;
  5851. }
  5852. device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
  5853. return 0;
  5854. }
  5855. static int
  5856. bnx2_nway_reset(struct net_device *dev)
  5857. {
  5858. struct bnx2 *bp = netdev_priv(dev);
  5859. u32 bmcr;
  5860. if (!netif_running(dev))
  5861. return -EAGAIN;
  5862. if (!(bp->autoneg & AUTONEG_SPEED)) {
  5863. return -EINVAL;
  5864. }
  5865. spin_lock_bh(&bp->phy_lock);
  5866. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  5867. int rc;
  5868. rc = bnx2_setup_remote_phy(bp, bp->phy_port);
  5869. spin_unlock_bh(&bp->phy_lock);
  5870. return rc;
  5871. }
  5872. /* Force a link down visible on the other side */
  5873. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  5874. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  5875. spin_unlock_bh(&bp->phy_lock);
  5876. msleep(20);
  5877. spin_lock_bh(&bp->phy_lock);
  5878. bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
  5879. bp->serdes_an_pending = 1;
  5880. mod_timer(&bp->timer, jiffies + bp->current_interval);
  5881. }
  5882. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  5883. bmcr &= ~BMCR_LOOPBACK;
  5884. bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
  5885. spin_unlock_bh(&bp->phy_lock);
  5886. return 0;
  5887. }
  5888. static u32
  5889. bnx2_get_link(struct net_device *dev)
  5890. {
  5891. struct bnx2 *bp = netdev_priv(dev);
  5892. return bp->link_up;
  5893. }
  5894. static int
  5895. bnx2_get_eeprom_len(struct net_device *dev)
  5896. {
  5897. struct bnx2 *bp = netdev_priv(dev);
  5898. if (!bp->flash_info)
  5899. return 0;
  5900. return (int) bp->flash_size;
  5901. }
  5902. static int
  5903. bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  5904. u8 *eebuf)
  5905. {
  5906. struct bnx2 *bp = netdev_priv(dev);
  5907. int rc;
  5908. /* parameters already validated in ethtool_get_eeprom */
  5909. rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
  5910. return rc;
  5911. }
  5912. static int
  5913. bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  5914. u8 *eebuf)
  5915. {
  5916. struct bnx2 *bp = netdev_priv(dev);
  5917. int rc;
  5918. /* parameters already validated in ethtool_set_eeprom */
  5919. rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
  5920. return rc;
  5921. }
  5922. static int
  5923. bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  5924. {
  5925. struct bnx2 *bp = netdev_priv(dev);
  5926. memset(coal, 0, sizeof(struct ethtool_coalesce));
  5927. coal->rx_coalesce_usecs = bp->rx_ticks;
  5928. coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
  5929. coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
  5930. coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
  5931. coal->tx_coalesce_usecs = bp->tx_ticks;
  5932. coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
  5933. coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
  5934. coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
  5935. coal->stats_block_coalesce_usecs = bp->stats_ticks;
  5936. return 0;
  5937. }
  5938. static int
  5939. bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  5940. {
  5941. struct bnx2 *bp = netdev_priv(dev);
  5942. bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
  5943. if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
  5944. bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
  5945. if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
  5946. bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
  5947. if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
  5948. bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
  5949. if (bp->rx_quick_cons_trip_int > 0xff)
  5950. bp->rx_quick_cons_trip_int = 0xff;
  5951. bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
  5952. if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
  5953. bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
  5954. if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
  5955. bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
  5956. if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
  5957. bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
  5958. if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
  5959. 0xff;
  5960. bp->stats_ticks = coal->stats_block_coalesce_usecs;
  5961. if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
  5962. if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
  5963. bp->stats_ticks = USEC_PER_SEC;
  5964. }
  5965. if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
  5966. bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  5967. bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  5968. if (netif_running(bp->dev)) {
  5969. bnx2_netif_stop(bp, true);
  5970. bnx2_init_nic(bp, 0);
  5971. bnx2_netif_start(bp, true);
  5972. }
  5973. return 0;
  5974. }
  5975. static void
  5976. bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  5977. {
  5978. struct bnx2 *bp = netdev_priv(dev);
  5979. ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT;
  5980. ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
  5981. ering->rx_pending = bp->rx_ring_size;
  5982. ering->rx_jumbo_pending = bp->rx_pg_ring_size;
  5983. ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT;
  5984. ering->tx_pending = bp->tx_ring_size;
  5985. }
  5986. static int
  5987. bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)
  5988. {
  5989. if (netif_running(bp->dev)) {
  5990. /* Reset will erase chipset stats; save them */
  5991. bnx2_save_stats(bp);
  5992. bnx2_netif_stop(bp, true);
  5993. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
  5994. if (reset_irq) {
  5995. bnx2_free_irq(bp);
  5996. bnx2_del_napi(bp);
  5997. } else {
  5998. __bnx2_free_irq(bp);
  5999. }
  6000. bnx2_free_skbs(bp);
  6001. bnx2_free_mem(bp);
  6002. }
  6003. bnx2_set_rx_ring_size(bp, rx);
  6004. bp->tx_ring_size = tx;
  6005. if (netif_running(bp->dev)) {
  6006. int rc = 0;
  6007. if (reset_irq) {
  6008. rc = bnx2_setup_int_mode(bp, disable_msi);
  6009. bnx2_init_napi(bp);
  6010. }
  6011. if (!rc)
  6012. rc = bnx2_alloc_mem(bp);
  6013. if (!rc)
  6014. rc = bnx2_request_irq(bp);
  6015. if (!rc)
  6016. rc = bnx2_init_nic(bp, 0);
  6017. if (rc) {
  6018. bnx2_napi_enable(bp);
  6019. dev_close(bp->dev);
  6020. return rc;
  6021. }
  6022. #ifdef BCM_CNIC
  6023. mutex_lock(&bp->cnic_lock);
  6024. /* Let cnic know about the new status block. */
  6025. if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
  6026. bnx2_setup_cnic_irq_info(bp);
  6027. mutex_unlock(&bp->cnic_lock);
  6028. #endif
  6029. bnx2_netif_start(bp, true);
  6030. }
  6031. return 0;
  6032. }
  6033. static int
  6034. bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  6035. {
  6036. struct bnx2 *bp = netdev_priv(dev);
  6037. int rc;
  6038. if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) ||
  6039. (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) ||
  6040. (ering->tx_pending <= MAX_SKB_FRAGS)) {
  6041. return -EINVAL;
  6042. }
  6043. rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,
  6044. false);
  6045. return rc;
  6046. }
  6047. static void
  6048. bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  6049. {
  6050. struct bnx2 *bp = netdev_priv(dev);
  6051. epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
  6052. epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
  6053. epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
  6054. }
  6055. static int
  6056. bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  6057. {
  6058. struct bnx2 *bp = netdev_priv(dev);
  6059. bp->req_flow_ctrl = 0;
  6060. if (epause->rx_pause)
  6061. bp->req_flow_ctrl |= FLOW_CTRL_RX;
  6062. if (epause->tx_pause)
  6063. bp->req_flow_ctrl |= FLOW_CTRL_TX;
  6064. if (epause->autoneg) {
  6065. bp->autoneg |= AUTONEG_FLOW_CTRL;
  6066. }
  6067. else {
  6068. bp->autoneg &= ~AUTONEG_FLOW_CTRL;
  6069. }
  6070. if (netif_running(dev)) {
  6071. spin_lock_bh(&bp->phy_lock);
  6072. bnx2_setup_phy(bp, bp->phy_port);
  6073. spin_unlock_bh(&bp->phy_lock);
  6074. }
  6075. return 0;
  6076. }
  6077. static struct {
  6078. char string[ETH_GSTRING_LEN];
  6079. } bnx2_stats_str_arr[] = {
  6080. { "rx_bytes" },
  6081. { "rx_error_bytes" },
  6082. { "tx_bytes" },
  6083. { "tx_error_bytes" },
  6084. { "rx_ucast_packets" },
  6085. { "rx_mcast_packets" },
  6086. { "rx_bcast_packets" },
  6087. { "tx_ucast_packets" },
  6088. { "tx_mcast_packets" },
  6089. { "tx_bcast_packets" },
  6090. { "tx_mac_errors" },
  6091. { "tx_carrier_errors" },
  6092. { "rx_crc_errors" },
  6093. { "rx_align_errors" },
  6094. { "tx_single_collisions" },
  6095. { "tx_multi_collisions" },
  6096. { "tx_deferred" },
  6097. { "tx_excess_collisions" },
  6098. { "tx_late_collisions" },
  6099. { "tx_total_collisions" },
  6100. { "rx_fragments" },
  6101. { "rx_jabbers" },
  6102. { "rx_undersize_packets" },
  6103. { "rx_oversize_packets" },
  6104. { "rx_64_byte_packets" },
  6105. { "rx_65_to_127_byte_packets" },
  6106. { "rx_128_to_255_byte_packets" },
  6107. { "rx_256_to_511_byte_packets" },
  6108. { "rx_512_to_1023_byte_packets" },
  6109. { "rx_1024_to_1522_byte_packets" },
  6110. { "rx_1523_to_9022_byte_packets" },
  6111. { "tx_64_byte_packets" },
  6112. { "tx_65_to_127_byte_packets" },
  6113. { "tx_128_to_255_byte_packets" },
  6114. { "tx_256_to_511_byte_packets" },
  6115. { "tx_512_to_1023_byte_packets" },
  6116. { "tx_1024_to_1522_byte_packets" },
  6117. { "tx_1523_to_9022_byte_packets" },
  6118. { "rx_xon_frames" },
  6119. { "rx_xoff_frames" },
  6120. { "tx_xon_frames" },
  6121. { "tx_xoff_frames" },
  6122. { "rx_mac_ctrl_frames" },
  6123. { "rx_filtered_packets" },
  6124. { "rx_ftq_discards" },
  6125. { "rx_discards" },
  6126. { "rx_fw_discards" },
  6127. };
  6128. #define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr)
  6129. #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
  6130. static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
  6131. STATS_OFFSET32(stat_IfHCInOctets_hi),
  6132. STATS_OFFSET32(stat_IfHCInBadOctets_hi),
  6133. STATS_OFFSET32(stat_IfHCOutOctets_hi),
  6134. STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
  6135. STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
  6136. STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
  6137. STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
  6138. STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
  6139. STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
  6140. STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
  6141. STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
  6142. STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
  6143. STATS_OFFSET32(stat_Dot3StatsFCSErrors),
  6144. STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
  6145. STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
  6146. STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
  6147. STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
  6148. STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
  6149. STATS_OFFSET32(stat_Dot3StatsLateCollisions),
  6150. STATS_OFFSET32(stat_EtherStatsCollisions),
  6151. STATS_OFFSET32(stat_EtherStatsFragments),
  6152. STATS_OFFSET32(stat_EtherStatsJabbers),
  6153. STATS_OFFSET32(stat_EtherStatsUndersizePkts),
  6154. STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
  6155. STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
  6156. STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
  6157. STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
  6158. STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
  6159. STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
  6160. STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
  6161. STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
  6162. STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
  6163. STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
  6164. STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
  6165. STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
  6166. STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
  6167. STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
  6168. STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
  6169. STATS_OFFSET32(stat_XonPauseFramesReceived),
  6170. STATS_OFFSET32(stat_XoffPauseFramesReceived),
  6171. STATS_OFFSET32(stat_OutXonSent),
  6172. STATS_OFFSET32(stat_OutXoffSent),
  6173. STATS_OFFSET32(stat_MacControlFramesReceived),
  6174. STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
  6175. STATS_OFFSET32(stat_IfInFTQDiscards),
  6176. STATS_OFFSET32(stat_IfInMBUFDiscards),
  6177. STATS_OFFSET32(stat_FwRxDrop),
  6178. };
  6179. /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
  6180. * skipped because of errata.
  6181. */
  6182. static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
  6183. 8,0,8,8,8,8,8,8,8,8,
  6184. 4,0,4,4,4,4,4,4,4,4,
  6185. 4,4,4,4,4,4,4,4,4,4,
  6186. 4,4,4,4,4,4,4,4,4,4,
  6187. 4,4,4,4,4,4,4,
  6188. };
  6189. static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
  6190. 8,0,8,8,8,8,8,8,8,8,
  6191. 4,4,4,4,4,4,4,4,4,4,
  6192. 4,4,4,4,4,4,4,4,4,4,
  6193. 4,4,4,4,4,4,4,4,4,4,
  6194. 4,4,4,4,4,4,4,
  6195. };
  6196. #define BNX2_NUM_TESTS 6
  6197. static struct {
  6198. char string[ETH_GSTRING_LEN];
  6199. } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
  6200. { "register_test (offline)" },
  6201. { "memory_test (offline)" },
  6202. { "loopback_test (offline)" },
  6203. { "nvram_test (online)" },
  6204. { "interrupt_test (online)" },
  6205. { "link_test (online)" },
  6206. };
  6207. static int
  6208. bnx2_get_sset_count(struct net_device *dev, int sset)
  6209. {
  6210. switch (sset) {
  6211. case ETH_SS_TEST:
  6212. return BNX2_NUM_TESTS;
  6213. case ETH_SS_STATS:
  6214. return BNX2_NUM_STATS;
  6215. default:
  6216. return -EOPNOTSUPP;
  6217. }
  6218. }
  6219. static void
  6220. bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
  6221. {
  6222. struct bnx2 *bp = netdev_priv(dev);
  6223. memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
  6224. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  6225. int i;
  6226. bnx2_netif_stop(bp, true);
  6227. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
  6228. bnx2_free_skbs(bp);
  6229. if (bnx2_test_registers(bp) != 0) {
  6230. buf[0] = 1;
  6231. etest->flags |= ETH_TEST_FL_FAILED;
  6232. }
  6233. if (bnx2_test_memory(bp) != 0) {
  6234. buf[1] = 1;
  6235. etest->flags |= ETH_TEST_FL_FAILED;
  6236. }
  6237. if ((buf[2] = bnx2_test_loopback(bp)) != 0)
  6238. etest->flags |= ETH_TEST_FL_FAILED;
  6239. if (!netif_running(bp->dev))
  6240. bnx2_shutdown_chip(bp);
  6241. else {
  6242. bnx2_init_nic(bp, 1);
  6243. bnx2_netif_start(bp, true);
  6244. }
  6245. /* wait for link up */
  6246. for (i = 0; i < 7; i++) {
  6247. if (bp->link_up)
  6248. break;
  6249. msleep_interruptible(1000);
  6250. }
  6251. }
  6252. if (bnx2_test_nvram(bp) != 0) {
  6253. buf[3] = 1;
  6254. etest->flags |= ETH_TEST_FL_FAILED;
  6255. }
  6256. if (bnx2_test_intr(bp) != 0) {
  6257. buf[4] = 1;
  6258. etest->flags |= ETH_TEST_FL_FAILED;
  6259. }
  6260. if (bnx2_test_link(bp) != 0) {
  6261. buf[5] = 1;
  6262. etest->flags |= ETH_TEST_FL_FAILED;
  6263. }
  6264. }
  6265. static void
  6266. bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  6267. {
  6268. switch (stringset) {
  6269. case ETH_SS_STATS:
  6270. memcpy(buf, bnx2_stats_str_arr,
  6271. sizeof(bnx2_stats_str_arr));
  6272. break;
  6273. case ETH_SS_TEST:
  6274. memcpy(buf, bnx2_tests_str_arr,
  6275. sizeof(bnx2_tests_str_arr));
  6276. break;
  6277. }
  6278. }
  6279. static void
  6280. bnx2_get_ethtool_stats(struct net_device *dev,
  6281. struct ethtool_stats *stats, u64 *buf)
  6282. {
  6283. struct bnx2 *bp = netdev_priv(dev);
  6284. int i;
  6285. u32 *hw_stats = (u32 *) bp->stats_blk;
  6286. u32 *temp_stats = (u32 *) bp->temp_stats_blk;
  6287. u8 *stats_len_arr = NULL;
  6288. if (!hw_stats) {
  6289. memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
  6290. return;
  6291. }
  6292. if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
  6293. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||
  6294. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||
  6295. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
  6296. stats_len_arr = bnx2_5706_stats_len_arr;
  6297. else
  6298. stats_len_arr = bnx2_5708_stats_len_arr;
  6299. for (i = 0; i < BNX2_NUM_STATS; i++) {
  6300. unsigned long offset;
  6301. if (stats_len_arr[i] == 0) {
  6302. /* skip this counter */
  6303. buf[i] = 0;
  6304. continue;
  6305. }
  6306. offset = bnx2_stats_offset_arr[i];
  6307. if (stats_len_arr[i] == 4) {
  6308. /* 4-byte counter */
  6309. buf[i] = (u64) *(hw_stats + offset) +
  6310. *(temp_stats + offset);
  6311. continue;
  6312. }
  6313. /* 8-byte counter */
  6314. buf[i] = (((u64) *(hw_stats + offset)) << 32) +
  6315. *(hw_stats + offset + 1) +
  6316. (((u64) *(temp_stats + offset)) << 32) +
  6317. *(temp_stats + offset + 1);
  6318. }
  6319. }
  6320. static int
  6321. bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
  6322. {
  6323. struct bnx2 *bp = netdev_priv(dev);
  6324. switch (state) {
  6325. case ETHTOOL_ID_ACTIVE:
  6326. bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
  6327. BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
  6328. return 1; /* cycle on/off once per second */
  6329. case ETHTOOL_ID_ON:
  6330. BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
  6331. BNX2_EMAC_LED_1000MB_OVERRIDE |
  6332. BNX2_EMAC_LED_100MB_OVERRIDE |
  6333. BNX2_EMAC_LED_10MB_OVERRIDE |
  6334. BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
  6335. BNX2_EMAC_LED_TRAFFIC);
  6336. break;
  6337. case ETHTOOL_ID_OFF:
  6338. BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
  6339. break;
  6340. case ETHTOOL_ID_INACTIVE:
  6341. BNX2_WR(bp, BNX2_EMAC_LED, 0);
  6342. BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
  6343. break;
  6344. }
  6345. return 0;
  6346. }
  6347. static int
  6348. bnx2_set_features(struct net_device *dev, netdev_features_t features)
  6349. {
  6350. struct bnx2 *bp = netdev_priv(dev);
  6351. /* TSO with VLAN tag won't work with current firmware */
  6352. if (features & NETIF_F_HW_VLAN_CTAG_TX)
  6353. dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
  6354. else
  6355. dev->vlan_features &= ~NETIF_F_ALL_TSO;
  6356. if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) !=
  6357. !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
  6358. netif_running(dev)) {
  6359. bnx2_netif_stop(bp, false);
  6360. dev->features = features;
  6361. bnx2_set_rx_mode(dev);
  6362. bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
  6363. bnx2_netif_start(bp, false);
  6364. return 1;
  6365. }
  6366. return 0;
  6367. }
  6368. static void bnx2_get_channels(struct net_device *dev,
  6369. struct ethtool_channels *channels)
  6370. {
  6371. struct bnx2 *bp = netdev_priv(dev);
  6372. u32 max_rx_rings = 1;
  6373. u32 max_tx_rings = 1;
  6374. if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
  6375. max_rx_rings = RX_MAX_RINGS;
  6376. max_tx_rings = TX_MAX_RINGS;
  6377. }
  6378. channels->max_rx = max_rx_rings;
  6379. channels->max_tx = max_tx_rings;
  6380. channels->max_other = 0;
  6381. channels->max_combined = 0;
  6382. channels->rx_count = bp->num_rx_rings;
  6383. channels->tx_count = bp->num_tx_rings;
  6384. channels->other_count = 0;
  6385. channels->combined_count = 0;
  6386. }
  6387. static int bnx2_set_channels(struct net_device *dev,
  6388. struct ethtool_channels *channels)
  6389. {
  6390. struct bnx2 *bp = netdev_priv(dev);
  6391. u32 max_rx_rings = 1;
  6392. u32 max_tx_rings = 1;
  6393. int rc = 0;
  6394. if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
  6395. max_rx_rings = RX_MAX_RINGS;
  6396. max_tx_rings = TX_MAX_RINGS;
  6397. }
  6398. if (channels->rx_count > max_rx_rings ||
  6399. channels->tx_count > max_tx_rings)
  6400. return -EINVAL;
  6401. bp->num_req_rx_rings = channels->rx_count;
  6402. bp->num_req_tx_rings = channels->tx_count;
  6403. if (netif_running(dev))
  6404. rc = bnx2_change_ring_size(bp, bp->rx_ring_size,
  6405. bp->tx_ring_size, true);
  6406. return rc;
  6407. }
  6408. static const struct ethtool_ops bnx2_ethtool_ops = {
  6409. .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
  6410. ETHTOOL_COALESCE_MAX_FRAMES |
  6411. ETHTOOL_COALESCE_USECS_IRQ |
  6412. ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
  6413. ETHTOOL_COALESCE_STATS_BLOCK_USECS,
  6414. .get_drvinfo = bnx2_get_drvinfo,
  6415. .get_regs_len = bnx2_get_regs_len,
  6416. .get_regs = bnx2_get_regs,
  6417. .get_wol = bnx2_get_wol,
  6418. .set_wol = bnx2_set_wol,
  6419. .nway_reset = bnx2_nway_reset,
  6420. .get_link = bnx2_get_link,
  6421. .get_eeprom_len = bnx2_get_eeprom_len,
  6422. .get_eeprom = bnx2_get_eeprom,
  6423. .set_eeprom = bnx2_set_eeprom,
  6424. .get_coalesce = bnx2_get_coalesce,
  6425. .set_coalesce = bnx2_set_coalesce,
  6426. .get_ringparam = bnx2_get_ringparam,
  6427. .set_ringparam = bnx2_set_ringparam,
  6428. .get_pauseparam = bnx2_get_pauseparam,
  6429. .set_pauseparam = bnx2_set_pauseparam,
  6430. .self_test = bnx2_self_test,
  6431. .get_strings = bnx2_get_strings,
  6432. .set_phys_id = bnx2_set_phys_id,
  6433. .get_ethtool_stats = bnx2_get_ethtool_stats,
  6434. .get_sset_count = bnx2_get_sset_count,
  6435. .get_channels = bnx2_get_channels,
  6436. .set_channels = bnx2_set_channels,
  6437. .get_link_ksettings = bnx2_get_link_ksettings,
  6438. .set_link_ksettings = bnx2_set_link_ksettings,
  6439. };
  6440. /* Called with rtnl_lock */
  6441. static int
  6442. bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  6443. {
  6444. struct mii_ioctl_data *data = if_mii(ifr);
  6445. struct bnx2 *bp = netdev_priv(dev);
  6446. int err;
  6447. switch(cmd) {
  6448. case SIOCGMIIPHY:
  6449. data->phy_id = bp->phy_addr;
  6450. /* fallthru */
  6451. case SIOCGMIIREG: {
  6452. u32 mii_regval;
  6453. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  6454. return -EOPNOTSUPP;
  6455. if (!netif_running(dev))
  6456. return -EAGAIN;
  6457. spin_lock_bh(&bp->phy_lock);
  6458. err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
  6459. spin_unlock_bh(&bp->phy_lock);
  6460. data->val_out = mii_regval;
  6461. return err;
  6462. }
  6463. case SIOCSMIIREG:
  6464. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  6465. return -EOPNOTSUPP;
  6466. if (!netif_running(dev))
  6467. return -EAGAIN;
  6468. spin_lock_bh(&bp->phy_lock);
  6469. err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
  6470. spin_unlock_bh(&bp->phy_lock);
  6471. return err;
  6472. default:
  6473. /* do nothing */
  6474. break;
  6475. }
  6476. return -EOPNOTSUPP;
  6477. }
  6478. /* Called with rtnl_lock */
  6479. static int
  6480. bnx2_change_mac_addr(struct net_device *dev, void *p)
  6481. {
  6482. struct sockaddr *addr = p;
  6483. struct bnx2 *bp = netdev_priv(dev);
  6484. if (!is_valid_ether_addr(addr->sa_data))
  6485. return -EADDRNOTAVAIL;
  6486. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  6487. if (netif_running(dev))
  6488. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  6489. return 0;
  6490. }
  6491. /* Called with rtnl_lock */
  6492. static int
  6493. bnx2_change_mtu(struct net_device *dev, int new_mtu)
  6494. {
  6495. struct bnx2 *bp = netdev_priv(dev);
  6496. dev->mtu = new_mtu;
  6497. return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
  6498. false);
  6499. }
  6500. #ifdef CONFIG_NET_POLL_CONTROLLER
  6501. static void
  6502. poll_bnx2(struct net_device *dev)
  6503. {
  6504. struct bnx2 *bp = netdev_priv(dev);
  6505. int i;
  6506. for (i = 0; i < bp->irq_nvecs; i++) {
  6507. struct bnx2_irq *irq = &bp->irq_tbl[i];
  6508. disable_irq(irq->vector);
  6509. irq->handler(irq->vector, &bp->bnx2_napi[i]);
  6510. enable_irq(irq->vector);
  6511. }
  6512. }
  6513. #endif
  6514. static void
  6515. bnx2_get_5709_media(struct bnx2 *bp)
  6516. {
  6517. u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
  6518. u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
  6519. u32 strap;
  6520. if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
  6521. return;
  6522. else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
  6523. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6524. return;
  6525. }
  6526. if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
  6527. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
  6528. else
  6529. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
  6530. if (bp->func == 0) {
  6531. switch (strap) {
  6532. case 0x4:
  6533. case 0x5:
  6534. case 0x6:
  6535. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6536. return;
  6537. }
  6538. } else {
  6539. switch (strap) {
  6540. case 0x1:
  6541. case 0x2:
  6542. case 0x4:
  6543. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6544. return;
  6545. }
  6546. }
  6547. }
  6548. static void
  6549. bnx2_get_pci_speed(struct bnx2 *bp)
  6550. {
  6551. u32 reg;
  6552. reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
  6553. if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
  6554. u32 clkreg;
  6555. bp->flags |= BNX2_FLAG_PCIX;
  6556. clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
  6557. clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
  6558. switch (clkreg) {
  6559. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
  6560. bp->bus_speed_mhz = 133;
  6561. break;
  6562. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
  6563. bp->bus_speed_mhz = 100;
  6564. break;
  6565. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
  6566. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
  6567. bp->bus_speed_mhz = 66;
  6568. break;
  6569. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
  6570. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
  6571. bp->bus_speed_mhz = 50;
  6572. break;
  6573. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
  6574. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
  6575. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
  6576. bp->bus_speed_mhz = 33;
  6577. break;
  6578. }
  6579. }
  6580. else {
  6581. if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
  6582. bp->bus_speed_mhz = 66;
  6583. else
  6584. bp->bus_speed_mhz = 33;
  6585. }
  6586. if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
  6587. bp->flags |= BNX2_FLAG_PCI_32BIT;
  6588. }
  6589. static void
  6590. bnx2_read_vpd_fw_ver(struct bnx2 *bp)
  6591. {
  6592. int rc, i, j;
  6593. u8 *data;
  6594. unsigned int block_end, rosize, len;
  6595. #define BNX2_VPD_NVRAM_OFFSET 0x300
  6596. #define BNX2_VPD_LEN 128
  6597. #define BNX2_MAX_VER_SLEN 30
  6598. data = kmalloc(256, GFP_KERNEL);
  6599. if (!data)
  6600. return;
  6601. rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
  6602. BNX2_VPD_LEN);
  6603. if (rc)
  6604. goto vpd_done;
  6605. for (i = 0; i < BNX2_VPD_LEN; i += 4) {
  6606. data[i] = data[i + BNX2_VPD_LEN + 3];
  6607. data[i + 1] = data[i + BNX2_VPD_LEN + 2];
  6608. data[i + 2] = data[i + BNX2_VPD_LEN + 1];
  6609. data[i + 3] = data[i + BNX2_VPD_LEN];
  6610. }
  6611. i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
  6612. if (i < 0)
  6613. goto vpd_done;
  6614. rosize = pci_vpd_lrdt_size(&data[i]);
  6615. i += PCI_VPD_LRDT_TAG_SIZE;
  6616. block_end = i + rosize;
  6617. if (block_end > BNX2_VPD_LEN)
  6618. goto vpd_done;
  6619. j = pci_vpd_find_info_keyword(data, i, rosize,
  6620. PCI_VPD_RO_KEYWORD_MFR_ID);
  6621. if (j < 0)
  6622. goto vpd_done;
  6623. len = pci_vpd_info_field_size(&data[j]);
  6624. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  6625. if (j + len > block_end || len != 4 ||
  6626. memcmp(&data[j], "1028", 4))
  6627. goto vpd_done;
  6628. j = pci_vpd_find_info_keyword(data, i, rosize,
  6629. PCI_VPD_RO_KEYWORD_VENDOR0);
  6630. if (j < 0)
  6631. goto vpd_done;
  6632. len = pci_vpd_info_field_size(&data[j]);
  6633. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  6634. if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
  6635. goto vpd_done;
  6636. memcpy(bp->fw_version, &data[j], len);
  6637. bp->fw_version[len] = ' ';
  6638. vpd_done:
  6639. kfree(data);
  6640. }
  6641. static int
  6642. bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
  6643. {
  6644. struct bnx2 *bp;
  6645. int rc, i, j;
  6646. u32 reg;
  6647. u64 dma_mask, persist_dma_mask;
  6648. int err;
  6649. SET_NETDEV_DEV(dev, &pdev->dev);
  6650. bp = netdev_priv(dev);
  6651. bp->flags = 0;
  6652. bp->phy_flags = 0;
  6653. bp->temp_stats_blk =
  6654. kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
  6655. if (!bp->temp_stats_blk) {
  6656. rc = -ENOMEM;
  6657. goto err_out;
  6658. }
  6659. /* enable device (incl. PCI PM wakeup), and bus-mastering */
  6660. rc = pci_enable_device(pdev);
  6661. if (rc) {
  6662. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  6663. goto err_out;
  6664. }
  6665. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  6666. dev_err(&pdev->dev,
  6667. "Cannot find PCI device base address, aborting\n");
  6668. rc = -ENODEV;
  6669. goto err_out_disable;
  6670. }
  6671. rc = pci_request_regions(pdev, DRV_MODULE_NAME);
  6672. if (rc) {
  6673. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  6674. goto err_out_disable;
  6675. }
  6676. pci_set_master(pdev);
  6677. bp->pm_cap = pdev->pm_cap;
  6678. if (bp->pm_cap == 0) {
  6679. dev_err(&pdev->dev,
  6680. "Cannot find power management capability, aborting\n");
  6681. rc = -EIO;
  6682. goto err_out_release;
  6683. }
  6684. bp->dev = dev;
  6685. bp->pdev = pdev;
  6686. spin_lock_init(&bp->phy_lock);
  6687. spin_lock_init(&bp->indirect_lock);
  6688. #ifdef BCM_CNIC
  6689. mutex_init(&bp->cnic_lock);
  6690. #endif
  6691. INIT_WORK(&bp->reset_task, bnx2_reset_task);
  6692. bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
  6693. TX_MAX_TSS_RINGS + 1));
  6694. if (!bp->regview) {
  6695. dev_err(&pdev->dev, "Cannot map register space, aborting\n");
  6696. rc = -ENOMEM;
  6697. goto err_out_release;
  6698. }
  6699. /* Configure byte swap and enable write to the reg_window registers.
  6700. * Rely on CPU to do target byte swapping on big endian systems
  6701. * The chip's target access swapping will not swap all accesses
  6702. */
  6703. BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
  6704. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  6705. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
  6706. bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
  6707. if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
  6708. if (!pci_is_pcie(pdev)) {
  6709. dev_err(&pdev->dev, "Not PCIE, aborting\n");
  6710. rc = -EIO;
  6711. goto err_out_unmap;
  6712. }
  6713. bp->flags |= BNX2_FLAG_PCIE;
  6714. if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
  6715. bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
  6716. /* AER (Advanced Error Reporting) hooks */
  6717. err = pci_enable_pcie_error_reporting(pdev);
  6718. if (!err)
  6719. bp->flags |= BNX2_FLAG_AER_ENABLED;
  6720. } else {
  6721. bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
  6722. if (bp->pcix_cap == 0) {
  6723. dev_err(&pdev->dev,
  6724. "Cannot find PCIX capability, aborting\n");
  6725. rc = -EIO;
  6726. goto err_out_unmap;
  6727. }
  6728. bp->flags |= BNX2_FLAG_BROKEN_STATS;
  6729. }
  6730. if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
  6731. BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {
  6732. if (pdev->msix_cap)
  6733. bp->flags |= BNX2_FLAG_MSIX_CAP;
  6734. }
  6735. if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&
  6736. BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {
  6737. if (pdev->msi_cap)
  6738. bp->flags |= BNX2_FLAG_MSI_CAP;
  6739. }
  6740. /* 5708 cannot support DMA addresses > 40-bit. */
  6741. if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
  6742. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  6743. else
  6744. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  6745. /* Configure DMA attributes. */
  6746. if (pci_set_dma_mask(pdev, dma_mask) == 0) {
  6747. dev->features |= NETIF_F_HIGHDMA;
  6748. rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
  6749. if (rc) {
  6750. dev_err(&pdev->dev,
  6751. "pci_set_consistent_dma_mask failed, aborting\n");
  6752. goto err_out_unmap;
  6753. }
  6754. } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
  6755. dev_err(&pdev->dev, "System does not support DMA, aborting\n");
  6756. goto err_out_unmap;
  6757. }
  6758. if (!(bp->flags & BNX2_FLAG_PCIE))
  6759. bnx2_get_pci_speed(bp);
  6760. /* 5706A0 may falsely detect SERR and PERR. */
  6761. if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
  6762. reg = BNX2_RD(bp, PCI_COMMAND);
  6763. reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  6764. BNX2_WR(bp, PCI_COMMAND, reg);
  6765. } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&
  6766. !(bp->flags & BNX2_FLAG_PCIX)) {
  6767. dev_err(&pdev->dev,
  6768. "5706 A1 can only be used in a PCIX bus, aborting\n");
  6769. goto err_out_unmap;
  6770. }
  6771. bnx2_init_nvram(bp);
  6772. reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
  6773. if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)
  6774. bp->func = 1;
  6775. if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
  6776. BNX2_SHM_HDR_SIGNATURE_SIG) {
  6777. u32 off = bp->func << 2;
  6778. bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
  6779. } else
  6780. bp->shmem_base = HOST_VIEW_SHMEM_BASE;
  6781. /* Get the permanent MAC address. First we need to make sure the
  6782. * firmware is actually running.
  6783. */
  6784. reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
  6785. if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
  6786. BNX2_DEV_INFO_SIGNATURE_MAGIC) {
  6787. dev_err(&pdev->dev, "Firmware not running, aborting\n");
  6788. rc = -ENODEV;
  6789. goto err_out_unmap;
  6790. }
  6791. bnx2_read_vpd_fw_ver(bp);
  6792. j = strlen(bp->fw_version);
  6793. reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
  6794. for (i = 0; i < 3 && j < 24; i++) {
  6795. u8 num, k, skip0;
  6796. if (i == 0) {
  6797. bp->fw_version[j++] = 'b';
  6798. bp->fw_version[j++] = 'c';
  6799. bp->fw_version[j++] = ' ';
  6800. }
  6801. num = (u8) (reg >> (24 - (i * 8)));
  6802. for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
  6803. if (num >= k || !skip0 || k == 1) {
  6804. bp->fw_version[j++] = (num / k) + '0';
  6805. skip0 = 0;
  6806. }
  6807. }
  6808. if (i != 2)
  6809. bp->fw_version[j++] = '.';
  6810. }
  6811. reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
  6812. if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
  6813. bp->wol = 1;
  6814. if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
  6815. bp->flags |= BNX2_FLAG_ASF_ENABLE;
  6816. for (i = 0; i < 30; i++) {
  6817. reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
  6818. if (reg & BNX2_CONDITION_MFW_RUN_MASK)
  6819. break;
  6820. msleep(10);
  6821. }
  6822. }
  6823. reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
  6824. reg &= BNX2_CONDITION_MFW_RUN_MASK;
  6825. if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
  6826. reg != BNX2_CONDITION_MFW_RUN_NONE) {
  6827. u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
  6828. if (j < 32)
  6829. bp->fw_version[j++] = ' ';
  6830. for (i = 0; i < 3 && j < 28; i++) {
  6831. reg = bnx2_reg_rd_ind(bp, addr + i * 4);
  6832. reg = be32_to_cpu(reg);
  6833. memcpy(&bp->fw_version[j], &reg, 4);
  6834. j += 4;
  6835. }
  6836. }
  6837. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
  6838. bp->mac_addr[0] = (u8) (reg >> 8);
  6839. bp->mac_addr[1] = (u8) reg;
  6840. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
  6841. bp->mac_addr[2] = (u8) (reg >> 24);
  6842. bp->mac_addr[3] = (u8) (reg >> 16);
  6843. bp->mac_addr[4] = (u8) (reg >> 8);
  6844. bp->mac_addr[5] = (u8) reg;
  6845. bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;
  6846. bnx2_set_rx_ring_size(bp, 255);
  6847. bp->tx_quick_cons_trip_int = 2;
  6848. bp->tx_quick_cons_trip = 20;
  6849. bp->tx_ticks_int = 18;
  6850. bp->tx_ticks = 80;
  6851. bp->rx_quick_cons_trip_int = 2;
  6852. bp->rx_quick_cons_trip = 12;
  6853. bp->rx_ticks_int = 18;
  6854. bp->rx_ticks = 18;
  6855. bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  6856. bp->current_interval = BNX2_TIMER_INTERVAL;
  6857. bp->phy_addr = 1;
  6858. /* allocate stats_blk */
  6859. rc = bnx2_alloc_stats_blk(dev);
  6860. if (rc)
  6861. goto err_out_unmap;
  6862. /* Disable WOL support if we are running on a SERDES chip. */
  6863. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  6864. bnx2_get_5709_media(bp);
  6865. else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)
  6866. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6867. bp->phy_port = PORT_TP;
  6868. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  6869. bp->phy_port = PORT_FIBRE;
  6870. reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
  6871. if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
  6872. bp->flags |= BNX2_FLAG_NO_WOL;
  6873. bp->wol = 0;
  6874. }
  6875. if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {
  6876. /* Don't do parallel detect on this board because of
  6877. * some board problems. The link will not go down
  6878. * if we do parallel detect.
  6879. */
  6880. if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  6881. pdev->subsystem_device == 0x310c)
  6882. bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
  6883. } else {
  6884. bp->phy_addr = 2;
  6885. if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
  6886. bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
  6887. }
  6888. } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||
  6889. BNX2_CHIP(bp) == BNX2_CHIP_5708)
  6890. bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
  6891. else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
  6892. (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||
  6893. BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))
  6894. bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
  6895. bnx2_init_fw_cap(bp);
  6896. if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
  6897. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
  6898. (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||
  6899. !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
  6900. bp->flags |= BNX2_FLAG_NO_WOL;
  6901. bp->wol = 0;
  6902. }
  6903. if (bp->flags & BNX2_FLAG_NO_WOL)
  6904. device_set_wakeup_capable(&bp->pdev->dev, false);
  6905. else
  6906. device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
  6907. if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
  6908. bp->tx_quick_cons_trip_int =
  6909. bp->tx_quick_cons_trip;
  6910. bp->tx_ticks_int = bp->tx_ticks;
  6911. bp->rx_quick_cons_trip_int =
  6912. bp->rx_quick_cons_trip;
  6913. bp->rx_ticks_int = bp->rx_ticks;
  6914. bp->comp_prod_trip_int = bp->comp_prod_trip;
  6915. bp->com_ticks_int = bp->com_ticks;
  6916. bp->cmd_ticks_int = bp->cmd_ticks;
  6917. }
  6918. /* Disable MSI on 5706 if AMD 8132 bridge is found.
  6919. *
  6920. * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
  6921. * with byte enables disabled on the unused 32-bit word. This is legal
  6922. * but causes problems on the AMD 8132 which will eventually stop
  6923. * responding after a while.
  6924. *
  6925. * AMD believes this incompatibility is unique to the 5706, and
  6926. * prefers to locally disable MSI rather than globally disabling it.
  6927. */
  6928. if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {
  6929. struct pci_dev *amd_8132 = NULL;
  6930. while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
  6931. PCI_DEVICE_ID_AMD_8132_BRIDGE,
  6932. amd_8132))) {
  6933. if (amd_8132->revision >= 0x10 &&
  6934. amd_8132->revision <= 0x13) {
  6935. disable_msi = 1;
  6936. pci_dev_put(amd_8132);
  6937. break;
  6938. }
  6939. }
  6940. }
  6941. bnx2_set_default_link(bp);
  6942. bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
  6943. timer_setup(&bp->timer, bnx2_timer, 0);
  6944. bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
  6945. #ifdef BCM_CNIC
  6946. if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
  6947. bp->cnic_eth_dev.max_iscsi_conn =
  6948. (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
  6949. BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
  6950. bp->cnic_probe = bnx2_cnic_probe;
  6951. #endif
  6952. pci_save_state(pdev);
  6953. return 0;
  6954. err_out_unmap:
  6955. if (bp->flags & BNX2_FLAG_AER_ENABLED) {
  6956. pci_disable_pcie_error_reporting(pdev);
  6957. bp->flags &= ~BNX2_FLAG_AER_ENABLED;
  6958. }
  6959. pci_iounmap(pdev, bp->regview);
  6960. bp->regview = NULL;
  6961. err_out_release:
  6962. pci_release_regions(pdev);
  6963. err_out_disable:
  6964. pci_disable_device(pdev);
  6965. err_out:
  6966. kfree(bp->temp_stats_blk);
  6967. return rc;
  6968. }
  6969. static char *
  6970. bnx2_bus_string(struct bnx2 *bp, char *str)
  6971. {
  6972. char *s = str;
  6973. if (bp->flags & BNX2_FLAG_PCIE) {
  6974. s += sprintf(s, "PCI Express");
  6975. } else {
  6976. s += sprintf(s, "PCI");
  6977. if (bp->flags & BNX2_FLAG_PCIX)
  6978. s += sprintf(s, "-X");
  6979. if (bp->flags & BNX2_FLAG_PCI_32BIT)
  6980. s += sprintf(s, " 32-bit");
  6981. else
  6982. s += sprintf(s, " 64-bit");
  6983. s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
  6984. }
  6985. return str;
  6986. }
  6987. static void
  6988. bnx2_del_napi(struct bnx2 *bp)
  6989. {
  6990. int i;
  6991. for (i = 0; i < bp->irq_nvecs; i++)
  6992. netif_napi_del(&bp->bnx2_napi[i].napi);
  6993. }
  6994. static void
  6995. bnx2_init_napi(struct bnx2 *bp)
  6996. {
  6997. int i;
  6998. for (i = 0; i < bp->irq_nvecs; i++) {
  6999. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  7000. int (*poll)(struct napi_struct *, int);
  7001. if (i == 0)
  7002. poll = bnx2_poll;
  7003. else
  7004. poll = bnx2_poll_msix;
  7005. netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
  7006. bnapi->bp = bp;
  7007. }
  7008. }
  7009. static const struct net_device_ops bnx2_netdev_ops = {
  7010. .ndo_open = bnx2_open,
  7011. .ndo_start_xmit = bnx2_start_xmit,
  7012. .ndo_stop = bnx2_close,
  7013. .ndo_get_stats64 = bnx2_get_stats64,
  7014. .ndo_set_rx_mode = bnx2_set_rx_mode,
  7015. .ndo_do_ioctl = bnx2_ioctl,
  7016. .ndo_validate_addr = eth_validate_addr,
  7017. .ndo_set_mac_address = bnx2_change_mac_addr,
  7018. .ndo_change_mtu = bnx2_change_mtu,
  7019. .ndo_set_features = bnx2_set_features,
  7020. .ndo_tx_timeout = bnx2_tx_timeout,
  7021. #ifdef CONFIG_NET_POLL_CONTROLLER
  7022. .ndo_poll_controller = poll_bnx2,
  7023. #endif
  7024. };
  7025. static int
  7026. bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  7027. {
  7028. struct net_device *dev;
  7029. struct bnx2 *bp;
  7030. int rc;
  7031. char str[40];
  7032. /* dev zeroed in init_etherdev */
  7033. dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
  7034. if (!dev)
  7035. return -ENOMEM;
  7036. rc = bnx2_init_board(pdev, dev);
  7037. if (rc < 0)
  7038. goto err_free;
  7039. dev->netdev_ops = &bnx2_netdev_ops;
  7040. dev->watchdog_timeo = TX_TIMEOUT;
  7041. dev->ethtool_ops = &bnx2_ethtool_ops;
  7042. bp = netdev_priv(dev);
  7043. pci_set_drvdata(pdev, dev);
  7044. /*
  7045. * In-flight DMA from 1st kernel could continue going in kdump kernel.
  7046. * New io-page table has been created before bnx2 does reset at open stage.
  7047. * We have to wait for the in-flight DMA to complete to avoid it look up
  7048. * into the newly created io-page table.
  7049. */
  7050. if (is_kdump_kernel())
  7051. bnx2_wait_dma_complete(bp);
  7052. memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);
  7053. dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
  7054. NETIF_F_TSO | NETIF_F_TSO_ECN |
  7055. NETIF_F_RXHASH | NETIF_F_RXCSUM;
  7056. if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
  7057. dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  7058. dev->vlan_features = dev->hw_features;
  7059. dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
  7060. dev->features |= dev->hw_features;
  7061. dev->priv_flags |= IFF_UNICAST_FLT;
  7062. dev->min_mtu = MIN_ETHERNET_PACKET_SIZE;
  7063. dev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE;
  7064. if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
  7065. dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
  7066. if ((rc = register_netdev(dev))) {
  7067. dev_err(&pdev->dev, "Cannot register net device\n");
  7068. goto error;
  7069. }
  7070. netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, "
  7071. "node addr %pM\n", board_info[ent->driver_data].name,
  7072. ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',
  7073. ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),
  7074. bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),
  7075. pdev->irq, dev->dev_addr);
  7076. return 0;
  7077. error:
  7078. pci_iounmap(pdev, bp->regview);
  7079. pci_release_regions(pdev);
  7080. pci_disable_device(pdev);
  7081. err_free:
  7082. bnx2_free_stats_blk(dev);
  7083. free_netdev(dev);
  7084. return rc;
  7085. }
  7086. static void
  7087. bnx2_remove_one(struct pci_dev *pdev)
  7088. {
  7089. struct net_device *dev = pci_get_drvdata(pdev);
  7090. struct bnx2 *bp = netdev_priv(dev);
  7091. unregister_netdev(dev);
  7092. del_timer_sync(&bp->timer);
  7093. cancel_work_sync(&bp->reset_task);
  7094. pci_iounmap(bp->pdev, bp->regview);
  7095. bnx2_free_stats_blk(dev);
  7096. kfree(bp->temp_stats_blk);
  7097. if (bp->flags & BNX2_FLAG_AER_ENABLED) {
  7098. pci_disable_pcie_error_reporting(pdev);
  7099. bp->flags &= ~BNX2_FLAG_AER_ENABLED;
  7100. }
  7101. bnx2_release_firmware(bp);
  7102. free_netdev(dev);
  7103. pci_release_regions(pdev);
  7104. pci_disable_device(pdev);
  7105. }
  7106. #ifdef CONFIG_PM_SLEEP
  7107. static int
  7108. bnx2_suspend(struct device *device)
  7109. {
  7110. struct net_device *dev = dev_get_drvdata(device);
  7111. struct bnx2 *bp = netdev_priv(dev);
  7112. if (netif_running(dev)) {
  7113. cancel_work_sync(&bp->reset_task);
  7114. bnx2_netif_stop(bp, true);
  7115. netif_device_detach(dev);
  7116. del_timer_sync(&bp->timer);
  7117. bnx2_shutdown_chip(bp);
  7118. __bnx2_free_irq(bp);
  7119. bnx2_free_skbs(bp);
  7120. }
  7121. bnx2_setup_wol(bp);
  7122. return 0;
  7123. }
  7124. static int
  7125. bnx2_resume(struct device *device)
  7126. {
  7127. struct net_device *dev = dev_get_drvdata(device);
  7128. struct bnx2 *bp = netdev_priv(dev);
  7129. if (!netif_running(dev))
  7130. return 0;
  7131. bnx2_set_power_state(bp, PCI_D0);
  7132. netif_device_attach(dev);
  7133. bnx2_request_irq(bp);
  7134. bnx2_init_nic(bp, 1);
  7135. bnx2_netif_start(bp, true);
  7136. return 0;
  7137. }
  7138. static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume);
  7139. #define BNX2_PM_OPS (&bnx2_pm_ops)
  7140. #else
  7141. #define BNX2_PM_OPS NULL
  7142. #endif /* CONFIG_PM_SLEEP */
  7143. /**
  7144. * bnx2_io_error_detected - called when PCI error is detected
  7145. * @pdev: Pointer to PCI device
  7146. * @state: The current pci connection state
  7147. *
  7148. * This function is called after a PCI bus error affecting
  7149. * this device has been detected.
  7150. */
  7151. static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
  7152. pci_channel_state_t state)
  7153. {
  7154. struct net_device *dev = pci_get_drvdata(pdev);
  7155. struct bnx2 *bp = netdev_priv(dev);
  7156. rtnl_lock();
  7157. netif_device_detach(dev);
  7158. if (state == pci_channel_io_perm_failure) {
  7159. rtnl_unlock();
  7160. return PCI_ERS_RESULT_DISCONNECT;
  7161. }
  7162. if (netif_running(dev)) {
  7163. bnx2_netif_stop(bp, true);
  7164. del_timer_sync(&bp->timer);
  7165. bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
  7166. }
  7167. pci_disable_device(pdev);
  7168. rtnl_unlock();
  7169. /* Request a slot slot reset. */
  7170. return PCI_ERS_RESULT_NEED_RESET;
  7171. }
  7172. /**
  7173. * bnx2_io_slot_reset - called after the pci bus has been reset.
  7174. * @pdev: Pointer to PCI device
  7175. *
  7176. * Restart the card from scratch, as if from a cold-boot.
  7177. */
  7178. static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
  7179. {
  7180. struct net_device *dev = pci_get_drvdata(pdev);
  7181. struct bnx2 *bp = netdev_priv(dev);
  7182. pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
  7183. int err = 0;
  7184. rtnl_lock();
  7185. if (pci_enable_device(pdev)) {
  7186. dev_err(&pdev->dev,
  7187. "Cannot re-enable PCI device after reset\n");
  7188. } else {
  7189. pci_set_master(pdev);
  7190. pci_restore_state(pdev);
  7191. pci_save_state(pdev);
  7192. if (netif_running(dev))
  7193. err = bnx2_init_nic(bp, 1);
  7194. if (!err)
  7195. result = PCI_ERS_RESULT_RECOVERED;
  7196. }
  7197. if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) {
  7198. bnx2_napi_enable(bp);
  7199. dev_close(dev);
  7200. }
  7201. rtnl_unlock();
  7202. if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
  7203. return result;
  7204. return result;
  7205. }
  7206. /**
  7207. * bnx2_io_resume - called when traffic can start flowing again.
  7208. * @pdev: Pointer to PCI device
  7209. *
  7210. * This callback is called when the error recovery driver tells us that
  7211. * its OK to resume normal operation.
  7212. */
  7213. static void bnx2_io_resume(struct pci_dev *pdev)
  7214. {
  7215. struct net_device *dev = pci_get_drvdata(pdev);
  7216. struct bnx2 *bp = netdev_priv(dev);
  7217. rtnl_lock();
  7218. if (netif_running(dev))
  7219. bnx2_netif_start(bp, true);
  7220. netif_device_attach(dev);
  7221. rtnl_unlock();
  7222. }
  7223. static void bnx2_shutdown(struct pci_dev *pdev)
  7224. {
  7225. struct net_device *dev = pci_get_drvdata(pdev);
  7226. struct bnx2 *bp;
  7227. if (!dev)
  7228. return;
  7229. bp = netdev_priv(dev);
  7230. if (!bp)
  7231. return;
  7232. rtnl_lock();
  7233. if (netif_running(dev))
  7234. dev_close(bp->dev);
  7235. if (system_state == SYSTEM_POWER_OFF)
  7236. bnx2_set_power_state(bp, PCI_D3hot);
  7237. rtnl_unlock();
  7238. }
  7239. static const struct pci_error_handlers bnx2_err_handler = {
  7240. .error_detected = bnx2_io_error_detected,
  7241. .slot_reset = bnx2_io_slot_reset,
  7242. .resume = bnx2_io_resume,
  7243. };
  7244. static struct pci_driver bnx2_pci_driver = {
  7245. .name = DRV_MODULE_NAME,
  7246. .id_table = bnx2_pci_tbl,
  7247. .probe = bnx2_init_one,
  7248. .remove = bnx2_remove_one,
  7249. .driver.pm = BNX2_PM_OPS,
  7250. .err_handler = &bnx2_err_handler,
  7251. .shutdown = bnx2_shutdown,
  7252. };
  7253. module_pci_driver(bnx2_pci_driver);